1 /*******************************************************************************
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 The full GNU General Public License is included in this distribution in the
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * Shared functions for accessing and configuring the MAC
35 static int32_t e1000_set_phy_type(struct e1000_hw *hw);
36 static void e1000_phy_init_script(struct e1000_hw *hw);
37 static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
38 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
39 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
40 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
41 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
42 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
43 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
44 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
46 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
47 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
48 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
49 uint16_t words, uint16_t *data);
50 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
51 uint16_t offset, uint16_t words,
53 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
54 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
55 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
56 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
58 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
60 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
62 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
63 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
64 static void e1000_release_eeprom(struct e1000_hw *hw);
65 static void e1000_standby_eeprom(struct e1000_hw *hw);
66 static int32_t e1000_id_led_init(struct e1000_hw * hw);
67 static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
68 static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
70 /* IGP cable length table */
72 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
73 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
74 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
75 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
76 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
77 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
78 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
79 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
80 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
83 /******************************************************************************
84 * Set the phy type member in the hw struct.
86 * hw - Struct containing variables accessed by shared code
87 *****************************************************************************/
89 e1000_set_phy_type(struct e1000_hw *hw)
91 DEBUGFUNC("e1000_set_phy_type");
94 case M88E1000_E_PHY_ID:
95 case M88E1000_I_PHY_ID:
96 case M88E1011_I_PHY_ID:
97 hw->phy_type = e1000_phy_m88;
99 case IGP01E1000_I_PHY_ID:
100 if(hw->mac_type == e1000_82541 ||
101 hw->mac_type == e1000_82541_rev_2 ||
102 hw->mac_type == e1000_82547 ||
103 hw->mac_type == e1000_82547_rev_2) {
104 hw->phy_type = e1000_phy_igp;
109 /* Should never have loaded on this device */
110 hw->phy_type = e1000_phy_undefined;
111 return -E1000_ERR_PHY_TYPE;
114 return E1000_SUCCESS;
117 /******************************************************************************
118 * IGP phy init script - initializes the GbE PHY
120 * hw - Struct containing variables accessed by shared code
121 *****************************************************************************/
123 e1000_phy_init_script(struct e1000_hw *hw)
125 DEBUGFUNC("e1000_phy_init_script");
127 if(hw->phy_init_script) {
130 e1000_write_phy_reg(hw,0x0000,0x0140);
134 if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) {
135 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
137 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
139 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
141 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
143 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
145 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
147 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
149 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
151 e1000_write_phy_reg(hw, 0x2010, 0x0008);
153 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
156 e1000_write_phy_reg(hw, 0x0000, 0x3300);
158 if(hw->mac_type == e1000_82547) {
159 uint16_t fused, fine, coarse;
161 /* Move to analog registers page */
162 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
164 if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
165 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
167 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
168 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
170 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
171 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
172 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
173 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
174 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
176 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
177 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
178 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
180 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
181 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
182 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
188 /******************************************************************************
189 * Set the mac type member in the hw struct.
191 * hw - Struct containing variables accessed by shared code
192 *****************************************************************************/
194 e1000_set_mac_type(struct e1000_hw *hw)
196 DEBUGFUNC("e1000_set_mac_type");
198 switch (hw->device_id) {
199 case E1000_DEV_ID_82542:
200 switch (hw->revision_id) {
201 case E1000_82542_2_0_REV_ID:
202 hw->mac_type = e1000_82542_rev2_0;
204 case E1000_82542_2_1_REV_ID:
205 hw->mac_type = e1000_82542_rev2_1;
208 /* Invalid 82542 revision ID */
209 return -E1000_ERR_MAC_TYPE;
212 case E1000_DEV_ID_82543GC_FIBER:
213 case E1000_DEV_ID_82543GC_COPPER:
214 hw->mac_type = e1000_82543;
216 case E1000_DEV_ID_82544EI_COPPER:
217 case E1000_DEV_ID_82544EI_FIBER:
218 case E1000_DEV_ID_82544GC_COPPER:
219 case E1000_DEV_ID_82544GC_LOM:
220 hw->mac_type = e1000_82544;
222 case E1000_DEV_ID_82540EM:
223 case E1000_DEV_ID_82540EM_LOM:
224 case E1000_DEV_ID_82540EP:
225 case E1000_DEV_ID_82540EP_LOM:
226 case E1000_DEV_ID_82540EP_LP:
227 hw->mac_type = e1000_82540;
229 case E1000_DEV_ID_82545EM_COPPER:
230 case E1000_DEV_ID_82545EM_FIBER:
231 hw->mac_type = e1000_82545;
233 case E1000_DEV_ID_82545GM_COPPER:
234 case E1000_DEV_ID_82545GM_FIBER:
235 case E1000_DEV_ID_82545GM_SERDES:
236 hw->mac_type = e1000_82545_rev_3;
238 case E1000_DEV_ID_82546EB_COPPER:
239 case E1000_DEV_ID_82546EB_FIBER:
240 case E1000_DEV_ID_82546EB_QUAD_COPPER:
241 hw->mac_type = e1000_82546;
243 case E1000_DEV_ID_82546GB_COPPER:
244 case E1000_DEV_ID_82546GB_FIBER:
245 case E1000_DEV_ID_82546GB_SERDES:
246 hw->mac_type = e1000_82546_rev_3;
248 case E1000_DEV_ID_82541EI:
249 case E1000_DEV_ID_82541EI_MOBILE:
250 hw->mac_type = e1000_82541;
252 case E1000_DEV_ID_82541ER:
253 case E1000_DEV_ID_82541GI:
254 case E1000_DEV_ID_82541GI_MOBILE:
255 hw->mac_type = e1000_82541_rev_2;
257 case E1000_DEV_ID_82547EI:
258 hw->mac_type = e1000_82547;
260 case E1000_DEV_ID_82547GI:
261 hw->mac_type = e1000_82547_rev_2;
264 /* Should never have loaded on this device */
265 return -E1000_ERR_MAC_TYPE;
268 return E1000_SUCCESS;
271 /*****************************************************************************
272 * Set media type and TBI compatibility.
274 * hw - Struct containing variables accessed by shared code
275 * **************************************************************************/
277 e1000_set_media_type(struct e1000_hw *hw)
281 DEBUGFUNC("e1000_set_media_type");
283 if(hw->mac_type != e1000_82543) {
284 /* tbi_compatibility is only valid on 82543 */
285 hw->tbi_compatibility_en = FALSE;
288 switch (hw->device_id) {
289 case E1000_DEV_ID_82545GM_SERDES:
290 case E1000_DEV_ID_82546GB_SERDES:
291 hw->media_type = e1000_media_type_internal_serdes;
294 if(hw->mac_type >= e1000_82543) {
295 status = E1000_READ_REG(hw, STATUS);
296 if(status & E1000_STATUS_TBIMODE) {
297 hw->media_type = e1000_media_type_fiber;
298 /* tbi_compatibility not valid on fiber */
299 hw->tbi_compatibility_en = FALSE;
301 hw->media_type = e1000_media_type_copper;
304 /* This is an 82542 (fiber only) */
305 hw->media_type = e1000_media_type_fiber;
310 /******************************************************************************
311 * Reset the transmit and receive units; mask and clear all interrupts.
313 * hw - Struct containing variables accessed by shared code
314 *****************************************************************************/
316 e1000_reset_hw(struct e1000_hw *hw)
324 DEBUGFUNC("e1000_reset_hw");
326 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
327 if(hw->mac_type == e1000_82542_rev2_0) {
328 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
329 e1000_pci_clear_mwi(hw);
332 /* Clear interrupt mask to stop board from generating interrupts */
333 DEBUGOUT("Masking off all interrupts\n");
334 E1000_WRITE_REG(hw, IMC, 0xffffffff);
336 /* Disable the Transmit and Receive units. Then delay to allow
337 * any pending transactions to complete before we hit the MAC with
340 E1000_WRITE_REG(hw, RCTL, 0);
341 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
342 E1000_WRITE_FLUSH(hw);
344 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
345 hw->tbi_compatibility_on = FALSE;
347 /* Delay to allow any outstanding PCI transactions to complete before
348 * resetting the device
352 ctrl = E1000_READ_REG(hw, CTRL);
354 /* Must reset the PHY before resetting the MAC */
355 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
356 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
360 /* Issue a global reset to the MAC. This will reset the chip's
361 * transmit, receive, DMA, and link units. It will not effect
362 * the current PCI configuration. The global reset bit is self-
363 * clearing, and should clear within a microsecond.
365 DEBUGOUT("Issuing a global reset to MAC\n");
367 switch(hw->mac_type) {
373 case e1000_82541_rev_2:
374 /* These controllers can't ack the 64-bit write when issuing the
375 * reset, so use IO-mapping as a workaround to issue the reset */
376 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
378 case e1000_82545_rev_3:
379 case e1000_82546_rev_3:
380 /* Reset is performed on a shadow of the control register */
381 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
384 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
388 /* After MAC reset, force reload of EEPROM to restore power-on settings to
389 * device. Later controllers reload the EEPROM automatically, so just wait
390 * for reload to complete.
392 switch(hw->mac_type) {
393 case e1000_82542_rev2_0:
394 case e1000_82542_rev2_1:
397 /* Wait for reset to complete */
399 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
400 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
401 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
402 E1000_WRITE_FLUSH(hw);
403 /* Wait for EEPROM reload */
407 case e1000_82541_rev_2:
409 case e1000_82547_rev_2:
410 /* Wait for EEPROM reload */
414 /* Wait for EEPROM reload (it happens automatically) */
419 /* Disable HW ARPs on ASF enabled adapters */
420 if(hw->mac_type >= e1000_82540) {
421 manc = E1000_READ_REG(hw, MANC);
422 manc &= ~(E1000_MANC_ARP_EN);
423 E1000_WRITE_REG(hw, MANC, manc);
426 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
427 e1000_phy_init_script(hw);
429 /* Configure activity LED after PHY reset */
430 led_ctrl = E1000_READ_REG(hw, LEDCTL);
431 led_ctrl &= IGP_ACTIVITY_LED_MASK;
432 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
433 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
436 /* Clear interrupt mask to stop board from generating interrupts */
437 DEBUGOUT("Masking off all interrupts\n");
438 E1000_WRITE_REG(hw, IMC, 0xffffffff);
440 /* Clear any pending interrupt events. */
441 icr = E1000_READ_REG(hw, ICR);
443 /* If MWI was previously enabled, reenable it. */
444 if(hw->mac_type == e1000_82542_rev2_0) {
445 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
446 e1000_pci_set_mwi(hw);
449 return E1000_SUCCESS;
452 /******************************************************************************
453 * Performs basic configuration of the adapter.
455 * hw - Struct containing variables accessed by shared code
457 * Assumes that the controller has previously been reset and is in a
458 * post-reset uninitialized state. Initializes the receive address registers,
459 * multicast table, and VLAN filter table. Calls routines to setup link
460 * configuration and flow control settings. Clears all on-chip counters. Leaves
461 * the transmit and receive units disabled and uninitialized.
462 *****************************************************************************/
464 e1000_init_hw(struct e1000_hw *hw)
469 uint16_t pcix_cmd_word;
470 uint16_t pcix_stat_hi_word;
473 DEBUGFUNC("e1000_init_hw");
475 /* Initialize Identification LED */
476 ret_val = e1000_id_led_init(hw);
478 DEBUGOUT("Error Initializing Identification LED\n");
482 /* Set the media type and TBI compatibility */
483 e1000_set_media_type(hw);
485 /* Disabling VLAN filtering. */
486 DEBUGOUT("Initializing the IEEE VLAN\n");
487 E1000_WRITE_REG(hw, VET, 0);
489 e1000_clear_vfta(hw);
491 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
492 if(hw->mac_type == e1000_82542_rev2_0) {
493 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
494 e1000_pci_clear_mwi(hw);
495 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
496 E1000_WRITE_FLUSH(hw);
500 /* Setup the receive address. This involves initializing all of the Receive
501 * Address Registers (RARs 0 - 15).
503 e1000_init_rx_addrs(hw);
505 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
506 if(hw->mac_type == e1000_82542_rev2_0) {
507 E1000_WRITE_REG(hw, RCTL, 0);
508 E1000_WRITE_FLUSH(hw);
510 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
511 e1000_pci_set_mwi(hw);
514 /* Zero out the Multicast HASH table */
515 DEBUGOUT("Zeroing the MTA\n");
516 for(i = 0; i < E1000_MC_TBL_SIZE; i++)
517 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
519 /* Set the PCI priority bit correctly in the CTRL register. This
520 * determines if the adapter gives priority to receives, or if it
521 * gives equal priority to transmits and receives.
523 if(hw->dma_fairness) {
524 ctrl = E1000_READ_REG(hw, CTRL);
525 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
528 switch(hw->mac_type) {
529 case e1000_82545_rev_3:
530 case e1000_82546_rev_3:
533 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
534 if(hw->bus_type == e1000_bus_type_pcix) {
535 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
536 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
538 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
539 PCIX_COMMAND_MMRBC_SHIFT;
540 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
541 PCIX_STATUS_HI_MMRBC_SHIFT;
542 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
543 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
544 if(cmd_mmrbc > stat_mmrbc) {
545 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
546 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
547 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
554 /* Call a subroutine to configure the link and setup flow control. */
555 ret_val = e1000_setup_link(hw);
557 /* Set the transmit descriptor write-back policy */
558 if(hw->mac_type > e1000_82544) {
559 ctrl = E1000_READ_REG(hw, TXDCTL);
560 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
561 E1000_WRITE_REG(hw, TXDCTL, ctrl);
564 /* Clear all of the statistics registers (clear on read). It is
565 * important that we do this after we have tried to establish link
566 * because the symbol error count will increment wildly if there
569 e1000_clear_hw_cntrs(hw);
574 /******************************************************************************
575 * Adjust SERDES output amplitude based on EEPROM setting.
577 * hw - Struct containing variables accessed by shared code.
578 *****************************************************************************/
580 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
582 uint16_t eeprom_data;
585 DEBUGFUNC("e1000_adjust_serdes_amplitude");
587 if(hw->media_type != e1000_media_type_internal_serdes)
588 return E1000_SUCCESS;
590 switch(hw->mac_type) {
591 case e1000_82545_rev_3:
592 case e1000_82546_rev_3:
595 return E1000_SUCCESS;
598 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
603 if(eeprom_data != EEPROM_RESERVED_WORD) {
604 /* Adjust SERDES output amplitude only. */
605 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
606 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
611 return E1000_SUCCESS;
614 /******************************************************************************
615 * Configures flow control and link settings.
617 * hw - Struct containing variables accessed by shared code
619 * Determines which flow control settings to use. Calls the apropriate media-
620 * specific link configuration function. Configures the flow control settings.
621 * Assuming the adapter has a valid link partner, a valid link should be
622 * established. Assumes the hardware has previously been reset and the
623 * transmitter and receiver are not enabled.
624 *****************************************************************************/
626 e1000_setup_link(struct e1000_hw *hw)
630 uint16_t eeprom_data;
632 DEBUGFUNC("e1000_setup_link");
634 /* Read and store word 0x0F of the EEPROM. This word contains bits
635 * that determine the hardware's default PAUSE (flow control) mode,
636 * a bit that determines whether the HW defaults to enabling or
637 * disabling auto-negotiation, and the direction of the
638 * SW defined pins. If there is no SW over-ride of the flow
639 * control setting, then the variable hw->fc will
640 * be initialized based on a value in the EEPROM.
642 if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
643 DEBUGOUT("EEPROM Read Error\n");
644 return -E1000_ERR_EEPROM;
647 if(hw->fc == e1000_fc_default) {
648 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
649 hw->fc = e1000_fc_none;
650 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
651 EEPROM_WORD0F_ASM_DIR)
652 hw->fc = e1000_fc_tx_pause;
654 hw->fc = e1000_fc_full;
657 /* We want to save off the original Flow Control configuration just
658 * in case we get disconnected and then reconnected into a different
659 * hub or switch with different Flow Control capabilities.
661 if(hw->mac_type == e1000_82542_rev2_0)
662 hw->fc &= (~e1000_fc_tx_pause);
664 if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
665 hw->fc &= (~e1000_fc_rx_pause);
667 hw->original_fc = hw->fc;
669 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
671 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
672 * polarity value for the SW controlled pins, and setup the
673 * Extended Device Control reg with that info.
674 * This is needed because one of the SW controlled pins is used for
675 * signal detection. So this should be done before e1000_setup_pcs_link()
676 * or e1000_phy_setup() is called.
678 if(hw->mac_type == e1000_82543) {
679 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
681 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
684 /* Call the necessary subroutine to configure the link. */
685 ret_val = (hw->media_type == e1000_media_type_copper) ?
686 e1000_setup_copper_link(hw) :
687 e1000_setup_fiber_serdes_link(hw);
689 /* Initialize the flow control address, type, and PAUSE timer
690 * registers to their default values. This is done even if flow
691 * control is disabled, because it does not hurt anything to
692 * initialize these registers.
694 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
696 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
697 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
698 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
699 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
701 /* Set the flow control receive threshold registers. Normally,
702 * these registers will be set to a default threshold that may be
703 * adjusted later by the driver's runtime code. However, if the
704 * ability to transmit pause frames in not enabled, then these
705 * registers will be set to 0.
707 if(!(hw->fc & e1000_fc_tx_pause)) {
708 E1000_WRITE_REG(hw, FCRTL, 0);
709 E1000_WRITE_REG(hw, FCRTH, 0);
711 /* We need to set up the Receive Threshold high and low water marks
712 * as well as (optionally) enabling the transmission of XON frames.
714 if(hw->fc_send_xon) {
715 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
716 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
718 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
719 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
725 /******************************************************************************
726 * Sets up link for a fiber based or serdes based adapter
728 * hw - Struct containing variables accessed by shared code
730 * Manipulates Physical Coding Sublayer functions in order to configure
731 * link. Assumes the hardware has been previously reset and the transmitter
732 * and receiver are not enabled.
733 *****************************************************************************/
735 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
744 DEBUGFUNC("e1000_setup_fiber_serdes_link");
746 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
747 * set when the optics detect a signal. On older adapters, it will be
748 * cleared when there is a signal. This applies to fiber media only.
749 * If we're on serdes media, adjust the output amplitude to value set in
752 ctrl = E1000_READ_REG(hw, CTRL);
753 if(hw->media_type == e1000_media_type_fiber)
754 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
756 ret_val = e1000_adjust_serdes_amplitude(hw);
760 /* Take the link out of reset */
761 ctrl &= ~(E1000_CTRL_LRST);
763 /* Adjust VCO speed to improve BER performance */
764 ret_val = e1000_set_vco_speed(hw);
768 e1000_config_collision_dist(hw);
770 /* Check for a software override of the flow control settings, and setup
771 * the device accordingly. If auto-negotiation is enabled, then software
772 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
773 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
774 * auto-negotiation is disabled, then software will have to manually
775 * configure the two flow control enable bits in the CTRL register.
777 * The possible values of the "fc" parameter are:
778 * 0: Flow control is completely disabled
779 * 1: Rx flow control is enabled (we can receive pause frames, but
780 * not send pause frames).
781 * 2: Tx flow control is enabled (we can send pause frames but we do
782 * not support receiving pause frames).
783 * 3: Both Rx and TX flow control (symmetric) are enabled.
787 /* Flow control is completely disabled by a software over-ride. */
788 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
790 case e1000_fc_rx_pause:
791 /* RX Flow control is enabled and TX Flow control is disabled by a
792 * software over-ride. Since there really isn't a way to advertise
793 * that we are capable of RX Pause ONLY, we will advertise that we
794 * support both symmetric and asymmetric RX PAUSE. Later, we will
795 * disable the adapter's ability to send PAUSE frames.
797 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
799 case e1000_fc_tx_pause:
800 /* TX Flow control is enabled, and RX Flow control is disabled, by a
801 * software over-ride.
803 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
806 /* Flow control (both RX and TX) is enabled by a software over-ride. */
807 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
810 DEBUGOUT("Flow control param set incorrectly\n");
811 return -E1000_ERR_CONFIG;
815 /* Since auto-negotiation is enabled, take the link out of reset (the link
816 * will be in reset, because we previously reset the chip). This will
817 * restart auto-negotiation. If auto-neogtiation is successful then the
818 * link-up status bit will be set and the flow control enable bits (RFCE
819 * and TFCE) will be set according to their negotiated value.
821 DEBUGOUT("Auto-negotiation enabled\n");
823 E1000_WRITE_REG(hw, TXCW, txcw);
824 E1000_WRITE_REG(hw, CTRL, ctrl);
825 E1000_WRITE_FLUSH(hw);
830 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
831 * indication in the Device Status Register. Time-out if a link isn't
832 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
833 * less than 500 milliseconds even if the other end is doing it in SW).
834 * For internal serdes, we just assume a signal is present, then poll.
836 if(hw->media_type == e1000_media_type_internal_serdes ||
837 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
838 DEBUGOUT("Looking for Link\n");
839 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
841 status = E1000_READ_REG(hw, STATUS);
842 if(status & E1000_STATUS_LU) break;
844 if(i == (LINK_UP_TIMEOUT / 10)) {
845 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
846 hw->autoneg_failed = 1;
847 /* AutoNeg failed to achieve a link, so we'll call
848 * e1000_check_for_link. This routine will force the link up if
849 * we detect a signal. This will allow us to communicate with
850 * non-autonegotiating link partners.
852 ret_val = e1000_check_for_link(hw);
854 DEBUGOUT("Error while checking for link\n");
857 hw->autoneg_failed = 0;
859 hw->autoneg_failed = 0;
860 DEBUGOUT("Valid Link Found\n");
863 DEBUGOUT("No Signal Detected\n");
865 return E1000_SUCCESS;
868 /******************************************************************************
869 * Detects which PHY is present and the speed and duplex
871 * hw - Struct containing variables accessed by shared code
872 ******************************************************************************/
874 e1000_setup_copper_link(struct e1000_hw *hw)
882 DEBUGFUNC("e1000_setup_copper_link");
884 ctrl = E1000_READ_REG(hw, CTRL);
885 /* With 82543, we need to force speed and duplex on the MAC equal to what
886 * the PHY speed and duplex configuration is. In addition, we need to
887 * perform a hardware reset on the PHY to take it out of reset.
889 if(hw->mac_type > e1000_82543) {
890 ctrl |= E1000_CTRL_SLU;
891 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
892 E1000_WRITE_REG(hw, CTRL, ctrl);
894 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
895 E1000_WRITE_REG(hw, CTRL, ctrl);
896 e1000_phy_hw_reset(hw);
899 /* Make sure we have a valid PHY */
900 ret_val = e1000_detect_gig_phy(hw);
902 DEBUGOUT("Error, did not detect valid phy.\n");
905 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
907 /* Set PHY to class A mode (if necessary) */
908 ret_val = e1000_set_phy_mode(hw);
912 if(hw->mac_type == e1000_82545_rev_3) {
913 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
914 phy_data |= 0x00000008;
915 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
918 if(hw->mac_type <= e1000_82543 ||
919 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
920 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
921 hw->phy_reset_disable = FALSE;
923 if(!hw->phy_reset_disable) {
924 if (hw->phy_type == e1000_phy_igp) {
926 ret_val = e1000_phy_reset(hw);
928 DEBUGOUT("Error Resetting the PHY\n");
932 /* Wait 10ms for MAC to configure PHY from eeprom settings */
935 /* Configure activity LED after PHY reset */
936 led_ctrl = E1000_READ_REG(hw, LEDCTL);
937 led_ctrl &= IGP_ACTIVITY_LED_MASK;
938 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
939 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
941 /* disable lplu d3 during driver init */
942 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
944 DEBUGOUT("Error Disabling LPLU D3\n");
948 /* Configure mdi-mdix settings */
949 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
954 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
955 hw->dsp_config_state = e1000_dsp_config_disabled;
956 /* Force MDI for IGP B-0 PHY */
957 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
958 IGP01E1000_PSCR_FORCE_MDI_MDIX);
962 hw->dsp_config_state = e1000_dsp_config_enabled;
963 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
967 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
970 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
974 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
978 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
983 /* set auto-master slave resolution settings */
985 e1000_ms_type phy_ms_setting = hw->master_slave;
987 if(hw->ffe_config_state == e1000_ffe_config_active)
988 hw->ffe_config_state = e1000_ffe_config_enabled;
990 if(hw->dsp_config_state == e1000_dsp_config_activated)
991 hw->dsp_config_state = e1000_dsp_config_enabled;
993 /* when autonegotiation advertisment is only 1000Mbps then we
994 * should disable SmartSpeed and enable Auto MasterSlave
995 * resolution as hardware default. */
996 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
997 /* Disable SmartSpeed */
998 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1002 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1003 ret_val = e1000_write_phy_reg(hw,
1004 IGP01E1000_PHY_PORT_CONFIG,
1008 /* Set auto Master/Slave resolution process */
1009 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1012 phy_data &= ~CR_1000T_MS_ENABLE;
1013 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1018 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1022 /* load defaults for future use */
1023 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1024 ((phy_data & CR_1000T_MS_VALUE) ?
1025 e1000_ms_force_master :
1026 e1000_ms_force_slave) :
1029 switch (phy_ms_setting) {
1030 case e1000_ms_force_master:
1031 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1033 case e1000_ms_force_slave:
1034 phy_data |= CR_1000T_MS_ENABLE;
1035 phy_data &= ~(CR_1000T_MS_VALUE);
1038 phy_data &= ~CR_1000T_MS_ENABLE;
1042 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1047 /* Enable CRS on TX. This must be set for half-duplex operation. */
1048 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1053 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1056 * MDI/MDI-X = 0 (default)
1057 * 0 - Auto for all speeds
1060 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1062 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1066 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1069 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1072 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1076 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1081 * disable_polarity_correction = 0 (default)
1082 * Automatic Correction for Reversed Cable Polarity
1086 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1087 if(hw->disable_polarity_correction == 1)
1088 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1089 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1094 /* Force TX_CLK in the Extended PHY Specific Control Register
1097 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1102 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1104 if (hw->phy_revision < M88E1011_I_REV_4) {
1105 /* Configure Master and Slave downshift values */
1106 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1107 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1108 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1109 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1110 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1116 /* SW Reset the PHY so all changes take effect */
1117 ret_val = e1000_phy_reset(hw);
1119 DEBUGOUT("Error Resetting the PHY\n");
1125 * autoneg = 1 (default)
1126 * PHY will advertise value(s) parsed from
1127 * autoneg_advertised and fc
1129 * PHY will be set to 10H, 10F, 100H, or 100F
1130 * depending on value parsed from forced_speed_duplex.
1133 /* Is autoneg enabled? This is enabled by default or by software
1134 * override. If so, call e1000_phy_setup_autoneg routine to parse the
1135 * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1136 * the user should have provided a speed/duplex override. If so, then
1137 * call e1000_phy_force_speed_duplex to parse and set this up.
1140 /* Perform some bounds checking on the hw->autoneg_advertised
1141 * parameter. If this variable is zero, then set it to the default.
1143 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1145 /* If autoneg_advertised is zero, we assume it was not defaulted
1146 * by the calling code so we set to advertise full capability.
1148 if(hw->autoneg_advertised == 0)
1149 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1151 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1152 ret_val = e1000_phy_setup_autoneg(hw);
1154 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1157 DEBUGOUT("Restarting Auto-Neg\n");
1159 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1160 * the Auto Neg Restart bit in the PHY control register.
1162 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1166 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1167 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1171 /* Does the user want to wait for Auto-Neg to complete here, or
1172 * check at a later time (for example, callback routine).
1174 if(hw->wait_autoneg_complete) {
1175 ret_val = e1000_wait_autoneg(hw);
1177 DEBUGOUT("Error while waiting for autoneg to complete\n");
1181 hw->get_link_status = TRUE;
1183 DEBUGOUT("Forcing speed and duplex\n");
1184 ret_val = e1000_phy_force_speed_duplex(hw);
1186 DEBUGOUT("Error Forcing Speed and Duplex\n");
1190 } /* !hw->phy_reset_disable */
1192 /* Check link status. Wait up to 100 microseconds for link to become
1195 for(i = 0; i < 10; i++) {
1196 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1199 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1203 if(phy_data & MII_SR_LINK_STATUS) {
1204 /* We have link, so we need to finish the config process:
1205 * 1) Set up the MAC to the current PHY speed/duplex
1206 * if we are on 82543. If we
1207 * are on newer silicon, we only need to configure
1208 * collision distance in the Transmit Control Register.
1209 * 2) Set up flow control on the MAC to that established with
1212 if(hw->mac_type >= e1000_82544) {
1213 e1000_config_collision_dist(hw);
1215 ret_val = e1000_config_mac_to_phy(hw);
1217 DEBUGOUT("Error configuring MAC to PHY settings\n");
1221 ret_val = e1000_config_fc_after_link_up(hw);
1223 DEBUGOUT("Error Configuring Flow Control\n");
1226 DEBUGOUT("Valid link established!!!\n");
1228 if(hw->phy_type == e1000_phy_igp) {
1229 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1231 DEBUGOUT("Error Configuring DSP after link up\n");
1235 DEBUGOUT("Valid link established!!!\n");
1236 return E1000_SUCCESS;
1241 DEBUGOUT("Unable to establish link!!!\n");
1242 return E1000_SUCCESS;
1245 /******************************************************************************
1246 * Configures PHY autoneg and flow control advertisement settings
1248 * hw - Struct containing variables accessed by shared code
1249 ******************************************************************************/
1251 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1254 uint16_t mii_autoneg_adv_reg;
1255 uint16_t mii_1000t_ctrl_reg;
1257 DEBUGFUNC("e1000_phy_setup_autoneg");
1259 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1260 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1264 /* Read the MII 1000Base-T Control Register (Address 9). */
1265 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1269 /* Need to parse both autoneg_advertised and fc and set up
1270 * the appropriate PHY registers. First we will parse for
1271 * autoneg_advertised software override. Since we can advertise
1272 * a plethora of combinations, we need to check each bit
1276 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1277 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1278 * the 1000Base-T Control Register (Address 9).
1280 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1281 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1283 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1285 /* Do we want to advertise 10 Mb Half Duplex? */
1286 if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1287 DEBUGOUT("Advertise 10mb Half duplex\n");
1288 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1291 /* Do we want to advertise 10 Mb Full Duplex? */
1292 if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1293 DEBUGOUT("Advertise 10mb Full duplex\n");
1294 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1297 /* Do we want to advertise 100 Mb Half Duplex? */
1298 if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1299 DEBUGOUT("Advertise 100mb Half duplex\n");
1300 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1303 /* Do we want to advertise 100 Mb Full Duplex? */
1304 if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1305 DEBUGOUT("Advertise 100mb Full duplex\n");
1306 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1309 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1310 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1311 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1314 /* Do we want to advertise 1000 Mb Full Duplex? */
1315 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1316 DEBUGOUT("Advertise 1000mb Full duplex\n");
1317 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1320 /* Check for a software override of the flow control settings, and
1321 * setup the PHY advertisement registers accordingly. If
1322 * auto-negotiation is enabled, then software will have to set the
1323 * "PAUSE" bits to the correct value in the Auto-Negotiation
1324 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1326 * The possible values of the "fc" parameter are:
1327 * 0: Flow control is completely disabled
1328 * 1: Rx flow control is enabled (we can receive pause frames
1329 * but not send pause frames).
1330 * 2: Tx flow control is enabled (we can send pause frames
1331 * but we do not support receiving pause frames).
1332 * 3: Both Rx and TX flow control (symmetric) are enabled.
1333 * other: No software override. The flow control configuration
1334 * in the EEPROM is used.
1337 case e1000_fc_none: /* 0 */
1338 /* Flow control (RX & TX) is completely disabled by a
1339 * software over-ride.
1341 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1343 case e1000_fc_rx_pause: /* 1 */
1344 /* RX Flow control is enabled, and TX Flow control is
1345 * disabled, by a software over-ride.
1347 /* Since there really isn't a way to advertise that we are
1348 * capable of RX Pause ONLY, we will advertise that we
1349 * support both symmetric and asymmetric RX PAUSE. Later
1350 * (in e1000_config_fc_after_link_up) we will disable the
1351 *hw's ability to send PAUSE frames.
1353 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1355 case e1000_fc_tx_pause: /* 2 */
1356 /* TX Flow control is enabled, and RX Flow control is
1357 * disabled, by a software over-ride.
1359 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1360 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1362 case e1000_fc_full: /* 3 */
1363 /* Flow control (both RX and TX) is enabled by a software
1366 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1369 DEBUGOUT("Flow control param set incorrectly\n");
1370 return -E1000_ERR_CONFIG;
1373 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1377 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1379 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1383 return E1000_SUCCESS;
1386 /******************************************************************************
1387 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1389 * hw - Struct containing variables accessed by shared code
1390 ******************************************************************************/
1392 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1396 uint16_t mii_ctrl_reg;
1397 uint16_t mii_status_reg;
1401 DEBUGFUNC("e1000_phy_force_speed_duplex");
1403 /* Turn off Flow control if we are forcing speed and duplex. */
1404 hw->fc = e1000_fc_none;
1406 DEBUGOUT1("hw->fc = %d\n", hw->fc);
1408 /* Read the Device Control Register. */
1409 ctrl = E1000_READ_REG(hw, CTRL);
1411 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1412 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1413 ctrl &= ~(DEVICE_SPEED_MASK);
1415 /* Clear the Auto Speed Detect Enable bit. */
1416 ctrl &= ~E1000_CTRL_ASDE;
1418 /* Read the MII Control Register. */
1419 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1423 /* We need to disable autoneg in order to force link and duplex. */
1425 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1427 /* Are we forcing Full or Half Duplex? */
1428 if(hw->forced_speed_duplex == e1000_100_full ||
1429 hw->forced_speed_duplex == e1000_10_full) {
1430 /* We want to force full duplex so we SET the full duplex bits in the
1431 * Device and MII Control Registers.
1433 ctrl |= E1000_CTRL_FD;
1434 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1435 DEBUGOUT("Full Duplex\n");
1437 /* We want to force half duplex so we CLEAR the full duplex bits in
1438 * the Device and MII Control Registers.
1440 ctrl &= ~E1000_CTRL_FD;
1441 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1442 DEBUGOUT("Half Duplex\n");
1445 /* Are we forcing 100Mbps??? */
1446 if(hw->forced_speed_duplex == e1000_100_full ||
1447 hw->forced_speed_duplex == e1000_100_half) {
1448 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1449 ctrl |= E1000_CTRL_SPD_100;
1450 mii_ctrl_reg |= MII_CR_SPEED_100;
1451 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1452 DEBUGOUT("Forcing 100mb ");
1454 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1455 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1456 mii_ctrl_reg |= MII_CR_SPEED_10;
1457 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1458 DEBUGOUT("Forcing 10mb ");
1461 e1000_config_collision_dist(hw);
1463 /* Write the configured values back to the Device Control Reg. */
1464 E1000_WRITE_REG(hw, CTRL, ctrl);
1466 if (hw->phy_type == e1000_phy_m88) {
1467 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1471 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1472 * forced whenever speed are duplex are forced.
1474 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1475 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1479 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
1481 /* Need to reset the PHY or these changes will be ignored */
1482 mii_ctrl_reg |= MII_CR_RESET;
1484 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1485 * forced whenever speed or duplex are forced.
1487 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1491 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1492 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1494 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1499 /* Write back the modified PHY MII control register. */
1500 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1506 /* The wait_autoneg_complete flag may be a little misleading here.
1507 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1508 * But we do want to delay for a period while forcing only so we
1509 * don't generate false No Link messages. So we will wait here
1510 * only if the user has set wait_autoneg_complete to 1, which is
1513 if(hw->wait_autoneg_complete) {
1514 /* We will wait for autoneg to complete. */
1515 DEBUGOUT("Waiting for forced speed/duplex link.\n");
1518 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1519 for(i = PHY_FORCE_TIME; i > 0; i--) {
1520 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1523 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1527 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1531 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1534 if((i == 0) && (hw->phy_type == e1000_phy_m88)) {
1535 /* We didn't get link. Reset the DSP and wait again for link. */
1536 ret_val = e1000_phy_reset_dsp(hw);
1538 DEBUGOUT("Error Resetting PHY DSP\n");
1542 /* This loop will early-out if the link condition has been met. */
1543 for(i = PHY_FORCE_TIME; i > 0; i--) {
1544 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1546 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1549 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1553 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1559 if (hw->phy_type == e1000_phy_m88) {
1560 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1561 * Extended PHY Specific Control Register to 25MHz clock. This value
1562 * defaults back to a 2.5MHz clock when the PHY is reset.
1564 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1568 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1569 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1573 /* In addition, because of the s/w reset above, we need to enable CRS on
1574 * TX. This must be set for both full and half duplex operation.
1576 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1580 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1581 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1585 return E1000_SUCCESS;
1588 /******************************************************************************
1589 * Sets the collision distance in the Transmit Control register
1591 * hw - Struct containing variables accessed by shared code
1593 * Link should have been established previously. Reads the speed and duplex
1594 * information from the Device Status register.
1595 ******************************************************************************/
1597 e1000_config_collision_dist(struct e1000_hw *hw)
1601 DEBUGFUNC("e1000_config_collision_dist");
1603 tctl = E1000_READ_REG(hw, TCTL);
1605 tctl &= ~E1000_TCTL_COLD;
1606 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1608 E1000_WRITE_REG(hw, TCTL, tctl);
1609 E1000_WRITE_FLUSH(hw);
1612 /******************************************************************************
1613 * Sets MAC speed and duplex settings to reflect the those in the PHY
1615 * hw - Struct containing variables accessed by shared code
1616 * mii_reg - data to write to the MII control register
1618 * The contents of the PHY register containing the needed information need to
1620 ******************************************************************************/
1622 e1000_config_mac_to_phy(struct e1000_hw *hw)
1628 DEBUGFUNC("e1000_config_mac_to_phy");
1630 /* Read the Device Control Register and set the bits to Force Speed
1633 ctrl = E1000_READ_REG(hw, CTRL);
1634 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1635 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1637 /* Set up duplex in the Device Control and Transmit Control
1638 * registers depending on negotiated values.
1640 if (hw->phy_type == e1000_phy_igp) {
1641 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
1646 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
1647 else ctrl &= ~E1000_CTRL_FD;
1649 e1000_config_collision_dist(hw);
1651 /* Set up speed in the Device Control register depending on
1652 * negotiated values.
1654 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1655 IGP01E1000_PSSR_SPEED_1000MBPS)
1656 ctrl |= E1000_CTRL_SPD_1000;
1657 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1658 IGP01E1000_PSSR_SPEED_100MBPS)
1659 ctrl |= E1000_CTRL_SPD_100;
1661 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1666 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
1667 else ctrl &= ~E1000_CTRL_FD;
1669 e1000_config_collision_dist(hw);
1671 /* Set up speed in the Device Control register depending on
1672 * negotiated values.
1674 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1675 ctrl |= E1000_CTRL_SPD_1000;
1676 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1677 ctrl |= E1000_CTRL_SPD_100;
1679 /* Write the configured values back to the Device Control Reg. */
1680 E1000_WRITE_REG(hw, CTRL, ctrl);
1681 return E1000_SUCCESS;
1684 /******************************************************************************
1685 * Forces the MAC's flow control settings.
1687 * hw - Struct containing variables accessed by shared code
1689 * Sets the TFCE and RFCE bits in the device control register to reflect
1690 * the adapter settings. TFCE and RFCE need to be explicitly set by
1691 * software when a Copper PHY is used because autonegotiation is managed
1692 * by the PHY rather than the MAC. Software must also configure these
1693 * bits when link is forced on a fiber connection.
1694 *****************************************************************************/
1696 e1000_force_mac_fc(struct e1000_hw *hw)
1700 DEBUGFUNC("e1000_force_mac_fc");
1702 /* Get the current configuration of the Device Control Register */
1703 ctrl = E1000_READ_REG(hw, CTRL);
1705 /* Because we didn't get link via the internal auto-negotiation
1706 * mechanism (we either forced link or we got link via PHY
1707 * auto-neg), we have to manually enable/disable transmit an
1708 * receive flow control.
1710 * The "Case" statement below enables/disable flow control
1711 * according to the "hw->fc" parameter.
1713 * The possible values of the "fc" parameter are:
1714 * 0: Flow control is completely disabled
1715 * 1: Rx flow control is enabled (we can receive pause
1716 * frames but not send pause frames).
1717 * 2: Tx flow control is enabled (we can send pause frames
1718 * frames but we do not receive pause frames).
1719 * 3: Both Rx and TX flow control (symmetric) is enabled.
1720 * other: No other values should be possible at this point.
1725 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1727 case e1000_fc_rx_pause:
1728 ctrl &= (~E1000_CTRL_TFCE);
1729 ctrl |= E1000_CTRL_RFCE;
1731 case e1000_fc_tx_pause:
1732 ctrl &= (~E1000_CTRL_RFCE);
1733 ctrl |= E1000_CTRL_TFCE;
1736 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1739 DEBUGOUT("Flow control param set incorrectly\n");
1740 return -E1000_ERR_CONFIG;
1743 /* Disable TX Flow Control for 82542 (rev 2.0) */
1744 if(hw->mac_type == e1000_82542_rev2_0)
1745 ctrl &= (~E1000_CTRL_TFCE);
1747 E1000_WRITE_REG(hw, CTRL, ctrl);
1748 return E1000_SUCCESS;
1751 /******************************************************************************
1752 * Configures flow control settings after link is established
1754 * hw - Struct containing variables accessed by shared code
1756 * Should be called immediately after a valid link has been established.
1757 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1758 * and autonegotiation is enabled, the MAC flow control settings will be set
1759 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1760 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
1761 *****************************************************************************/
1763 e1000_config_fc_after_link_up(struct e1000_hw *hw)
1766 uint16_t mii_status_reg;
1767 uint16_t mii_nway_adv_reg;
1768 uint16_t mii_nway_lp_ability_reg;
1772 DEBUGFUNC("e1000_config_fc_after_link_up");
1774 /* Check for the case where we have fiber media and auto-neg failed
1775 * so we had to force link. In this case, we need to force the
1776 * configuration of the MAC to match the "fc" parameter.
1778 if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
1779 ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) ||
1780 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
1781 ret_val = e1000_force_mac_fc(hw);
1783 DEBUGOUT("Error forcing flow control settings\n");
1788 /* Check for the case where we have copper media and auto-neg is
1789 * enabled. In this case, we need to check and see if Auto-Neg
1790 * has completed, and if so, how the PHY and link partner has
1791 * flow control configured.
1793 if((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
1794 /* Read the MII Status Register and check to see if AutoNeg
1795 * has completed. We read this twice because this reg has
1796 * some "sticky" (latched) bits.
1798 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1801 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1805 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1806 /* The AutoNeg process has completed, so we now need to
1807 * read both the Auto Negotiation Advertisement Register
1808 * (Address 4) and the Auto_Negotiation Base Page Ability
1809 * Register (Address 5) to determine how flow control was
1812 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1816 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
1817 &mii_nway_lp_ability_reg);
1821 /* Two bits in the Auto Negotiation Advertisement Register
1822 * (Address 4) and two bits in the Auto Negotiation Base
1823 * Page Ability Register (Address 5) determine flow control
1824 * for both the PHY and the link partner. The following
1825 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1826 * 1999, describes these PAUSE resolution bits and how flow
1827 * control is determined based upon these settings.
1828 * NOTE: DC = Don't Care
1830 * LOCAL DEVICE | LINK PARTNER
1831 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1832 *-------|---------|-------|---------|--------------------
1833 * 0 | 0 | DC | DC | e1000_fc_none
1834 * 0 | 1 | 0 | DC | e1000_fc_none
1835 * 0 | 1 | 1 | 0 | e1000_fc_none
1836 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1837 * 1 | 0 | 0 | DC | e1000_fc_none
1838 * 1 | DC | 1 | DC | e1000_fc_full
1839 * 1 | 1 | 0 | 0 | e1000_fc_none
1840 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1843 /* Are both PAUSE bits set to 1? If so, this implies
1844 * Symmetric Flow Control is enabled at both ends. The
1845 * ASM_DIR bits are irrelevant per the spec.
1847 * For Symmetric Flow Control:
1849 * LOCAL DEVICE | LINK PARTNER
1850 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1851 *-------|---------|-------|---------|--------------------
1852 * 1 | DC | 1 | DC | e1000_fc_full
1855 if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1856 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1857 /* Now we need to check if the user selected RX ONLY
1858 * of pause frames. In this case, we had to advertise
1859 * FULL flow control because we could not advertise RX
1860 * ONLY. Hence, we must now check to see if we need to
1861 * turn OFF the TRANSMISSION of PAUSE frames.
1863 if(hw->original_fc == e1000_fc_full) {
1864 hw->fc = e1000_fc_full;
1865 DEBUGOUT("Flow Control = FULL.\r\n");
1867 hw->fc = e1000_fc_rx_pause;
1868 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1871 /* For receiving PAUSE frames ONLY.
1873 * LOCAL DEVICE | LINK PARTNER
1874 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1875 *-------|---------|-------|---------|--------------------
1876 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1879 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1880 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1881 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1882 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1883 hw->fc = e1000_fc_tx_pause;
1884 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1886 /* For transmitting PAUSE frames ONLY.
1888 * LOCAL DEVICE | LINK PARTNER
1889 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1890 *-------|---------|-------|---------|--------------------
1891 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1894 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1895 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1896 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1897 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1898 hw->fc = e1000_fc_rx_pause;
1899 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1901 /* Per the IEEE spec, at this point flow control should be
1902 * disabled. However, we want to consider that we could
1903 * be connected to a legacy switch that doesn't advertise
1904 * desired flow control, but can be forced on the link
1905 * partner. So if we advertised no flow control, that is
1906 * what we will resolve to. If we advertised some kind of
1907 * receive capability (Rx Pause Only or Full Flow Control)
1908 * and the link partner advertised none, we will configure
1909 * ourselves to enable Rx Flow Control only. We can do
1910 * this safely for two reasons: If the link partner really
1911 * didn't want flow control enabled, and we enable Rx, no
1912 * harm done since we won't be receiving any PAUSE frames
1913 * anyway. If the intent on the link partner was to have
1914 * flow control enabled, then by us enabling RX only, we
1915 * can at least receive pause frames and process them.
1916 * This is a good idea because in most cases, since we are
1917 * predominantly a server NIC, more times than not we will
1918 * be asked to delay transmission of packets than asking
1919 * our link partner to pause transmission of frames.
1921 else if((hw->original_fc == e1000_fc_none ||
1922 hw->original_fc == e1000_fc_tx_pause) ||
1923 hw->fc_strict_ieee) {
1924 hw->fc = e1000_fc_none;
1925 DEBUGOUT("Flow Control = NONE.\r\n");
1927 hw->fc = e1000_fc_rx_pause;
1928 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1931 /* Now we need to do one last check... If we auto-
1932 * negotiated to HALF DUPLEX, flow control should not be
1933 * enabled per IEEE 802.3 spec.
1935 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
1937 DEBUGOUT("Error getting link speed and duplex\n");
1941 if(duplex == HALF_DUPLEX)
1942 hw->fc = e1000_fc_none;
1944 /* Now we call a subroutine to actually force the MAC
1945 * controller to use the correct flow control settings.
1947 ret_val = e1000_force_mac_fc(hw);
1949 DEBUGOUT("Error forcing flow control settings\n");
1953 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
1956 return E1000_SUCCESS;
1959 /******************************************************************************
1960 * Checks to see if the link status of the hardware has changed.
1962 * hw - Struct containing variables accessed by shared code
1964 * Called by any function that needs to check the link status of the adapter.
1965 *****************************************************************************/
1967 e1000_check_for_link(struct e1000_hw *hw)
1973 uint32_t signal = 0;
1977 DEBUGFUNC("e1000_check_for_link");
1979 ctrl = E1000_READ_REG(hw, CTRL);
1980 status = E1000_READ_REG(hw, STATUS);
1982 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
1983 * set when the optics detect a signal. On older adapters, it will be
1984 * cleared when there is a signal. This applies to fiber media only.
1986 if((hw->media_type == e1000_media_type_fiber) ||
1987 (hw->media_type == e1000_media_type_internal_serdes)) {
1988 rxcw = E1000_READ_REG(hw, RXCW);
1990 if(hw->media_type == e1000_media_type_fiber) {
1991 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1992 if(status & E1000_STATUS_LU)
1993 hw->get_link_status = FALSE;
1997 /* If we have a copper PHY then we only want to go out to the PHY
1998 * registers to see if Auto-Neg has completed and/or if our link
1999 * status has changed. The get_link_status flag will be set if we
2000 * receive a Link Status Change interrupt or we have Rx Sequence
2003 if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2004 /* First we want to see if the MII Status Register reports
2005 * link. If so, then we want to get the current speed/duplex
2007 * Read the register twice since the link bit is sticky.
2009 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2012 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2016 if(phy_data & MII_SR_LINK_STATUS) {
2017 hw->get_link_status = FALSE;
2018 /* Check if there was DownShift, must be checked immediately after
2020 e1000_check_downshift(hw);
2023 /* No link detected */
2024 e1000_config_dsp_after_link_change(hw, FALSE);
2028 /* If we are forcing speed/duplex, then we simply return since
2029 * we have already determined whether we have link or not.
2031 if(!hw->autoneg) return -E1000_ERR_CONFIG;
2033 /* optimize the dsp settings for the igp phy */
2034 e1000_config_dsp_after_link_change(hw, TRUE);
2036 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2037 * have Si on board that is 82544 or newer, Auto
2038 * Speed Detection takes care of MAC speed/duplex
2039 * configuration. So we only need to configure Collision
2040 * Distance in the MAC. Otherwise, we need to force
2041 * speed/duplex on the MAC to the current PHY speed/duplex
2044 if(hw->mac_type >= e1000_82544)
2045 e1000_config_collision_dist(hw);
2047 ret_val = e1000_config_mac_to_phy(hw);
2049 DEBUGOUT("Error configuring MAC to PHY settings\n");
2054 /* Configure Flow Control now that Auto-Neg has completed. First, we
2055 * need to restore the desired flow control settings because we may
2056 * have had to re-autoneg with a different link partner.
2058 ret_val = e1000_config_fc_after_link_up(hw);
2060 DEBUGOUT("Error configuring flow control\n");
2064 /* At this point we know that we are on copper and we have
2065 * auto-negotiated link. These are conditions for checking the link
2066 * partner capability register. We use the link speed to determine if
2067 * TBI compatibility needs to be turned on or off. If the link is not
2068 * at gigabit speed, then TBI compatibility is not needed. If we are
2069 * at gigabit speed, we turn on TBI compatibility.
2071 if(hw->tbi_compatibility_en) {
2072 uint16_t speed, duplex;
2073 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2074 if(speed != SPEED_1000) {
2075 /* If link speed is not set to gigabit speed, we do not need
2076 * to enable TBI compatibility.
2078 if(hw->tbi_compatibility_on) {
2079 /* If we previously were in the mode, turn it off. */
2080 rctl = E1000_READ_REG(hw, RCTL);
2081 rctl &= ~E1000_RCTL_SBP;
2082 E1000_WRITE_REG(hw, RCTL, rctl);
2083 hw->tbi_compatibility_on = FALSE;
2086 /* If TBI compatibility is was previously off, turn it on. For
2087 * compatibility with a TBI link partner, we will store bad
2088 * packets. Some frames have an additional byte on the end and
2089 * will look like CRC errors to to the hardware.
2091 if(!hw->tbi_compatibility_on) {
2092 hw->tbi_compatibility_on = TRUE;
2093 rctl = E1000_READ_REG(hw, RCTL);
2094 rctl |= E1000_RCTL_SBP;
2095 E1000_WRITE_REG(hw, RCTL, rctl);
2100 /* If we don't have link (auto-negotiation failed or link partner cannot
2101 * auto-negotiate), the cable is plugged in (we have signal), and our
2102 * link partner is not trying to auto-negotiate with us (we are receiving
2103 * idles or data), we need to force link up. We also need to give
2104 * auto-negotiation time to complete, in case the cable was just plugged
2105 * in. The autoneg_failed flag does this.
2107 else if((((hw->media_type == e1000_media_type_fiber) &&
2108 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2109 (hw->media_type == e1000_media_type_internal_serdes)) &&
2110 (!(status & E1000_STATUS_LU)) &&
2111 (!(rxcw & E1000_RXCW_C))) {
2112 if(hw->autoneg_failed == 0) {
2113 hw->autoneg_failed = 1;
2116 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2118 /* Disable auto-negotiation in the TXCW register */
2119 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2121 /* Force link-up and also force full-duplex. */
2122 ctrl = E1000_READ_REG(hw, CTRL);
2123 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2124 E1000_WRITE_REG(hw, CTRL, ctrl);
2126 /* Configure Flow Control after forcing link up. */
2127 ret_val = e1000_config_fc_after_link_up(hw);
2129 DEBUGOUT("Error configuring flow control\n");
2133 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2134 * auto-negotiation in the TXCW register and disable forced link in the
2135 * Device Control register in an attempt to auto-negotiate with our link
2138 else if(((hw->media_type == e1000_media_type_fiber) ||
2139 (hw->media_type == e1000_media_type_internal_serdes)) &&
2140 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2141 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2142 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2143 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2145 hw->serdes_link_down = FALSE;
2147 /* If we force link for non-auto-negotiation switch, check link status
2148 * based on MAC synchronization for internal serdes media type.
2150 else if((hw->media_type == e1000_media_type_internal_serdes) &&
2151 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2152 /* SYNCH bit and IV bit are sticky. */
2154 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2155 if(!(rxcw & E1000_RXCW_IV)) {
2156 hw->serdes_link_down = FALSE;
2157 DEBUGOUT("SERDES: Link is up.\n");
2160 hw->serdes_link_down = TRUE;
2161 DEBUGOUT("SERDES: Link is down.\n");
2164 if((hw->media_type == e1000_media_type_internal_serdes) &&
2165 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2166 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
2168 return E1000_SUCCESS;
2171 /******************************************************************************
2172 * Detects the current speed and duplex settings of the hardware.
2174 * hw - Struct containing variables accessed by shared code
2175 * speed - Speed of the connection
2176 * duplex - Duplex setting of the connection
2177 *****************************************************************************/
2179 e1000_get_speed_and_duplex(struct e1000_hw *hw,
2187 DEBUGFUNC("e1000_get_speed_and_duplex");
2189 if(hw->mac_type >= e1000_82543) {
2190 status = E1000_READ_REG(hw, STATUS);
2191 if(status & E1000_STATUS_SPEED_1000) {
2192 *speed = SPEED_1000;
2193 DEBUGOUT("1000 Mbs, ");
2194 } else if(status & E1000_STATUS_SPEED_100) {
2196 DEBUGOUT("100 Mbs, ");
2199 DEBUGOUT("10 Mbs, ");
2202 if(status & E1000_STATUS_FD) {
2203 *duplex = FULL_DUPLEX;
2204 DEBUGOUT("Full Duplex\r\n");
2206 *duplex = HALF_DUPLEX;
2207 DEBUGOUT(" Half Duplex\r\n");
2210 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2211 *speed = SPEED_1000;
2212 *duplex = FULL_DUPLEX;
2215 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2216 * if it is operating at half duplex. Here we set the duplex settings to
2217 * match the duplex in the link partner's capabilities.
2219 if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2220 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2224 if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2225 *duplex = HALF_DUPLEX;
2227 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2230 if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2231 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2232 *duplex = HALF_DUPLEX;
2236 return E1000_SUCCESS;
2239 /******************************************************************************
2240 * Blocks until autoneg completes or times out (~4.5 seconds)
2242 * hw - Struct containing variables accessed by shared code
2243 ******************************************************************************/
2245 e1000_wait_autoneg(struct e1000_hw *hw)
2251 DEBUGFUNC("e1000_wait_autoneg");
2252 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2254 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2255 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2256 /* Read the MII Status Register and wait for Auto-Neg
2257 * Complete bit to be set.
2259 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2262 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2265 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2266 return E1000_SUCCESS;
2270 return E1000_SUCCESS;
2273 /******************************************************************************
2274 * Raises the Management Data Clock
2276 * hw - Struct containing variables accessed by shared code
2277 * ctrl - Device control register's current value
2278 ******************************************************************************/
2280 e1000_raise_mdi_clk(struct e1000_hw *hw,
2283 /* Raise the clock input to the Management Data Clock (by setting the MDC
2284 * bit), and then delay 10 microseconds.
2286 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2287 E1000_WRITE_FLUSH(hw);
2291 /******************************************************************************
2292 * Lowers the Management Data Clock
2294 * hw - Struct containing variables accessed by shared code
2295 * ctrl - Device control register's current value
2296 ******************************************************************************/
2298 e1000_lower_mdi_clk(struct e1000_hw *hw,
2301 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2302 * bit), and then delay 10 microseconds.
2304 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2305 E1000_WRITE_FLUSH(hw);
2309 /******************************************************************************
2310 * Shifts data bits out to the PHY
2312 * hw - Struct containing variables accessed by shared code
2313 * data - Data to send out to the PHY
2314 * count - Number of bits to shift out
2316 * Bits are shifted out in MSB to LSB order.
2317 ******************************************************************************/
2319 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
2326 /* We need to shift "count" number of bits out to the PHY. So, the value
2327 * in the "data" parameter will be shifted out to the PHY one bit at a
2328 * time. In order to do this, "data" must be broken down into bits.
2331 mask <<= (count - 1);
2333 ctrl = E1000_READ_REG(hw, CTRL);
2335 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2336 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2339 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2340 * then raising and lowering the Management Data Clock. A "0" is
2341 * shifted out to the PHY by setting the MDIO bit to "0" and then
2342 * raising and lowering the clock.
2344 if(data & mask) ctrl |= E1000_CTRL_MDIO;
2345 else ctrl &= ~E1000_CTRL_MDIO;
2347 E1000_WRITE_REG(hw, CTRL, ctrl);
2348 E1000_WRITE_FLUSH(hw);
2352 e1000_raise_mdi_clk(hw, &ctrl);
2353 e1000_lower_mdi_clk(hw, &ctrl);
2359 /******************************************************************************
2360 * Shifts data bits in from the PHY
2362 * hw - Struct containing variables accessed by shared code
2364 * Bits are shifted in in MSB to LSB order.
2365 ******************************************************************************/
2367 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2373 /* In order to read a register from the PHY, we need to shift in a total
2374 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2375 * to avoid contention on the MDIO pin when a read operation is performed.
2376 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2377 * by raising the input to the Management Data Clock (setting the MDC bit),
2378 * and then reading the value of the MDIO bit.
2380 ctrl = E1000_READ_REG(hw, CTRL);
2382 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2383 ctrl &= ~E1000_CTRL_MDIO_DIR;
2384 ctrl &= ~E1000_CTRL_MDIO;
2386 E1000_WRITE_REG(hw, CTRL, ctrl);
2387 E1000_WRITE_FLUSH(hw);
2389 /* Raise and Lower the clock before reading in the data. This accounts for
2390 * the turnaround bits. The first clock occurred when we clocked out the
2391 * last bit of the Register Address.
2393 e1000_raise_mdi_clk(hw, &ctrl);
2394 e1000_lower_mdi_clk(hw, &ctrl);
2396 for(data = 0, i = 0; i < 16; i++) {
2398 e1000_raise_mdi_clk(hw, &ctrl);
2399 ctrl = E1000_READ_REG(hw, CTRL);
2400 /* Check to see if we shifted in a "1". */
2401 if(ctrl & E1000_CTRL_MDIO) data |= 1;
2402 e1000_lower_mdi_clk(hw, &ctrl);
2405 e1000_raise_mdi_clk(hw, &ctrl);
2406 e1000_lower_mdi_clk(hw, &ctrl);
2411 /*****************************************************************************
2412 * Reads the value from a PHY register, if the value is on a specific non zero
2413 * page, sets the page first.
2414 * hw - Struct containing variables accessed by shared code
2415 * reg_addr - address of the PHY register to read
2416 ******************************************************************************/
2418 e1000_read_phy_reg(struct e1000_hw *hw,
2424 DEBUGFUNC("e1000_read_phy_reg");
2426 if(hw->phy_type == e1000_phy_igp &&
2427 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2428 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2429 (uint16_t)reg_addr);
2434 ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2441 e1000_read_phy_reg_ex(struct e1000_hw *hw,
2447 const uint32_t phy_addr = 1;
2449 DEBUGFUNC("e1000_read_phy_reg_ex");
2451 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2452 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2453 return -E1000_ERR_PARAM;
2456 if(hw->mac_type > e1000_82543) {
2457 /* Set up Op-code, Phy Address, and register address in the MDI
2458 * Control register. The MAC will take care of interfacing with the
2459 * PHY to retrieve the desired data.
2461 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2462 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2463 (E1000_MDIC_OP_READ));
2465 E1000_WRITE_REG(hw, MDIC, mdic);
2467 /* Poll the ready bit to see if the MDI read completed */
2468 for(i = 0; i < 64; i++) {
2470 mdic = E1000_READ_REG(hw, MDIC);
2471 if(mdic & E1000_MDIC_READY) break;
2473 if(!(mdic & E1000_MDIC_READY)) {
2474 DEBUGOUT("MDI Read did not complete\n");
2475 return -E1000_ERR_PHY;
2477 if(mdic & E1000_MDIC_ERROR) {
2478 DEBUGOUT("MDI Error\n");
2479 return -E1000_ERR_PHY;
2481 *phy_data = (uint16_t) mdic;
2483 /* We must first send a preamble through the MDIO pin to signal the
2484 * beginning of an MII instruction. This is done by sending 32
2485 * consecutive "1" bits.
2487 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2489 /* Now combine the next few fields that are required for a read
2490 * operation. We use this method instead of calling the
2491 * e1000_shift_out_mdi_bits routine five different times. The format of
2492 * a MII read instruction consists of a shift out of 14 bits and is
2493 * defined as follows:
2494 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2495 * followed by a shift in of 18 bits. This first two bits shifted in
2496 * are TurnAround bits used to avoid contention on the MDIO pin when a
2497 * READ operation is performed. These two bits are thrown away
2498 * followed by a shift in of 16 bits which contains the desired data.
2500 mdic = ((reg_addr) | (phy_addr << 5) |
2501 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2503 e1000_shift_out_mdi_bits(hw, mdic, 14);
2505 /* Now that we've shifted out the read command to the MII, we need to
2506 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2509 *phy_data = e1000_shift_in_mdi_bits(hw);
2511 return E1000_SUCCESS;
2514 /******************************************************************************
2515 * Writes a value to a PHY register
2517 * hw - Struct containing variables accessed by shared code
2518 * reg_addr - address of the PHY register to write
2519 * data - data to write to the PHY
2520 ******************************************************************************/
2522 e1000_write_phy_reg(struct e1000_hw *hw,
2528 DEBUGFUNC("e1000_write_phy_reg");
2530 if(hw->phy_type == e1000_phy_igp &&
2531 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2532 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2533 (uint16_t)reg_addr);
2538 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2545 e1000_write_phy_reg_ex(struct e1000_hw *hw,
2551 const uint32_t phy_addr = 1;
2553 DEBUGFUNC("e1000_write_phy_reg_ex");
2555 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2556 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2557 return -E1000_ERR_PARAM;
2560 if(hw->mac_type > e1000_82543) {
2561 /* Set up Op-code, Phy Address, register address, and data intended
2562 * for the PHY register in the MDI Control register. The MAC will take
2563 * care of interfacing with the PHY to send the desired data.
2565 mdic = (((uint32_t) phy_data) |
2566 (reg_addr << E1000_MDIC_REG_SHIFT) |
2567 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2568 (E1000_MDIC_OP_WRITE));
2570 E1000_WRITE_REG(hw, MDIC, mdic);
2572 /* Poll the ready bit to see if the MDI read completed */
2573 for(i = 0; i < 640; i++) {
2575 mdic = E1000_READ_REG(hw, MDIC);
2576 if(mdic & E1000_MDIC_READY) break;
2578 if(!(mdic & E1000_MDIC_READY)) {
2579 DEBUGOUT("MDI Write did not complete\n");
2580 return -E1000_ERR_PHY;
2583 /* We'll need to use the SW defined pins to shift the write command
2584 * out to the PHY. We first send a preamble to the PHY to signal the
2585 * beginning of the MII instruction. This is done by sending 32
2586 * consecutive "1" bits.
2588 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2590 /* Now combine the remaining required fields that will indicate a
2591 * write operation. We use this method instead of calling the
2592 * e1000_shift_out_mdi_bits routine for each field in the command. The
2593 * format of a MII write instruction is as follows:
2594 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2596 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2597 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2599 mdic |= (uint32_t) phy_data;
2601 e1000_shift_out_mdi_bits(hw, mdic, 32);
2604 return E1000_SUCCESS;
2607 /******************************************************************************
2608 * Returns the PHY to the power-on reset state
2610 * hw - Struct containing variables accessed by shared code
2611 ******************************************************************************/
2613 e1000_phy_hw_reset(struct e1000_hw *hw)
2615 uint32_t ctrl, ctrl_ext;
2618 DEBUGFUNC("e1000_phy_hw_reset");
2620 DEBUGOUT("Resetting Phy...\n");
2622 if(hw->mac_type > e1000_82543) {
2623 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2624 * bit. Then, take it out of reset.
2626 ctrl = E1000_READ_REG(hw, CTRL);
2627 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
2628 E1000_WRITE_FLUSH(hw);
2630 E1000_WRITE_REG(hw, CTRL, ctrl);
2631 E1000_WRITE_FLUSH(hw);
2633 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2634 * bit to put the PHY into reset. Then, take it out of reset.
2636 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2637 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2638 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2639 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2640 E1000_WRITE_FLUSH(hw);
2642 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2643 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2644 E1000_WRITE_FLUSH(hw);
2648 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2649 /* Configure activity LED after PHY reset */
2650 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2651 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2652 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2653 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2657 /******************************************************************************
2660 * hw - Struct containing variables accessed by shared code
2662 * Sets bit 15 of the MII Control regiser
2663 ******************************************************************************/
2665 e1000_phy_reset(struct e1000_hw *hw)
2670 DEBUGFUNC("e1000_phy_reset");
2672 if(hw->mac_type != e1000_82541_rev_2) {
2673 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2677 phy_data |= MII_CR_RESET;
2678 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2683 } else e1000_phy_hw_reset(hw);
2685 if(hw->phy_type == e1000_phy_igp)
2686 e1000_phy_init_script(hw);
2688 return E1000_SUCCESS;
2691 /******************************************************************************
2692 * Probes the expected PHY address for known PHY IDs
2694 * hw - Struct containing variables accessed by shared code
2695 ******************************************************************************/
2697 e1000_detect_gig_phy(struct e1000_hw *hw)
2699 int32_t phy_init_status, ret_val;
2700 uint16_t phy_id_high, phy_id_low;
2701 boolean_t match = FALSE;
2703 DEBUGFUNC("e1000_detect_gig_phy");
2705 /* Read the PHY ID Registers to identify which PHY is onboard. */
2706 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
2710 hw->phy_id = (uint32_t) (phy_id_high << 16);
2712 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
2716 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2717 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
2719 switch(hw->mac_type) {
2721 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
2724 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
2728 case e1000_82545_rev_3:
2730 case e1000_82546_rev_3:
2731 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
2734 case e1000_82541_rev_2:
2736 case e1000_82547_rev_2:
2737 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
2740 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2741 return -E1000_ERR_CONFIG;
2743 phy_init_status = e1000_set_phy_type(hw);
2745 if ((match) && (phy_init_status == E1000_SUCCESS)) {
2746 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
2747 return E1000_SUCCESS;
2749 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
2750 return -E1000_ERR_PHY;
2753 /******************************************************************************
2754 * Resets the PHY's DSP
2756 * hw - Struct containing variables accessed by shared code
2757 ******************************************************************************/
2759 e1000_phy_reset_dsp(struct e1000_hw *hw)
2762 DEBUGFUNC("e1000_phy_reset_dsp");
2765 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
2767 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
2769 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
2771 ret_val = E1000_SUCCESS;
2777 /******************************************************************************
2778 * Get PHY information from various PHY registers for igp PHY only.
2780 * hw - Struct containing variables accessed by shared code
2781 * phy_info - PHY information structure
2782 ******************************************************************************/
2784 e1000_phy_igp_get_info(struct e1000_hw *hw,
2785 struct e1000_phy_info *phy_info)
2788 uint16_t phy_data, polarity, min_length, max_length, average;
2790 DEBUGFUNC("e1000_phy_igp_get_info");
2792 /* The downshift status is checked only once, after link is established,
2793 * and it stored in the hw->speed_downgraded parameter. */
2794 phy_info->downshift = hw->speed_downgraded;
2796 /* IGP01E1000 does not need to support it. */
2797 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
2799 /* IGP01E1000 always correct polarity reversal */
2800 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
2802 /* Check polarity status */
2803 ret_val = e1000_check_polarity(hw, &polarity);
2807 phy_info->cable_polarity = polarity;
2809 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
2813 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
2814 IGP01E1000_PSSR_MDIX_SHIFT;
2816 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
2817 IGP01E1000_PSSR_SPEED_1000MBPS) {
2818 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
2819 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
2823 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2824 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2825 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2826 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2828 /* Get cable length */
2829 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
2833 /* transalte to old method */
2834 average = (max_length + min_length) / 2;
2836 if(average <= e1000_igp_cable_length_50)
2837 phy_info->cable_length = e1000_cable_length_50;
2838 else if(average <= e1000_igp_cable_length_80)
2839 phy_info->cable_length = e1000_cable_length_50_80;
2840 else if(average <= e1000_igp_cable_length_110)
2841 phy_info->cable_length = e1000_cable_length_80_110;
2842 else if(average <= e1000_igp_cable_length_140)
2843 phy_info->cable_length = e1000_cable_length_110_140;
2845 phy_info->cable_length = e1000_cable_length_140;
2848 return E1000_SUCCESS;
2851 /******************************************************************************
2852 * Get PHY information from various PHY registers fot m88 PHY only.
2854 * hw - Struct containing variables accessed by shared code
2855 * phy_info - PHY information structure
2856 ******************************************************************************/
2858 e1000_phy_m88_get_info(struct e1000_hw *hw,
2859 struct e1000_phy_info *phy_info)
2862 uint16_t phy_data, polarity;
2864 DEBUGFUNC("e1000_phy_m88_get_info");
2866 /* The downshift status is checked only once, after link is established,
2867 * and it stored in the hw->speed_downgraded parameter. */
2868 phy_info->downshift = hw->speed_downgraded;
2870 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2874 phy_info->extended_10bt_distance =
2875 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
2876 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
2877 phy_info->polarity_correction =
2878 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
2879 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
2881 /* Check polarity status */
2882 ret_val = e1000_check_polarity(hw, &polarity);
2886 phy_info->cable_polarity = polarity;
2888 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2892 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
2893 M88E1000_PSSR_MDIX_SHIFT;
2895 if(phy_data & M88E1000_PSSR_1000MBS) {
2896 /* Cable Length Estimation and Local/Remote Receiver Informatoion
2897 * are only valid at 1000 Mbps
2899 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2900 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2902 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
2906 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2907 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2909 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2910 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2913 return E1000_SUCCESS;
2916 /******************************************************************************
2917 * Get PHY information from various PHY registers
2919 * hw - Struct containing variables accessed by shared code
2920 * phy_info - PHY information structure
2921 ******************************************************************************/
2923 e1000_phy_get_info(struct e1000_hw *hw,
2924 struct e1000_phy_info *phy_info)
2929 DEBUGFUNC("e1000_phy_get_info");
2931 phy_info->cable_length = e1000_cable_length_undefined;
2932 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
2933 phy_info->cable_polarity = e1000_rev_polarity_undefined;
2934 phy_info->downshift = e1000_downshift_undefined;
2935 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
2936 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
2937 phy_info->local_rx = e1000_1000t_rx_status_undefined;
2938 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
2940 if(hw->media_type != e1000_media_type_copper) {
2941 DEBUGOUT("PHY info is only valid for copper media\n");
2942 return -E1000_ERR_CONFIG;
2945 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2949 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2953 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
2954 DEBUGOUT("PHY info is only valid if link is up\n");
2955 return -E1000_ERR_CONFIG;
2958 if(hw->phy_type == e1000_phy_igp)
2959 return e1000_phy_igp_get_info(hw, phy_info);
2961 return e1000_phy_m88_get_info(hw, phy_info);
2965 e1000_validate_mdi_setting(struct e1000_hw *hw)
2967 DEBUGFUNC("e1000_validate_mdi_settings");
2969 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
2970 DEBUGOUT("Invalid MDI setting detected\n");
2972 return -E1000_ERR_CONFIG;
2974 return E1000_SUCCESS;
2978 /******************************************************************************
2979 * Sets up eeprom variables in the hw struct. Must be called after mac_type
2982 * hw - Struct containing variables accessed by shared code
2983 *****************************************************************************/
2985 e1000_init_eeprom_params(struct e1000_hw *hw)
2987 struct e1000_eeprom_info *eeprom = &hw->eeprom;
2988 uint32_t eecd = E1000_READ_REG(hw, EECD);
2989 uint16_t eeprom_size;
2991 DEBUGFUNC("e1000_init_eeprom_params");
2993 switch (hw->mac_type) {
2994 case e1000_82542_rev2_0:
2995 case e1000_82542_rev2_1:
2998 eeprom->type = e1000_eeprom_microwire;
2999 eeprom->word_size = 64;
3000 eeprom->opcode_bits = 3;
3001 eeprom->address_bits = 6;
3002 eeprom->delay_usec = 50;
3006 case e1000_82545_rev_3:
3008 case e1000_82546_rev_3:
3009 eeprom->type = e1000_eeprom_microwire;
3010 eeprom->opcode_bits = 3;
3011 eeprom->delay_usec = 50;
3012 if(eecd & E1000_EECD_SIZE) {
3013 eeprom->word_size = 256;
3014 eeprom->address_bits = 8;
3016 eeprom->word_size = 64;
3017 eeprom->address_bits = 6;
3021 case e1000_82541_rev_2:
3023 case e1000_82547_rev_2:
3024 if (eecd & E1000_EECD_TYPE) {
3025 eeprom->type = e1000_eeprom_spi;
3026 eeprom->opcode_bits = 8;
3027 eeprom->delay_usec = 1;
3028 if (eecd & E1000_EECD_ADDR_BITS) {
3029 eeprom->page_size = 32;
3030 eeprom->address_bits = 16;
3032 eeprom->page_size = 8;
3033 eeprom->address_bits = 8;
3036 eeprom->type = e1000_eeprom_microwire;
3037 eeprom->opcode_bits = 3;
3038 eeprom->delay_usec = 50;
3039 if (eecd & E1000_EECD_ADDR_BITS) {
3040 eeprom->word_size = 256;
3041 eeprom->address_bits = 8;
3043 eeprom->word_size = 64;
3044 eeprom->address_bits = 6;
3049 eeprom->type = e1000_eeprom_spi;
3050 eeprom->opcode_bits = 8;
3051 eeprom->delay_usec = 1;
3052 if (eecd & E1000_EECD_ADDR_BITS) {
3053 eeprom->page_size = 32;
3054 eeprom->address_bits = 16;
3056 eeprom->page_size = 8;
3057 eeprom->address_bits = 8;
3062 if (eeprom->type == e1000_eeprom_spi) {
3063 eeprom->word_size = 64;
3064 if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
3065 eeprom_size &= EEPROM_SIZE_MASK;
3067 switch (eeprom_size) {
3068 case EEPROM_SIZE_16KB:
3069 eeprom->word_size = 8192;
3071 case EEPROM_SIZE_8KB:
3072 eeprom->word_size = 4096;
3074 case EEPROM_SIZE_4KB:
3075 eeprom->word_size = 2048;
3077 case EEPROM_SIZE_2KB:
3078 eeprom->word_size = 1024;
3080 case EEPROM_SIZE_1KB:
3081 eeprom->word_size = 512;
3083 case EEPROM_SIZE_512B:
3084 eeprom->word_size = 256;
3086 case EEPROM_SIZE_128B:
3088 eeprom->word_size = 64;
3095 /******************************************************************************
3096 * Raises the EEPROM's clock input.
3098 * hw - Struct containing variables accessed by shared code
3099 * eecd - EECD's current value
3100 *****************************************************************************/
3102 e1000_raise_ee_clk(struct e1000_hw *hw,
3105 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3106 * wait <delay> microseconds.
3108 *eecd = *eecd | E1000_EECD_SK;
3109 E1000_WRITE_REG(hw, EECD, *eecd);
3110 E1000_WRITE_FLUSH(hw);
3111 udelay(hw->eeprom.delay_usec);
3114 /******************************************************************************
3115 * Lowers the EEPROM's clock input.
3117 * hw - Struct containing variables accessed by shared code
3118 * eecd - EECD's current value
3119 *****************************************************************************/
3121 e1000_lower_ee_clk(struct e1000_hw *hw,
3124 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3125 * wait 50 microseconds.
3127 *eecd = *eecd & ~E1000_EECD_SK;
3128 E1000_WRITE_REG(hw, EECD, *eecd);
3129 E1000_WRITE_FLUSH(hw);
3130 udelay(hw->eeprom.delay_usec);
3133 /******************************************************************************
3134 * Shift data bits out to the EEPROM.
3136 * hw - Struct containing variables accessed by shared code
3137 * data - data to send to the EEPROM
3138 * count - number of bits to shift out
3139 *****************************************************************************/
3141 e1000_shift_out_ee_bits(struct e1000_hw *hw,
3145 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3149 /* We need to shift "count" bits out to the EEPROM. So, value in the
3150 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3151 * In order to do this, "data" must be broken down into bits.
3153 mask = 0x01 << (count - 1);
3154 eecd = E1000_READ_REG(hw, EECD);
3155 if (eeprom->type == e1000_eeprom_microwire) {
3156 eecd &= ~E1000_EECD_DO;
3157 } else if (eeprom->type == e1000_eeprom_spi) {
3158 eecd |= E1000_EECD_DO;
3161 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3162 * and then raising and then lowering the clock (the SK bit controls
3163 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3164 * by setting "DI" to "0" and then raising and then lowering the clock.
3166 eecd &= ~E1000_EECD_DI;
3169 eecd |= E1000_EECD_DI;
3171 E1000_WRITE_REG(hw, EECD, eecd);
3172 E1000_WRITE_FLUSH(hw);
3174 udelay(eeprom->delay_usec);
3176 e1000_raise_ee_clk(hw, &eecd);
3177 e1000_lower_ee_clk(hw, &eecd);
3183 /* We leave the "DI" bit set to "0" when we leave this routine. */
3184 eecd &= ~E1000_EECD_DI;
3185 E1000_WRITE_REG(hw, EECD, eecd);
3188 /******************************************************************************
3189 * Shift data bits in from the EEPROM
3191 * hw - Struct containing variables accessed by shared code
3192 *****************************************************************************/
3194 e1000_shift_in_ee_bits(struct e1000_hw *hw,
3201 /* In order to read a register from the EEPROM, we need to shift 'count'
3202 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3203 * input to the EEPROM (setting the SK bit), and then reading the value of
3204 * the "DO" bit. During this "shifting in" process the "DI" bit should
3208 eecd = E1000_READ_REG(hw, EECD);
3210 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3213 for(i = 0; i < count; i++) {
3215 e1000_raise_ee_clk(hw, &eecd);
3217 eecd = E1000_READ_REG(hw, EECD);
3219 eecd &= ~(E1000_EECD_DI);
3220 if(eecd & E1000_EECD_DO)
3223 e1000_lower_ee_clk(hw, &eecd);
3229 /******************************************************************************
3230 * Prepares EEPROM for access
3232 * hw - Struct containing variables accessed by shared code
3234 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3235 * function should be called before issuing a command to the EEPROM.
3236 *****************************************************************************/
3238 e1000_acquire_eeprom(struct e1000_hw *hw)
3240 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3243 DEBUGFUNC("e1000_acquire_eeprom");
3245 eecd = E1000_READ_REG(hw, EECD);
3247 /* Request EEPROM Access */
3248 if(hw->mac_type > e1000_82544) {
3249 eecd |= E1000_EECD_REQ;
3250 E1000_WRITE_REG(hw, EECD, eecd);
3251 eecd = E1000_READ_REG(hw, EECD);
3252 while((!(eecd & E1000_EECD_GNT)) &&
3253 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3256 eecd = E1000_READ_REG(hw, EECD);
3258 if(!(eecd & E1000_EECD_GNT)) {
3259 eecd &= ~E1000_EECD_REQ;
3260 E1000_WRITE_REG(hw, EECD, eecd);
3261 DEBUGOUT("Could not acquire EEPROM grant\n");
3262 return -E1000_ERR_EEPROM;
3266 /* Setup EEPROM for Read/Write */
3268 if (eeprom->type == e1000_eeprom_microwire) {
3269 /* Clear SK and DI */
3270 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3271 E1000_WRITE_REG(hw, EECD, eecd);
3274 eecd |= E1000_EECD_CS;
3275 E1000_WRITE_REG(hw, EECD, eecd);
3276 } else if (eeprom->type == e1000_eeprom_spi) {
3277 /* Clear SK and CS */
3278 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3279 E1000_WRITE_REG(hw, EECD, eecd);
3283 return E1000_SUCCESS;
3286 /******************************************************************************
3287 * Returns EEPROM to a "standby" state
3289 * hw - Struct containing variables accessed by shared code
3290 *****************************************************************************/
3292 e1000_standby_eeprom(struct e1000_hw *hw)
3294 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3297 eecd = E1000_READ_REG(hw, EECD);
3299 if(eeprom->type == e1000_eeprom_microwire) {
3300 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3301 E1000_WRITE_REG(hw, EECD, eecd);
3302 E1000_WRITE_FLUSH(hw);
3303 udelay(eeprom->delay_usec);
3306 eecd |= E1000_EECD_SK;
3307 E1000_WRITE_REG(hw, EECD, eecd);
3308 E1000_WRITE_FLUSH(hw);
3309 udelay(eeprom->delay_usec);
3312 eecd |= E1000_EECD_CS;
3313 E1000_WRITE_REG(hw, EECD, eecd);
3314 E1000_WRITE_FLUSH(hw);
3315 udelay(eeprom->delay_usec);
3318 eecd &= ~E1000_EECD_SK;
3319 E1000_WRITE_REG(hw, EECD, eecd);
3320 E1000_WRITE_FLUSH(hw);
3321 udelay(eeprom->delay_usec);
3322 } else if(eeprom->type == e1000_eeprom_spi) {
3323 /* Toggle CS to flush commands */
3324 eecd |= E1000_EECD_CS;
3325 E1000_WRITE_REG(hw, EECD, eecd);
3326 E1000_WRITE_FLUSH(hw);
3327 udelay(eeprom->delay_usec);
3328 eecd &= ~E1000_EECD_CS;
3329 E1000_WRITE_REG(hw, EECD, eecd);
3330 E1000_WRITE_FLUSH(hw);
3331 udelay(eeprom->delay_usec);
3335 /******************************************************************************
3336 * Terminates a command by inverting the EEPROM's chip select pin
3338 * hw - Struct containing variables accessed by shared code
3339 *****************************************************************************/
3341 e1000_release_eeprom(struct e1000_hw *hw)
3345 DEBUGFUNC("e1000_release_eeprom");
3347 eecd = E1000_READ_REG(hw, EECD);
3349 if (hw->eeprom.type == e1000_eeprom_spi) {
3350 eecd |= E1000_EECD_CS; /* Pull CS high */
3351 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3353 E1000_WRITE_REG(hw, EECD, eecd);
3355 udelay(hw->eeprom.delay_usec);
3356 } else if(hw->eeprom.type == e1000_eeprom_microwire) {
3357 /* cleanup eeprom */
3359 /* CS on Microwire is active-high */
3360 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3362 E1000_WRITE_REG(hw, EECD, eecd);
3364 /* Rising edge of clock */
3365 eecd |= E1000_EECD_SK;
3366 E1000_WRITE_REG(hw, EECD, eecd);
3367 E1000_WRITE_FLUSH(hw);
3368 udelay(hw->eeprom.delay_usec);
3370 /* Falling edge of clock */
3371 eecd &= ~E1000_EECD_SK;
3372 E1000_WRITE_REG(hw, EECD, eecd);
3373 E1000_WRITE_FLUSH(hw);
3374 udelay(hw->eeprom.delay_usec);
3377 /* Stop requesting EEPROM access */
3378 if(hw->mac_type > e1000_82544) {
3379 eecd &= ~E1000_EECD_REQ;
3380 E1000_WRITE_REG(hw, EECD, eecd);
3384 /******************************************************************************
3385 * Reads a 16 bit word from the EEPROM.
3387 * hw - Struct containing variables accessed by shared code
3388 *****************************************************************************/
3390 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3392 uint16_t retry_count = 0;
3393 uint8_t spi_stat_reg;
3395 DEBUGFUNC("e1000_spi_eeprom_ready");
3397 /* Read "Status Register" repeatedly until the LSB is cleared. The
3398 * EEPROM will signal that the command has been completed by clearing
3399 * bit 0 of the internal status register. If it's not cleared within
3400 * 5 milliseconds, then error out.
3404 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3405 hw->eeprom.opcode_bits);
3406 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
3407 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3413 e1000_standby_eeprom(hw);
3414 } while(retry_count < EEPROM_MAX_RETRY_SPI);
3416 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3417 * only 0-5mSec on 5V devices)
3419 if(retry_count >= EEPROM_MAX_RETRY_SPI) {
3420 DEBUGOUT("SPI EEPROM Status error\n");
3421 return -E1000_ERR_EEPROM;
3424 return E1000_SUCCESS;
3427 /******************************************************************************
3428 * Reads a 16 bit word from the EEPROM.
3430 * hw - Struct containing variables accessed by shared code
3431 * offset - offset of word in the EEPROM to read
3432 * data - word read from the EEPROM
3433 * words - number of words to read
3434 *****************************************************************************/
3436 e1000_read_eeprom(struct e1000_hw *hw,
3441 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3444 DEBUGFUNC("e1000_read_eeprom");
3446 /* A check for invalid values: offset too large, too many words, and not
3449 if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3451 DEBUGOUT("\"words\" parameter out of bounds\n");
3452 return -E1000_ERR_EEPROM;
3455 /* Prepare the EEPROM for reading */
3456 if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3457 return -E1000_ERR_EEPROM;
3459 if(eeprom->type == e1000_eeprom_spi) {
3461 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
3463 if(e1000_spi_eeprom_ready(hw)) {
3464 e1000_release_eeprom(hw);
3465 return -E1000_ERR_EEPROM;
3468 e1000_standby_eeprom(hw);
3470 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3471 if((eeprom->address_bits == 8) && (offset >= 128))
3472 read_opcode |= EEPROM_A8_OPCODE_SPI;
3474 /* Send the READ command (opcode + addr) */
3475 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3476 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
3478 /* Read the data. The address of the eeprom internally increments with
3479 * each byte (spi) being read, saving on the overhead of eeprom setup
3480 * and tear-down. The address counter will roll over if reading beyond
3481 * the size of the eeprom, thus allowing the entire memory to be read
3482 * starting from any offset. */
3483 for (i = 0; i < words; i++) {
3484 word_in = e1000_shift_in_ee_bits(hw, 16);
3485 data[i] = (word_in >> 8) | (word_in << 8);
3487 } else if(eeprom->type == e1000_eeprom_microwire) {
3488 for (i = 0; i < words; i++) {
3489 /* Send the READ command (opcode + addr) */
3490 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
3491 eeprom->opcode_bits);
3492 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
3493 eeprom->address_bits);
3495 /* Read the data. For microwire, each word requires the overhead
3496 * of eeprom setup and tear-down. */
3497 data[i] = e1000_shift_in_ee_bits(hw, 16);
3498 e1000_standby_eeprom(hw);
3502 /* End this read operation */
3503 e1000_release_eeprom(hw);
3505 return E1000_SUCCESS;
3508 /******************************************************************************
3509 * Verifies that the EEPROM has a valid checksum
3511 * hw - Struct containing variables accessed by shared code
3513 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3514 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3516 *****************************************************************************/
3518 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3520 uint16_t checksum = 0;
3521 uint16_t i, eeprom_data;
3523 DEBUGFUNC("e1000_validate_eeprom_checksum");
3525 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3526 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3527 DEBUGOUT("EEPROM Read Error\n");
3528 return -E1000_ERR_EEPROM;
3530 checksum += eeprom_data;
3533 if(checksum == (uint16_t) EEPROM_SUM)
3534 return E1000_SUCCESS;
3536 DEBUGOUT("EEPROM Checksum Invalid\n");
3537 return -E1000_ERR_EEPROM;
3541 /******************************************************************************
3542 * Calculates the EEPROM checksum and writes it to the EEPROM
3544 * hw - Struct containing variables accessed by shared code
3546 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
3547 * Writes the difference to word offset 63 of the EEPROM.
3548 *****************************************************************************/
3550 e1000_update_eeprom_checksum(struct e1000_hw *hw)
3552 uint16_t checksum = 0;
3553 uint16_t i, eeprom_data;
3555 DEBUGFUNC("e1000_update_eeprom_checksum");
3557 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3558 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3559 DEBUGOUT("EEPROM Read Error\n");
3560 return -E1000_ERR_EEPROM;
3562 checksum += eeprom_data;
3564 checksum = (uint16_t) EEPROM_SUM - checksum;
3565 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3566 DEBUGOUT("EEPROM Write Error\n");
3567 return -E1000_ERR_EEPROM;
3569 return E1000_SUCCESS;
3572 /******************************************************************************
3573 * Parent function for writing words to the different EEPROM types.
3575 * hw - Struct containing variables accessed by shared code
3576 * offset - offset within the EEPROM to be written to
3577 * words - number of words to write
3578 * data - 16 bit word to be written to the EEPROM
3580 * If e1000_update_eeprom_checksum is not called after this function, the
3581 * EEPROM will most likely contain an invalid checksum.
3582 *****************************************************************************/
3584 e1000_write_eeprom(struct e1000_hw *hw,
3589 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3592 DEBUGFUNC("e1000_write_eeprom");
3594 /* A check for invalid values: offset too large, too many words, and not
3597 if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3599 DEBUGOUT("\"words\" parameter out of bounds\n");
3600 return -E1000_ERR_EEPROM;
3603 /* Prepare the EEPROM for writing */
3604 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3605 return -E1000_ERR_EEPROM;
3607 if(eeprom->type == e1000_eeprom_microwire) {
3608 status = e1000_write_eeprom_microwire(hw, offset, words, data);
3610 status = e1000_write_eeprom_spi(hw, offset, words, data);
3614 /* Done with writing */
3615 e1000_release_eeprom(hw);
3620 /******************************************************************************
3621 * Writes a 16 bit word to a given offset in an SPI EEPROM.
3623 * hw - Struct containing variables accessed by shared code
3624 * offset - offset within the EEPROM to be written to
3625 * words - number of words to write
3626 * data - pointer to array of 8 bit words to be written to the EEPROM
3628 *****************************************************************************/
3630 e1000_write_eeprom_spi(struct e1000_hw *hw,
3635 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3638 DEBUGFUNC("e1000_write_eeprom_spi");
3640 while (widx < words) {
3641 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
3643 if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
3645 e1000_standby_eeprom(hw);
3647 /* Send the WRITE ENABLE command (8 bit opcode ) */
3648 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
3649 eeprom->opcode_bits);
3651 e1000_standby_eeprom(hw);
3653 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3654 if((eeprom->address_bits == 8) && (offset >= 128))
3655 write_opcode |= EEPROM_A8_OPCODE_SPI;
3657 /* Send the Write command (8-bit opcode + addr) */
3658 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
3660 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
3661 eeprom->address_bits);
3665 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
3666 while (widx < words) {
3667 uint16_t word_out = data[widx];
3668 word_out = (word_out >> 8) | (word_out << 8);
3669 e1000_shift_out_ee_bits(hw, word_out, 16);
3672 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
3673 * operation, while the smaller eeproms are capable of an 8-byte
3674 * PAGE WRITE operation. Break the inner loop to pass new address
3676 if((((offset + widx)*2) % eeprom->page_size) == 0) {
3677 e1000_standby_eeprom(hw);
3683 return E1000_SUCCESS;
3686 /******************************************************************************
3687 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
3689 * hw - Struct containing variables accessed by shared code
3690 * offset - offset within the EEPROM to be written to
3691 * words - number of words to write
3692 * data - pointer to array of 16 bit words to be written to the EEPROM
3694 *****************************************************************************/
3696 e1000_write_eeprom_microwire(struct e1000_hw *hw,
3701 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3703 uint16_t words_written = 0;
3706 DEBUGFUNC("e1000_write_eeprom_microwire");
3708 /* Send the write enable command to the EEPROM (3-bit opcode plus
3709 * 6/8-bit dummy address beginning with 11). It's less work to include
3710 * the 11 of the dummy address as part of the opcode than it is to shift
3711 * it over the correct number of bits for the address. This puts the
3712 * EEPROM into write/erase mode.
3714 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
3715 (uint16_t)(eeprom->opcode_bits + 2));
3717 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
3719 /* Prepare the EEPROM */
3720 e1000_standby_eeprom(hw);
3722 while (words_written < words) {
3723 /* Send the Write command (3-bit opcode + addr) */
3724 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
3725 eeprom->opcode_bits);
3727 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
3728 eeprom->address_bits);
3731 e1000_shift_out_ee_bits(hw, data[words_written], 16);
3733 /* Toggle the CS line. This in effect tells the EEPROM to execute
3734 * the previous command.
3736 e1000_standby_eeprom(hw);
3738 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
3739 * signal that the command has been completed by raising the DO signal.
3740 * If DO does not go high in 10 milliseconds, then error out.
3742 for(i = 0; i < 200; i++) {
3743 eecd = E1000_READ_REG(hw, EECD);
3744 if(eecd & E1000_EECD_DO) break;
3748 DEBUGOUT("EEPROM Write did not complete\n");
3749 return -E1000_ERR_EEPROM;
3752 /* Recover from write */
3753 e1000_standby_eeprom(hw);
3758 /* Send the write disable command to the EEPROM (3-bit opcode plus
3759 * 6/8-bit dummy address beginning with 10). It's less work to include
3760 * the 10 of the dummy address as part of the opcode than it is to shift
3761 * it over the correct number of bits for the address. This takes the
3762 * EEPROM out of write/erase mode.
3764 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
3765 (uint16_t)(eeprom->opcode_bits + 2));
3767 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
3769 return E1000_SUCCESS;
3772 /******************************************************************************
3773 * Reads the adapter's part number from the EEPROM
3775 * hw - Struct containing variables accessed by shared code
3776 * part_num - Adapter's part number
3777 *****************************************************************************/
3779 e1000_read_part_num(struct e1000_hw *hw,
3782 uint16_t offset = EEPROM_PBA_BYTE_1;
3783 uint16_t eeprom_data;
3785 DEBUGFUNC("e1000_read_part_num");
3787 /* Get word 0 from EEPROM */
3788 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3789 DEBUGOUT("EEPROM Read Error\n");
3790 return -E1000_ERR_EEPROM;
3792 /* Save word 0 in upper half of part_num */
3793 *part_num = (uint32_t) (eeprom_data << 16);
3795 /* Get word 1 from EEPROM */
3796 if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
3797 DEBUGOUT("EEPROM Read Error\n");
3798 return -E1000_ERR_EEPROM;
3800 /* Save word 1 in lower half of part_num */
3801 *part_num |= eeprom_data;
3803 return E1000_SUCCESS;
3806 /******************************************************************************
3807 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
3808 * second function of dual function devices
3810 * hw - Struct containing variables accessed by shared code
3811 *****************************************************************************/
3813 e1000_read_mac_addr(struct e1000_hw * hw)
3816 uint16_t eeprom_data, i;
3818 DEBUGFUNC("e1000_read_mac_addr");
3820 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
3822 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3823 DEBUGOUT("EEPROM Read Error\n");
3824 return -E1000_ERR_EEPROM;
3826 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
3827 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
3829 if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
3830 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
3831 hw->perm_mac_addr[5] ^= 0x01;
3833 for(i = 0; i < NODE_ADDRESS_SIZE; i++)
3834 hw->mac_addr[i] = hw->perm_mac_addr[i];
3835 return E1000_SUCCESS;
3838 /******************************************************************************
3839 * Initializes receive address filters.
3841 * hw - Struct containing variables accessed by shared code
3843 * Places the MAC address in receive address register 0 and clears the rest
3844 * of the receive addresss registers. Clears the multicast table. Assumes
3845 * the receiver is in reset when the routine is called.
3846 *****************************************************************************/
3848 e1000_init_rx_addrs(struct e1000_hw *hw)
3852 DEBUGFUNC("e1000_init_rx_addrs");
3854 /* Setup the receive address. */
3855 DEBUGOUT("Programming MAC Address into RAR[0]\n");
3857 e1000_rar_set(hw, hw->mac_addr, 0);
3859 /* Zero out the other 15 receive addresses. */
3860 DEBUGOUT("Clearing RAR[1-15]\n");
3861 for(i = 1; i < E1000_RAR_ENTRIES; i++) {
3862 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3863 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3867 /******************************************************************************
3868 * Updates the MAC's list of multicast addresses.
3870 * hw - Struct containing variables accessed by shared code
3871 * mc_addr_list - the list of new multicast addresses
3872 * mc_addr_count - number of addresses
3873 * pad - number of bytes between addresses in the list
3874 * rar_used_count - offset where to start adding mc addresses into the RAR's
3876 * The given list replaces any existing list. Clears the last 15 receive
3877 * address registers and the multicast table. Uses receive address registers
3878 * for the first 15 multicast addresses, and hashes the rest into the
3880 *****************************************************************************/
3882 e1000_mc_addr_list_update(struct e1000_hw *hw,
3883 uint8_t *mc_addr_list,
3884 uint32_t mc_addr_count,
3886 uint32_t rar_used_count)
3888 uint32_t hash_value;
3891 DEBUGFUNC("e1000_mc_addr_list_update");
3893 /* Set the new number of MC addresses that we are being requested to use. */
3894 hw->num_mc_addrs = mc_addr_count;
3896 /* Clear RAR[1-15] */
3897 DEBUGOUT(" Clearing RAR[1-15]\n");
3898 for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) {
3899 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3900 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3904 DEBUGOUT(" Clearing MTA\n");
3905 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) {
3906 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
3909 /* Add the new addresses */
3910 for(i = 0; i < mc_addr_count; i++) {
3911 DEBUGOUT(" Adding the multicast addresses:\n");
3912 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
3913 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
3914 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
3915 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
3916 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
3917 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
3918 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
3920 hash_value = e1000_hash_mc_addr(hw,
3922 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
3924 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
3926 /* Place this multicast address in the RAR if there is room, *
3927 * else put it in the MTA
3929 if(rar_used_count < E1000_RAR_ENTRIES) {
3931 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
3935 e1000_mta_set(hw, hash_value);
3938 DEBUGOUT("MC Update Complete\n");
3941 /******************************************************************************
3942 * Hashes an address to determine its location in the multicast table
3944 * hw - Struct containing variables accessed by shared code
3945 * mc_addr - the multicast address to hash
3946 *****************************************************************************/
3948 e1000_hash_mc_addr(struct e1000_hw *hw,
3951 uint32_t hash_value = 0;
3953 /* The portion of the address that is used for the hash table is
3954 * determined by the mc_filter_type setting.
3956 switch (hw->mc_filter_type) {
3957 /* [0] [1] [2] [3] [4] [5]
3962 /* [47:36] i.e. 0x563 for above example address */
3963 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
3966 /* [46:35] i.e. 0xAC6 for above example address */
3967 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
3970 /* [45:34] i.e. 0x5D8 for above example address */
3971 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
3974 /* [43:32] i.e. 0x634 for above example address */
3975 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
3979 hash_value &= 0xFFF;
3983 /******************************************************************************
3984 * Sets the bit in the multicast table corresponding to the hash value.
3986 * hw - Struct containing variables accessed by shared code
3987 * hash_value - Multicast address hash value
3988 *****************************************************************************/
3990 e1000_mta_set(struct e1000_hw *hw,
3991 uint32_t hash_value)
3993 uint32_t hash_bit, hash_reg;
3997 /* The MTA is a register array of 128 32-bit registers.
3998 * It is treated like an array of 4096 bits. We want to set
3999 * bit BitArray[hash_value]. So we figure out what register
4000 * the bit is in, read it, OR in the new bit, then write
4001 * back the new value. The register is determined by the
4002 * upper 7 bits of the hash value and the bit within that
4003 * register are determined by the lower 5 bits of the value.
4005 hash_reg = (hash_value >> 5) & 0x7F;
4006 hash_bit = hash_value & 0x1F;
4008 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
4010 mta |= (1 << hash_bit);
4012 /* If we are on an 82544 and we are trying to write an odd offset
4013 * in the MTA, save off the previous entry before writing and
4014 * restore the old value after writing.
4016 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
4017 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
4018 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4019 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
4021 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4025 /******************************************************************************
4026 * Puts an ethernet address into a receive address register.
4028 * hw - Struct containing variables accessed by shared code
4029 * addr - Address to put into receive address register
4030 * index - Receive address register to write
4031 *****************************************************************************/
4033 e1000_rar_set(struct e1000_hw *hw,
4037 uint32_t rar_low, rar_high;
4039 /* HW expects these in little endian so we reverse the byte order
4040 * from network order (big endian) to little endian
4042 rar_low = ((uint32_t) addr[0] |
4043 ((uint32_t) addr[1] << 8) |
4044 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
4046 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV);
4048 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4049 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4052 /******************************************************************************
4053 * Writes a value to the specified offset in the VLAN filter table.
4055 * hw - Struct containing variables accessed by shared code
4056 * offset - Offset in VLAN filer table to write
4057 * value - Value to write into VLAN filter table
4058 *****************************************************************************/
4060 e1000_write_vfta(struct e1000_hw *hw,
4066 if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4067 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4068 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4069 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4071 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4075 /******************************************************************************
4076 * Clears the VLAN filer table
4078 * hw - Struct containing variables accessed by shared code
4079 *****************************************************************************/
4081 e1000_clear_vfta(struct e1000_hw *hw)
4085 for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
4086 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
4090 e1000_id_led_init(struct e1000_hw * hw)
4093 const uint32_t ledctl_mask = 0x000000FF;
4094 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4095 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4096 uint16_t eeprom_data, i, temp;
4097 const uint16_t led_mask = 0x0F;
4099 DEBUGFUNC("e1000_id_led_init");
4101 if(hw->mac_type < e1000_82540) {
4103 return E1000_SUCCESS;
4106 ledctl = E1000_READ_REG(hw, LEDCTL);
4107 hw->ledctl_default = ledctl;
4108 hw->ledctl_mode1 = hw->ledctl_default;
4109 hw->ledctl_mode2 = hw->ledctl_default;
4111 if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4112 DEBUGOUT("EEPROM Read Error\n");
4113 return -E1000_ERR_EEPROM;
4115 if((eeprom_data== ID_LED_RESERVED_0000) ||
4116 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
4117 for(i = 0; i < 4; i++) {
4118 temp = (eeprom_data >> (i << 2)) & led_mask;
4120 case ID_LED_ON1_DEF2:
4121 case ID_LED_ON1_ON2:
4122 case ID_LED_ON1_OFF2:
4123 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4124 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4126 case ID_LED_OFF1_DEF2:
4127 case ID_LED_OFF1_ON2:
4128 case ID_LED_OFF1_OFF2:
4129 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4130 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4137 case ID_LED_DEF1_ON2:
4138 case ID_LED_ON1_ON2:
4139 case ID_LED_OFF1_ON2:
4140 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4141 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4143 case ID_LED_DEF1_OFF2:
4144 case ID_LED_ON1_OFF2:
4145 case ID_LED_OFF1_OFF2:
4146 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4147 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4154 return E1000_SUCCESS;
4157 /******************************************************************************
4158 * Prepares SW controlable LED for use and saves the current state of the LED.
4160 * hw - Struct containing variables accessed by shared code
4161 *****************************************************************************/
4163 e1000_setup_led(struct e1000_hw *hw)
4166 int32_t ret_val = E1000_SUCCESS;
4168 DEBUGFUNC("e1000_setup_led");
4170 switch(hw->mac_type) {
4171 case e1000_82542_rev2_0:
4172 case e1000_82542_rev2_1:
4175 /* No setup necessary */
4179 case e1000_82541_rev_2:
4180 case e1000_82547_rev_2:
4181 /* Turn off PHY Smart Power Down (if enabled) */
4182 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4183 &hw->phy_spd_default);
4186 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4187 (uint16_t)(hw->phy_spd_default &
4188 ~IGP01E1000_GMII_SPD));
4193 if(hw->media_type == e1000_media_type_fiber) {
4194 ledctl = E1000_READ_REG(hw, LEDCTL);
4195 /* Save current LEDCTL settings */
4196 hw->ledctl_default = ledctl;
4198 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4199 E1000_LEDCTL_LED0_BLINK |
4200 E1000_LEDCTL_LED0_MODE_MASK);
4201 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4202 E1000_LEDCTL_LED0_MODE_SHIFT);
4203 E1000_WRITE_REG(hw, LEDCTL, ledctl);
4204 } else if(hw->media_type == e1000_media_type_copper)
4205 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
4209 return E1000_SUCCESS;
4212 /******************************************************************************
4213 * Restores the saved state of the SW controlable LED.
4215 * hw - Struct containing variables accessed by shared code
4216 *****************************************************************************/
4218 e1000_cleanup_led(struct e1000_hw *hw)
4220 int32_t ret_val = E1000_SUCCESS;
4222 DEBUGFUNC("e1000_cleanup_led");
4224 switch(hw->mac_type) {
4225 case e1000_82542_rev2_0:
4226 case e1000_82542_rev2_1:
4229 /* No cleanup necessary */
4233 case e1000_82541_rev_2:
4234 case e1000_82547_rev_2:
4235 /* Turn on PHY Smart Power Down (if previously enabled) */
4236 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4237 hw->phy_spd_default);
4242 /* Restore LEDCTL settings */
4243 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
4247 return E1000_SUCCESS;
4250 /******************************************************************************
4251 * Turns on the software controllable LED
4253 * hw - Struct containing variables accessed by shared code
4254 *****************************************************************************/
4256 e1000_led_on(struct e1000_hw *hw)
4258 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4260 DEBUGFUNC("e1000_led_on");
4262 switch(hw->mac_type) {
4263 case e1000_82542_rev2_0:
4264 case e1000_82542_rev2_1:
4266 /* Set SW Defineable Pin 0 to turn on the LED */
4267 ctrl |= E1000_CTRL_SWDPIN0;
4268 ctrl |= E1000_CTRL_SWDPIO0;
4271 if(hw->media_type == e1000_media_type_fiber) {
4272 /* Set SW Defineable Pin 0 to turn on the LED */
4273 ctrl |= E1000_CTRL_SWDPIN0;
4274 ctrl |= E1000_CTRL_SWDPIO0;
4276 /* Clear SW Defineable Pin 0 to turn on the LED */
4277 ctrl &= ~E1000_CTRL_SWDPIN0;
4278 ctrl |= E1000_CTRL_SWDPIO0;
4282 if(hw->media_type == e1000_media_type_fiber) {
4283 /* Clear SW Defineable Pin 0 to turn on the LED */
4284 ctrl &= ~E1000_CTRL_SWDPIN0;
4285 ctrl |= E1000_CTRL_SWDPIO0;
4286 } else if(hw->media_type == e1000_media_type_copper) {
4287 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
4288 return E1000_SUCCESS;
4293 E1000_WRITE_REG(hw, CTRL, ctrl);
4295 return E1000_SUCCESS;
4298 /******************************************************************************
4299 * Turns off the software controllable LED
4301 * hw - Struct containing variables accessed by shared code
4302 *****************************************************************************/
4304 e1000_led_off(struct e1000_hw *hw)
4306 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4308 DEBUGFUNC("e1000_led_off");
4310 switch(hw->mac_type) {
4311 case e1000_82542_rev2_0:
4312 case e1000_82542_rev2_1:
4314 /* Clear SW Defineable Pin 0 to turn off the LED */
4315 ctrl &= ~E1000_CTRL_SWDPIN0;
4316 ctrl |= E1000_CTRL_SWDPIO0;
4319 if(hw->media_type == e1000_media_type_fiber) {
4320 /* Clear SW Defineable Pin 0 to turn off the LED */
4321 ctrl &= ~E1000_CTRL_SWDPIN0;
4322 ctrl |= E1000_CTRL_SWDPIO0;
4324 /* Set SW Defineable Pin 0 to turn off the LED */
4325 ctrl |= E1000_CTRL_SWDPIN0;
4326 ctrl |= E1000_CTRL_SWDPIO0;
4330 if(hw->media_type == e1000_media_type_fiber) {
4331 /* Set SW Defineable Pin 0 to turn off the LED */
4332 ctrl |= E1000_CTRL_SWDPIN0;
4333 ctrl |= E1000_CTRL_SWDPIO0;
4334 } else if(hw->media_type == e1000_media_type_copper) {
4335 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
4336 return E1000_SUCCESS;
4341 E1000_WRITE_REG(hw, CTRL, ctrl);
4343 return E1000_SUCCESS;
4346 /******************************************************************************
4347 * Clears all hardware statistics counters.
4349 * hw - Struct containing variables accessed by shared code
4350 *****************************************************************************/
4352 e1000_clear_hw_cntrs(struct e1000_hw *hw)
4354 volatile uint32_t temp;
4356 temp = E1000_READ_REG(hw, CRCERRS);
4357 temp = E1000_READ_REG(hw, SYMERRS);
4358 temp = E1000_READ_REG(hw, MPC);
4359 temp = E1000_READ_REG(hw, SCC);
4360 temp = E1000_READ_REG(hw, ECOL);
4361 temp = E1000_READ_REG(hw, MCC);
4362 temp = E1000_READ_REG(hw, LATECOL);
4363 temp = E1000_READ_REG(hw, COLC);
4364 temp = E1000_READ_REG(hw, DC);
4365 temp = E1000_READ_REG(hw, SEC);
4366 temp = E1000_READ_REG(hw, RLEC);
4367 temp = E1000_READ_REG(hw, XONRXC);
4368 temp = E1000_READ_REG(hw, XONTXC);
4369 temp = E1000_READ_REG(hw, XOFFRXC);
4370 temp = E1000_READ_REG(hw, XOFFTXC);
4371 temp = E1000_READ_REG(hw, FCRUC);
4372 temp = E1000_READ_REG(hw, PRC64);
4373 temp = E1000_READ_REG(hw, PRC127);
4374 temp = E1000_READ_REG(hw, PRC255);
4375 temp = E1000_READ_REG(hw, PRC511);
4376 temp = E1000_READ_REG(hw, PRC1023);
4377 temp = E1000_READ_REG(hw, PRC1522);
4378 temp = E1000_READ_REG(hw, GPRC);
4379 temp = E1000_READ_REG(hw, BPRC);
4380 temp = E1000_READ_REG(hw, MPRC);
4381 temp = E1000_READ_REG(hw, GPTC);
4382 temp = E1000_READ_REG(hw, GORCL);
4383 temp = E1000_READ_REG(hw, GORCH);
4384 temp = E1000_READ_REG(hw, GOTCL);
4385 temp = E1000_READ_REG(hw, GOTCH);
4386 temp = E1000_READ_REG(hw, RNBC);
4387 temp = E1000_READ_REG(hw, RUC);
4388 temp = E1000_READ_REG(hw, RFC);
4389 temp = E1000_READ_REG(hw, ROC);
4390 temp = E1000_READ_REG(hw, RJC);
4391 temp = E1000_READ_REG(hw, TORL);
4392 temp = E1000_READ_REG(hw, TORH);
4393 temp = E1000_READ_REG(hw, TOTL);
4394 temp = E1000_READ_REG(hw, TOTH);
4395 temp = E1000_READ_REG(hw, TPR);
4396 temp = E1000_READ_REG(hw, TPT);
4397 temp = E1000_READ_REG(hw, PTC64);
4398 temp = E1000_READ_REG(hw, PTC127);
4399 temp = E1000_READ_REG(hw, PTC255);
4400 temp = E1000_READ_REG(hw, PTC511);
4401 temp = E1000_READ_REG(hw, PTC1023);
4402 temp = E1000_READ_REG(hw, PTC1522);
4403 temp = E1000_READ_REG(hw, MPTC);
4404 temp = E1000_READ_REG(hw, BPTC);
4406 if(hw->mac_type < e1000_82543) return;
4408 temp = E1000_READ_REG(hw, ALGNERRC);
4409 temp = E1000_READ_REG(hw, RXERRC);
4410 temp = E1000_READ_REG(hw, TNCRS);
4411 temp = E1000_READ_REG(hw, CEXTERR);
4412 temp = E1000_READ_REG(hw, TSCTC);
4413 temp = E1000_READ_REG(hw, TSCTFC);
4415 if(hw->mac_type <= e1000_82544) return;
4417 temp = E1000_READ_REG(hw, MGTPRC);
4418 temp = E1000_READ_REG(hw, MGTPDC);
4419 temp = E1000_READ_REG(hw, MGTPTC);
4422 /******************************************************************************
4423 * Resets Adaptive IFS to its default state.
4425 * hw - Struct containing variables accessed by shared code
4427 * Call this after e1000_init_hw. You may override the IFS defaults by setting
4428 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
4429 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4430 * before calling this function.
4431 *****************************************************************************/
4433 e1000_reset_adaptive(struct e1000_hw *hw)
4435 DEBUGFUNC("e1000_reset_adaptive");
4437 if(hw->adaptive_ifs) {
4438 if(!hw->ifs_params_forced) {
4439 hw->current_ifs_val = 0;
4440 hw->ifs_min_val = IFS_MIN;
4441 hw->ifs_max_val = IFS_MAX;
4442 hw->ifs_step_size = IFS_STEP;
4443 hw->ifs_ratio = IFS_RATIO;
4445 hw->in_ifs_mode = FALSE;
4446 E1000_WRITE_REG(hw, AIT, 0);
4448 DEBUGOUT("Not in Adaptive IFS mode!\n");
4452 /******************************************************************************
4453 * Called during the callback/watchdog routine to update IFS value based on
4454 * the ratio of transmits to collisions.
4456 * hw - Struct containing variables accessed by shared code
4457 * tx_packets - Number of transmits since last callback
4458 * total_collisions - Number of collisions since last callback
4459 *****************************************************************************/
4461 e1000_update_adaptive(struct e1000_hw *hw)
4463 DEBUGFUNC("e1000_update_adaptive");
4465 if(hw->adaptive_ifs) {
4466 if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
4467 if(hw->tx_packet_delta > MIN_NUM_XMITS) {
4468 hw->in_ifs_mode = TRUE;
4469 if(hw->current_ifs_val < hw->ifs_max_val) {
4470 if(hw->current_ifs_val == 0)
4471 hw->current_ifs_val = hw->ifs_min_val;
4473 hw->current_ifs_val += hw->ifs_step_size;
4474 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
4478 if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4479 hw->current_ifs_val = 0;
4480 hw->in_ifs_mode = FALSE;
4481 E1000_WRITE_REG(hw, AIT, 0);
4485 DEBUGOUT("Not in Adaptive IFS mode!\n");
4489 /******************************************************************************
4490 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
4492 * hw - Struct containing variables accessed by shared code
4493 * frame_len - The length of the frame in question
4494 * mac_addr - The Ethernet destination address of the frame in question
4495 *****************************************************************************/
4497 e1000_tbi_adjust_stats(struct e1000_hw *hw,
4498 struct e1000_hw_stats *stats,
4504 /* First adjust the frame length. */
4506 /* We need to adjust the statistics counters, since the hardware
4507 * counters overcount this packet as a CRC error and undercount
4508 * the packet as a good packet
4510 /* This packet should not be counted as a CRC error. */
4512 /* This packet does count as a Good Packet Received. */
4515 /* Adjust the Good Octets received counters */
4516 carry_bit = 0x80000000 & stats->gorcl;
4517 stats->gorcl += frame_len;
4518 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
4519 * Received Count) was one before the addition,
4520 * AND it is zero after, then we lost the carry out,
4521 * need to add one to Gorch (Good Octets Received Count High).
4522 * This could be simplified if all environments supported
4525 if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
4527 /* Is this a broadcast or multicast? Check broadcast first,
4528 * since the test for a multicast frame will test positive on
4529 * a broadcast frame.
4531 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
4532 /* Broadcast packet */
4534 else if(*mac_addr & 0x01)
4535 /* Multicast packet */
4538 if(frame_len == hw->max_frame_size) {
4539 /* In this case, the hardware has overcounted the number of
4546 /* Adjust the bin counters when the extra byte put the frame in the
4547 * wrong bin. Remember that the frame_len was adjusted above.
4549 if(frame_len == 64) {
4552 } else if(frame_len == 127) {
4555 } else if(frame_len == 255) {
4558 } else if(frame_len == 511) {
4561 } else if(frame_len == 1023) {
4564 } else if(frame_len == 1522) {
4569 /******************************************************************************
4570 * Gets the current PCI bus type, speed, and width of the hardware
4572 * hw - Struct containing variables accessed by shared code
4573 *****************************************************************************/
4575 e1000_get_bus_info(struct e1000_hw *hw)
4579 if(hw->mac_type < e1000_82543) {
4580 hw->bus_type = e1000_bus_type_unknown;
4581 hw->bus_speed = e1000_bus_speed_unknown;
4582 hw->bus_width = e1000_bus_width_unknown;
4586 status = E1000_READ_REG(hw, STATUS);
4587 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4588 e1000_bus_type_pcix : e1000_bus_type_pci;
4590 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4591 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4592 e1000_bus_speed_66 : e1000_bus_speed_120;
4593 } else if(hw->bus_type == e1000_bus_type_pci) {
4594 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4595 e1000_bus_speed_66 : e1000_bus_speed_33;
4597 switch (status & E1000_STATUS_PCIX_SPEED) {
4598 case E1000_STATUS_PCIX_SPEED_66:
4599 hw->bus_speed = e1000_bus_speed_66;
4601 case E1000_STATUS_PCIX_SPEED_100:
4602 hw->bus_speed = e1000_bus_speed_100;
4604 case E1000_STATUS_PCIX_SPEED_133:
4605 hw->bus_speed = e1000_bus_speed_133;
4608 hw->bus_speed = e1000_bus_speed_reserved;
4612 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4613 e1000_bus_width_64 : e1000_bus_width_32;
4615 /******************************************************************************
4616 * Reads a value from one of the devices registers using port I/O (as opposed
4617 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4619 * hw - Struct containing variables accessed by shared code
4620 * offset - offset to read from
4621 *****************************************************************************/
4623 e1000_read_reg_io(struct e1000_hw *hw,
4626 unsigned long io_addr = hw->io_base;
4627 unsigned long io_data = hw->io_base + 4;
4629 e1000_io_write(hw, io_addr, offset);
4630 return e1000_io_read(hw, io_data);
4633 /******************************************************************************
4634 * Writes a value to one of the devices registers using port I/O (as opposed to
4635 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4637 * hw - Struct containing variables accessed by shared code
4638 * offset - offset to write to
4639 * value - value to write
4640 *****************************************************************************/
4642 e1000_write_reg_io(struct e1000_hw *hw,
4646 unsigned long io_addr = hw->io_base;
4647 unsigned long io_data = hw->io_base + 4;
4649 e1000_io_write(hw, io_addr, offset);
4650 e1000_io_write(hw, io_data, value);
4654 /******************************************************************************
4655 * Estimates the cable length.
4657 * hw - Struct containing variables accessed by shared code
4658 * min_length - The estimated minimum length
4659 * max_length - The estimated maximum length
4661 * returns: - E1000_ERR_XXX
4664 * This function always returns a ranged length (minimum & maximum).
4665 * So for M88 phy's, this function interprets the one value returned from the
4666 * register to the minimum and maximum range.
4667 * For IGP phy's, the function calculates the range by the AGC registers.
4668 *****************************************************************************/
4670 e1000_get_cable_length(struct e1000_hw *hw,
4671 uint16_t *min_length,
4672 uint16_t *max_length)
4675 uint16_t agc_value = 0;
4676 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
4677 uint16_t i, phy_data;
4679 DEBUGFUNC("e1000_get_cable_length");
4681 *min_length = *max_length = 0;
4683 /* Use old method for Phy older than IGP */
4684 if(hw->phy_type == e1000_phy_m88) {
4685 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4690 /* Convert the enum value to ranged values */
4691 switch((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4692 M88E1000_PSSR_CABLE_LENGTH_SHIFT) {
4693 case e1000_cable_length_50:
4695 *max_length = e1000_igp_cable_length_50;
4697 case e1000_cable_length_50_80:
4698 *min_length = e1000_igp_cable_length_50;
4699 *max_length = e1000_igp_cable_length_80;
4701 case e1000_cable_length_80_110:
4702 *min_length = e1000_igp_cable_length_80;
4703 *max_length = e1000_igp_cable_length_110;
4705 case e1000_cable_length_110_140:
4706 *min_length = e1000_igp_cable_length_110;
4707 *max_length = e1000_igp_cable_length_140;
4709 case e1000_cable_length_140:
4710 *min_length = e1000_igp_cable_length_140;
4711 *max_length = e1000_igp_cable_length_170;
4714 return -E1000_ERR_PHY;
4717 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
4718 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
4719 {IGP01E1000_PHY_AGC_A,
4720 IGP01E1000_PHY_AGC_B,
4721 IGP01E1000_PHY_AGC_C,
4722 IGP01E1000_PHY_AGC_D};
4723 /* Read the AGC registers for all channels */
4724 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4726 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
4730 cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
4732 /* Array bound check. */
4733 if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
4735 return -E1000_ERR_PHY;
4737 agc_value += cur_agc;
4739 /* Update minimal AGC value. */
4740 if(min_agc > cur_agc)
4744 /* Remove the minimal AGC result for length < 50m */
4745 if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
4746 agc_value -= min_agc;
4748 /* Get the average length of the remaining 3 channels */
4749 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
4751 /* Get the average length of all the 4 channels. */
4752 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
4755 /* Set the range of the calculated length. */
4756 *min_length = ((e1000_igp_cable_length_table[agc_value] -
4757 IGP01E1000_AGC_RANGE) > 0) ?
4758 (e1000_igp_cable_length_table[agc_value] -
4759 IGP01E1000_AGC_RANGE) : 0;
4760 *max_length = e1000_igp_cable_length_table[agc_value] +
4761 IGP01E1000_AGC_RANGE;
4764 return E1000_SUCCESS;
4767 /******************************************************************************
4768 * Check the cable polarity
4770 * hw - Struct containing variables accessed by shared code
4771 * polarity - output parameter : 0 - Polarity is not reversed
4772 * 1 - Polarity is reversed.
4774 * returns: - E1000_ERR_XXX
4777 * For phy's older then IGP, this function simply reads the polarity bit in the
4778 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
4779 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
4780 * return 0. If the link speed is 1000 Mbps the polarity status is in the
4781 * IGP01E1000_PHY_PCS_INIT_REG.
4782 *****************************************************************************/
4784 e1000_check_polarity(struct e1000_hw *hw,
4790 DEBUGFUNC("e1000_check_polarity");
4792 if(hw->phy_type == e1000_phy_m88) {
4793 /* return the Polarity bit in the Status register. */
4794 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4798 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
4799 M88E1000_PSSR_REV_POLARITY_SHIFT;
4800 } else if(hw->phy_type == e1000_phy_igp) {
4801 /* Read the Status register to check the speed */
4802 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
4807 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
4808 * find the polarity status */
4809 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4810 IGP01E1000_PSSR_SPEED_1000MBPS) {
4812 /* Read the GIG initialization PCS register (0x00B4) */
4813 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
4818 /* Check the polarity bits */
4819 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
4821 /* For 10 Mbps, read the polarity bit in the status register. (for
4822 * 100 Mbps this bit is always 0) */
4823 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
4826 return E1000_SUCCESS;
4829 /******************************************************************************
4830 * Check if Downshift occured
4832 * hw - Struct containing variables accessed by shared code
4833 * downshift - output parameter : 0 - No Downshift ocured.
4834 * 1 - Downshift ocured.
4836 * returns: - E1000_ERR_XXX
4839 * For phy's older then IGP, this function reads the Downshift bit in the Phy
4840 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
4841 * Link Health register. In IGP this bit is latched high, so the driver must
4842 * read it immediately after link is established.
4843 *****************************************************************************/
4845 e1000_check_downshift(struct e1000_hw *hw)
4850 DEBUGFUNC("e1000_check_downshift");
4852 if(hw->phy_type == e1000_phy_igp) {
4853 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
4858 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
4860 else if(hw->phy_type == e1000_phy_m88) {
4861 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4866 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
4867 M88E1000_PSSR_DOWNSHIFT_SHIFT;
4869 return E1000_SUCCESS;
4872 /*****************************************************************************
4874 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
4875 * gigabit link is achieved to improve link quality.
4877 * hw: Struct containing variables accessed by shared code
4879 * returns: - E1000_ERR_PHY if fail to read/write the PHY
4880 * E1000_SUCCESS at any other case.
4882 ****************************************************************************/
4885 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
4889 uint16_t phy_data, speed, duplex, i;
4890 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
4891 {IGP01E1000_PHY_AGC_PARAM_A,
4892 IGP01E1000_PHY_AGC_PARAM_B,
4893 IGP01E1000_PHY_AGC_PARAM_C,
4894 IGP01E1000_PHY_AGC_PARAM_D};
4895 uint16_t min_length, max_length;
4897 DEBUGFUNC("e1000_config_dsp_after_link_change");
4899 if(hw->phy_type != e1000_phy_igp)
4900 return E1000_SUCCESS;
4903 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
4905 DEBUGOUT("Error getting link speed and duplex\n");
4909 if(speed == SPEED_1000) {
4911 e1000_get_cable_length(hw, &min_length, &max_length);
4913 if((hw->dsp_config_state == e1000_dsp_config_enabled) &&
4914 min_length >= e1000_igp_cable_length_50) {
4916 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4917 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
4922 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
4924 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
4929 hw->dsp_config_state = e1000_dsp_config_activated;
4932 if((hw->ffe_config_state == e1000_ffe_config_enabled) &&
4933 (min_length < e1000_igp_cable_length_50)) {
4935 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
4936 uint32_t idle_errs = 0;
4938 /* clear previous idle error counts */
4939 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
4944 for(i = 0; i < ffe_idle_err_timeout; i++) {
4946 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
4951 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
4952 if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
4953 hw->ffe_config_state = e1000_ffe_config_active;
4955 ret_val = e1000_write_phy_reg(hw,
4956 IGP01E1000_PHY_DSP_FFE,
4957 IGP01E1000_PHY_DSP_FFE_CM_CP);
4964 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
4969 if(hw->dsp_config_state == e1000_dsp_config_activated) {
4970 ret_val = e1000_write_phy_reg(hw, 0x0000,
4971 IGP01E1000_IEEE_FORCE_GIGA);
4974 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4975 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
4979 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
4980 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
4982 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
4987 ret_val = e1000_write_phy_reg(hw, 0x0000,
4988 IGP01E1000_IEEE_RESTART_AUTONEG);
4992 hw->dsp_config_state = e1000_dsp_config_enabled;
4995 if(hw->ffe_config_state == e1000_ffe_config_active) {
4996 ret_val = e1000_write_phy_reg(hw, 0x0000,
4997 IGP01E1000_IEEE_FORCE_GIGA);
5000 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5001 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5005 ret_val = e1000_write_phy_reg(hw, 0x0000,
5006 IGP01E1000_IEEE_RESTART_AUTONEG);
5009 hw->ffe_config_state = e1000_ffe_config_enabled;
5012 return E1000_SUCCESS;
5015 /*****************************************************************************
5016 * Set PHY to class A mode
5017 * Assumes the following operations will follow to enable the new class mode.
5018 * 1. Do a PHY soft reset
5019 * 2. Restart auto-negotiation or force link.
5021 * hw - Struct containing variables accessed by shared code
5022 ****************************************************************************/
5024 e1000_set_phy_mode(struct e1000_hw *hw)
5027 uint16_t eeprom_data;
5029 DEBUGFUNC("e1000_set_phy_mode");
5031 if((hw->mac_type == e1000_82545_rev_3) &&
5032 (hw->media_type == e1000_media_type_copper)) {
5033 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
5038 if((eeprom_data != EEPROM_RESERVED_WORD) &&
5039 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5040 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
5043 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
5047 hw->phy_reset_disable = FALSE;
5051 return E1000_SUCCESS;
5054 /*****************************************************************************
5056 * This function sets the lplu state according to the active flag. When
5057 * activating lplu this function also disables smart speed and vise versa.
5058 * lplu will not be activated unless the device autonegotiation advertisment
5059 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5060 * hw: Struct containing variables accessed by shared code
5061 * active - true to enable lplu false to disable lplu.
5063 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5064 * E1000_SUCCESS at any other case.
5066 ****************************************************************************/
5069 e1000_set_d3_lplu_state(struct e1000_hw *hw,
5074 DEBUGFUNC("e1000_set_d3_lplu_state");
5076 if(!((hw->mac_type == e1000_82541_rev_2) ||
5077 (hw->mac_type == e1000_82547_rev_2)))
5078 return E1000_SUCCESS;
5080 /* During driver activity LPLU should not be used or it will attain link
5081 * from the lowest speeds starting from 10Mbps. The capability is used for
5082 * Dx transitions and states */
5083 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5088 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5089 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5093 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5094 * Dx states where the power conservation is most important. During
5095 * driver activity we should enable SmartSpeed, so performance is
5097 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
5101 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5102 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
5106 } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
5107 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
5108 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5110 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5111 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5115 /* When LPLU is enabled we should disable SmartSpeed */
5116 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
5120 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5121 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
5126 return E1000_SUCCESS;
5129 /******************************************************************************
5130 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
5132 * hw - Struct containing variables accessed by shared code
5133 *****************************************************************************/
5135 e1000_set_vco_speed(struct e1000_hw *hw)
5138 uint16_t default_page = 0;
5141 DEBUGFUNC("e1000_set_vco_speed");
5143 switch(hw->mac_type) {
5144 case e1000_82545_rev_3:
5145 case e1000_82546_rev_3:
5148 return E1000_SUCCESS;
5151 /* Set PHY register 30, page 5, bit 8 to 0 */
5153 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5157 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5161 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5165 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5166 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5170 /* Set PHY register 30, page 4, bit 11 to 1 */
5172 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5176 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5180 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5181 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5185 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5189 return E1000_SUCCESS;