1 /*******************************************************************************
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 The full GNU General Public License is included in this distribution in the
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * Shared functions for accessing and configuring the MAC
35 static int32_t e1000_set_phy_type(struct e1000_hw *hw);
36 static void e1000_phy_init_script(struct e1000_hw *hw);
37 static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
38 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
39 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
40 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
41 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
42 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
43 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
44 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
46 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
47 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
48 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
49 uint16_t words, uint16_t *data);
50 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
51 uint16_t offset, uint16_t words,
53 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
54 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
55 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
56 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
58 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
60 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
62 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
63 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
64 static void e1000_release_eeprom(struct e1000_hw *hw);
65 static void e1000_standby_eeprom(struct e1000_hw *hw);
66 static int32_t e1000_id_led_init(struct e1000_hw * hw);
67 static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
68 static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
70 /* IGP cable length table */
72 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
73 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
74 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
75 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
76 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
77 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
78 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
79 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
80 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
83 /******************************************************************************
84 * Set the phy type member in the hw struct.
86 * hw - Struct containing variables accessed by shared code
87 *****************************************************************************/
89 e1000_set_phy_type(struct e1000_hw *hw)
91 DEBUGFUNC("e1000_set_phy_type");
94 case M88E1000_E_PHY_ID:
95 case M88E1000_I_PHY_ID:
96 case M88E1011_I_PHY_ID:
97 hw->phy_type = e1000_phy_m88;
99 case IGP01E1000_I_PHY_ID:
100 if(hw->mac_type == e1000_82541 ||
101 hw->mac_type == e1000_82541_rev_2 ||
102 hw->mac_type == e1000_82547 ||
103 hw->mac_type == e1000_82547_rev_2) {
104 hw->phy_type = e1000_phy_igp;
109 /* Should never have loaded on this device */
110 hw->phy_type = e1000_phy_undefined;
111 return -E1000_ERR_PHY_TYPE;
114 return E1000_SUCCESS;
117 /******************************************************************************
118 * IGP phy init script - initializes the GbE PHY
120 * hw - Struct containing variables accessed by shared code
121 *****************************************************************************/
123 e1000_phy_init_script(struct e1000_hw *hw)
125 DEBUGFUNC("e1000_phy_init_script");
127 if(hw->phy_init_script) {
130 e1000_write_phy_reg(hw,0x0000,0x0140);
134 if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) {
135 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
137 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
139 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
141 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
143 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
145 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
147 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
149 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
151 e1000_write_phy_reg(hw, 0x2010, 0x0008);
153 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
156 e1000_write_phy_reg(hw, 0x0000, 0x3300);
158 if(hw->mac_type == e1000_82547) {
159 uint16_t fused, fine, coarse;
161 /* Move to analog registers page */
162 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
164 if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
165 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
167 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
168 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
170 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
171 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
172 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
173 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
174 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
176 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
177 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
178 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
180 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
181 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
182 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
188 /******************************************************************************
189 * Set the mac type member in the hw struct.
191 * hw - Struct containing variables accessed by shared code
192 *****************************************************************************/
194 e1000_set_mac_type(struct e1000_hw *hw)
196 DEBUGFUNC("e1000_set_mac_type");
198 switch (hw->device_id) {
199 case E1000_DEV_ID_82542:
200 switch (hw->revision_id) {
201 case E1000_82542_2_0_REV_ID:
202 hw->mac_type = e1000_82542_rev2_0;
204 case E1000_82542_2_1_REV_ID:
205 hw->mac_type = e1000_82542_rev2_1;
208 /* Invalid 82542 revision ID */
209 return -E1000_ERR_MAC_TYPE;
212 case E1000_DEV_ID_82543GC_FIBER:
213 case E1000_DEV_ID_82543GC_COPPER:
214 hw->mac_type = e1000_82543;
216 case E1000_DEV_ID_82544EI_COPPER:
217 case E1000_DEV_ID_82544EI_FIBER:
218 case E1000_DEV_ID_82544GC_COPPER:
219 case E1000_DEV_ID_82544GC_LOM:
220 hw->mac_type = e1000_82544;
222 case E1000_DEV_ID_82540EM:
223 case E1000_DEV_ID_82540EM_LOM:
224 case E1000_DEV_ID_82540EP:
225 case E1000_DEV_ID_82540EP_LOM:
226 case E1000_DEV_ID_82540EP_LP:
227 hw->mac_type = e1000_82540;
229 case E1000_DEV_ID_82545EM_COPPER:
230 case E1000_DEV_ID_82545EM_FIBER:
231 hw->mac_type = e1000_82545;
233 case E1000_DEV_ID_82545GM_COPPER:
234 case E1000_DEV_ID_82545GM_FIBER:
235 case E1000_DEV_ID_82545GM_SERDES:
236 hw->mac_type = e1000_82545_rev_3;
238 case E1000_DEV_ID_82546EB_COPPER:
239 case E1000_DEV_ID_82546EB_FIBER:
240 case E1000_DEV_ID_82546EB_QUAD_COPPER:
241 hw->mac_type = e1000_82546;
243 case E1000_DEV_ID_82546GB_COPPER:
244 case E1000_DEV_ID_82546GB_FIBER:
245 case E1000_DEV_ID_82546GB_SERDES:
246 hw->mac_type = e1000_82546_rev_3;
248 case E1000_DEV_ID_82541EI:
249 case E1000_DEV_ID_82541EI_MOBILE:
250 hw->mac_type = e1000_82541;
252 case E1000_DEV_ID_82541ER:
253 case E1000_DEV_ID_82541GI:
254 case E1000_DEV_ID_82541GI_MOBILE:
255 hw->mac_type = e1000_82541_rev_2;
257 case E1000_DEV_ID_82547EI:
258 hw->mac_type = e1000_82547;
260 case E1000_DEV_ID_82547GI:
261 hw->mac_type = e1000_82547_rev_2;
264 /* Should never have loaded on this device */
265 return -E1000_ERR_MAC_TYPE;
268 return E1000_SUCCESS;
271 /*****************************************************************************
272 * Set media type and TBI compatibility.
274 * hw - Struct containing variables accessed by shared code
275 * **************************************************************************/
277 e1000_set_media_type(struct e1000_hw *hw)
281 DEBUGFUNC("e1000_set_media_type");
283 if(hw->mac_type != e1000_82543) {
284 /* tbi_compatibility is only valid on 82543 */
285 hw->tbi_compatibility_en = FALSE;
288 switch (hw->device_id) {
289 case E1000_DEV_ID_82545GM_SERDES:
290 case E1000_DEV_ID_82546GB_SERDES:
291 hw->media_type = e1000_media_type_internal_serdes;
294 if(hw->mac_type >= e1000_82543) {
295 status = E1000_READ_REG(hw, STATUS);
296 if(status & E1000_STATUS_TBIMODE) {
297 hw->media_type = e1000_media_type_fiber;
298 /* tbi_compatibility not valid on fiber */
299 hw->tbi_compatibility_en = FALSE;
301 hw->media_type = e1000_media_type_copper;
304 /* This is an 82542 (fiber only) */
305 hw->media_type = e1000_media_type_fiber;
310 /******************************************************************************
311 * Reset the transmit and receive units; mask and clear all interrupts.
313 * hw - Struct containing variables accessed by shared code
314 *****************************************************************************/
316 e1000_reset_hw(struct e1000_hw *hw)
324 DEBUGFUNC("e1000_reset_hw");
326 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
327 if(hw->mac_type == e1000_82542_rev2_0) {
328 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
329 e1000_pci_clear_mwi(hw);
332 /* Clear interrupt mask to stop board from generating interrupts */
333 DEBUGOUT("Masking off all interrupts\n");
334 E1000_WRITE_REG(hw, IMC, 0xffffffff);
336 /* Disable the Transmit and Receive units. Then delay to allow
337 * any pending transactions to complete before we hit the MAC with
340 E1000_WRITE_REG(hw, RCTL, 0);
341 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
342 E1000_WRITE_FLUSH(hw);
344 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
345 hw->tbi_compatibility_on = FALSE;
347 /* Delay to allow any outstanding PCI transactions to complete before
348 * resetting the device
352 ctrl = E1000_READ_REG(hw, CTRL);
354 /* Must reset the PHY before resetting the MAC */
355 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
356 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
360 /* Issue a global reset to the MAC. This will reset the chip's
361 * transmit, receive, DMA, and link units. It will not effect
362 * the current PCI configuration. The global reset bit is self-
363 * clearing, and should clear within a microsecond.
365 DEBUGOUT("Issuing a global reset to MAC\n");
367 switch(hw->mac_type) {
373 case e1000_82541_rev_2:
374 /* These controllers can't ack the 64-bit write when issuing the
375 * reset, so use IO-mapping as a workaround to issue the reset */
376 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
378 case e1000_82545_rev_3:
379 case e1000_82546_rev_3:
380 /* Reset is performed on a shadow of the control register */
381 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
384 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
388 /* After MAC reset, force reload of EEPROM to restore power-on settings to
389 * device. Later controllers reload the EEPROM automatically, so just wait
390 * for reload to complete.
392 switch(hw->mac_type) {
393 case e1000_82542_rev2_0:
394 case e1000_82542_rev2_1:
397 /* Wait for reset to complete */
399 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
400 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
401 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
402 E1000_WRITE_FLUSH(hw);
403 /* Wait for EEPROM reload */
407 case e1000_82541_rev_2:
409 case e1000_82547_rev_2:
410 /* Wait for EEPROM reload */
414 /* Wait for EEPROM reload (it happens automatically) */
419 /* Disable HW ARPs on ASF enabled adapters */
420 if(hw->mac_type >= e1000_82540) {
421 manc = E1000_READ_REG(hw, MANC);
422 manc &= ~(E1000_MANC_ARP_EN);
423 E1000_WRITE_REG(hw, MANC, manc);
426 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
427 e1000_phy_init_script(hw);
429 /* Configure activity LED after PHY reset */
430 led_ctrl = E1000_READ_REG(hw, LEDCTL);
431 led_ctrl &= IGP_ACTIVITY_LED_MASK;
432 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
433 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
436 /* Clear interrupt mask to stop board from generating interrupts */
437 DEBUGOUT("Masking off all interrupts\n");
438 E1000_WRITE_REG(hw, IMC, 0xffffffff);
440 /* Clear any pending interrupt events. */
441 icr = E1000_READ_REG(hw, ICR);
443 /* If MWI was previously enabled, reenable it. */
444 if(hw->mac_type == e1000_82542_rev2_0) {
445 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
446 e1000_pci_set_mwi(hw);
449 return E1000_SUCCESS;
452 /******************************************************************************
453 * Performs basic configuration of the adapter.
455 * hw - Struct containing variables accessed by shared code
457 * Assumes that the controller has previously been reset and is in a
458 * post-reset uninitialized state. Initializes the receive address registers,
459 * multicast table, and VLAN filter table. Calls routines to setup link
460 * configuration and flow control settings. Clears all on-chip counters. Leaves
461 * the transmit and receive units disabled and uninitialized.
462 *****************************************************************************/
464 e1000_init_hw(struct e1000_hw *hw)
469 uint16_t pcix_cmd_word;
470 uint16_t pcix_stat_hi_word;
474 DEBUGFUNC("e1000_init_hw");
476 /* Initialize Identification LED */
477 ret_val = e1000_id_led_init(hw);
479 DEBUGOUT("Error Initializing Identification LED\n");
483 /* Set the media type and TBI compatibility */
484 e1000_set_media_type(hw);
486 /* Disabling VLAN filtering. */
487 DEBUGOUT("Initializing the IEEE VLAN\n");
488 E1000_WRITE_REG(hw, VET, 0);
490 e1000_clear_vfta(hw);
492 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
493 if(hw->mac_type == e1000_82542_rev2_0) {
494 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
495 e1000_pci_clear_mwi(hw);
496 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
497 E1000_WRITE_FLUSH(hw);
501 /* Setup the receive address. This involves initializing all of the Receive
502 * Address Registers (RARs 0 - 15).
504 e1000_init_rx_addrs(hw);
506 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
507 if(hw->mac_type == e1000_82542_rev2_0) {
508 E1000_WRITE_REG(hw, RCTL, 0);
509 E1000_WRITE_FLUSH(hw);
511 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
512 e1000_pci_set_mwi(hw);
515 /* Zero out the Multicast HASH table */
516 DEBUGOUT("Zeroing the MTA\n");
517 for(i = 0; i < E1000_MC_TBL_SIZE; i++)
518 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
520 /* Set the PCI priority bit correctly in the CTRL register. This
521 * determines if the adapter gives priority to receives, or if it
522 * gives equal priority to transmits and receives.
524 if(hw->dma_fairness) {
525 ctrl = E1000_READ_REG(hw, CTRL);
526 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
529 switch(hw->mac_type) {
530 case e1000_82545_rev_3:
531 case e1000_82546_rev_3:
534 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
535 if(hw->bus_type == e1000_bus_type_pcix) {
536 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
537 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
539 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
540 PCIX_COMMAND_MMRBC_SHIFT;
541 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
542 PCIX_STATUS_HI_MMRBC_SHIFT;
543 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
544 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
545 if(cmd_mmrbc > stat_mmrbc) {
546 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
547 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
548 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
555 /* Call a subroutine to configure the link and setup flow control. */
556 ret_val = e1000_setup_link(hw);
558 /* Set the transmit descriptor write-back policy */
559 if(hw->mac_type > e1000_82544) {
560 ctrl = E1000_READ_REG(hw, TXDCTL);
561 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
562 E1000_WRITE_REG(hw, TXDCTL, ctrl);
565 /* Clear all of the statistics registers (clear on read). It is
566 * important that we do this after we have tried to establish link
567 * because the symbol error count will increment wildly if there
570 e1000_clear_hw_cntrs(hw);
575 /******************************************************************************
576 * Adjust SERDES output amplitude based on EEPROM setting.
578 * hw - Struct containing variables accessed by shared code.
579 *****************************************************************************/
581 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
583 uint16_t eeprom_data;
586 DEBUGFUNC("e1000_adjust_serdes_amplitude");
588 if(hw->media_type != e1000_media_type_internal_serdes)
589 return E1000_SUCCESS;
591 switch(hw->mac_type) {
592 case e1000_82545_rev_3:
593 case e1000_82546_rev_3:
596 return E1000_SUCCESS;
599 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
604 if(eeprom_data != EEPROM_RESERVED_WORD) {
605 /* Adjust SERDES output amplitude only. */
606 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
607 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
612 return E1000_SUCCESS;
615 /******************************************************************************
616 * Configures flow control and link settings.
618 * hw - Struct containing variables accessed by shared code
620 * Determines which flow control settings to use. Calls the apropriate media-
621 * specific link configuration function. Configures the flow control settings.
622 * Assuming the adapter has a valid link partner, a valid link should be
623 * established. Assumes the hardware has previously been reset and the
624 * transmitter and receiver are not enabled.
625 *****************************************************************************/
627 e1000_setup_link(struct e1000_hw *hw)
631 uint16_t eeprom_data;
633 DEBUGFUNC("e1000_setup_link");
635 /* Read and store word 0x0F of the EEPROM. This word contains bits
636 * that determine the hardware's default PAUSE (flow control) mode,
637 * a bit that determines whether the HW defaults to enabling or
638 * disabling auto-negotiation, and the direction of the
639 * SW defined pins. If there is no SW over-ride of the flow
640 * control setting, then the variable hw->fc will
641 * be initialized based on a value in the EEPROM.
643 if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
644 DEBUGOUT("EEPROM Read Error\n");
645 return -E1000_ERR_EEPROM;
648 if(hw->fc == e1000_fc_default) {
649 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
650 hw->fc = e1000_fc_none;
651 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
652 EEPROM_WORD0F_ASM_DIR)
653 hw->fc = e1000_fc_tx_pause;
655 hw->fc = e1000_fc_full;
658 /* We want to save off the original Flow Control configuration just
659 * in case we get disconnected and then reconnected into a different
660 * hub or switch with different Flow Control capabilities.
662 if(hw->mac_type == e1000_82542_rev2_0)
663 hw->fc &= (~e1000_fc_tx_pause);
665 if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
666 hw->fc &= (~e1000_fc_rx_pause);
668 hw->original_fc = hw->fc;
670 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
672 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
673 * polarity value for the SW controlled pins, and setup the
674 * Extended Device Control reg with that info.
675 * This is needed because one of the SW controlled pins is used for
676 * signal detection. So this should be done before e1000_setup_pcs_link()
677 * or e1000_phy_setup() is called.
679 if(hw->mac_type == e1000_82543) {
680 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
682 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
685 /* Call the necessary subroutine to configure the link. */
686 ret_val = (hw->media_type == e1000_media_type_copper) ?
687 e1000_setup_copper_link(hw) :
688 e1000_setup_fiber_serdes_link(hw);
690 /* Initialize the flow control address, type, and PAUSE timer
691 * registers to their default values. This is done even if flow
692 * control is disabled, because it does not hurt anything to
693 * initialize these registers.
695 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
697 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
698 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
699 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
700 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
702 /* Set the flow control receive threshold registers. Normally,
703 * these registers will be set to a default threshold that may be
704 * adjusted later by the driver's runtime code. However, if the
705 * ability to transmit pause frames in not enabled, then these
706 * registers will be set to 0.
708 if(!(hw->fc & e1000_fc_tx_pause)) {
709 E1000_WRITE_REG(hw, FCRTL, 0);
710 E1000_WRITE_REG(hw, FCRTH, 0);
712 /* We need to set up the Receive Threshold high and low water marks
713 * as well as (optionally) enabling the transmission of XON frames.
715 if(hw->fc_send_xon) {
716 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
717 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
719 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
720 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
726 /******************************************************************************
727 * Sets up link for a fiber based or serdes based adapter
729 * hw - Struct containing variables accessed by shared code
731 * Manipulates Physical Coding Sublayer functions in order to configure
732 * link. Assumes the hardware has been previously reset and the transmitter
733 * and receiver are not enabled.
734 *****************************************************************************/
736 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
745 DEBUGFUNC("e1000_setup_fiber_serdes_link");
747 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
748 * set when the optics detect a signal. On older adapters, it will be
749 * cleared when there is a signal. This applies to fiber media only.
750 * If we're on serdes media, adjust the output amplitude to value set in
753 ctrl = E1000_READ_REG(hw, CTRL);
754 if(hw->media_type == e1000_media_type_fiber)
755 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
757 ret_val = e1000_adjust_serdes_amplitude(hw);
761 /* Take the link out of reset */
762 ctrl &= ~(E1000_CTRL_LRST);
764 /* Adjust VCO speed to improve BER performance */
765 ret_val = e1000_set_vco_speed(hw);
769 e1000_config_collision_dist(hw);
771 /* Check for a software override of the flow control settings, and setup
772 * the device accordingly. If auto-negotiation is enabled, then software
773 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
774 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
775 * auto-negotiation is disabled, then software will have to manually
776 * configure the two flow control enable bits in the CTRL register.
778 * The possible values of the "fc" parameter are:
779 * 0: Flow control is completely disabled
780 * 1: Rx flow control is enabled (we can receive pause frames, but
781 * not send pause frames).
782 * 2: Tx flow control is enabled (we can send pause frames but we do
783 * not support receiving pause frames).
784 * 3: Both Rx and TX flow control (symmetric) are enabled.
788 /* Flow control is completely disabled by a software over-ride. */
789 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
791 case e1000_fc_rx_pause:
792 /* RX Flow control is enabled and TX Flow control is disabled by a
793 * software over-ride. Since there really isn't a way to advertise
794 * that we are capable of RX Pause ONLY, we will advertise that we
795 * support both symmetric and asymmetric RX PAUSE. Later, we will
796 * disable the adapter's ability to send PAUSE frames.
798 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
800 case e1000_fc_tx_pause:
801 /* TX Flow control is enabled, and RX Flow control is disabled, by a
802 * software over-ride.
804 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
807 /* Flow control (both RX and TX) is enabled by a software over-ride. */
808 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
811 DEBUGOUT("Flow control param set incorrectly\n");
812 return -E1000_ERR_CONFIG;
816 /* Since auto-negotiation is enabled, take the link out of reset (the link
817 * will be in reset, because we previously reset the chip). This will
818 * restart auto-negotiation. If auto-neogtiation is successful then the
819 * link-up status bit will be set and the flow control enable bits (RFCE
820 * and TFCE) will be set according to their negotiated value.
822 DEBUGOUT("Auto-negotiation enabled\n");
824 E1000_WRITE_REG(hw, TXCW, txcw);
825 E1000_WRITE_REG(hw, CTRL, ctrl);
826 E1000_WRITE_FLUSH(hw);
831 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
832 * indication in the Device Status Register. Time-out if a link isn't
833 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
834 * less than 500 milliseconds even if the other end is doing it in SW).
835 * For internal serdes, we just assume a signal is present, then poll.
837 if(hw->media_type == e1000_media_type_internal_serdes ||
838 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
839 DEBUGOUT("Looking for Link\n");
840 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
842 status = E1000_READ_REG(hw, STATUS);
843 if(status & E1000_STATUS_LU) break;
845 if(i == (LINK_UP_TIMEOUT / 10)) {
846 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
847 hw->autoneg_failed = 1;
848 /* AutoNeg failed to achieve a link, so we'll call
849 * e1000_check_for_link. This routine will force the link up if
850 * we detect a signal. This will allow us to communicate with
851 * non-autonegotiating link partners.
853 ret_val = e1000_check_for_link(hw);
855 DEBUGOUT("Error while checking for link\n");
858 hw->autoneg_failed = 0;
860 hw->autoneg_failed = 0;
861 DEBUGOUT("Valid Link Found\n");
864 DEBUGOUT("No Signal Detected\n");
866 return E1000_SUCCESS;
869 /******************************************************************************
870 * Detects which PHY is present and the speed and duplex
872 * hw - Struct containing variables accessed by shared code
873 ******************************************************************************/
875 e1000_setup_copper_link(struct e1000_hw *hw)
883 DEBUGFUNC("e1000_setup_copper_link");
885 ctrl = E1000_READ_REG(hw, CTRL);
886 /* With 82543, we need to force speed and duplex on the MAC equal to what
887 * the PHY speed and duplex configuration is. In addition, we need to
888 * perform a hardware reset on the PHY to take it out of reset.
890 if(hw->mac_type > e1000_82543) {
891 ctrl |= E1000_CTRL_SLU;
892 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
893 E1000_WRITE_REG(hw, CTRL, ctrl);
895 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
896 E1000_WRITE_REG(hw, CTRL, ctrl);
897 e1000_phy_hw_reset(hw);
900 /* Make sure we have a valid PHY */
901 ret_val = e1000_detect_gig_phy(hw);
903 DEBUGOUT("Error, did not detect valid phy.\n");
906 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
908 /* Set PHY to class A mode (if necessary) */
909 ret_val = e1000_set_phy_mode(hw);
913 if(hw->mac_type <= e1000_82543 ||
914 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
915 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
916 hw->phy_reset_disable = FALSE;
918 if(!hw->phy_reset_disable) {
919 if (hw->phy_type == e1000_phy_igp) {
921 ret_val = e1000_phy_reset(hw);
923 DEBUGOUT("Error Resetting the PHY\n");
927 /* Wait 10ms for MAC to configure PHY from eeprom settings */
930 /* Configure activity LED after PHY reset */
931 led_ctrl = E1000_READ_REG(hw, LEDCTL);
932 led_ctrl &= IGP_ACTIVITY_LED_MASK;
933 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
934 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
936 /* disable lplu d3 during driver init */
937 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
939 DEBUGOUT("Error Disabling LPLU D3\n");
943 /* Configure mdi-mdix settings */
944 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
949 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
950 hw->dsp_config_state = e1000_dsp_config_disabled;
951 /* Force MDI for IGP B-0 PHY */
952 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
953 IGP01E1000_PSCR_FORCE_MDI_MDIX);
957 hw->dsp_config_state = e1000_dsp_config_enabled;
958 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
962 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
965 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
969 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
973 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
978 /* set auto-master slave resolution settings */
980 e1000_ms_type phy_ms_setting = hw->master_slave;
982 if(hw->ffe_config_state == e1000_ffe_config_active)
983 hw->ffe_config_state = e1000_ffe_config_enabled;
985 if(hw->dsp_config_state == e1000_dsp_config_activated)
986 hw->dsp_config_state = e1000_dsp_config_enabled;
988 /* when autonegotiation advertisment is only 1000Mbps then we
989 * should disable SmartSpeed and enable Auto MasterSlave
990 * resolution as hardware default. */
991 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
992 /* Disable SmartSpeed */
993 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
997 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
998 ret_val = e1000_write_phy_reg(hw,
999 IGP01E1000_PHY_PORT_CONFIG,
1003 /* Set auto Master/Slave resolution process */
1004 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1007 phy_data &= ~CR_1000T_MS_ENABLE;
1008 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1013 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1017 /* load defaults for future use */
1018 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1019 ((phy_data & CR_1000T_MS_VALUE) ?
1020 e1000_ms_force_master :
1021 e1000_ms_force_slave) :
1024 switch (phy_ms_setting) {
1025 case e1000_ms_force_master:
1026 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1028 case e1000_ms_force_slave:
1029 phy_data |= CR_1000T_MS_ENABLE;
1030 phy_data &= ~(CR_1000T_MS_VALUE);
1033 phy_data &= ~CR_1000T_MS_ENABLE;
1037 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1042 /* Enable CRS on TX. This must be set for half-duplex operation. */
1043 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1048 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1051 * MDI/MDI-X = 0 (default)
1052 * 0 - Auto for all speeds
1055 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1057 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1061 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1064 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1067 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1071 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1076 * disable_polarity_correction = 0 (default)
1077 * Automatic Correction for Reversed Cable Polarity
1081 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1082 if(hw->disable_polarity_correction == 1)
1083 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1084 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1089 /* Force TX_CLK in the Extended PHY Specific Control Register
1092 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1097 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1099 if (hw->phy_revision < M88E1011_I_REV_4) {
1100 /* Configure Master and Slave downshift values */
1101 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1102 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1103 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1104 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1105 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1111 /* SW Reset the PHY so all changes take effect */
1112 ret_val = e1000_phy_reset(hw);
1114 DEBUGOUT("Error Resetting the PHY\n");
1120 * autoneg = 1 (default)
1121 * PHY will advertise value(s) parsed from
1122 * autoneg_advertised and fc
1124 * PHY will be set to 10H, 10F, 100H, or 100F
1125 * depending on value parsed from forced_speed_duplex.
1128 /* Is autoneg enabled? This is enabled by default or by software
1129 * override. If so, call e1000_phy_setup_autoneg routine to parse the
1130 * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1131 * the user should have provided a speed/duplex override. If so, then
1132 * call e1000_phy_force_speed_duplex to parse and set this up.
1135 /* Perform some bounds checking on the hw->autoneg_advertised
1136 * parameter. If this variable is zero, then set it to the default.
1138 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1140 /* If autoneg_advertised is zero, we assume it was not defaulted
1141 * by the calling code so we set to advertise full capability.
1143 if(hw->autoneg_advertised == 0)
1144 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1146 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1147 ret_val = e1000_phy_setup_autoneg(hw);
1149 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1152 DEBUGOUT("Restarting Auto-Neg\n");
1154 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1155 * the Auto Neg Restart bit in the PHY control register.
1157 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1161 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1162 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1166 /* Does the user want to wait for Auto-Neg to complete here, or
1167 * check at a later time (for example, callback routine).
1169 if(hw->wait_autoneg_complete) {
1170 ret_val = e1000_wait_autoneg(hw);
1172 DEBUGOUT("Error while waiting for autoneg to complete\n");
1176 hw->get_link_status = TRUE;
1178 DEBUGOUT("Forcing speed and duplex\n");
1179 ret_val = e1000_phy_force_speed_duplex(hw);
1181 DEBUGOUT("Error Forcing Speed and Duplex\n");
1185 } /* !hw->phy_reset_disable */
1187 /* Check link status. Wait up to 100 microseconds for link to become
1190 for(i = 0; i < 10; i++) {
1191 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1194 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1198 if(phy_data & MII_SR_LINK_STATUS) {
1199 /* We have link, so we need to finish the config process:
1200 * 1) Set up the MAC to the current PHY speed/duplex
1201 * if we are on 82543. If we
1202 * are on newer silicon, we only need to configure
1203 * collision distance in the Transmit Control Register.
1204 * 2) Set up flow control on the MAC to that established with
1207 if(hw->mac_type >= e1000_82544) {
1208 e1000_config_collision_dist(hw);
1210 ret_val = e1000_config_mac_to_phy(hw);
1212 DEBUGOUT("Error configuring MAC to PHY settings\n");
1216 ret_val = e1000_config_fc_after_link_up(hw);
1218 DEBUGOUT("Error Configuring Flow Control\n");
1221 DEBUGOUT("Valid link established!!!\n");
1223 if(hw->phy_type == e1000_phy_igp) {
1224 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1226 DEBUGOUT("Error Configuring DSP after link up\n");
1230 DEBUGOUT("Valid link established!!!\n");
1231 return E1000_SUCCESS;
1236 DEBUGOUT("Unable to establish link!!!\n");
1237 return E1000_SUCCESS;
1240 /******************************************************************************
1241 * Configures PHY autoneg and flow control advertisement settings
1243 * hw - Struct containing variables accessed by shared code
1244 ******************************************************************************/
1246 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1249 uint16_t mii_autoneg_adv_reg;
1250 uint16_t mii_1000t_ctrl_reg;
1252 DEBUGFUNC("e1000_phy_setup_autoneg");
1254 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1255 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1259 /* Read the MII 1000Base-T Control Register (Address 9). */
1260 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1264 /* Need to parse both autoneg_advertised and fc and set up
1265 * the appropriate PHY registers. First we will parse for
1266 * autoneg_advertised software override. Since we can advertise
1267 * a plethora of combinations, we need to check each bit
1271 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1272 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1273 * the 1000Base-T Control Register (Address 9).
1275 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1276 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1278 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1280 /* Do we want to advertise 10 Mb Half Duplex? */
1281 if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1282 DEBUGOUT("Advertise 10mb Half duplex\n");
1283 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1286 /* Do we want to advertise 10 Mb Full Duplex? */
1287 if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1288 DEBUGOUT("Advertise 10mb Full duplex\n");
1289 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1292 /* Do we want to advertise 100 Mb Half Duplex? */
1293 if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1294 DEBUGOUT("Advertise 100mb Half duplex\n");
1295 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1298 /* Do we want to advertise 100 Mb Full Duplex? */
1299 if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1300 DEBUGOUT("Advertise 100mb Full duplex\n");
1301 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1304 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1305 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1306 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1309 /* Do we want to advertise 1000 Mb Full Duplex? */
1310 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1311 DEBUGOUT("Advertise 1000mb Full duplex\n");
1312 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1315 /* Check for a software override of the flow control settings, and
1316 * setup the PHY advertisement registers accordingly. If
1317 * auto-negotiation is enabled, then software will have to set the
1318 * "PAUSE" bits to the correct value in the Auto-Negotiation
1319 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1321 * The possible values of the "fc" parameter are:
1322 * 0: Flow control is completely disabled
1323 * 1: Rx flow control is enabled (we can receive pause frames
1324 * but not send pause frames).
1325 * 2: Tx flow control is enabled (we can send pause frames
1326 * but we do not support receiving pause frames).
1327 * 3: Both Rx and TX flow control (symmetric) are enabled.
1328 * other: No software override. The flow control configuration
1329 * in the EEPROM is used.
1332 case e1000_fc_none: /* 0 */
1333 /* Flow control (RX & TX) is completely disabled by a
1334 * software over-ride.
1336 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1338 case e1000_fc_rx_pause: /* 1 */
1339 /* RX Flow control is enabled, and TX Flow control is
1340 * disabled, by a software over-ride.
1342 /* Since there really isn't a way to advertise that we are
1343 * capable of RX Pause ONLY, we will advertise that we
1344 * support both symmetric and asymmetric RX PAUSE. Later
1345 * (in e1000_config_fc_after_link_up) we will disable the
1346 *hw's ability to send PAUSE frames.
1348 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1350 case e1000_fc_tx_pause: /* 2 */
1351 /* TX Flow control is enabled, and RX Flow control is
1352 * disabled, by a software over-ride.
1354 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1355 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1357 case e1000_fc_full: /* 3 */
1358 /* Flow control (both RX and TX) is enabled by a software
1361 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1364 DEBUGOUT("Flow control param set incorrectly\n");
1365 return -E1000_ERR_CONFIG;
1368 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1372 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1374 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1378 return E1000_SUCCESS;
1381 /******************************************************************************
1382 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1384 * hw - Struct containing variables accessed by shared code
1385 ******************************************************************************/
1387 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1391 uint16_t mii_ctrl_reg;
1392 uint16_t mii_status_reg;
1396 DEBUGFUNC("e1000_phy_force_speed_duplex");
1398 /* Turn off Flow control if we are forcing speed and duplex. */
1399 hw->fc = e1000_fc_none;
1401 DEBUGOUT1("hw->fc = %d\n", hw->fc);
1403 /* Read the Device Control Register. */
1404 ctrl = E1000_READ_REG(hw, CTRL);
1406 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1407 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1408 ctrl &= ~(DEVICE_SPEED_MASK);
1410 /* Clear the Auto Speed Detect Enable bit. */
1411 ctrl &= ~E1000_CTRL_ASDE;
1413 /* Read the MII Control Register. */
1414 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1418 /* We need to disable autoneg in order to force link and duplex. */
1420 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1422 /* Are we forcing Full or Half Duplex? */
1423 if(hw->forced_speed_duplex == e1000_100_full ||
1424 hw->forced_speed_duplex == e1000_10_full) {
1425 /* We want to force full duplex so we SET the full duplex bits in the
1426 * Device and MII Control Registers.
1428 ctrl |= E1000_CTRL_FD;
1429 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1430 DEBUGOUT("Full Duplex\n");
1432 /* We want to force half duplex so we CLEAR the full duplex bits in
1433 * the Device and MII Control Registers.
1435 ctrl &= ~E1000_CTRL_FD;
1436 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1437 DEBUGOUT("Half Duplex\n");
1440 /* Are we forcing 100Mbps??? */
1441 if(hw->forced_speed_duplex == e1000_100_full ||
1442 hw->forced_speed_duplex == e1000_100_half) {
1443 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1444 ctrl |= E1000_CTRL_SPD_100;
1445 mii_ctrl_reg |= MII_CR_SPEED_100;
1446 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1447 DEBUGOUT("Forcing 100mb ");
1449 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1450 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1451 mii_ctrl_reg |= MII_CR_SPEED_10;
1452 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1453 DEBUGOUT("Forcing 10mb ");
1456 e1000_config_collision_dist(hw);
1458 /* Write the configured values back to the Device Control Reg. */
1459 E1000_WRITE_REG(hw, CTRL, ctrl);
1461 if (hw->phy_type == e1000_phy_m88) {
1462 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1466 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1467 * forced whenever speed are duplex are forced.
1469 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1470 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1474 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
1476 /* Need to reset the PHY or these changes will be ignored */
1477 mii_ctrl_reg |= MII_CR_RESET;
1479 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1480 * forced whenever speed or duplex are forced.
1482 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1486 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1487 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1489 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1494 /* Write back the modified PHY MII control register. */
1495 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1501 /* The wait_autoneg_complete flag may be a little misleading here.
1502 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1503 * But we do want to delay for a period while forcing only so we
1504 * don't generate false No Link messages. So we will wait here
1505 * only if the user has set wait_autoneg_complete to 1, which is
1508 if(hw->wait_autoneg_complete) {
1509 /* We will wait for autoneg to complete. */
1510 DEBUGOUT("Waiting for forced speed/duplex link.\n");
1513 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1514 for(i = PHY_FORCE_TIME; i > 0; i--) {
1515 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1518 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1522 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1526 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1529 if((i == 0) && (hw->phy_type == e1000_phy_m88)) {
1530 /* We didn't get link. Reset the DSP and wait again for link. */
1531 ret_val = e1000_phy_reset_dsp(hw);
1533 DEBUGOUT("Error Resetting PHY DSP\n");
1537 /* This loop will early-out if the link condition has been met. */
1538 for(i = PHY_FORCE_TIME; i > 0; i--) {
1539 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1541 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1544 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1548 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1554 if (hw->phy_type == e1000_phy_m88) {
1555 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1556 * Extended PHY Specific Control Register to 25MHz clock. This value
1557 * defaults back to a 2.5MHz clock when the PHY is reset.
1559 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1563 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1564 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1568 /* In addition, because of the s/w reset above, we need to enable CRS on
1569 * TX. This must be set for both full and half duplex operation.
1571 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1575 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1576 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1580 return E1000_SUCCESS;
1583 /******************************************************************************
1584 * Sets the collision distance in the Transmit Control register
1586 * hw - Struct containing variables accessed by shared code
1588 * Link should have been established previously. Reads the speed and duplex
1589 * information from the Device Status register.
1590 ******************************************************************************/
1592 e1000_config_collision_dist(struct e1000_hw *hw)
1596 DEBUGFUNC("e1000_config_collision_dist");
1598 tctl = E1000_READ_REG(hw, TCTL);
1600 tctl &= ~E1000_TCTL_COLD;
1601 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1603 E1000_WRITE_REG(hw, TCTL, tctl);
1604 E1000_WRITE_FLUSH(hw);
1607 /******************************************************************************
1608 * Sets MAC speed and duplex settings to reflect the those in the PHY
1610 * hw - Struct containing variables accessed by shared code
1611 * mii_reg - data to write to the MII control register
1613 * The contents of the PHY register containing the needed information need to
1615 ******************************************************************************/
1617 e1000_config_mac_to_phy(struct e1000_hw *hw)
1623 DEBUGFUNC("e1000_config_mac_to_phy");
1625 /* Read the Device Control Register and set the bits to Force Speed
1628 ctrl = E1000_READ_REG(hw, CTRL);
1629 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1630 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1632 /* Set up duplex in the Device Control and Transmit Control
1633 * registers depending on negotiated values.
1635 if (hw->phy_type == e1000_phy_igp) {
1636 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
1641 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
1642 else ctrl &= ~E1000_CTRL_FD;
1644 e1000_config_collision_dist(hw);
1646 /* Set up speed in the Device Control register depending on
1647 * negotiated values.
1649 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1650 IGP01E1000_PSSR_SPEED_1000MBPS)
1651 ctrl |= E1000_CTRL_SPD_1000;
1652 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1653 IGP01E1000_PSSR_SPEED_100MBPS)
1654 ctrl |= E1000_CTRL_SPD_100;
1656 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1661 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
1662 else ctrl &= ~E1000_CTRL_FD;
1664 e1000_config_collision_dist(hw);
1666 /* Set up speed in the Device Control register depending on
1667 * negotiated values.
1669 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1670 ctrl |= E1000_CTRL_SPD_1000;
1671 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1672 ctrl |= E1000_CTRL_SPD_100;
1674 /* Write the configured values back to the Device Control Reg. */
1675 E1000_WRITE_REG(hw, CTRL, ctrl);
1676 return E1000_SUCCESS;
1679 /******************************************************************************
1680 * Forces the MAC's flow control settings.
1682 * hw - Struct containing variables accessed by shared code
1684 * Sets the TFCE and RFCE bits in the device control register to reflect
1685 * the adapter settings. TFCE and RFCE need to be explicitly set by
1686 * software when a Copper PHY is used because autonegotiation is managed
1687 * by the PHY rather than the MAC. Software must also configure these
1688 * bits when link is forced on a fiber connection.
1689 *****************************************************************************/
1691 e1000_force_mac_fc(struct e1000_hw *hw)
1695 DEBUGFUNC("e1000_force_mac_fc");
1697 /* Get the current configuration of the Device Control Register */
1698 ctrl = E1000_READ_REG(hw, CTRL);
1700 /* Because we didn't get link via the internal auto-negotiation
1701 * mechanism (we either forced link or we got link via PHY
1702 * auto-neg), we have to manually enable/disable transmit an
1703 * receive flow control.
1705 * The "Case" statement below enables/disable flow control
1706 * according to the "hw->fc" parameter.
1708 * The possible values of the "fc" parameter are:
1709 * 0: Flow control is completely disabled
1710 * 1: Rx flow control is enabled (we can receive pause
1711 * frames but not send pause frames).
1712 * 2: Tx flow control is enabled (we can send pause frames
1713 * frames but we do not receive pause frames).
1714 * 3: Both Rx and TX flow control (symmetric) is enabled.
1715 * other: No other values should be possible at this point.
1720 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1722 case e1000_fc_rx_pause:
1723 ctrl &= (~E1000_CTRL_TFCE);
1724 ctrl |= E1000_CTRL_RFCE;
1726 case e1000_fc_tx_pause:
1727 ctrl &= (~E1000_CTRL_RFCE);
1728 ctrl |= E1000_CTRL_TFCE;
1731 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1734 DEBUGOUT("Flow control param set incorrectly\n");
1735 return -E1000_ERR_CONFIG;
1738 /* Disable TX Flow Control for 82542 (rev 2.0) */
1739 if(hw->mac_type == e1000_82542_rev2_0)
1740 ctrl &= (~E1000_CTRL_TFCE);
1742 E1000_WRITE_REG(hw, CTRL, ctrl);
1743 return E1000_SUCCESS;
1746 /******************************************************************************
1747 * Configures flow control settings after link is established
1749 * hw - Struct containing variables accessed by shared code
1751 * Should be called immediately after a valid link has been established.
1752 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1753 * and autonegotiation is enabled, the MAC flow control settings will be set
1754 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1755 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
1756 *****************************************************************************/
1758 e1000_config_fc_after_link_up(struct e1000_hw *hw)
1761 uint16_t mii_status_reg;
1762 uint16_t mii_nway_adv_reg;
1763 uint16_t mii_nway_lp_ability_reg;
1767 DEBUGFUNC("e1000_config_fc_after_link_up");
1769 /* Check for the case where we have fiber media and auto-neg failed
1770 * so we had to force link. In this case, we need to force the
1771 * configuration of the MAC to match the "fc" parameter.
1773 if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
1774 ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) ||
1775 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
1776 ret_val = e1000_force_mac_fc(hw);
1778 DEBUGOUT("Error forcing flow control settings\n");
1783 /* Check for the case where we have copper media and auto-neg is
1784 * enabled. In this case, we need to check and see if Auto-Neg
1785 * has completed, and if so, how the PHY and link partner has
1786 * flow control configured.
1788 if((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
1789 /* Read the MII Status Register and check to see if AutoNeg
1790 * has completed. We read this twice because this reg has
1791 * some "sticky" (latched) bits.
1793 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1796 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1800 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1801 /* The AutoNeg process has completed, so we now need to
1802 * read both the Auto Negotiation Advertisement Register
1803 * (Address 4) and the Auto_Negotiation Base Page Ability
1804 * Register (Address 5) to determine how flow control was
1807 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1811 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
1812 &mii_nway_lp_ability_reg);
1816 /* Two bits in the Auto Negotiation Advertisement Register
1817 * (Address 4) and two bits in the Auto Negotiation Base
1818 * Page Ability Register (Address 5) determine flow control
1819 * for both the PHY and the link partner. The following
1820 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1821 * 1999, describes these PAUSE resolution bits and how flow
1822 * control is determined based upon these settings.
1823 * NOTE: DC = Don't Care
1825 * LOCAL DEVICE | LINK PARTNER
1826 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1827 *-------|---------|-------|---------|--------------------
1828 * 0 | 0 | DC | DC | e1000_fc_none
1829 * 0 | 1 | 0 | DC | e1000_fc_none
1830 * 0 | 1 | 1 | 0 | e1000_fc_none
1831 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1832 * 1 | 0 | 0 | DC | e1000_fc_none
1833 * 1 | DC | 1 | DC | e1000_fc_full
1834 * 1 | 1 | 0 | 0 | e1000_fc_none
1835 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1838 /* Are both PAUSE bits set to 1? If so, this implies
1839 * Symmetric Flow Control is enabled at both ends. The
1840 * ASM_DIR bits are irrelevant per the spec.
1842 * For Symmetric Flow Control:
1844 * LOCAL DEVICE | LINK PARTNER
1845 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1846 *-------|---------|-------|---------|--------------------
1847 * 1 | DC | 1 | DC | e1000_fc_full
1850 if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1851 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1852 /* Now we need to check if the user selected RX ONLY
1853 * of pause frames. In this case, we had to advertise
1854 * FULL flow control because we could not advertise RX
1855 * ONLY. Hence, we must now check to see if we need to
1856 * turn OFF the TRANSMISSION of PAUSE frames.
1858 if(hw->original_fc == e1000_fc_full) {
1859 hw->fc = e1000_fc_full;
1860 DEBUGOUT("Flow Control = FULL.\r\n");
1862 hw->fc = e1000_fc_rx_pause;
1863 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1866 /* For receiving PAUSE frames ONLY.
1868 * LOCAL DEVICE | LINK PARTNER
1869 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1870 *-------|---------|-------|---------|--------------------
1871 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1874 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1875 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1876 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1877 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1878 hw->fc = e1000_fc_tx_pause;
1879 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1881 /* For transmitting PAUSE frames ONLY.
1883 * LOCAL DEVICE | LINK PARTNER
1884 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1885 *-------|---------|-------|---------|--------------------
1886 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1889 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1890 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1891 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1892 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1893 hw->fc = e1000_fc_rx_pause;
1894 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1896 /* Per the IEEE spec, at this point flow control should be
1897 * disabled. However, we want to consider that we could
1898 * be connected to a legacy switch that doesn't advertise
1899 * desired flow control, but can be forced on the link
1900 * partner. So if we advertised no flow control, that is
1901 * what we will resolve to. If we advertised some kind of
1902 * receive capability (Rx Pause Only or Full Flow Control)
1903 * and the link partner advertised none, we will configure
1904 * ourselves to enable Rx Flow Control only. We can do
1905 * this safely for two reasons: If the link partner really
1906 * didn't want flow control enabled, and we enable Rx, no
1907 * harm done since we won't be receiving any PAUSE frames
1908 * anyway. If the intent on the link partner was to have
1909 * flow control enabled, then by us enabling RX only, we
1910 * can at least receive pause frames and process them.
1911 * This is a good idea because in most cases, since we are
1912 * predominantly a server NIC, more times than not we will
1913 * be asked to delay transmission of packets than asking
1914 * our link partner to pause transmission of frames.
1916 else if((hw->original_fc == e1000_fc_none ||
1917 hw->original_fc == e1000_fc_tx_pause) ||
1918 hw->fc_strict_ieee) {
1919 hw->fc = e1000_fc_none;
1920 DEBUGOUT("Flow Control = NONE.\r\n");
1922 hw->fc = e1000_fc_rx_pause;
1923 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1926 /* Now we need to do one last check... If we auto-
1927 * negotiated to HALF DUPLEX, flow control should not be
1928 * enabled per IEEE 802.3 spec.
1930 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
1932 DEBUGOUT("Error getting link speed and duplex\n");
1936 if(duplex == HALF_DUPLEX)
1937 hw->fc = e1000_fc_none;
1939 /* Now we call a subroutine to actually force the MAC
1940 * controller to use the correct flow control settings.
1942 ret_val = e1000_force_mac_fc(hw);
1944 DEBUGOUT("Error forcing flow control settings\n");
1948 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
1951 return E1000_SUCCESS;
1954 /******************************************************************************
1955 * Checks to see if the link status of the hardware has changed.
1957 * hw - Struct containing variables accessed by shared code
1959 * Called by any function that needs to check the link status of the adapter.
1960 *****************************************************************************/
1962 e1000_check_for_link(struct e1000_hw *hw)
1968 uint32_t signal = 0;
1972 DEBUGFUNC("e1000_check_for_link");
1974 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
1975 * set when the optics detect a signal. On older adapters, it will be
1976 * cleared when there is a signal. This applies to fiber media only.
1978 if(hw->media_type == e1000_media_type_fiber)
1979 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1981 ctrl = E1000_READ_REG(hw, CTRL);
1982 status = E1000_READ_REG(hw, STATUS);
1983 rxcw = E1000_READ_REG(hw, RXCW);
1985 /* If we have a copper PHY then we only want to go out to the PHY
1986 * registers to see if Auto-Neg has completed and/or if our link
1987 * status has changed. The get_link_status flag will be set if we
1988 * receive a Link Status Change interrupt or we have Rx Sequence
1991 if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
1992 /* First we want to see if the MII Status Register reports
1993 * link. If so, then we want to get the current speed/duplex
1995 * Read the register twice since the link bit is sticky.
1997 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2000 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2004 if(phy_data & MII_SR_LINK_STATUS) {
2005 hw->get_link_status = FALSE;
2006 /* Check if there was DownShift, must be checked immediately after
2008 e1000_check_downshift(hw);
2011 /* No link detected */
2012 e1000_config_dsp_after_link_change(hw, FALSE);
2016 /* If we are forcing speed/duplex, then we simply return since
2017 * we have already determined whether we have link or not.
2019 if(!hw->autoneg) return -E1000_ERR_CONFIG;
2021 /* optimize the dsp settings for the igp phy */
2022 e1000_config_dsp_after_link_change(hw, TRUE);
2024 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2025 * have Si on board that is 82544 or newer, Auto
2026 * Speed Detection takes care of MAC speed/duplex
2027 * configuration. So we only need to configure Collision
2028 * Distance in the MAC. Otherwise, we need to force
2029 * speed/duplex on the MAC to the current PHY speed/duplex
2032 if(hw->mac_type >= e1000_82544)
2033 e1000_config_collision_dist(hw);
2035 ret_val = e1000_config_mac_to_phy(hw);
2037 DEBUGOUT("Error configuring MAC to PHY settings\n");
2042 /* Configure Flow Control now that Auto-Neg has completed. First, we
2043 * need to restore the desired flow control settings because we may
2044 * have had to re-autoneg with a different link partner.
2046 ret_val = e1000_config_fc_after_link_up(hw);
2048 DEBUGOUT("Error configuring flow control\n");
2052 /* At this point we know that we are on copper and we have
2053 * auto-negotiated link. These are conditions for checking the link
2054 * partner capability register. We use the link speed to determine if
2055 * TBI compatibility needs to be turned on or off. If the link is not
2056 * at gigabit speed, then TBI compatibility is not needed. If we are
2057 * at gigabit speed, we turn on TBI compatibility.
2059 if(hw->tbi_compatibility_en) {
2060 uint16_t speed, duplex;
2061 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2062 if(speed != SPEED_1000) {
2063 /* If link speed is not set to gigabit speed, we do not need
2064 * to enable TBI compatibility.
2066 if(hw->tbi_compatibility_on) {
2067 /* If we previously were in the mode, turn it off. */
2068 rctl = E1000_READ_REG(hw, RCTL);
2069 rctl &= ~E1000_RCTL_SBP;
2070 E1000_WRITE_REG(hw, RCTL, rctl);
2071 hw->tbi_compatibility_on = FALSE;
2074 /* If TBI compatibility is was previously off, turn it on. For
2075 * compatibility with a TBI link partner, we will store bad
2076 * packets. Some frames have an additional byte on the end and
2077 * will look like CRC errors to to the hardware.
2079 if(!hw->tbi_compatibility_on) {
2080 hw->tbi_compatibility_on = TRUE;
2081 rctl = E1000_READ_REG(hw, RCTL);
2082 rctl |= E1000_RCTL_SBP;
2083 E1000_WRITE_REG(hw, RCTL, rctl);
2088 /* If we don't have link (auto-negotiation failed or link partner cannot
2089 * auto-negotiate), the cable is plugged in (we have signal), and our
2090 * link partner is not trying to auto-negotiate with us (we are receiving
2091 * idles or data), we need to force link up. We also need to give
2092 * auto-negotiation time to complete, in case the cable was just plugged
2093 * in. The autoneg_failed flag does this.
2095 else if((((hw->media_type == e1000_media_type_fiber) &&
2096 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2097 (hw->media_type == e1000_media_type_internal_serdes)) &&
2098 (!(status & E1000_STATUS_LU)) &&
2099 (!(rxcw & E1000_RXCW_C))) {
2100 if(hw->autoneg_failed == 0) {
2101 hw->autoneg_failed = 1;
2104 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2106 /* Disable auto-negotiation in the TXCW register */
2107 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2109 /* Force link-up and also force full-duplex. */
2110 ctrl = E1000_READ_REG(hw, CTRL);
2111 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2112 E1000_WRITE_REG(hw, CTRL, ctrl);
2114 /* Configure Flow Control after forcing link up. */
2115 ret_val = e1000_config_fc_after_link_up(hw);
2117 DEBUGOUT("Error configuring flow control\n");
2121 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2122 * auto-negotiation in the TXCW register and disable forced link in the
2123 * Device Control register in an attempt to auto-negotiate with our link
2126 else if(((hw->media_type == e1000_media_type_fiber) ||
2127 (hw->media_type == e1000_media_type_internal_serdes)) &&
2128 (ctrl & E1000_CTRL_SLU) &&
2129 (rxcw & E1000_RXCW_C)) {
2130 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2131 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2132 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2134 hw->serdes_link_down = FALSE;
2136 /* If we force link for non-auto-negotiation switch, check link status
2137 * based on MAC synchronization for internal serdes media type.
2139 else if((hw->media_type == e1000_media_type_internal_serdes) &&
2140 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2141 /* SYNCH bit and IV bit are sticky. */
2143 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2144 if(!(rxcw & E1000_RXCW_IV)) {
2145 hw->serdes_link_down = FALSE;
2146 DEBUGOUT("SERDES: Link is up.\n");
2149 hw->serdes_link_down = TRUE;
2150 DEBUGOUT("SERDES: Link is down.\n");
2153 if((hw->media_type == e1000_media_type_internal_serdes) &&
2154 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2155 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
2157 return E1000_SUCCESS;
2160 /******************************************************************************
2161 * Detects the current speed and duplex settings of the hardware.
2163 * hw - Struct containing variables accessed by shared code
2164 * speed - Speed of the connection
2165 * duplex - Duplex setting of the connection
2166 *****************************************************************************/
2168 e1000_get_speed_and_duplex(struct e1000_hw *hw,
2176 DEBUGFUNC("e1000_get_speed_and_duplex");
2178 if(hw->mac_type >= e1000_82543) {
2179 status = E1000_READ_REG(hw, STATUS);
2180 if(status & E1000_STATUS_SPEED_1000) {
2181 *speed = SPEED_1000;
2182 DEBUGOUT("1000 Mbs, ");
2183 } else if(status & E1000_STATUS_SPEED_100) {
2185 DEBUGOUT("100 Mbs, ");
2188 DEBUGOUT("10 Mbs, ");
2191 if(status & E1000_STATUS_FD) {
2192 *duplex = FULL_DUPLEX;
2193 DEBUGOUT("Full Duplex\r\n");
2195 *duplex = HALF_DUPLEX;
2196 DEBUGOUT(" Half Duplex\r\n");
2199 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2200 *speed = SPEED_1000;
2201 *duplex = FULL_DUPLEX;
2204 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2205 * if it is operating at half duplex. Here we set the duplex settings to
2206 * match the duplex in the link partner's capabilities.
2208 if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2209 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2213 if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2214 *duplex = HALF_DUPLEX;
2216 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2219 if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2220 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2221 *duplex = HALF_DUPLEX;
2225 return E1000_SUCCESS;
2228 /******************************************************************************
2229 * Blocks until autoneg completes or times out (~4.5 seconds)
2231 * hw - Struct containing variables accessed by shared code
2232 ******************************************************************************/
2234 e1000_wait_autoneg(struct e1000_hw *hw)
2240 DEBUGFUNC("e1000_wait_autoneg");
2241 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2243 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2244 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2245 /* Read the MII Status Register and wait for Auto-Neg
2246 * Complete bit to be set.
2248 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2251 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2254 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2255 return E1000_SUCCESS;
2259 return E1000_SUCCESS;
2262 /******************************************************************************
2263 * Raises the Management Data Clock
2265 * hw - Struct containing variables accessed by shared code
2266 * ctrl - Device control register's current value
2267 ******************************************************************************/
2269 e1000_raise_mdi_clk(struct e1000_hw *hw,
2272 /* Raise the clock input to the Management Data Clock (by setting the MDC
2273 * bit), and then delay 10 microseconds.
2275 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2276 E1000_WRITE_FLUSH(hw);
2280 /******************************************************************************
2281 * Lowers the Management Data Clock
2283 * hw - Struct containing variables accessed by shared code
2284 * ctrl - Device control register's current value
2285 ******************************************************************************/
2287 e1000_lower_mdi_clk(struct e1000_hw *hw,
2290 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2291 * bit), and then delay 10 microseconds.
2293 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2294 E1000_WRITE_FLUSH(hw);
2298 /******************************************************************************
2299 * Shifts data bits out to the PHY
2301 * hw - Struct containing variables accessed by shared code
2302 * data - Data to send out to the PHY
2303 * count - Number of bits to shift out
2305 * Bits are shifted out in MSB to LSB order.
2306 ******************************************************************************/
2308 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
2315 /* We need to shift "count" number of bits out to the PHY. So, the value
2316 * in the "data" parameter will be shifted out to the PHY one bit at a
2317 * time. In order to do this, "data" must be broken down into bits.
2320 mask <<= (count - 1);
2322 ctrl = E1000_READ_REG(hw, CTRL);
2324 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2325 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2328 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2329 * then raising and lowering the Management Data Clock. A "0" is
2330 * shifted out to the PHY by setting the MDIO bit to "0" and then
2331 * raising and lowering the clock.
2333 if(data & mask) ctrl |= E1000_CTRL_MDIO;
2334 else ctrl &= ~E1000_CTRL_MDIO;
2336 E1000_WRITE_REG(hw, CTRL, ctrl);
2337 E1000_WRITE_FLUSH(hw);
2341 e1000_raise_mdi_clk(hw, &ctrl);
2342 e1000_lower_mdi_clk(hw, &ctrl);
2348 /******************************************************************************
2349 * Shifts data bits in from the PHY
2351 * hw - Struct containing variables accessed by shared code
2353 * Bits are shifted in in MSB to LSB order.
2354 ******************************************************************************/
2356 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2362 /* In order to read a register from the PHY, we need to shift in a total
2363 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2364 * to avoid contention on the MDIO pin when a read operation is performed.
2365 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2366 * by raising the input to the Management Data Clock (setting the MDC bit),
2367 * and then reading the value of the MDIO bit.
2369 ctrl = E1000_READ_REG(hw, CTRL);
2371 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2372 ctrl &= ~E1000_CTRL_MDIO_DIR;
2373 ctrl &= ~E1000_CTRL_MDIO;
2375 E1000_WRITE_REG(hw, CTRL, ctrl);
2376 E1000_WRITE_FLUSH(hw);
2378 /* Raise and Lower the clock before reading in the data. This accounts for
2379 * the turnaround bits. The first clock occurred when we clocked out the
2380 * last bit of the Register Address.
2382 e1000_raise_mdi_clk(hw, &ctrl);
2383 e1000_lower_mdi_clk(hw, &ctrl);
2385 for(data = 0, i = 0; i < 16; i++) {
2387 e1000_raise_mdi_clk(hw, &ctrl);
2388 ctrl = E1000_READ_REG(hw, CTRL);
2389 /* Check to see if we shifted in a "1". */
2390 if(ctrl & E1000_CTRL_MDIO) data |= 1;
2391 e1000_lower_mdi_clk(hw, &ctrl);
2394 e1000_raise_mdi_clk(hw, &ctrl);
2395 e1000_lower_mdi_clk(hw, &ctrl);
2400 /*****************************************************************************
2401 * Reads the value from a PHY register, if the value is on a specific non zero
2402 * page, sets the page first.
2403 * hw - Struct containing variables accessed by shared code
2404 * reg_addr - address of the PHY register to read
2405 ******************************************************************************/
2407 e1000_read_phy_reg(struct e1000_hw *hw,
2413 DEBUGFUNC("e1000_read_phy_reg");
2415 if(hw->phy_type == e1000_phy_igp &&
2416 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2417 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2418 (uint16_t)reg_addr);
2423 ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2430 e1000_read_phy_reg_ex(struct e1000_hw *hw,
2436 const uint32_t phy_addr = 1;
2438 DEBUGFUNC("e1000_read_phy_reg_ex");
2440 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2441 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2442 return -E1000_ERR_PARAM;
2445 if(hw->mac_type > e1000_82543) {
2446 /* Set up Op-code, Phy Address, and register address in the MDI
2447 * Control register. The MAC will take care of interfacing with the
2448 * PHY to retrieve the desired data.
2450 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2451 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2452 (E1000_MDIC_OP_READ));
2454 E1000_WRITE_REG(hw, MDIC, mdic);
2456 /* Poll the ready bit to see if the MDI read completed */
2457 for(i = 0; i < 64; i++) {
2459 mdic = E1000_READ_REG(hw, MDIC);
2460 if(mdic & E1000_MDIC_READY) break;
2462 if(!(mdic & E1000_MDIC_READY)) {
2463 DEBUGOUT("MDI Read did not complete\n");
2464 return -E1000_ERR_PHY;
2466 if(mdic & E1000_MDIC_ERROR) {
2467 DEBUGOUT("MDI Error\n");
2468 return -E1000_ERR_PHY;
2470 *phy_data = (uint16_t) mdic;
2472 /* We must first send a preamble through the MDIO pin to signal the
2473 * beginning of an MII instruction. This is done by sending 32
2474 * consecutive "1" bits.
2476 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2478 /* Now combine the next few fields that are required for a read
2479 * operation. We use this method instead of calling the
2480 * e1000_shift_out_mdi_bits routine five different times. The format of
2481 * a MII read instruction consists of a shift out of 14 bits and is
2482 * defined as follows:
2483 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2484 * followed by a shift in of 18 bits. This first two bits shifted in
2485 * are TurnAround bits used to avoid contention on the MDIO pin when a
2486 * READ operation is performed. These two bits are thrown away
2487 * followed by a shift in of 16 bits which contains the desired data.
2489 mdic = ((reg_addr) | (phy_addr << 5) |
2490 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2492 e1000_shift_out_mdi_bits(hw, mdic, 14);
2494 /* Now that we've shifted out the read command to the MII, we need to
2495 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2498 *phy_data = e1000_shift_in_mdi_bits(hw);
2500 return E1000_SUCCESS;
2503 /******************************************************************************
2504 * Writes a value to a PHY register
2506 * hw - Struct containing variables accessed by shared code
2507 * reg_addr - address of the PHY register to write
2508 * data - data to write to the PHY
2509 ******************************************************************************/
2511 e1000_write_phy_reg(struct e1000_hw *hw,
2517 DEBUGFUNC("e1000_write_phy_reg");
2519 if(hw->phy_type == e1000_phy_igp &&
2520 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2521 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2522 (uint16_t)reg_addr);
2527 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2534 e1000_write_phy_reg_ex(struct e1000_hw *hw,
2540 const uint32_t phy_addr = 1;
2542 DEBUGFUNC("e1000_write_phy_reg_ex");
2544 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2545 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2546 return -E1000_ERR_PARAM;
2549 if(hw->mac_type > e1000_82543) {
2550 /* Set up Op-code, Phy Address, register address, and data intended
2551 * for the PHY register in the MDI Control register. The MAC will take
2552 * care of interfacing with the PHY to send the desired data.
2554 mdic = (((uint32_t) phy_data) |
2555 (reg_addr << E1000_MDIC_REG_SHIFT) |
2556 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2557 (E1000_MDIC_OP_WRITE));
2559 E1000_WRITE_REG(hw, MDIC, mdic);
2561 /* Poll the ready bit to see if the MDI read completed */
2562 for(i = 0; i < 640; i++) {
2564 mdic = E1000_READ_REG(hw, MDIC);
2565 if(mdic & E1000_MDIC_READY) break;
2567 if(!(mdic & E1000_MDIC_READY)) {
2568 DEBUGOUT("MDI Write did not complete\n");
2569 return -E1000_ERR_PHY;
2572 /* We'll need to use the SW defined pins to shift the write command
2573 * out to the PHY. We first send a preamble to the PHY to signal the
2574 * beginning of the MII instruction. This is done by sending 32
2575 * consecutive "1" bits.
2577 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2579 /* Now combine the remaining required fields that will indicate a
2580 * write operation. We use this method instead of calling the
2581 * e1000_shift_out_mdi_bits routine for each field in the command. The
2582 * format of a MII write instruction is as follows:
2583 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2585 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2586 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2588 mdic |= (uint32_t) phy_data;
2590 e1000_shift_out_mdi_bits(hw, mdic, 32);
2593 return E1000_SUCCESS;
2596 /******************************************************************************
2597 * Returns the PHY to the power-on reset state
2599 * hw - Struct containing variables accessed by shared code
2600 ******************************************************************************/
2602 e1000_phy_hw_reset(struct e1000_hw *hw)
2604 uint32_t ctrl, ctrl_ext;
2607 DEBUGFUNC("e1000_phy_hw_reset");
2609 DEBUGOUT("Resetting Phy...\n");
2611 if(hw->mac_type > e1000_82543) {
2612 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2613 * bit. Then, take it out of reset.
2615 ctrl = E1000_READ_REG(hw, CTRL);
2616 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
2617 E1000_WRITE_FLUSH(hw);
2619 E1000_WRITE_REG(hw, CTRL, ctrl);
2620 E1000_WRITE_FLUSH(hw);
2622 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2623 * bit to put the PHY into reset. Then, take it out of reset.
2625 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2626 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2627 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2628 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2629 E1000_WRITE_FLUSH(hw);
2631 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2632 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2633 E1000_WRITE_FLUSH(hw);
2637 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2638 /* Configure activity LED after PHY reset */
2639 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2640 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2641 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2642 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2646 /******************************************************************************
2649 * hw - Struct containing variables accessed by shared code
2651 * Sets bit 15 of the MII Control regiser
2652 ******************************************************************************/
2654 e1000_phy_reset(struct e1000_hw *hw)
2659 DEBUGFUNC("e1000_phy_reset");
2661 if(hw->mac_type != e1000_82541_rev_2) {
2662 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2666 phy_data |= MII_CR_RESET;
2667 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2672 } else e1000_phy_hw_reset(hw);
2674 if(hw->phy_type == e1000_phy_igp)
2675 e1000_phy_init_script(hw);
2677 return E1000_SUCCESS;
2680 /******************************************************************************
2681 * Probes the expected PHY address for known PHY IDs
2683 * hw - Struct containing variables accessed by shared code
2684 ******************************************************************************/
2686 e1000_detect_gig_phy(struct e1000_hw *hw)
2688 int32_t phy_init_status, ret_val;
2689 uint16_t phy_id_high, phy_id_low;
2690 boolean_t match = FALSE;
2692 DEBUGFUNC("e1000_detect_gig_phy");
2694 /* Read the PHY ID Registers to identify which PHY is onboard. */
2695 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
2699 hw->phy_id = (uint32_t) (phy_id_high << 16);
2701 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
2705 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2706 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
2708 switch(hw->mac_type) {
2710 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
2713 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
2717 case e1000_82545_rev_3:
2719 case e1000_82546_rev_3:
2720 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
2723 case e1000_82541_rev_2:
2725 case e1000_82547_rev_2:
2726 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
2729 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2730 return -E1000_ERR_CONFIG;
2732 phy_init_status = e1000_set_phy_type(hw);
2734 if ((match) && (phy_init_status == E1000_SUCCESS)) {
2735 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
2736 return E1000_SUCCESS;
2738 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
2739 return -E1000_ERR_PHY;
2742 /******************************************************************************
2743 * Resets the PHY's DSP
2745 * hw - Struct containing variables accessed by shared code
2746 ******************************************************************************/
2748 e1000_phy_reset_dsp(struct e1000_hw *hw)
2751 DEBUGFUNC("e1000_phy_reset_dsp");
2754 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
2756 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
2758 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
2760 ret_val = E1000_SUCCESS;
2766 /******************************************************************************
2767 * Get PHY information from various PHY registers for igp PHY only.
2769 * hw - Struct containing variables accessed by shared code
2770 * phy_info - PHY information structure
2771 ******************************************************************************/
2773 e1000_phy_igp_get_info(struct e1000_hw *hw,
2774 struct e1000_phy_info *phy_info)
2777 uint16_t phy_data, polarity, min_length, max_length, average;
2779 DEBUGFUNC("e1000_phy_igp_get_info");
2781 /* The downshift status is checked only once, after link is established,
2782 * and it stored in the hw->speed_downgraded parameter. */
2783 phy_info->downshift = hw->speed_downgraded;
2785 /* IGP01E1000 does not need to support it. */
2786 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
2788 /* IGP01E1000 always correct polarity reversal */
2789 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
2791 /* Check polarity status */
2792 ret_val = e1000_check_polarity(hw, &polarity);
2796 phy_info->cable_polarity = polarity;
2798 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
2802 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
2803 IGP01E1000_PSSR_MDIX_SHIFT;
2805 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
2806 IGP01E1000_PSSR_SPEED_1000MBPS) {
2807 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
2808 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
2812 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2813 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2814 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2815 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2817 /* Get cable length */
2818 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
2822 /* transalte to old method */
2823 average = (max_length + min_length) / 2;
2825 if(average <= e1000_igp_cable_length_50)
2826 phy_info->cable_length = e1000_cable_length_50;
2827 else if(average <= e1000_igp_cable_length_80)
2828 phy_info->cable_length = e1000_cable_length_50_80;
2829 else if(average <= e1000_igp_cable_length_110)
2830 phy_info->cable_length = e1000_cable_length_80_110;
2831 else if(average <= e1000_igp_cable_length_140)
2832 phy_info->cable_length = e1000_cable_length_110_140;
2834 phy_info->cable_length = e1000_cable_length_140;
2837 return E1000_SUCCESS;
2840 /******************************************************************************
2841 * Get PHY information from various PHY registers fot m88 PHY only.
2843 * hw - Struct containing variables accessed by shared code
2844 * phy_info - PHY information structure
2845 ******************************************************************************/
2847 e1000_phy_m88_get_info(struct e1000_hw *hw,
2848 struct e1000_phy_info *phy_info)
2851 uint16_t phy_data, polarity;
2853 DEBUGFUNC("e1000_phy_m88_get_info");
2855 /* The downshift status is checked only once, after link is established,
2856 * and it stored in the hw->speed_downgraded parameter. */
2857 phy_info->downshift = hw->speed_downgraded;
2859 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2863 phy_info->extended_10bt_distance =
2864 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
2865 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
2866 phy_info->polarity_correction =
2867 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
2868 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
2870 /* Check polarity status */
2871 ret_val = e1000_check_polarity(hw, &polarity);
2875 phy_info->cable_polarity = polarity;
2877 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2881 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
2882 M88E1000_PSSR_MDIX_SHIFT;
2884 if(phy_data & M88E1000_PSSR_1000MBS) {
2885 /* Cable Length Estimation and Local/Remote Receiver Informatoion
2886 * are only valid at 1000 Mbps
2888 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2889 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2891 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
2895 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2896 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2898 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2899 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2902 return E1000_SUCCESS;
2905 /******************************************************************************
2906 * Get PHY information from various PHY registers
2908 * hw - Struct containing variables accessed by shared code
2909 * phy_info - PHY information structure
2910 ******************************************************************************/
2912 e1000_phy_get_info(struct e1000_hw *hw,
2913 struct e1000_phy_info *phy_info)
2918 DEBUGFUNC("e1000_phy_get_info");
2920 phy_info->cable_length = e1000_cable_length_undefined;
2921 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
2922 phy_info->cable_polarity = e1000_rev_polarity_undefined;
2923 phy_info->downshift = e1000_downshift_undefined;
2924 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
2925 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
2926 phy_info->local_rx = e1000_1000t_rx_status_undefined;
2927 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
2929 if(hw->media_type != e1000_media_type_copper) {
2930 DEBUGOUT("PHY info is only valid for copper media\n");
2931 return -E1000_ERR_CONFIG;
2934 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2938 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2942 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
2943 DEBUGOUT("PHY info is only valid if link is up\n");
2944 return -E1000_ERR_CONFIG;
2947 if(hw->phy_type == e1000_phy_igp)
2948 return e1000_phy_igp_get_info(hw, phy_info);
2950 return e1000_phy_m88_get_info(hw, phy_info);
2954 e1000_validate_mdi_setting(struct e1000_hw *hw)
2956 DEBUGFUNC("e1000_validate_mdi_settings");
2958 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
2959 DEBUGOUT("Invalid MDI setting detected\n");
2961 return -E1000_ERR_CONFIG;
2963 return E1000_SUCCESS;
2967 /******************************************************************************
2968 * Sets up eeprom variables in the hw struct. Must be called after mac_type
2971 * hw - Struct containing variables accessed by shared code
2972 *****************************************************************************/
2974 e1000_init_eeprom_params(struct e1000_hw *hw)
2976 struct e1000_eeprom_info *eeprom = &hw->eeprom;
2977 uint32_t eecd = E1000_READ_REG(hw, EECD);
2978 uint16_t eeprom_size;
2980 DEBUGFUNC("e1000_init_eeprom_params");
2982 switch (hw->mac_type) {
2983 case e1000_82542_rev2_0:
2984 case e1000_82542_rev2_1:
2987 eeprom->type = e1000_eeprom_microwire;
2988 eeprom->word_size = 64;
2989 eeprom->opcode_bits = 3;
2990 eeprom->address_bits = 6;
2991 eeprom->delay_usec = 50;
2995 case e1000_82545_rev_3:
2997 case e1000_82546_rev_3:
2998 eeprom->type = e1000_eeprom_microwire;
2999 eeprom->opcode_bits = 3;
3000 eeprom->delay_usec = 50;
3001 if(eecd & E1000_EECD_SIZE) {
3002 eeprom->word_size = 256;
3003 eeprom->address_bits = 8;
3005 eeprom->word_size = 64;
3006 eeprom->address_bits = 6;
3010 case e1000_82541_rev_2:
3012 case e1000_82547_rev_2:
3013 if (eecd & E1000_EECD_TYPE) {
3014 eeprom->type = e1000_eeprom_spi;
3015 eeprom->opcode_bits = 8;
3016 eeprom->delay_usec = 1;
3017 if (eecd & E1000_EECD_ADDR_BITS) {
3018 eeprom->page_size = 32;
3019 eeprom->address_bits = 16;
3021 eeprom->page_size = 8;
3022 eeprom->address_bits = 8;
3025 eeprom->type = e1000_eeprom_microwire;
3026 eeprom->opcode_bits = 3;
3027 eeprom->delay_usec = 50;
3028 if (eecd & E1000_EECD_ADDR_BITS) {
3029 eeprom->word_size = 256;
3030 eeprom->address_bits = 8;
3032 eeprom->word_size = 64;
3033 eeprom->address_bits = 6;
3038 eeprom->type = e1000_eeprom_spi;
3039 eeprom->opcode_bits = 8;
3040 eeprom->delay_usec = 1;
3041 if (eecd & E1000_EECD_ADDR_BITS) {
3042 eeprom->page_size = 32;
3043 eeprom->address_bits = 16;
3045 eeprom->page_size = 8;
3046 eeprom->address_bits = 8;
3051 if (eeprom->type == e1000_eeprom_spi) {
3052 eeprom->word_size = 64;
3053 if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
3054 eeprom_size &= EEPROM_SIZE_MASK;
3056 switch (eeprom_size) {
3057 case EEPROM_SIZE_16KB:
3058 eeprom->word_size = 8192;
3060 case EEPROM_SIZE_8KB:
3061 eeprom->word_size = 4096;
3063 case EEPROM_SIZE_4KB:
3064 eeprom->word_size = 2048;
3066 case EEPROM_SIZE_2KB:
3067 eeprom->word_size = 1024;
3069 case EEPROM_SIZE_1KB:
3070 eeprom->word_size = 512;
3072 case EEPROM_SIZE_512B:
3073 eeprom->word_size = 256;
3075 case EEPROM_SIZE_128B:
3077 eeprom->word_size = 64;
3084 /******************************************************************************
3085 * Raises the EEPROM's clock input.
3087 * hw - Struct containing variables accessed by shared code
3088 * eecd - EECD's current value
3089 *****************************************************************************/
3091 e1000_raise_ee_clk(struct e1000_hw *hw,
3094 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3095 * wait <delay> microseconds.
3097 *eecd = *eecd | E1000_EECD_SK;
3098 E1000_WRITE_REG(hw, EECD, *eecd);
3099 E1000_WRITE_FLUSH(hw);
3100 udelay(hw->eeprom.delay_usec);
3103 /******************************************************************************
3104 * Lowers the EEPROM's clock input.
3106 * hw - Struct containing variables accessed by shared code
3107 * eecd - EECD's current value
3108 *****************************************************************************/
3110 e1000_lower_ee_clk(struct e1000_hw *hw,
3113 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3114 * wait 50 microseconds.
3116 *eecd = *eecd & ~E1000_EECD_SK;
3117 E1000_WRITE_REG(hw, EECD, *eecd);
3118 E1000_WRITE_FLUSH(hw);
3119 udelay(hw->eeprom.delay_usec);
3122 /******************************************************************************
3123 * Shift data bits out to the EEPROM.
3125 * hw - Struct containing variables accessed by shared code
3126 * data - data to send to the EEPROM
3127 * count - number of bits to shift out
3128 *****************************************************************************/
3130 e1000_shift_out_ee_bits(struct e1000_hw *hw,
3134 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3138 /* We need to shift "count" bits out to the EEPROM. So, value in the
3139 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3140 * In order to do this, "data" must be broken down into bits.
3142 mask = 0x01 << (count - 1);
3143 eecd = E1000_READ_REG(hw, EECD);
3144 if (eeprom->type == e1000_eeprom_microwire) {
3145 eecd &= ~E1000_EECD_DO;
3146 } else if (eeprom->type == e1000_eeprom_spi) {
3147 eecd |= E1000_EECD_DO;
3150 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3151 * and then raising and then lowering the clock (the SK bit controls
3152 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3153 * by setting "DI" to "0" and then raising and then lowering the clock.
3155 eecd &= ~E1000_EECD_DI;
3158 eecd |= E1000_EECD_DI;
3160 E1000_WRITE_REG(hw, EECD, eecd);
3161 E1000_WRITE_FLUSH(hw);
3163 udelay(eeprom->delay_usec);
3165 e1000_raise_ee_clk(hw, &eecd);
3166 e1000_lower_ee_clk(hw, &eecd);
3172 /* We leave the "DI" bit set to "0" when we leave this routine. */
3173 eecd &= ~E1000_EECD_DI;
3174 E1000_WRITE_REG(hw, EECD, eecd);
3177 /******************************************************************************
3178 * Shift data bits in from the EEPROM
3180 * hw - Struct containing variables accessed by shared code
3181 *****************************************************************************/
3183 e1000_shift_in_ee_bits(struct e1000_hw *hw,
3190 /* In order to read a register from the EEPROM, we need to shift 'count'
3191 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3192 * input to the EEPROM (setting the SK bit), and then reading the value of
3193 * the "DO" bit. During this "shifting in" process the "DI" bit should
3197 eecd = E1000_READ_REG(hw, EECD);
3199 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3202 for(i = 0; i < count; i++) {
3204 e1000_raise_ee_clk(hw, &eecd);
3206 eecd = E1000_READ_REG(hw, EECD);
3208 eecd &= ~(E1000_EECD_DI);
3209 if(eecd & E1000_EECD_DO)
3212 e1000_lower_ee_clk(hw, &eecd);
3218 /******************************************************************************
3219 * Prepares EEPROM for access
3221 * hw - Struct containing variables accessed by shared code
3223 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3224 * function should be called before issuing a command to the EEPROM.
3225 *****************************************************************************/
3227 e1000_acquire_eeprom(struct e1000_hw *hw)
3229 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3232 DEBUGFUNC("e1000_acquire_eeprom");
3234 eecd = E1000_READ_REG(hw, EECD);
3236 /* Request EEPROM Access */
3237 if(hw->mac_type > e1000_82544) {
3238 eecd |= E1000_EECD_REQ;
3239 E1000_WRITE_REG(hw, EECD, eecd);
3240 eecd = E1000_READ_REG(hw, EECD);
3241 while((!(eecd & E1000_EECD_GNT)) &&
3242 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3245 eecd = E1000_READ_REG(hw, EECD);
3247 if(!(eecd & E1000_EECD_GNT)) {
3248 eecd &= ~E1000_EECD_REQ;
3249 E1000_WRITE_REG(hw, EECD, eecd);
3250 DEBUGOUT("Could not acquire EEPROM grant\n");
3251 return -E1000_ERR_EEPROM;
3255 /* Setup EEPROM for Read/Write */
3257 if (eeprom->type == e1000_eeprom_microwire) {
3258 /* Clear SK and DI */
3259 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3260 E1000_WRITE_REG(hw, EECD, eecd);
3263 eecd |= E1000_EECD_CS;
3264 E1000_WRITE_REG(hw, EECD, eecd);
3265 } else if (eeprom->type == e1000_eeprom_spi) {
3266 /* Clear SK and CS */
3267 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3268 E1000_WRITE_REG(hw, EECD, eecd);
3272 return E1000_SUCCESS;
3275 /******************************************************************************
3276 * Returns EEPROM to a "standby" state
3278 * hw - Struct containing variables accessed by shared code
3279 *****************************************************************************/
3281 e1000_standby_eeprom(struct e1000_hw *hw)
3283 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3286 eecd = E1000_READ_REG(hw, EECD);
3288 if(eeprom->type == e1000_eeprom_microwire) {
3289 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3290 E1000_WRITE_REG(hw, EECD, eecd);
3291 E1000_WRITE_FLUSH(hw);
3292 udelay(eeprom->delay_usec);
3295 eecd |= E1000_EECD_SK;
3296 E1000_WRITE_REG(hw, EECD, eecd);
3297 E1000_WRITE_FLUSH(hw);
3298 udelay(eeprom->delay_usec);
3301 eecd |= E1000_EECD_CS;
3302 E1000_WRITE_REG(hw, EECD, eecd);
3303 E1000_WRITE_FLUSH(hw);
3304 udelay(eeprom->delay_usec);
3307 eecd &= ~E1000_EECD_SK;
3308 E1000_WRITE_REG(hw, EECD, eecd);
3309 E1000_WRITE_FLUSH(hw);
3310 udelay(eeprom->delay_usec);
3311 } else if(eeprom->type == e1000_eeprom_spi) {
3312 /* Toggle CS to flush commands */
3313 eecd |= E1000_EECD_CS;
3314 E1000_WRITE_REG(hw, EECD, eecd);
3315 E1000_WRITE_FLUSH(hw);
3316 udelay(eeprom->delay_usec);
3317 eecd &= ~E1000_EECD_CS;
3318 E1000_WRITE_REG(hw, EECD, eecd);
3319 E1000_WRITE_FLUSH(hw);
3320 udelay(eeprom->delay_usec);
3324 /******************************************************************************
3325 * Terminates a command by inverting the EEPROM's chip select pin
3327 * hw - Struct containing variables accessed by shared code
3328 *****************************************************************************/
3330 e1000_release_eeprom(struct e1000_hw *hw)
3334 DEBUGFUNC("e1000_release_eeprom");
3336 eecd = E1000_READ_REG(hw, EECD);
3338 if (hw->eeprom.type == e1000_eeprom_spi) {
3339 eecd |= E1000_EECD_CS; /* Pull CS high */
3340 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3342 E1000_WRITE_REG(hw, EECD, eecd);
3344 udelay(hw->eeprom.delay_usec);
3345 } else if(hw->eeprom.type == e1000_eeprom_microwire) {
3346 /* cleanup eeprom */
3348 /* CS on Microwire is active-high */
3349 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3351 E1000_WRITE_REG(hw, EECD, eecd);
3353 /* Rising edge of clock */
3354 eecd |= E1000_EECD_SK;
3355 E1000_WRITE_REG(hw, EECD, eecd);
3356 E1000_WRITE_FLUSH(hw);
3357 udelay(hw->eeprom.delay_usec);
3359 /* Falling edge of clock */
3360 eecd &= ~E1000_EECD_SK;
3361 E1000_WRITE_REG(hw, EECD, eecd);
3362 E1000_WRITE_FLUSH(hw);
3363 udelay(hw->eeprom.delay_usec);
3366 /* Stop requesting EEPROM access */
3367 if(hw->mac_type > e1000_82544) {
3368 eecd &= ~E1000_EECD_REQ;
3369 E1000_WRITE_REG(hw, EECD, eecd);
3373 /******************************************************************************
3374 * Reads a 16 bit word from the EEPROM.
3376 * hw - Struct containing variables accessed by shared code
3377 *****************************************************************************/
3379 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3381 uint16_t retry_count = 0;
3382 uint8_t spi_stat_reg;
3384 DEBUGFUNC("e1000_spi_eeprom_ready");
3386 /* Read "Status Register" repeatedly until the LSB is cleared. The
3387 * EEPROM will signal that the command has been completed by clearing
3388 * bit 0 of the internal status register. If it's not cleared within
3389 * 5 milliseconds, then error out.
3393 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3394 hw->eeprom.opcode_bits);
3395 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
3396 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3402 e1000_standby_eeprom(hw);
3403 } while(retry_count < EEPROM_MAX_RETRY_SPI);
3405 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3406 * only 0-5mSec on 5V devices)
3408 if(retry_count >= EEPROM_MAX_RETRY_SPI) {
3409 DEBUGOUT("SPI EEPROM Status error\n");
3410 return -E1000_ERR_EEPROM;
3413 return E1000_SUCCESS;
3416 /******************************************************************************
3417 * Reads a 16 bit word from the EEPROM.
3419 * hw - Struct containing variables accessed by shared code
3420 * offset - offset of word in the EEPROM to read
3421 * data - word read from the EEPROM
3422 * words - number of words to read
3423 *****************************************************************************/
3425 e1000_read_eeprom(struct e1000_hw *hw,
3430 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3433 DEBUGFUNC("e1000_read_eeprom");
3435 /* A check for invalid values: offset too large, too many words, and not
3438 if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3440 DEBUGOUT("\"words\" parameter out of bounds\n");
3441 return -E1000_ERR_EEPROM;
3444 /* Prepare the EEPROM for reading */
3445 if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3446 return -E1000_ERR_EEPROM;
3448 if(eeprom->type == e1000_eeprom_spi) {
3450 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
3452 if(e1000_spi_eeprom_ready(hw)) {
3453 e1000_release_eeprom(hw);
3454 return -E1000_ERR_EEPROM;
3457 e1000_standby_eeprom(hw);
3459 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3460 if((eeprom->address_bits == 8) && (offset >= 128))
3461 read_opcode |= EEPROM_A8_OPCODE_SPI;
3463 /* Send the READ command (opcode + addr) */
3464 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3465 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
3467 /* Read the data. The address of the eeprom internally increments with
3468 * each byte (spi) being read, saving on the overhead of eeprom setup
3469 * and tear-down. The address counter will roll over if reading beyond
3470 * the size of the eeprom, thus allowing the entire memory to be read
3471 * starting from any offset. */
3472 for (i = 0; i < words; i++) {
3473 word_in = e1000_shift_in_ee_bits(hw, 16);
3474 data[i] = (word_in >> 8) | (word_in << 8);
3476 } else if(eeprom->type == e1000_eeprom_microwire) {
3477 for (i = 0; i < words; i++) {
3478 /* Send the READ command (opcode + addr) */
3479 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
3480 eeprom->opcode_bits);
3481 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
3482 eeprom->address_bits);
3484 /* Read the data. For microwire, each word requires the overhead
3485 * of eeprom setup and tear-down. */
3486 data[i] = e1000_shift_in_ee_bits(hw, 16);
3487 e1000_standby_eeprom(hw);
3491 /* End this read operation */
3492 e1000_release_eeprom(hw);
3494 return E1000_SUCCESS;
3497 /******************************************************************************
3498 * Verifies that the EEPROM has a valid checksum
3500 * hw - Struct containing variables accessed by shared code
3502 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3503 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3505 *****************************************************************************/
3507 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3509 uint16_t checksum = 0;
3510 uint16_t i, eeprom_data;
3512 DEBUGFUNC("e1000_validate_eeprom_checksum");
3514 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3515 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3516 DEBUGOUT("EEPROM Read Error\n");
3517 return -E1000_ERR_EEPROM;
3519 checksum += eeprom_data;
3522 if(checksum == (uint16_t) EEPROM_SUM)
3523 return E1000_SUCCESS;
3525 DEBUGOUT("EEPROM Checksum Invalid\n");
3526 return -E1000_ERR_EEPROM;
3530 /******************************************************************************
3531 * Calculates the EEPROM checksum and writes it to the EEPROM
3533 * hw - Struct containing variables accessed by shared code
3535 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
3536 * Writes the difference to word offset 63 of the EEPROM.
3537 *****************************************************************************/
3539 e1000_update_eeprom_checksum(struct e1000_hw *hw)
3541 uint16_t checksum = 0;
3542 uint16_t i, eeprom_data;
3544 DEBUGFUNC("e1000_update_eeprom_checksum");
3546 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3547 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3548 DEBUGOUT("EEPROM Read Error\n");
3549 return -E1000_ERR_EEPROM;
3551 checksum += eeprom_data;
3553 checksum = (uint16_t) EEPROM_SUM - checksum;
3554 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3555 DEBUGOUT("EEPROM Write Error\n");
3556 return -E1000_ERR_EEPROM;
3558 return E1000_SUCCESS;
3561 /******************************************************************************
3562 * Parent function for writing words to the different EEPROM types.
3564 * hw - Struct containing variables accessed by shared code
3565 * offset - offset within the EEPROM to be written to
3566 * words - number of words to write
3567 * data - 16 bit word to be written to the EEPROM
3569 * If e1000_update_eeprom_checksum is not called after this function, the
3570 * EEPROM will most likely contain an invalid checksum.
3571 *****************************************************************************/
3573 e1000_write_eeprom(struct e1000_hw *hw,
3578 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3581 DEBUGFUNC("e1000_write_eeprom");
3583 /* A check for invalid values: offset too large, too many words, and not
3586 if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3588 DEBUGOUT("\"words\" parameter out of bounds\n");
3589 return -E1000_ERR_EEPROM;
3592 /* Prepare the EEPROM for writing */
3593 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3594 return -E1000_ERR_EEPROM;
3596 if(eeprom->type == e1000_eeprom_microwire) {
3597 status = e1000_write_eeprom_microwire(hw, offset, words, data);
3599 status = e1000_write_eeprom_spi(hw, offset, words, data);
3603 /* Done with writing */
3604 e1000_release_eeprom(hw);
3609 /******************************************************************************
3610 * Writes a 16 bit word to a given offset in an SPI EEPROM.
3612 * hw - Struct containing variables accessed by shared code
3613 * offset - offset within the EEPROM to be written to
3614 * words - number of words to write
3615 * data - pointer to array of 8 bit words to be written to the EEPROM
3617 *****************************************************************************/
3619 e1000_write_eeprom_spi(struct e1000_hw *hw,
3624 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3627 DEBUGFUNC("e1000_write_eeprom_spi");
3629 while (widx < words) {
3630 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
3632 if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
3634 e1000_standby_eeprom(hw);
3636 /* Send the WRITE ENABLE command (8 bit opcode ) */
3637 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
3638 eeprom->opcode_bits);
3640 e1000_standby_eeprom(hw);
3642 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3643 if((eeprom->address_bits == 8) && (offset >= 128))
3644 write_opcode |= EEPROM_A8_OPCODE_SPI;
3646 /* Send the Write command (8-bit opcode + addr) */
3647 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
3649 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
3650 eeprom->address_bits);
3654 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
3655 while (widx < words) {
3656 uint16_t word_out = data[widx];
3657 word_out = (word_out >> 8) | (word_out << 8);
3658 e1000_shift_out_ee_bits(hw, word_out, 16);
3661 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
3662 * operation, while the smaller eeproms are capable of an 8-byte
3663 * PAGE WRITE operation. Break the inner loop to pass new address
3665 if((((offset + widx)*2) % eeprom->page_size) == 0) {
3666 e1000_standby_eeprom(hw);
3672 return E1000_SUCCESS;
3675 /******************************************************************************
3676 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
3678 * hw - Struct containing variables accessed by shared code
3679 * offset - offset within the EEPROM to be written to
3680 * words - number of words to write
3681 * data - pointer to array of 16 bit words to be written to the EEPROM
3683 *****************************************************************************/
3685 e1000_write_eeprom_microwire(struct e1000_hw *hw,
3690 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3692 uint16_t words_written = 0;
3695 DEBUGFUNC("e1000_write_eeprom_microwire");
3697 /* Send the write enable command to the EEPROM (3-bit opcode plus
3698 * 6/8-bit dummy address beginning with 11). It's less work to include
3699 * the 11 of the dummy address as part of the opcode than it is to shift
3700 * it over the correct number of bits for the address. This puts the
3701 * EEPROM into write/erase mode.
3703 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
3704 (uint16_t)(eeprom->opcode_bits + 2));
3706 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
3708 /* Prepare the EEPROM */
3709 e1000_standby_eeprom(hw);
3711 while (words_written < words) {
3712 /* Send the Write command (3-bit opcode + addr) */
3713 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
3714 eeprom->opcode_bits);
3716 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
3717 eeprom->address_bits);
3720 e1000_shift_out_ee_bits(hw, data[words_written], 16);
3722 /* Toggle the CS line. This in effect tells the EEPROM to execute
3723 * the previous command.
3725 e1000_standby_eeprom(hw);
3727 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
3728 * signal that the command has been completed by raising the DO signal.
3729 * If DO does not go high in 10 milliseconds, then error out.
3731 for(i = 0; i < 200; i++) {
3732 eecd = E1000_READ_REG(hw, EECD);
3733 if(eecd & E1000_EECD_DO) break;
3737 DEBUGOUT("EEPROM Write did not complete\n");
3738 return -E1000_ERR_EEPROM;
3741 /* Recover from write */
3742 e1000_standby_eeprom(hw);
3747 /* Send the write disable command to the EEPROM (3-bit opcode plus
3748 * 6/8-bit dummy address beginning with 10). It's less work to include
3749 * the 10 of the dummy address as part of the opcode than it is to shift
3750 * it over the correct number of bits for the address. This takes the
3751 * EEPROM out of write/erase mode.
3753 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
3754 (uint16_t)(eeprom->opcode_bits + 2));
3756 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
3758 return E1000_SUCCESS;
3761 /******************************************************************************
3762 * Reads the adapter's part number from the EEPROM
3764 * hw - Struct containing variables accessed by shared code
3765 * part_num - Adapter's part number
3766 *****************************************************************************/
3768 e1000_read_part_num(struct e1000_hw *hw,
3771 uint16_t offset = EEPROM_PBA_BYTE_1;
3772 uint16_t eeprom_data;
3774 DEBUGFUNC("e1000_read_part_num");
3776 /* Get word 0 from EEPROM */
3777 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3778 DEBUGOUT("EEPROM Read Error\n");
3779 return -E1000_ERR_EEPROM;
3781 /* Save word 0 in upper half of part_num */
3782 *part_num = (uint32_t) (eeprom_data << 16);
3784 /* Get word 1 from EEPROM */
3785 if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
3786 DEBUGOUT("EEPROM Read Error\n");
3787 return -E1000_ERR_EEPROM;
3789 /* Save word 1 in lower half of part_num */
3790 *part_num |= eeprom_data;
3792 return E1000_SUCCESS;
3795 /******************************************************************************
3796 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
3797 * second function of dual function devices
3799 * hw - Struct containing variables accessed by shared code
3800 *****************************************************************************/
3802 e1000_read_mac_addr(struct e1000_hw * hw)
3805 uint16_t eeprom_data, i;
3807 DEBUGFUNC("e1000_read_mac_addr");
3809 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
3811 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3812 DEBUGOUT("EEPROM Read Error\n");
3813 return -E1000_ERR_EEPROM;
3815 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
3816 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
3818 if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
3819 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
3820 hw->perm_mac_addr[5] ^= 0x01;
3822 for(i = 0; i < NODE_ADDRESS_SIZE; i++)
3823 hw->mac_addr[i] = hw->perm_mac_addr[i];
3824 return E1000_SUCCESS;
3827 /******************************************************************************
3828 * Initializes receive address filters.
3830 * hw - Struct containing variables accessed by shared code
3832 * Places the MAC address in receive address register 0 and clears the rest
3833 * of the receive addresss registers. Clears the multicast table. Assumes
3834 * the receiver is in reset when the routine is called.
3835 *****************************************************************************/
3837 e1000_init_rx_addrs(struct e1000_hw *hw)
3841 DEBUGFUNC("e1000_init_rx_addrs");
3843 /* Setup the receive address. */
3844 DEBUGOUT("Programming MAC Address into RAR[0]\n");
3846 e1000_rar_set(hw, hw->mac_addr, 0);
3848 /* Zero out the other 15 receive addresses. */
3849 DEBUGOUT("Clearing RAR[1-15]\n");
3850 for(i = 1; i < E1000_RAR_ENTRIES; i++) {
3851 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3852 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3856 /******************************************************************************
3857 * Updates the MAC's list of multicast addresses.
3859 * hw - Struct containing variables accessed by shared code
3860 * mc_addr_list - the list of new multicast addresses
3861 * mc_addr_count - number of addresses
3862 * pad - number of bytes between addresses in the list
3863 * rar_used_count - offset where to start adding mc addresses into the RAR's
3865 * The given list replaces any existing list. Clears the last 15 receive
3866 * address registers and the multicast table. Uses receive address registers
3867 * for the first 15 multicast addresses, and hashes the rest into the
3869 *****************************************************************************/
3871 e1000_mc_addr_list_update(struct e1000_hw *hw,
3872 uint8_t *mc_addr_list,
3873 uint32_t mc_addr_count,
3875 uint32_t rar_used_count)
3877 uint32_t hash_value;
3880 DEBUGFUNC("e1000_mc_addr_list_update");
3882 /* Set the new number of MC addresses that we are being requested to use. */
3883 hw->num_mc_addrs = mc_addr_count;
3885 /* Clear RAR[1-15] */
3886 DEBUGOUT(" Clearing RAR[1-15]\n");
3887 for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) {
3888 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3889 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3893 DEBUGOUT(" Clearing MTA\n");
3894 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) {
3895 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
3898 /* Add the new addresses */
3899 for(i = 0; i < mc_addr_count; i++) {
3900 DEBUGOUT(" Adding the multicast addresses:\n");
3901 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
3902 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
3903 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
3904 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
3905 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
3906 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
3907 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
3909 hash_value = e1000_hash_mc_addr(hw,
3911 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
3913 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
3915 /* Place this multicast address in the RAR if there is room, *
3916 * else put it in the MTA
3918 if(rar_used_count < E1000_RAR_ENTRIES) {
3920 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
3924 e1000_mta_set(hw, hash_value);
3927 DEBUGOUT("MC Update Complete\n");
3930 /******************************************************************************
3931 * Hashes an address to determine its location in the multicast table
3933 * hw - Struct containing variables accessed by shared code
3934 * mc_addr - the multicast address to hash
3935 *****************************************************************************/
3937 e1000_hash_mc_addr(struct e1000_hw *hw,
3940 uint32_t hash_value = 0;
3942 /* The portion of the address that is used for the hash table is
3943 * determined by the mc_filter_type setting.
3945 switch (hw->mc_filter_type) {
3946 /* [0] [1] [2] [3] [4] [5]
3951 /* [47:36] i.e. 0x563 for above example address */
3952 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
3955 /* [46:35] i.e. 0xAC6 for above example address */
3956 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
3959 /* [45:34] i.e. 0x5D8 for above example address */
3960 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
3963 /* [43:32] i.e. 0x634 for above example address */
3964 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
3968 hash_value &= 0xFFF;
3972 /******************************************************************************
3973 * Sets the bit in the multicast table corresponding to the hash value.
3975 * hw - Struct containing variables accessed by shared code
3976 * hash_value - Multicast address hash value
3977 *****************************************************************************/
3979 e1000_mta_set(struct e1000_hw *hw,
3980 uint32_t hash_value)
3982 uint32_t hash_bit, hash_reg;
3986 /* The MTA is a register array of 128 32-bit registers.
3987 * It is treated like an array of 4096 bits. We want to set
3988 * bit BitArray[hash_value]. So we figure out what register
3989 * the bit is in, read it, OR in the new bit, then write
3990 * back the new value. The register is determined by the
3991 * upper 7 bits of the hash value and the bit within that
3992 * register are determined by the lower 5 bits of the value.
3994 hash_reg = (hash_value >> 5) & 0x7F;
3995 hash_bit = hash_value & 0x1F;
3997 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
3999 mta |= (1 << hash_bit);
4001 /* If we are on an 82544 and we are trying to write an odd offset
4002 * in the MTA, save off the previous entry before writing and
4003 * restore the old value after writing.
4005 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
4006 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
4007 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4008 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
4010 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4014 /******************************************************************************
4015 * Puts an ethernet address into a receive address register.
4017 * hw - Struct containing variables accessed by shared code
4018 * addr - Address to put into receive address register
4019 * index - Receive address register to write
4020 *****************************************************************************/
4022 e1000_rar_set(struct e1000_hw *hw,
4026 uint32_t rar_low, rar_high;
4028 /* HW expects these in little endian so we reverse the byte order
4029 * from network order (big endian) to little endian
4031 rar_low = ((uint32_t) addr[0] |
4032 ((uint32_t) addr[1] << 8) |
4033 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
4035 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV);
4037 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4038 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4041 /******************************************************************************
4042 * Writes a value to the specified offset in the VLAN filter table.
4044 * hw - Struct containing variables accessed by shared code
4045 * offset - Offset in VLAN filer table to write
4046 * value - Value to write into VLAN filter table
4047 *****************************************************************************/
4049 e1000_write_vfta(struct e1000_hw *hw,
4055 if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4056 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4057 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4058 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4060 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4064 /******************************************************************************
4065 * Clears the VLAN filer table
4067 * hw - Struct containing variables accessed by shared code
4068 *****************************************************************************/
4070 e1000_clear_vfta(struct e1000_hw *hw)
4074 for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
4075 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
4079 e1000_id_led_init(struct e1000_hw * hw)
4082 const uint32_t ledctl_mask = 0x000000FF;
4083 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4084 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4085 uint16_t eeprom_data, i, temp;
4086 const uint16_t led_mask = 0x0F;
4088 DEBUGFUNC("e1000_id_led_init");
4090 if(hw->mac_type < e1000_82540) {
4092 return E1000_SUCCESS;
4095 ledctl = E1000_READ_REG(hw, LEDCTL);
4096 hw->ledctl_default = ledctl;
4097 hw->ledctl_mode1 = hw->ledctl_default;
4098 hw->ledctl_mode2 = hw->ledctl_default;
4100 if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4101 DEBUGOUT("EEPROM Read Error\n");
4102 return -E1000_ERR_EEPROM;
4104 if((eeprom_data== ID_LED_RESERVED_0000) ||
4105 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
4106 for(i = 0; i < 4; i++) {
4107 temp = (eeprom_data >> (i << 2)) & led_mask;
4109 case ID_LED_ON1_DEF2:
4110 case ID_LED_ON1_ON2:
4111 case ID_LED_ON1_OFF2:
4112 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4113 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4115 case ID_LED_OFF1_DEF2:
4116 case ID_LED_OFF1_ON2:
4117 case ID_LED_OFF1_OFF2:
4118 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4119 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4126 case ID_LED_DEF1_ON2:
4127 case ID_LED_ON1_ON2:
4128 case ID_LED_OFF1_ON2:
4129 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4130 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4132 case ID_LED_DEF1_OFF2:
4133 case ID_LED_ON1_OFF2:
4134 case ID_LED_OFF1_OFF2:
4135 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4136 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4143 return E1000_SUCCESS;
4146 /******************************************************************************
4147 * Prepares SW controlable LED for use and saves the current state of the LED.
4149 * hw - Struct containing variables accessed by shared code
4150 *****************************************************************************/
4152 e1000_setup_led(struct e1000_hw *hw)
4155 int32_t ret_val = E1000_SUCCESS;
4157 DEBUGFUNC("e1000_setup_led");
4159 switch(hw->mac_type) {
4160 case e1000_82542_rev2_0:
4161 case e1000_82542_rev2_1:
4164 /* No setup necessary */
4168 case e1000_82541_rev_2:
4169 case e1000_82547_rev_2:
4170 /* Turn off PHY Smart Power Down (if enabled) */
4171 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4172 &hw->phy_spd_default);
4175 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4176 (uint16_t)(hw->phy_spd_default &
4177 ~IGP01E1000_GMII_SPD));
4182 if(hw->media_type == e1000_media_type_fiber) {
4183 ledctl = E1000_READ_REG(hw, LEDCTL);
4184 /* Save current LEDCTL settings */
4185 hw->ledctl_default = ledctl;
4187 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4188 E1000_LEDCTL_LED0_BLINK |
4189 E1000_LEDCTL_LED0_MODE_MASK);
4190 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4191 E1000_LEDCTL_LED0_MODE_SHIFT);
4192 E1000_WRITE_REG(hw, LEDCTL, ledctl);
4193 } else if(hw->media_type == e1000_media_type_copper)
4194 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
4198 return E1000_SUCCESS;
4201 /******************************************************************************
4202 * Restores the saved state of the SW controlable LED.
4204 * hw - Struct containing variables accessed by shared code
4205 *****************************************************************************/
4207 e1000_cleanup_led(struct e1000_hw *hw)
4209 int32_t ret_val = E1000_SUCCESS;
4211 DEBUGFUNC("e1000_cleanup_led");
4213 switch(hw->mac_type) {
4214 case e1000_82542_rev2_0:
4215 case e1000_82542_rev2_1:
4218 /* No cleanup necessary */
4222 case e1000_82541_rev_2:
4223 case e1000_82547_rev_2:
4224 /* Turn on PHY Smart Power Down (if previously enabled) */
4225 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4226 hw->phy_spd_default);
4231 /* Restore LEDCTL settings */
4232 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
4236 return E1000_SUCCESS;
4239 /******************************************************************************
4240 * Turns on the software controllable LED
4242 * hw - Struct containing variables accessed by shared code
4243 *****************************************************************************/
4245 e1000_led_on(struct e1000_hw *hw)
4247 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4249 DEBUGFUNC("e1000_led_on");
4251 switch(hw->mac_type) {
4252 case e1000_82542_rev2_0:
4253 case e1000_82542_rev2_1:
4255 /* Set SW Defineable Pin 0 to turn on the LED */
4256 ctrl |= E1000_CTRL_SWDPIN0;
4257 ctrl |= E1000_CTRL_SWDPIO0;
4260 if(hw->media_type == e1000_media_type_fiber) {
4261 /* Set SW Defineable Pin 0 to turn on the LED */
4262 ctrl |= E1000_CTRL_SWDPIN0;
4263 ctrl |= E1000_CTRL_SWDPIO0;
4265 /* Clear SW Defineable Pin 0 to turn on the LED */
4266 ctrl &= ~E1000_CTRL_SWDPIN0;
4267 ctrl |= E1000_CTRL_SWDPIO0;
4271 if(hw->media_type == e1000_media_type_fiber) {
4272 /* Clear SW Defineable Pin 0 to turn on the LED */
4273 ctrl &= ~E1000_CTRL_SWDPIN0;
4274 ctrl |= E1000_CTRL_SWDPIO0;
4275 } else if(hw->media_type == e1000_media_type_copper) {
4276 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
4277 return E1000_SUCCESS;
4282 E1000_WRITE_REG(hw, CTRL, ctrl);
4284 return E1000_SUCCESS;
4287 /******************************************************************************
4288 * Turns off the software controllable LED
4290 * hw - Struct containing variables accessed by shared code
4291 *****************************************************************************/
4293 e1000_led_off(struct e1000_hw *hw)
4295 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4297 DEBUGFUNC("e1000_led_off");
4299 switch(hw->mac_type) {
4300 case e1000_82542_rev2_0:
4301 case e1000_82542_rev2_1:
4303 /* Clear SW Defineable Pin 0 to turn off the LED */
4304 ctrl &= ~E1000_CTRL_SWDPIN0;
4305 ctrl |= E1000_CTRL_SWDPIO0;
4308 if(hw->media_type == e1000_media_type_fiber) {
4309 /* Clear SW Defineable Pin 0 to turn off the LED */
4310 ctrl &= ~E1000_CTRL_SWDPIN0;
4311 ctrl |= E1000_CTRL_SWDPIO0;
4313 /* Set SW Defineable Pin 0 to turn off the LED */
4314 ctrl |= E1000_CTRL_SWDPIN0;
4315 ctrl |= E1000_CTRL_SWDPIO0;
4319 if(hw->media_type == e1000_media_type_fiber) {
4320 /* Set SW Defineable Pin 0 to turn off the LED */
4321 ctrl |= E1000_CTRL_SWDPIN0;
4322 ctrl |= E1000_CTRL_SWDPIO0;
4323 } else if(hw->media_type == e1000_media_type_copper) {
4324 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
4325 return E1000_SUCCESS;
4330 E1000_WRITE_REG(hw, CTRL, ctrl);
4332 return E1000_SUCCESS;
4335 /******************************************************************************
4336 * Clears all hardware statistics counters.
4338 * hw - Struct containing variables accessed by shared code
4339 *****************************************************************************/
4341 e1000_clear_hw_cntrs(struct e1000_hw *hw)
4343 volatile uint32_t temp;
4345 temp = E1000_READ_REG(hw, CRCERRS);
4346 temp = E1000_READ_REG(hw, SYMERRS);
4347 temp = E1000_READ_REG(hw, MPC);
4348 temp = E1000_READ_REG(hw, SCC);
4349 temp = E1000_READ_REG(hw, ECOL);
4350 temp = E1000_READ_REG(hw, MCC);
4351 temp = E1000_READ_REG(hw, LATECOL);
4352 temp = E1000_READ_REG(hw, COLC);
4353 temp = E1000_READ_REG(hw, DC);
4354 temp = E1000_READ_REG(hw, SEC);
4355 temp = E1000_READ_REG(hw, RLEC);
4356 temp = E1000_READ_REG(hw, XONRXC);
4357 temp = E1000_READ_REG(hw, XONTXC);
4358 temp = E1000_READ_REG(hw, XOFFRXC);
4359 temp = E1000_READ_REG(hw, XOFFTXC);
4360 temp = E1000_READ_REG(hw, FCRUC);
4361 temp = E1000_READ_REG(hw, PRC64);
4362 temp = E1000_READ_REG(hw, PRC127);
4363 temp = E1000_READ_REG(hw, PRC255);
4364 temp = E1000_READ_REG(hw, PRC511);
4365 temp = E1000_READ_REG(hw, PRC1023);
4366 temp = E1000_READ_REG(hw, PRC1522);
4367 temp = E1000_READ_REG(hw, GPRC);
4368 temp = E1000_READ_REG(hw, BPRC);
4369 temp = E1000_READ_REG(hw, MPRC);
4370 temp = E1000_READ_REG(hw, GPTC);
4371 temp = E1000_READ_REG(hw, GORCL);
4372 temp = E1000_READ_REG(hw, GORCH);
4373 temp = E1000_READ_REG(hw, GOTCL);
4374 temp = E1000_READ_REG(hw, GOTCH);
4375 temp = E1000_READ_REG(hw, RNBC);
4376 temp = E1000_READ_REG(hw, RUC);
4377 temp = E1000_READ_REG(hw, RFC);
4378 temp = E1000_READ_REG(hw, ROC);
4379 temp = E1000_READ_REG(hw, RJC);
4380 temp = E1000_READ_REG(hw, TORL);
4381 temp = E1000_READ_REG(hw, TORH);
4382 temp = E1000_READ_REG(hw, TOTL);
4383 temp = E1000_READ_REG(hw, TOTH);
4384 temp = E1000_READ_REG(hw, TPR);
4385 temp = E1000_READ_REG(hw, TPT);
4386 temp = E1000_READ_REG(hw, PTC64);
4387 temp = E1000_READ_REG(hw, PTC127);
4388 temp = E1000_READ_REG(hw, PTC255);
4389 temp = E1000_READ_REG(hw, PTC511);
4390 temp = E1000_READ_REG(hw, PTC1023);
4391 temp = E1000_READ_REG(hw, PTC1522);
4392 temp = E1000_READ_REG(hw, MPTC);
4393 temp = E1000_READ_REG(hw, BPTC);
4395 if(hw->mac_type < e1000_82543) return;
4397 temp = E1000_READ_REG(hw, ALGNERRC);
4398 temp = E1000_READ_REG(hw, RXERRC);
4399 temp = E1000_READ_REG(hw, TNCRS);
4400 temp = E1000_READ_REG(hw, CEXTERR);
4401 temp = E1000_READ_REG(hw, TSCTC);
4402 temp = E1000_READ_REG(hw, TSCTFC);
4404 if(hw->mac_type <= e1000_82544) return;
4406 temp = E1000_READ_REG(hw, MGTPRC);
4407 temp = E1000_READ_REG(hw, MGTPDC);
4408 temp = E1000_READ_REG(hw, MGTPTC);
4411 /******************************************************************************
4412 * Resets Adaptive IFS to its default state.
4414 * hw - Struct containing variables accessed by shared code
4416 * Call this after e1000_init_hw. You may override the IFS defaults by setting
4417 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
4418 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4419 * before calling this function.
4420 *****************************************************************************/
4422 e1000_reset_adaptive(struct e1000_hw *hw)
4424 DEBUGFUNC("e1000_reset_adaptive");
4426 if(hw->adaptive_ifs) {
4427 if(!hw->ifs_params_forced) {
4428 hw->current_ifs_val = 0;
4429 hw->ifs_min_val = IFS_MIN;
4430 hw->ifs_max_val = IFS_MAX;
4431 hw->ifs_step_size = IFS_STEP;
4432 hw->ifs_ratio = IFS_RATIO;
4434 hw->in_ifs_mode = FALSE;
4435 E1000_WRITE_REG(hw, AIT, 0);
4437 DEBUGOUT("Not in Adaptive IFS mode!\n");
4441 /******************************************************************************
4442 * Called during the callback/watchdog routine to update IFS value based on
4443 * the ratio of transmits to collisions.
4445 * hw - Struct containing variables accessed by shared code
4446 * tx_packets - Number of transmits since last callback
4447 * total_collisions - Number of collisions since last callback
4448 *****************************************************************************/
4450 e1000_update_adaptive(struct e1000_hw *hw)
4452 DEBUGFUNC("e1000_update_adaptive");
4454 if(hw->adaptive_ifs) {
4455 if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
4456 if(hw->tx_packet_delta > MIN_NUM_XMITS) {
4457 hw->in_ifs_mode = TRUE;
4458 if(hw->current_ifs_val < hw->ifs_max_val) {
4459 if(hw->current_ifs_val == 0)
4460 hw->current_ifs_val = hw->ifs_min_val;
4462 hw->current_ifs_val += hw->ifs_step_size;
4463 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
4467 if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4468 hw->current_ifs_val = 0;
4469 hw->in_ifs_mode = FALSE;
4470 E1000_WRITE_REG(hw, AIT, 0);
4474 DEBUGOUT("Not in Adaptive IFS mode!\n");
4478 /******************************************************************************
4479 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
4481 * hw - Struct containing variables accessed by shared code
4482 * frame_len - The length of the frame in question
4483 * mac_addr - The Ethernet destination address of the frame in question
4484 *****************************************************************************/
4486 e1000_tbi_adjust_stats(struct e1000_hw *hw,
4487 struct e1000_hw_stats *stats,
4493 /* First adjust the frame length. */
4495 /* We need to adjust the statistics counters, since the hardware
4496 * counters overcount this packet as a CRC error and undercount
4497 * the packet as a good packet
4499 /* This packet should not be counted as a CRC error. */
4501 /* This packet does count as a Good Packet Received. */
4504 /* Adjust the Good Octets received counters */
4505 carry_bit = 0x80000000 & stats->gorcl;
4506 stats->gorcl += frame_len;
4507 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
4508 * Received Count) was one before the addition,
4509 * AND it is zero after, then we lost the carry out,
4510 * need to add one to Gorch (Good Octets Received Count High).
4511 * This could be simplified if all environments supported
4514 if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
4516 /* Is this a broadcast or multicast? Check broadcast first,
4517 * since the test for a multicast frame will test positive on
4518 * a broadcast frame.
4520 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
4521 /* Broadcast packet */
4523 else if(*mac_addr & 0x01)
4524 /* Multicast packet */
4527 if(frame_len == hw->max_frame_size) {
4528 /* In this case, the hardware has overcounted the number of
4535 /* Adjust the bin counters when the extra byte put the frame in the
4536 * wrong bin. Remember that the frame_len was adjusted above.
4538 if(frame_len == 64) {
4541 } else if(frame_len == 127) {
4544 } else if(frame_len == 255) {
4547 } else if(frame_len == 511) {
4550 } else if(frame_len == 1023) {
4553 } else if(frame_len == 1522) {
4558 /******************************************************************************
4559 * Gets the current PCI bus type, speed, and width of the hardware
4561 * hw - Struct containing variables accessed by shared code
4562 *****************************************************************************/
4564 e1000_get_bus_info(struct e1000_hw *hw)
4568 if(hw->mac_type < e1000_82543) {
4569 hw->bus_type = e1000_bus_type_unknown;
4570 hw->bus_speed = e1000_bus_speed_unknown;
4571 hw->bus_width = e1000_bus_width_unknown;
4575 status = E1000_READ_REG(hw, STATUS);
4576 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4577 e1000_bus_type_pcix : e1000_bus_type_pci;
4579 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4580 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4581 e1000_bus_speed_66 : e1000_bus_speed_120;
4582 } else if(hw->bus_type == e1000_bus_type_pci) {
4583 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4584 e1000_bus_speed_66 : e1000_bus_speed_33;
4586 switch (status & E1000_STATUS_PCIX_SPEED) {
4587 case E1000_STATUS_PCIX_SPEED_66:
4588 hw->bus_speed = e1000_bus_speed_66;
4590 case E1000_STATUS_PCIX_SPEED_100:
4591 hw->bus_speed = e1000_bus_speed_100;
4593 case E1000_STATUS_PCIX_SPEED_133:
4594 hw->bus_speed = e1000_bus_speed_133;
4597 hw->bus_speed = e1000_bus_speed_reserved;
4601 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4602 e1000_bus_width_64 : e1000_bus_width_32;
4604 /******************************************************************************
4605 * Reads a value from one of the devices registers using port I/O (as opposed
4606 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4608 * hw - Struct containing variables accessed by shared code
4609 * offset - offset to read from
4610 *****************************************************************************/
4612 e1000_read_reg_io(struct e1000_hw *hw,
4615 unsigned long io_addr = hw->io_base;
4616 unsigned long io_data = hw->io_base + 4;
4618 e1000_io_write(hw, io_addr, offset);
4619 return e1000_io_read(hw, io_data);
4622 /******************************************************************************
4623 * Writes a value to one of the devices registers using port I/O (as opposed to
4624 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4626 * hw - Struct containing variables accessed by shared code
4627 * offset - offset to write to
4628 * value - value to write
4629 *****************************************************************************/
4631 e1000_write_reg_io(struct e1000_hw *hw,
4635 unsigned long io_addr = hw->io_base;
4636 unsigned long io_data = hw->io_base + 4;
4638 e1000_io_write(hw, io_addr, offset);
4639 e1000_io_write(hw, io_data, value);
4643 /******************************************************************************
4644 * Estimates the cable length.
4646 * hw - Struct containing variables accessed by shared code
4647 * min_length - The estimated minimum length
4648 * max_length - The estimated maximum length
4650 * returns: - E1000_ERR_XXX
4653 * This function always returns a ranged length (minimum & maximum).
4654 * So for M88 phy's, this function interprets the one value returned from the
4655 * register to the minimum and maximum range.
4656 * For IGP phy's, the function calculates the range by the AGC registers.
4657 *****************************************************************************/
4659 e1000_get_cable_length(struct e1000_hw *hw,
4660 uint16_t *min_length,
4661 uint16_t *max_length)
4664 uint16_t agc_value = 0;
4665 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
4666 uint16_t i, phy_data;
4668 DEBUGFUNC("e1000_get_cable_length");
4670 *min_length = *max_length = 0;
4672 /* Use old method for Phy older than IGP */
4673 if(hw->phy_type == e1000_phy_m88) {
4674 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4679 /* Convert the enum value to ranged values */
4680 switch((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4681 M88E1000_PSSR_CABLE_LENGTH_SHIFT) {
4682 case e1000_cable_length_50:
4684 *max_length = e1000_igp_cable_length_50;
4686 case e1000_cable_length_50_80:
4687 *min_length = e1000_igp_cable_length_50;
4688 *max_length = e1000_igp_cable_length_80;
4690 case e1000_cable_length_80_110:
4691 *min_length = e1000_igp_cable_length_80;
4692 *max_length = e1000_igp_cable_length_110;
4694 case e1000_cable_length_110_140:
4695 *min_length = e1000_igp_cable_length_110;
4696 *max_length = e1000_igp_cable_length_140;
4698 case e1000_cable_length_140:
4699 *min_length = e1000_igp_cable_length_140;
4700 *max_length = e1000_igp_cable_length_170;
4703 return -E1000_ERR_PHY;
4706 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
4707 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
4708 {IGP01E1000_PHY_AGC_A,
4709 IGP01E1000_PHY_AGC_B,
4710 IGP01E1000_PHY_AGC_C,
4711 IGP01E1000_PHY_AGC_D};
4712 /* Read the AGC registers for all channels */
4713 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4715 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
4719 cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
4721 /* Array bound check. */
4722 if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
4724 return -E1000_ERR_PHY;
4726 agc_value += cur_agc;
4728 /* Update minimal AGC value. */
4729 if(min_agc > cur_agc)
4733 /* Remove the minimal AGC result for length < 50m */
4734 if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
4735 agc_value -= min_agc;
4737 /* Get the average length of the remaining 3 channels */
4738 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
4740 /* Get the average length of all the 4 channels. */
4741 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
4744 /* Set the range of the calculated length. */
4745 *min_length = ((e1000_igp_cable_length_table[agc_value] -
4746 IGP01E1000_AGC_RANGE) > 0) ?
4747 (e1000_igp_cable_length_table[agc_value] -
4748 IGP01E1000_AGC_RANGE) : 0;
4749 *max_length = e1000_igp_cable_length_table[agc_value] +
4750 IGP01E1000_AGC_RANGE;
4753 return E1000_SUCCESS;
4756 /******************************************************************************
4757 * Check the cable polarity
4759 * hw - Struct containing variables accessed by shared code
4760 * polarity - output parameter : 0 - Polarity is not reversed
4761 * 1 - Polarity is reversed.
4763 * returns: - E1000_ERR_XXX
4766 * For phy's older then IGP, this function simply reads the polarity bit in the
4767 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
4768 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
4769 * return 0. If the link speed is 1000 Mbps the polarity status is in the
4770 * IGP01E1000_PHY_PCS_INIT_REG.
4771 *****************************************************************************/
4773 e1000_check_polarity(struct e1000_hw *hw,
4779 DEBUGFUNC("e1000_check_polarity");
4781 if(hw->phy_type == e1000_phy_m88) {
4782 /* return the Polarity bit in the Status register. */
4783 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4787 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
4788 M88E1000_PSSR_REV_POLARITY_SHIFT;
4789 } else if(hw->phy_type == e1000_phy_igp) {
4790 /* Read the Status register to check the speed */
4791 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
4796 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
4797 * find the polarity status */
4798 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4799 IGP01E1000_PSSR_SPEED_1000MBPS) {
4801 /* Read the GIG initialization PCS register (0x00B4) */
4802 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
4807 /* Check the polarity bits */
4808 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
4810 /* For 10 Mbps, read the polarity bit in the status register. (for
4811 * 100 Mbps this bit is always 0) */
4812 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
4815 return E1000_SUCCESS;
4818 /******************************************************************************
4819 * Check if Downshift occured
4821 * hw - Struct containing variables accessed by shared code
4822 * downshift - output parameter : 0 - No Downshift ocured.
4823 * 1 - Downshift ocured.
4825 * returns: - E1000_ERR_XXX
4828 * For phy's older then IGP, this function reads the Downshift bit in the Phy
4829 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
4830 * Link Health register. In IGP this bit is latched high, so the driver must
4831 * read it immediately after link is established.
4832 *****************************************************************************/
4834 e1000_check_downshift(struct e1000_hw *hw)
4839 DEBUGFUNC("e1000_check_downshift");
4841 if(hw->phy_type == e1000_phy_igp) {
4842 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
4847 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
4849 else if(hw->phy_type == e1000_phy_m88) {
4850 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4855 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
4856 M88E1000_PSSR_DOWNSHIFT_SHIFT;
4858 return E1000_SUCCESS;
4861 /*****************************************************************************
4863 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
4864 * gigabit link is achieved to improve link quality.
4866 * hw: Struct containing variables accessed by shared code
4868 * returns: - E1000_ERR_PHY if fail to read/write the PHY
4869 * E1000_SUCCESS at any other case.
4871 ****************************************************************************/
4874 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
4878 uint16_t phy_data, speed, duplex, i;
4879 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
4880 {IGP01E1000_PHY_AGC_PARAM_A,
4881 IGP01E1000_PHY_AGC_PARAM_B,
4882 IGP01E1000_PHY_AGC_PARAM_C,
4883 IGP01E1000_PHY_AGC_PARAM_D};
4884 uint16_t min_length, max_length;
4886 DEBUGFUNC("e1000_config_dsp_after_link_change");
4888 if(hw->phy_type != e1000_phy_igp)
4889 return E1000_SUCCESS;
4892 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
4894 DEBUGOUT("Error getting link speed and duplex\n");
4898 if(speed == SPEED_1000) {
4900 e1000_get_cable_length(hw, &min_length, &max_length);
4902 if((hw->dsp_config_state == e1000_dsp_config_enabled) &&
4903 min_length >= e1000_igp_cable_length_50) {
4905 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4906 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
4911 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
4913 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
4918 hw->dsp_config_state = e1000_dsp_config_activated;
4921 if((hw->ffe_config_state == e1000_ffe_config_enabled) &&
4922 (min_length < e1000_igp_cable_length_50)) {
4924 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
4925 uint32_t idle_errs = 0;
4927 /* clear previous idle error counts */
4928 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
4933 for(i = 0; i < ffe_idle_err_timeout; i++) {
4935 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
4940 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
4941 if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
4942 hw->ffe_config_state = e1000_ffe_config_active;
4944 ret_val = e1000_write_phy_reg(hw,
4945 IGP01E1000_PHY_DSP_FFE,
4946 IGP01E1000_PHY_DSP_FFE_CM_CP);
4953 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
4958 if(hw->dsp_config_state == e1000_dsp_config_activated) {
4959 ret_val = e1000_write_phy_reg(hw, 0x0000,
4960 IGP01E1000_IEEE_FORCE_GIGA);
4963 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4964 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
4968 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
4969 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
4971 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
4976 ret_val = e1000_write_phy_reg(hw, 0x0000,
4977 IGP01E1000_IEEE_RESTART_AUTONEG);
4981 hw->dsp_config_state = e1000_dsp_config_enabled;
4984 if(hw->ffe_config_state == e1000_ffe_config_active) {
4985 ret_val = e1000_write_phy_reg(hw, 0x0000,
4986 IGP01E1000_IEEE_FORCE_GIGA);
4989 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
4990 IGP01E1000_PHY_DSP_FFE_DEFAULT);
4994 ret_val = e1000_write_phy_reg(hw, 0x0000,
4995 IGP01E1000_IEEE_RESTART_AUTONEG);
4998 hw->ffe_config_state = e1000_ffe_config_enabled;
5001 return E1000_SUCCESS;
5004 /*****************************************************************************
5005 * Set PHY to class A mode
5006 * Assumes the following operations will follow to enable the new class mode.
5007 * 1. Do a PHY soft reset
5008 * 2. Restart auto-negotiation or force link.
5010 * hw - Struct containing variables accessed by shared code
5011 ****************************************************************************/
5013 e1000_set_phy_mode(struct e1000_hw *hw)
5016 uint16_t eeprom_data;
5018 DEBUGFUNC("e1000_set_phy_mode");
5020 if((hw->mac_type == e1000_82545_rev_3) &&
5021 (hw->media_type == e1000_media_type_copper)) {
5022 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
5027 if((eeprom_data != EEPROM_RESERVED_WORD) &&
5028 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5029 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
5032 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
5036 hw->phy_reset_disable = FALSE;
5040 return E1000_SUCCESS;
5043 /*****************************************************************************
5045 * This function sets the lplu state according to the active flag. When
5046 * activating lplu this function also disables smart speed and vise versa.
5047 * lplu will not be activated unless the device autonegotiation advertisment
5048 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5049 * hw: Struct containing variables accessed by shared code
5050 * active - true to enable lplu false to disable lplu.
5052 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5053 * E1000_SUCCESS at any other case.
5055 ****************************************************************************/
5058 e1000_set_d3_lplu_state(struct e1000_hw *hw,
5063 DEBUGFUNC("e1000_set_d3_lplu_state");
5065 if(!((hw->mac_type == e1000_82541_rev_2) ||
5066 (hw->mac_type == e1000_82547_rev_2)))
5067 return E1000_SUCCESS;
5069 /* During driver activity LPLU should not be used or it will attain link
5070 * from the lowest speeds starting from 10Mbps. The capability is used for
5071 * Dx transitions and states */
5072 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5077 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5078 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5082 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5083 * Dx states where the power conservation is most important. During
5084 * driver activity we should enable SmartSpeed, so performance is
5086 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
5090 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5091 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
5095 } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
5096 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
5097 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5099 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5100 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5104 /* When LPLU is enabled we should disable SmartSpeed */
5105 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
5109 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5110 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
5115 return E1000_SUCCESS;
5118 /******************************************************************************
5119 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
5121 * hw - Struct containing variables accessed by shared code
5122 *****************************************************************************/
5124 e1000_set_vco_speed(struct e1000_hw *hw)
5127 uint16_t default_page = 0;
5130 DEBUGFUNC("e1000_set_vco_speed");
5132 switch(hw->mac_type) {
5133 case e1000_82545_rev_3:
5134 case e1000_82546_rev_3:
5137 return E1000_SUCCESS;
5140 /* Set PHY register 30, page 5, bit 8 to 0 */
5142 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5146 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5150 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5154 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5155 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5159 /* Set PHY register 30, page 4, bit 11 to 1 */
5161 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5165 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5169 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5170 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5174 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5178 return E1000_SUCCESS;