2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * This version of the driver is specific to the FADS implementation,
6 * since the board contains control registers external to the processor
7 * for the control of the LevelOne LXT970 transceiver. The MPC860T manual
8 * describes connections using the internal parallel port I/O, which
9 * is basically all of Port D.
11 * Right now, I am very watseful with the buffers. I allocate memory
12 * pages and then divide them into 2K frame buffers. This way I know I
13 * have buffers large enough to hold one frame within one buffer descriptor.
14 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
15 * will be much more memory efficient and will easily handle lots of
18 * Much better multiple PHY support by Magnus Damm.
19 * Copyright (c) 2000 Ericsson Radio Systems AB.
21 * Support for FEC controller of ColdFire/5272.
22 * Copyrught (c) 2001-2002 Greg Ungerer (gerg@snapgear.com)
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/kernel.h>
28 #include <linux/string.h>
29 #include <linux/ptrace.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/slab.h>
33 #include <linux/interrupt.h>
34 #include <linux/pci.h>
35 #include <linux/init.h>
36 #include <linux/delay.h>
37 #include <linux/netdevice.h>
38 #include <linux/etherdevice.h>
39 #include <linux/skbuff.h>
40 #include <linux/spinlock.h>
41 #include <linux/workqueue.h>
44 #include <asm/bitops.h>
45 #include <asm/uaccess.h>
47 #include <asm/pgtable.h>
50 #include <asm/coldfire.h>
51 #include <asm/mcfsim.h>
54 #include <asm/8xx_immap.h>
55 #include <asm/mpc8xx.h>
59 static int opened = 0;
63 * Define the fixed address of the FEC hardware.
66 static volatile fec_t *fec_hwp = (volatile fec_t *) (MCF_MBAR + 0x840);
67 static ushort my_enet_addr[] = { 0x00d0, 0xcf00, 0x0072 };
69 static volatile fec_t *fec_hwp = &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec)
70 static ushort my_enet_addr[3];
71 #endif /* CONFIG_M5272 */
74 * Some hardware gets it MAC address out of local flash memory.
75 * if this is non-zero then assume it is the address to get MAC from.
77 #if defined(CONFIG_NETtel)
78 #define FEC_FLASHMAC 0xf0006006
79 #elif defined(CONFIG_GILBARCONAP)
80 #define FEC_FLASHMAC 0xf0006000
81 #elif defined (CONFIG_MTD_KeyTechnology)
82 #define FEC_FLASHMAC 0xffe04000
84 #define FEC_FLASHMAC 0
87 unsigned char *fec_flashmac = (unsigned char *) FEC_FLASHMAC;
89 /* Forward declarations of some structures to support different PHYs
94 void (*funct)(uint mii_reg, struct net_device *dev);
101 const phy_cmd_t *config;
102 const phy_cmd_t *startup;
103 const phy_cmd_t *ack_int;
104 const phy_cmd_t *shutdown;
107 /* The number of Tx and Rx buffers. These are allocated from the page
108 * pool. The code may assume these are power of two, so it it best
109 * to keep them that size.
110 * We don't need to allocate pages for the transmitter. We just use
111 * the skbuffer directly.
114 #define FEC_ENET_RX_PAGES 4
115 #define FEC_ENET_RX_FRSIZE 2048
116 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
117 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
118 #define TX_RING_SIZE 8 /* Must be power of two */
119 #define TX_RING_MOD_MASK 7 /* for this to work */
121 #define FEC_ENET_RX_PAGES 16
122 #define FEC_ENET_RX_FRSIZE 2048
123 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
124 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
125 #define TX_RING_SIZE 16 /* Must be power of two */
126 #define TX_RING_MOD_MASK 15 /* for this to work */
129 /* Interrupt events/masks.
131 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
132 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
133 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
134 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
135 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
136 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
137 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
138 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
139 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
140 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
142 /* The FEC stores dest/src/type, data, and checksum for receive packets.
144 #define PKT_MAXBUF_SIZE 1518
145 #define PKT_MINBUF_SIZE 64
146 #define PKT_MAXBLR_SIZE 1520
148 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
149 * tx_bd_base always point to the base of the buffer descriptors. The
150 * cur_rx and cur_tx point to the currently available buffer.
151 * The dirty_tx tracks the current buffer that is being sent by the
152 * controller. The cur_tx and dirty_tx are equal under both completely
153 * empty and completely full conditions. The empty/ready indicator in
154 * the buffer descriptor determines the actual condition.
156 struct fec_enet_private {
157 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
158 struct sk_buff* tx_skbuff[TX_RING_SIZE];
162 /* CPM dual port RAM relative addresses.
164 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
166 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
167 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
168 struct net_device_stats stats;
177 struct work_struct phy_task;
188 static int fec_enet_open(struct net_device *dev);
189 static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
190 static void fec_enet_mii(struct net_device *dev);
191 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs);
192 static void fec_enet_tx(struct net_device *dev);
193 static void fec_enet_rx(struct net_device *dev);
194 static int fec_enet_close(struct net_device *dev);
195 static struct net_device_stats *fec_enet_get_stats(struct net_device *dev);
196 static void set_multicast_list(struct net_device *dev);
197 static void fec_restart(struct net_device *dev, int duplex);
198 static void fec_stop(struct net_device *dev);
199 static void fec_set_mac_address(struct net_device *dev);
202 /* MII processing. We keep this as simple as possible. Requests are
203 * placed on the list (if there is room). When the request is finished
204 * by the MII, an optional function may be called.
206 typedef struct mii_list {
208 void (*mii_func)(uint val, struct net_device *dev);
209 struct mii_list *mii_next;
213 mii_list_t mii_cmds[NMII];
214 mii_list_t *mii_free;
215 mii_list_t *mii_head;
216 mii_list_t *mii_tail;
218 static int mii_queue(struct net_device *dev, int request,
219 void (*func)(uint, struct net_device *));
221 /* Make MII read/write commands for the FEC.
223 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
224 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
228 /* Transmitter timeout.
230 #define TX_TIMEOUT (2*HZ)
232 /* Register definitions for the PHY.
235 #define MII_REG_CR 0 /* Control Register */
236 #define MII_REG_SR 1 /* Status Register */
237 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
238 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
239 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
240 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
241 #define MII_REG_ANER 6 /* A-N Expansion Register */
242 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
243 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
245 /* values for phy_status */
247 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
248 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
249 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
250 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
251 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
252 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
253 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
255 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
256 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
257 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
258 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
259 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
260 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
261 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
262 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
266 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
268 struct fec_enet_private *fep;
269 volatile fec_t *fecp;
272 fep = netdev_priv(dev);
273 fecp = (volatile fec_t*)dev->base_addr;
276 /* Link is down or autonegotiation is in progress. */
280 /* Fill in a Tx ring entry */
283 #ifndef final_version
284 if (bdp->cbd_sc & BD_ENET_TX_READY) {
285 /* Ooops. All transmit buffers are full. Bail out.
286 * This should not happen, since dev->tbusy should be set.
288 printk("%s: tx queue full!.\n", dev->name);
293 /* Clear all of the status flags.
295 bdp->cbd_sc &= ~BD_ENET_TX_STATS;
297 /* Set buffer length and buffer pointer.
299 bdp->cbd_bufaddr = __pa(skb->data);
300 bdp->cbd_datlen = skb->len;
304 fep->tx_skbuff[fep->skb_cur] = skb;
306 fep->stats.tx_bytes += skb->len;
307 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
309 /* Push the data cache so the CPM does not get stale memory
312 flush_dcache_range((unsigned long)skb->data,
313 (unsigned long)skb->data + skb->len);
315 spin_lock_irq(&fep->lock);
317 /* Send it on its way. Tell FEC its ready, interrupt when done,
318 * its the last BD of the frame, and to put the CRC on the end.
321 bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
322 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
324 dev->trans_start = jiffies;
326 /* Trigger transmission start */
327 fecp->fec_x_des_active = 0x01000000;
329 /* If this was the last BD in the ring, start at the beginning again.
331 if (bdp->cbd_sc & BD_ENET_TX_WRAP) {
332 bdp = fep->tx_bd_base;
337 if (bdp == fep->dirty_tx) {
339 netif_stop_queue(dev);
342 fep->cur_tx = (cbd_t *)bdp;
344 spin_unlock_irq(&fep->lock);
350 fec_timeout(struct net_device *dev)
352 struct fec_enet_private *fep = netdev_priv(dev);
354 printk("%s: transmit timed out.\n", dev->name);
355 fep->stats.tx_errors++;
356 #ifndef final_version
361 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
362 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
363 (unsigned long)fep->dirty_tx,
364 (unsigned long)fep->cur_rx);
366 bdp = fep->tx_bd_base;
367 printk(" tx: %u buffers\n", TX_RING_SIZE);
368 for (i = 0 ; i < TX_RING_SIZE; i++) {
369 printk(" %08x: %04x %04x %08x\n",
373 (int) bdp->cbd_bufaddr);
377 bdp = fep->rx_bd_base;
378 printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
379 for (i = 0 ; i < RX_RING_SIZE; i++) {
380 printk(" %08x: %04x %04x %08x\n",
384 (int) bdp->cbd_bufaddr);
390 netif_wake_queue(dev);
393 /* The interrupt handler.
394 * This is called from the MPC core interrupt.
397 fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
399 struct net_device *dev = dev_id;
400 volatile fec_t *fecp;
404 fecp = (volatile fec_t*)dev->base_addr;
406 /* Get the interrupt events that caused us to be here.
408 while ((int_events = fecp->fec_ievent) != 0) {
409 fecp->fec_ievent = int_events;
410 if ((int_events & (FEC_ENET_HBERR | FEC_ENET_BABR |
411 FEC_ENET_BABT | FEC_ENET_EBERR)) != 0) {
412 printk("FEC ERROR %x\n", int_events);
415 /* Handle receive event in its own function.
417 if (int_events & FEC_ENET_RXF) {
422 /* Transmit OK, or non-fatal error. Update the buffer
423 descriptors. FEC handles all errors, we just discover
424 them as part of the transmit process.
426 if (int_events & FEC_ENET_TXF) {
431 if (int_events & FEC_ENET_MII) {
437 return IRQ_RETVAL(handled);
442 fec_enet_tx(struct net_device *dev)
444 struct fec_enet_private *fep;
448 fep = netdev_priv(dev);
449 spin_lock(&fep->lock);
452 while ((bdp->cbd_sc&BD_ENET_TX_READY) == 0) {
453 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
455 skb = fep->tx_skbuff[fep->skb_dirty];
456 /* Check for errors. */
457 if (bdp->cbd_sc & (BD_ENET_TX_HB | BD_ENET_TX_LC |
458 BD_ENET_TX_RL | BD_ENET_TX_UN |
460 fep->stats.tx_errors++;
461 if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */
462 fep->stats.tx_heartbeat_errors++;
463 if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */
464 fep->stats.tx_window_errors++;
465 if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */
466 fep->stats.tx_aborted_errors++;
467 if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */
468 fep->stats.tx_fifo_errors++;
469 if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */
470 fep->stats.tx_carrier_errors++;
472 fep->stats.tx_packets++;
475 #ifndef final_version
476 if (bdp->cbd_sc & BD_ENET_TX_READY)
477 printk("HEY! Enet xmit interrupt and TX_READY.\n");
479 /* Deferred means some collisions occurred during transmit,
480 * but we eventually sent the packet OK.
482 if (bdp->cbd_sc & BD_ENET_TX_DEF)
483 fep->stats.collisions++;
485 /* Free the sk buffer associated with this last transmit.
487 dev_kfree_skb_any(skb);
488 fep->tx_skbuff[fep->skb_dirty] = NULL;
489 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
491 /* Update pointer to next buffer descriptor to be transmitted.
493 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
494 bdp = fep->tx_bd_base;
498 /* Since we have freed up a buffer, the ring is no longer
503 if (netif_queue_stopped(dev))
504 netif_wake_queue(dev);
507 fep->dirty_tx = (cbd_t *)bdp;
508 spin_unlock(&fep->lock);
512 /* During a receive, the cur_rx points to the current incoming buffer.
513 * When we update through the ring, if the next incoming buffer has
514 * not been given to the system, we just set the empty indicator,
515 * effectively tossing the packet.
518 fec_enet_rx(struct net_device *dev)
520 struct fec_enet_private *fep;
521 volatile fec_t *fecp;
527 fep = netdev_priv(dev);
528 fecp = (volatile fec_t*)dev->base_addr;
530 /* First, grab all of the stats for the incoming packet.
531 * These get messed up if we get called due to a busy condition.
535 while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) {
537 #ifndef final_version
538 /* Since we have allocated space to hold a complete frame,
539 * the last indicator should be set.
541 if ((bdp->cbd_sc & BD_ENET_RX_LAST) == 0)
542 printk("FEC ENET: rcv is not +last\n");
546 goto rx_processing_done;
548 /* Check for errors. */
549 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
550 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
551 fep->stats.rx_errors++;
552 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
553 /* Frame too long or too short. */
554 fep->stats.rx_length_errors++;
556 if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */
557 fep->stats.rx_frame_errors++;
558 if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */
559 fep->stats.rx_crc_errors++;
560 if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */
561 fep->stats.rx_crc_errors++;
564 /* Report late collisions as a frame error.
565 * On this error, the BD is closed, but we don't know what we
566 * have in the buffer. So, just drop this frame on the floor.
568 if (bdp->cbd_sc & BD_ENET_RX_CL) {
569 fep->stats.rx_errors++;
570 fep->stats.rx_frame_errors++;
571 goto rx_processing_done;
574 /* Process the incoming frame.
576 fep->stats.rx_packets++;
577 pkt_len = bdp->cbd_datlen;
578 fep->stats.rx_bytes += pkt_len;
579 data = (__u8*)__va(bdp->cbd_bufaddr);
581 /* This does 16 byte alignment, exactly what we need.
582 * The packet length includes FCS, but we don't want to
583 * include that when passing upstream as it messes up
584 * bridging applications.
586 skb = dev_alloc_skb(pkt_len-4);
589 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
590 fep->stats.rx_dropped++;
593 skb_put(skb,pkt_len-4); /* Make room */
594 eth_copy_and_sum(skb,
595 (unsigned char *)__va(bdp->cbd_bufaddr),
597 skb->protocol=eth_type_trans(skb,dev);
602 /* Clear the status flags for this buffer.
604 bdp->cbd_sc &= ~BD_ENET_RX_STATS;
606 /* Mark the buffer empty.
608 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
610 /* Update BD pointer to next entry.
612 if (bdp->cbd_sc & BD_ENET_RX_WRAP)
613 bdp = fep->rx_bd_base;
618 /* Doing this here will keep the FEC running while we process
619 * incoming frames. On a heavily loaded network, we should be
620 * able to keep up at the expense of system resources.
622 fecp->fec_r_des_active = 0x01000000;
624 } /* while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) */
625 fep->cur_rx = (cbd_t *)bdp;
628 /* Doing this here will allow us to process all frames in the
629 * ring before the FEC is allowed to put more there. On a heavily
630 * loaded network, some frames may be lost. Unfortunately, this
631 * increases the interrupt overhead since we can potentially work
632 * our way back to the interrupt return only to come right back
635 fecp->fec_r_des_active = 0x01000000;
641 fec_enet_mii(struct net_device *dev)
643 struct fec_enet_private *fep;
648 fep = netdev_priv(dev);
650 mii_reg = ep->fec_mii_data;
652 if ((mip = mii_head) == NULL) {
653 printk("MII and no head!\n");
657 if (mip->mii_func != NULL)
658 (*(mip->mii_func))(mii_reg, dev);
660 mii_head = mip->mii_next;
661 mip->mii_next = mii_free;
664 if ((mip = mii_head) != NULL)
665 ep->fec_mii_data = mip->mii_regval;
669 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
671 struct fec_enet_private *fep;
676 /* Add PHY address to register command.
678 fep = netdev_priv(dev);
679 regval |= fep->phy_addr << 23;
686 if ((mip = mii_free) != NULL) {
687 mii_free = mip->mii_next;
688 mip->mii_regval = regval;
689 mip->mii_func = func;
690 mip->mii_next = NULL;
692 mii_tail->mii_next = mip;
696 mii_head = mii_tail = mip;
697 fec_hwp->fec_mii_data = regval;
704 restore_flags(flags);
709 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
716 for(k = 0; (c+k)->mii_data != mk_mii_end; k++) {
717 mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
721 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
723 struct fec_enet_private *fep = netdev_priv(dev);
724 volatile uint *s = &(fep->phy_status);
726 *s &= ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
728 if (mii_reg & 0x0004)
730 if (mii_reg & 0x0010)
731 *s |= PHY_STAT_FAULT;
732 if (mii_reg & 0x0020)
736 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
738 struct fec_enet_private *fep = netdev_priv(dev);
739 volatile uint *s = &(fep->phy_status);
741 *s &= ~(PHY_CONF_ANE | PHY_CONF_LOOP);
743 if (mii_reg & 0x1000)
745 if (mii_reg & 0x4000)
749 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
751 struct fec_enet_private *fep = netdev_priv(dev);
752 volatile uint *s = &(fep->phy_status);
754 *s &= ~(PHY_CONF_SPMASK);
756 if (mii_reg & 0x0020)
757 *s |= PHY_CONF_10HDX;
758 if (mii_reg & 0x0040)
759 *s |= PHY_CONF_10FDX;
760 if (mii_reg & 0x0080)
761 *s |= PHY_CONF_100HDX;
762 if (mii_reg & 0x00100)
763 *s |= PHY_CONF_100FDX;
766 /* ------------------------------------------------------------------------- */
767 /* The Level one LXT970 is used by many boards */
769 #define MII_LXT970_MIRROR 16 /* Mirror register */
770 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
771 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
772 #define MII_LXT970_CONFIG 19 /* Configuration Register */
773 #define MII_LXT970_CSR 20 /* Chip Status Register */
775 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
777 struct fec_enet_private *fep = netdev_priv(dev);
778 volatile uint *s = &(fep->phy_status);
780 *s &= ~(PHY_STAT_SPMASK);
782 if (mii_reg & 0x0800) {
783 if (mii_reg & 0x1000)
784 *s |= PHY_STAT_100FDX;
786 *s |= PHY_STAT_100HDX;
788 if (mii_reg & 0x1000)
789 *s |= PHY_STAT_10FDX;
791 *s |= PHY_STAT_10HDX;
795 static phy_info_t phy_info_lxt970 = {
799 (const phy_cmd_t []) { /* config */
800 { mk_mii_read(MII_REG_CR), mii_parse_cr },
801 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
804 (const phy_cmd_t []) { /* startup - enable interrupts */
805 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
806 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
809 (const phy_cmd_t []) { /* ack_int */
810 /* read SR and ISR to acknowledge */
811 { mk_mii_read(MII_REG_SR), mii_parse_sr },
812 { mk_mii_read(MII_LXT970_ISR), NULL },
814 /* find out the current status */
815 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
818 (const phy_cmd_t []) { /* shutdown - disable interrupts */
819 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
824 /* ------------------------------------------------------------------------- */
825 /* The Level one LXT971 is used on some of my custom boards */
827 /* register definitions for the 971 */
829 #define MII_LXT971_PCR 16 /* Port Control Register */
830 #define MII_LXT971_SR2 17 /* Status Register 2 */
831 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
832 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
833 #define MII_LXT971_LCR 20 /* LED Control Register */
834 #define MII_LXT971_TCR 30 /* Transmit Control Register */
837 * I had some nice ideas of running the MDIO faster...
838 * The 971 should support 8MHz and I tried it, but things acted really
839 * weird, so 2.5 MHz ought to be enough for anyone...
842 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
844 struct fec_enet_private *fep = netdev_priv(dev);
845 volatile uint *s = &(fep->phy_status);
847 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
849 if (mii_reg & 0x0400) {
855 if (mii_reg & 0x0080)
857 if (mii_reg & 0x4000) {
858 if (mii_reg & 0x0200)
859 *s |= PHY_STAT_100FDX;
861 *s |= PHY_STAT_100HDX;
863 if (mii_reg & 0x0200)
864 *s |= PHY_STAT_10FDX;
866 *s |= PHY_STAT_10HDX;
868 if (mii_reg & 0x0008)
869 *s |= PHY_STAT_FAULT;
872 static phy_info_t phy_info_lxt971 = {
876 (const phy_cmd_t []) { /* config */
877 /* limit to 10MBit because my protorype board
878 * doesn't work with 100. */
879 { mk_mii_read(MII_REG_CR), mii_parse_cr },
880 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
881 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
884 (const phy_cmd_t []) { /* startup - enable interrupts */
885 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
886 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
887 { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
888 /* Somehow does the 971 tell me that the link is down
889 * the first read after power-up.
890 * read here to get a valid value in ack_int */
891 { mk_mii_read(MII_REG_SR), mii_parse_sr },
894 (const phy_cmd_t []) { /* ack_int */
895 /* find out the current status */
896 { mk_mii_read(MII_REG_SR), mii_parse_sr },
897 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
898 /* we only need to read ISR to acknowledge */
899 { mk_mii_read(MII_LXT971_ISR), NULL },
902 (const phy_cmd_t []) { /* shutdown - disable interrupts */
903 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
908 /* ------------------------------------------------------------------------- */
909 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
911 /* register definitions */
913 #define MII_QS6612_MCR 17 /* Mode Control Register */
914 #define MII_QS6612_FTR 27 /* Factory Test Register */
915 #define MII_QS6612_MCO 28 /* Misc. Control Register */
916 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
917 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
918 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
920 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
922 struct fec_enet_private *fep = netdev_priv(dev);
923 volatile uint *s = &(fep->phy_status);
925 *s &= ~(PHY_STAT_SPMASK);
927 switch((mii_reg >> 2) & 7) {
928 case 1: *s |= PHY_STAT_10HDX; break;
929 case 2: *s |= PHY_STAT_100HDX; break;
930 case 5: *s |= PHY_STAT_10FDX; break;
931 case 6: *s |= PHY_STAT_100FDX; break;
935 static phy_info_t phy_info_qs6612 = {
939 (const phy_cmd_t []) { /* config */
940 /* The PHY powers up isolated on the RPX,
941 * so send a command to allow operation.
943 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
945 /* parse cr and anar to get some info */
946 { mk_mii_read(MII_REG_CR), mii_parse_cr },
947 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
950 (const phy_cmd_t []) { /* startup - enable interrupts */
951 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
952 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
955 (const phy_cmd_t []) { /* ack_int */
956 /* we need to read ISR, SR and ANER to acknowledge */
957 { mk_mii_read(MII_QS6612_ISR), NULL },
958 { mk_mii_read(MII_REG_SR), mii_parse_sr },
959 { mk_mii_read(MII_REG_ANER), NULL },
961 /* read pcr to get info */
962 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
965 (const phy_cmd_t []) { /* shutdown - disable interrupts */
966 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
971 /* ------------------------------------------------------------------------- */
972 /* AMD AM79C874 phy */
974 /* register definitions for the 874 */
976 #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
977 #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
978 #define MII_AM79C874_DR 18 /* Diagnostic Register */
979 #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
980 #define MII_AM79C874_MCR 21 /* ModeControl Register */
981 #define MII_AM79C874_DC 23 /* Disconnect Counter */
982 #define MII_AM79C874_REC 24 /* Recieve Error Counter */
984 static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
986 struct fec_enet_private *fep = netdev_priv(dev);
987 volatile uint *s = &(fep->phy_status);
989 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
991 if (mii_reg & 0x0080)
993 if (mii_reg & 0x0400)
994 *s |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
996 *s |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
999 static phy_info_t phy_info_am79c874 = {
1003 (const phy_cmd_t []) { /* config */
1004 /* limit to 10MBit because my protorype board
1005 * doesn't work with 100. */
1006 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1007 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1008 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1011 (const phy_cmd_t []) { /* startup - enable interrupts */
1012 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1013 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1014 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1017 (const phy_cmd_t []) { /* ack_int */
1018 /* find out the current status */
1019 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1020 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1021 /* we only need to read ISR to acknowledge */
1022 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1025 (const phy_cmd_t []) { /* shutdown - disable interrupts */
1026 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1031 /* ------------------------------------------------------------------------- */
1033 static phy_info_t *phy_info[] = {
1041 /* ------------------------------------------------------------------------- */
1044 #ifdef CONFIG_RPXCLASSIC
1045 mii_link_interrupt(void *dev_id);
1047 mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs);
1053 * Code specific to Coldfire 5272 setup.
1055 static void __inline__ fec_request_intrs(struct net_device *dev, volatile fec_t *fecp)
1057 volatile unsigned long *icrp;
1059 /* Setup interrupt handlers. */
1060 if (request_irq(86, fec_enet_interrupt, 0, "fec(RX)", dev) != 0)
1061 printk("FEC: Could not allocate FEC(RC) IRQ(86)!\n");
1062 if (request_irq(87, fec_enet_interrupt, 0, "fec(TX)", dev) != 0)
1063 printk("FEC: Could not allocate FEC(RC) IRQ(87)!\n");
1064 if (request_irq(88, fec_enet_interrupt, 0, "fec(OTHER)", dev) != 0)
1065 printk("FEC: Could not allocate FEC(OTHER) IRQ(88)!\n");
1066 if (request_irq(66, mii_link_interrupt, 0, "fec(MII)", dev) != 0)
1067 printk("FEC: Could not allocate MII IRQ(66)!\n");
1069 /* Unmask interrupt at ColdFire 5272 SIM */
1070 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
1072 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1073 *icrp = (*icrp & 0x70777777) | 0x0d000000;
1076 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1078 volatile fec_t *fecp;
1081 fecp->fec_r_cntrl = 0x04;
1082 fecp->fec_x_cntrl = 0x00;
1084 /* Set MII speed to 2.5 MHz
1086 fecp->fec_mii_speed = fep->phy_speed = 0x0e;
1088 fec_restart(dev, 0);
1091 static void __inline__ fec_get_mac(struct net_device *dev, struct fec_enet_private *fep)
1093 volatile fec_t *fecp;
1094 unsigned char *eap, *iap, tmpaddr[6];
1098 eap = (unsigned char *) my_enet_addr;
1102 * Get MAC address from FLASH.
1103 * If it is all 1's or 0's, use the default.
1106 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1107 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1109 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1110 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1113 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1114 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1119 dev->dev_addr[i] = *eap++ = *iap++;
1122 static void __inline__ fec_enable_phy_intr(void)
1126 static void __inline__ fec_disable_phy_intr(void)
1128 volatile unsigned long *icrp;
1129 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1130 *icrp = (*icrp & 0x70777777) | 0x08000000;
1133 static void __inline__ fec_phy_ack_intr(void)
1135 volatile unsigned long *icrp;
1136 /* Acknowledge the interrupt */
1137 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1138 *icrp = (*icrp & 0x77777777) | 0x08000000;
1141 static void __inline__ fec_localhw_setup(void)
1146 * Do not need to make region uncached on 5272.
1148 static void __inline__ fec_uncache(unsigned long addr)
1152 /* ------------------------------------------------------------------------- */
1157 * Code sepcific to the MPC860T setup.
1159 static void __inline__ fec_request_intrs(struct net_device *dev, volatile fec_t *fecp)
1161 volatile immap_t *immap;
1163 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1165 if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0)
1166 panic("Could not allocate FEC IRQ!");
1168 #ifdef CONFIG_RPXCLASSIC
1169 /* Make Port C, bit 15 an input that causes interrupts.
1171 immap->im_ioport.iop_pcpar &= ~0x0001;
1172 immap->im_ioport.iop_pcdir &= ~0x0001;
1173 immap->im_ioport.iop_pcso &= ~0x0001;
1174 immap->im_ioport.iop_pcint |= 0x0001;
1175 cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev);
1177 /* Make LEDS reflect Link status.
1179 *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE;
1182 if (request_8xxirq(SIU_IRQ2, mii_link_interrupt, 0, "mii", dev) != 0)
1183 panic("Could not allocate MII IRQ!");
1187 static void __inline__ fec_get_mac(struct net_device *dev, struct fec_enet_private *fep)
1189 unsigned char *eap, *iap, tmpaddr[6];
1193 eap = (unsigned char *)my_enet_addr;
1194 iap = bd->bi_enetaddr;
1197 #ifdef CONFIG_RPXCLASSIC
1198 /* The Embedded Planet boards have only one MAC address in
1199 * the EEPROM, but can have two Ethernet ports. For the
1200 * FEC port, we create another address by setting one of
1201 * the address bits above something that would have (up to
1202 * now) been allocated.
1205 tmpaddr[i] = *iap++;
1211 dev->dev_addr[i] = *eap++ = *iap++;
1214 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1216 extern uint _get_IMMR(void);
1217 volatile immap_t *immap;
1218 volatile fec_t *fecp;
1221 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1223 /* Configure all of port D for MII.
1225 immap->im_ioport.iop_pdpar = 0x1fff;
1227 /* Bits moved from Rev. D onward.
1229 if ((_get_IMMR() & 0xffff) < 0x0501)
1230 immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
1232 immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
1234 /* Set MII speed to 2.5 MHz
1236 fecp->fec_mii_speed = fep->phy_speed =
1237 ((bd->bi_busfreq * 1000000) / 2500000) & 0x7e;
1240 static void __inline__ fec_enable_phy_intr(void)
1242 volatile fec_t *fecp;
1245 /* Enable MII command finished interrupt
1247 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1250 static void __inline__ fec_disable_phy_intr(void)
1254 static void __inline__ fec_phy_ack_intr(void)
1258 static void __inline__ fec_localhw_setup(void)
1260 volatile fec_t *fecp;
1263 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
1264 /* Enable big endian and don't care about SDMA FC.
1266 fecp->fec_fun_code = 0x78000000;
1269 static void __inline__ fec_uncache(unsigned long addr)
1272 pte = va_to_pte(mem_addr);
1273 pte_val(*pte) |= _PAGE_NO_CACHE;
1274 flush_tlb_page(init_mm.mmap, mem_addr);
1279 /* ------------------------------------------------------------------------- */
1281 static void mii_display_status(struct net_device *dev)
1283 struct fec_enet_private *fep = netdev_priv(dev);
1284 volatile uint *s = &(fep->phy_status);
1286 if (!fep->link && !fep->old_link) {
1287 /* Link is still down - don't print anything */
1291 printk("%s: status: ", dev->name);
1294 printk("link down");
1298 switch(*s & PHY_STAT_SPMASK) {
1299 case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
1300 case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
1301 case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
1302 case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
1304 printk(", Unknown speed/duplex");
1307 if (*s & PHY_STAT_ANC)
1308 printk(", auto-negotiation complete");
1311 if (*s & PHY_STAT_FAULT)
1312 printk(", remote fault");
1317 static void mii_display_config(struct net_device *dev)
1319 struct fec_enet_private *fep = netdev_priv(dev);
1320 volatile uint *s = &(fep->phy_status);
1322 printk("%s: config: auto-negotiation ", dev->name);
1324 if (*s & PHY_CONF_ANE)
1329 if (*s & PHY_CONF_100FDX)
1331 if (*s & PHY_CONF_100HDX)
1333 if (*s & PHY_CONF_10FDX)
1335 if (*s & PHY_CONF_10HDX)
1337 if (!(*s & PHY_CONF_SPMASK))
1338 printk(", No speed/duplex selected?");
1340 if (*s & PHY_CONF_LOOP)
1341 printk(", loopback enabled");
1345 fep->sequence_done = 1;
1348 static void mii_relink(struct net_device *dev)
1350 struct fec_enet_private *fep = netdev_priv(dev);
1353 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1354 mii_display_status(dev);
1355 fep->old_link = fep->link;
1360 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1362 fec_restart(dev, duplex);
1368 enable_irq(fep->mii_irq);
1373 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1375 struct fec_enet_private *fep = netdev_priv(dev);
1377 INIT_WORK(&fep->phy_task, (void*)mii_relink, dev);
1378 schedule_work(&fep->phy_task);
1381 static void mii_queue_config(uint mii_reg, struct net_device *dev)
1383 struct fec_enet_private *fep = netdev_priv(dev);
1385 INIT_WORK(&fep->phy_task, (void*)mii_display_config, dev);
1386 schedule_work(&fep->phy_task);
1391 phy_cmd_t phy_cmd_relink[] = { { mk_mii_read(MII_REG_CR), mii_queue_relink },
1393 phy_cmd_t phy_cmd_config[] = { { mk_mii_read(MII_REG_CR), mii_queue_config },
1398 /* Read remainder of PHY ID.
1401 mii_discover_phy3(uint mii_reg, struct net_device *dev)
1403 struct fec_enet_private *fep;
1406 fep = netdev_priv(dev);
1407 fep->phy_id |= (mii_reg & 0xffff);
1408 printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
1410 for(i = 0; phy_info[i]; i++) {
1411 if(phy_info[i]->id == (fep->phy_id >> 4))
1416 printk(" -- %s\n", phy_info[i]->name);
1418 printk(" -- unknown PHY!\n");
1420 fep->phy = phy_info[i];
1421 fep->phy_id_done = 1;
1424 /* Scan all of the MII PHY addresses looking for someone to respond
1425 * with a valid ID. This usually happens quickly.
1428 mii_discover_phy(uint mii_reg, struct net_device *dev)
1430 struct fec_enet_private *fep;
1431 volatile fec_t *fecp;
1434 fep = netdev_priv(dev);
1437 if (fep->phy_addr < 32) {
1438 if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
1440 /* Got first part of ID, now get remainder.
1442 fep->phy_id = phytype << 16;
1443 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
1448 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
1452 printk("FEC: No PHY device found.\n");
1453 /* Disable external MII interface */
1454 fecp->fec_mii_speed = fep->phy_speed = 0;
1455 fec_disable_phy_intr();
1459 /* This interrupt occurs when the PHY detects a link change.
1462 #ifdef CONFIG_RPXCLASSIC
1463 mii_link_interrupt(void *dev_id)
1465 mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs)
1468 struct net_device *dev = dev_id;
1469 struct fec_enet_private *fep = netdev_priv(dev);
1474 disable_irq(fep->mii_irq); /* disable now, enable later */
1477 mii_do_cmd(dev, fep->phy->ack_int);
1478 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
1483 fec_enet_open(struct net_device *dev)
1485 struct fec_enet_private *fep = netdev_priv(dev);
1487 /* I should reset the ring buffers here, but I don't yet know
1488 * a simple way to do that.
1491 fec_set_mac_address(dev);
1493 fep->sequence_done = 0;
1497 mii_do_cmd(dev, fep->phy->ack_int);
1498 mii_do_cmd(dev, fep->phy->config);
1499 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
1501 /* FIXME: use netif_carrier_{on,off} ; this polls
1502 * until link is up which is wrong... could be
1503 * 30 seconds or more we are trapped in here. -jgarzik
1505 while(!fep->sequence_done)
1508 mii_do_cmd(dev, fep->phy->startup);
1510 fep->link = 1; /* lets just try it and see */
1511 /* no phy, go full duplex, it's most likely a hub chip */
1512 fec_restart(dev, 1);
1515 netif_start_queue(dev);
1517 return 0; /* Success */
1521 fec_enet_close(struct net_device *dev)
1523 /* Don't know what to do yet.
1526 netif_stop_queue(dev);
1532 static struct net_device_stats *fec_enet_get_stats(struct net_device *dev)
1534 struct fec_enet_private *fep = netdev_priv(dev);
1539 /* Set or clear the multicast filter for this adaptor.
1540 * Skeleton taken from sunlance driver.
1541 * The CPM Ethernet implementation allows Multicast as well as individual
1542 * MAC address filtering. Some of the drivers check to make sure it is
1543 * a group multicast address, and discard those that are not. I guess I
1544 * will do the same for now, but just remove the test if you want
1545 * individual filtering as well (do the upper net layers want or support
1546 * this kind of feature?).
1549 #define HASH_BITS 6 /* #bits in hash */
1550 #define CRC32_POLY 0xEDB88320
1552 static void set_multicast_list(struct net_device *dev)
1554 struct fec_enet_private *fep;
1556 struct dev_mc_list *dmi;
1557 unsigned int i, j, bit, data, crc;
1560 fep = netdev_priv(dev);
1563 if (dev->flags&IFF_PROMISC) {
1564 /* Log any net taps. */
1565 printk("%s: Promiscuous mode enabled.\n", dev->name);
1566 ep->fec_r_cntrl |= 0x0008;
1569 ep->fec_r_cntrl &= ~0x0008;
1571 if (dev->flags & IFF_ALLMULTI) {
1572 /* Catch all multicast addresses, so set the
1573 * filter to all 1's.
1575 ep->fec_hash_table_high = 0xffffffff;
1576 ep->fec_hash_table_low = 0xffffffff;
1578 /* Clear filter and add the addresses in hash register.
1580 ep->fec_hash_table_high = 0;
1581 ep->fec_hash_table_low = 0;
1585 for (j = 0; j < dev->mc_count; j++, dmi = dmi->next)
1587 /* Only support group multicast for now.
1589 if (!(dmi->dmi_addr[0] & 1))
1592 /* calculate crc32 value of mac address
1596 for (i = 0; i < dmi->dmi_addrlen; i++)
1598 data = dmi->dmi_addr[i];
1599 for (bit = 0; bit < 8; bit++, data >>= 1)
1602 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1606 /* only upper 6 bits (HASH_BITS) are used
1607 which point to specific bit in he hash registers
1609 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1612 ep->fec_hash_table_high |= 1 << (hash - 32);
1614 ep->fec_hash_table_low |= 1 << hash;
1620 /* Set a MAC change in hardware.
1623 fec_set_mac_address(struct net_device *dev)
1626 volatile fec_t *fecp;
1630 /* Set our copy of the Ethernet address */
1631 for (i = 0; i < (ETH_ALEN / 2); i++)
1632 my_enet_addr[i] = (dev->dev_addr[i*2] << 8) | dev->dev_addr[i*2 + 1];
1634 /* Set station address. */
1635 fecp->fec_addr_low = (my_enet_addr[0] << 16) | my_enet_addr[1];
1636 fecp->fec_addr_high = my_enet_addr[2] << 16;
1639 /* Initialize the FEC Ethernet on 860T (or ColdFire 5272).
1642 * XXX: We need to clean up on failure exits here.
1644 int __init fec_enet_init(struct net_device *dev)
1646 struct fec_enet_private *fep = netdev_priv(dev);
1647 unsigned long mem_addr;
1648 volatile cbd_t *bdp;
1650 volatile fec_t *fecp;
1653 /* Only allow us to be probed once. */
1657 /* Create an Ethernet device instance.
1661 /* Whack a reset. We should wait for this.
1663 fecp->fec_ecntrl = 1;
1666 /* Clear and enable interrupts */
1667 fecp->fec_ievent = 0xffc0;
1668 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
1669 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
1670 fecp->fec_hash_table_high = 0;
1671 fecp->fec_hash_table_low = 0;
1672 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
1673 fecp->fec_ecntrl = 2;
1674 fecp->fec_r_des_active = 0x01000000;
1676 /* Set the Ethernet address. If using multiple Enets on the 8xx,
1677 * this needs some work to get unique addresses.
1679 * This is our default MAC address unless the user changes
1680 * it via eth_mac_addr (our dev->set_mac_addr handler).
1682 fec_get_mac(dev, fep);
1684 /* Allocate memory for buffer descriptors.
1686 if (((RX_RING_SIZE + TX_RING_SIZE) * sizeof(cbd_t)) > PAGE_SIZE) {
1687 printk("FEC init error. Need more space.\n");
1688 printk("FEC initialization failed.\n");
1691 mem_addr = __get_free_page(GFP_KERNEL);
1692 cbd_base = (cbd_t *)mem_addr;
1693 /* XXX: missing check for allocation failure */
1695 fec_uncache(mem_addr);
1697 /* Set receive and transmit descriptor base.
1699 fep->rx_bd_base = cbd_base;
1700 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1702 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
1703 fep->cur_rx = fep->rx_bd_base;
1705 fep->skb_cur = fep->skb_dirty = 0;
1707 /* Initialize the receive buffer descriptors.
1709 bdp = fep->rx_bd_base;
1710 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
1714 mem_addr = __get_free_page(GFP_KERNEL);
1715 /* XXX: missing check for allocation failure */
1717 fec_uncache(mem_addr);
1719 /* Initialize the BD for every fragment in the page.
1721 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
1722 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1723 bdp->cbd_bufaddr = __pa(mem_addr);
1724 mem_addr += FEC_ENET_RX_FRSIZE;
1729 /* Set the last buffer to wrap.
1732 bdp->cbd_sc |= BD_SC_WRAP;
1734 /* ...and the same for transmmit.
1736 bdp = fep->tx_bd_base;
1737 for (i=0; i<TX_RING_SIZE; i++) {
1739 /* Initialize the BD for every fragment in the page.
1742 bdp->cbd_bufaddr = 0;
1746 /* Set the last buffer to wrap.
1749 bdp->cbd_sc |= BD_SC_WRAP;
1751 /* Set receive and transmit descriptor base.
1753 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
1754 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
1756 /* Install our interrupt handlers. This varies depending on
1759 fec_request_intrs(dev, fecp);
1761 dev->base_addr = (unsigned long)fecp;
1763 /* The FEC Ethernet specific entries in the device structure. */
1764 dev->open = fec_enet_open;
1765 dev->hard_start_xmit = fec_enet_start_xmit;
1766 dev->tx_timeout = fec_timeout;
1767 dev->watchdog_timeo = TX_TIMEOUT;
1768 dev->stop = fec_enet_close;
1769 dev->get_stats = fec_enet_get_stats;
1770 dev->set_multicast_list = set_multicast_list;
1772 for (i=0; i<NMII-1; i++)
1773 mii_cmds[i].mii_next = &mii_cmds[i+1];
1774 mii_free = mii_cmds;
1776 /* setup MII interface */
1777 fec_set_mii(dev, fep);
1779 printk("%s: FEC ENET Version 0.2, ", dev->name);
1781 printk("%02x:", dev->dev_addr[i]);
1782 printk("%02x\n", dev->dev_addr[5]);
1784 /* Queue up command to detect the PHY and initialize the
1785 * remainder of the interface.
1787 fep->phy_id_done = 0;
1789 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
1795 /* This function is called to start or restart the FEC during a link
1796 * change. This only happens when switching between half and full
1800 fec_restart(struct net_device *dev, int duplex)
1802 struct fec_enet_private *fep;
1805 volatile cbd_t *bdp;
1806 volatile fec_t *fecp;
1810 fep = netdev_priv(dev);
1812 /* Whack a reset. We should wait for this.
1814 fecp->fec_ecntrl = 1;
1817 /* Enable interrupts we wish to service.
1819 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
1820 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
1822 /* Clear any outstanding interrupt.
1824 fecp->fec_ievent = 0xffc0;
1825 fec_enable_phy_intr();
1827 /* Set station address.
1829 fecp->fec_addr_low = (my_enet_addr[0] << 16) | my_enet_addr[1];
1830 fecp->fec_addr_high = (my_enet_addr[2] << 16);
1832 eap = (unsigned char *)&my_enet_addr[0];
1834 dev->dev_addr[i] = *eap++;
1836 /* Reset all multicast.
1838 fecp->fec_hash_table_high = 0;
1839 fecp->fec_hash_table_low = 0;
1841 /* Set maximum receive buffer size.
1843 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
1845 fec_localhw_setup();
1847 /* Set receive and transmit descriptor base.
1849 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
1850 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
1852 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
1853 fep->cur_rx = fep->rx_bd_base;
1855 /* Reset SKB transmit buffers.
1857 fep->skb_cur = fep->skb_dirty = 0;
1858 for (i=0; i<=TX_RING_MOD_MASK; i++) {
1859 if (fep->tx_skbuff[i] != NULL) {
1860 dev_kfree_skb_any(fep->tx_skbuff[i]);
1861 fep->tx_skbuff[i] = NULL;
1865 /* Initialize the receive buffer descriptors.
1867 bdp = fep->rx_bd_base;
1868 for (i=0; i<RX_RING_SIZE; i++) {
1870 /* Initialize the BD for every fragment in the page.
1872 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1876 /* Set the last buffer to wrap.
1879 bdp->cbd_sc |= BD_SC_WRAP;
1881 /* ...and the same for transmmit.
1883 bdp = fep->tx_bd_base;
1884 for (i=0; i<TX_RING_SIZE; i++) {
1886 /* Initialize the BD for every fragment in the page.
1889 bdp->cbd_bufaddr = 0;
1893 /* Set the last buffer to wrap.
1896 bdp->cbd_sc |= BD_SC_WRAP;
1901 fecp->fec_r_cntrl = 0x04; /* MII enable */
1902 fecp->fec_x_cntrl = 0x04; /* FD enable */
1905 fecp->fec_r_cntrl = 0x06; /* MII enable|No Rcv on Xmit */
1906 fecp->fec_x_cntrl = 0x00;
1908 fep->full_duplex = duplex;
1912 fecp->fec_mii_speed = fep->phy_speed;
1914 /* And last, enable the transmit and receive processing.
1916 fecp->fec_ecntrl = 2;
1917 fecp->fec_r_des_active = 0x01000000;
1921 fec_stop(struct net_device *dev)
1923 volatile fec_t *fecp;
1924 struct fec_enet_private *fep;
1927 fep = netdev_priv(dev);
1929 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
1931 while(!(fecp->fec_ievent & 0x10000000));
1933 /* Whack a reset. We should wait for this.
1935 fecp->fec_ecntrl = 1;
1938 /* Clear outstanding MII command interrupts.
1940 fecp->fec_ievent = FEC_ENET_MII;
1941 fec_enable_phy_intr();
1943 fecp->fec_imask = FEC_ENET_MII;
1944 fecp->fec_mii_speed = fep->phy_speed;
1947 static struct net_device *fec_dev;
1949 static int __init fec_enet_module_init(void)
1951 struct net_device *dev;
1954 dev = alloc_etherdev(sizeof(struct fec_enet_private));
1957 err = fec_enet_init(dev);
1963 if (register_netdev(dev) != 0) {
1964 /* XXX: missing cleanup here */
1972 module_init(fec_enet_module_init);
1974 MODULE_LICENSE("GPL");