2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
13 * Copyright (C) 2003 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 * 0.01: 05 Oct 2003: First release that compiles without warnings.
32 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
33 * Check all PCI BARs for the register window.
34 * udelay added to mii_rw.
35 * 0.03: 06 Oct 2003: Initialize dev->irq.
36 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
37 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
38 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
40 * 0.07: 14 Oct 2003: Further irq mask updates.
41 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
42 * added into irq handler, NULL check for drain_ring.
43 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
44 * requested interrupt sources.
45 * 0.10: 20 Oct 2003: First cleanup for release.
46 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
47 * MAC Address init fix, set_multicast cleanup.
48 * 0.12: 23 Oct 2003: Cleanups for release.
49 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
50 * Set link speed correctly. start rx before starting
51 * tx (nv_start_rx sets the link speed).
52 * 0.14: 25 Oct 2003: Nic dependant irq mask.
53 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
55 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
56 * increased to 1628 bytes.
57 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
59 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
60 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
61 * addresses, really stop rx if already running
62 * in nv_start_rx, clean up a bit.
63 * (C) Carl-Daniel Hailfinger
64 * 0.20: 07 Dec 2003: alloc fixes
65 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
66 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
68 * (C) Carl-Daniel Hailfinger, Manfred Spraul
69 * 0.23: 26 Jan 2004: various small cleanups
70 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
71 * 0.25: 09 Mar 2004: wol support
74 * We suspect that on some hardware no TX done interrupts are generated.
75 * This means recovery from netif_stop_queue only happens if the hw timer
76 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
77 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
78 * If your hardware reliably generates tx done interrupts, then you can remove
79 * DEV_NEED_TIMERIRQ from the driver_data flags.
80 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
81 * superfluous timer interrupts from the nic.
83 #define FORCEDETH_VERSION "0.25"
85 #include <linux/module.h>
86 #include <linux/types.h>
87 #include <linux/pci.h>
88 #include <linux/interrupt.h>
89 #include <linux/netdevice.h>
90 #include <linux/etherdevice.h>
91 #include <linux/delay.h>
92 #include <linux/spinlock.h>
93 #include <linux/ethtool.h>
94 #include <linux/timer.h>
95 #include <linux/skbuff.h>
96 #include <linux/mii.h>
97 #include <linux/random.h>
98 #include <linux/init.h>
102 #include <asm/uaccess.h>
103 #include <asm/system.h>
106 #define dprintk printk
108 #define dprintk(x...) do { } while (0)
116 #define DEV_NEED_LASTPACKET1 0x0001
117 #define DEV_IRQMASK_1 0x0002
118 #define DEV_IRQMASK_2 0x0004
119 #define DEV_NEED_TIMERIRQ 0x0008
122 NvRegIrqStatus = 0x000,
123 #define NVREG_IRQSTAT_MIIEVENT 0x040
124 #define NVREG_IRQSTAT_MASK 0x1ff
125 NvRegIrqMask = 0x004,
126 #define NVREG_IRQ_RX 0x0002
127 #define NVREG_IRQ_RX_NOBUF 0x0004
128 #define NVREG_IRQ_TX_ERR 0x0008
129 #define NVREG_IRQ_TX2 0x0010
130 #define NVREG_IRQ_TIMER 0x0020
131 #define NVREG_IRQ_LINK 0x0040
132 #define NVREG_IRQ_TX1 0x0100
133 #define NVREG_IRQMASK_WANTED_1 0x005f
134 #define NVREG_IRQMASK_WANTED_2 0x0147
135 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
137 NvRegUnknownSetupReg6 = 0x008,
138 #define NVREG_UNKSETUP6_VAL 3
141 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
142 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
144 NvRegPollingInterval = 0x00c,
145 #define NVREG_POLL_DEFAULT 970
147 #define NVREG_MISC1_HD 0x02
148 #define NVREG_MISC1_FORCE 0x3b0f3c
150 NvRegTransmitterControl = 0x084,
151 #define NVREG_XMITCTL_START 0x01
152 NvRegTransmitterStatus = 0x088,
153 #define NVREG_XMITSTAT_BUSY 0x01
155 NvRegPacketFilterFlags = 0x8c,
156 #define NVREG_PFF_ALWAYS 0x7F0008
157 #define NVREG_PFF_PROMISC 0x80
158 #define NVREG_PFF_MYADDR 0x20
160 NvRegOffloadConfig = 0x90,
161 #define NVREG_OFFLOAD_HOMEPHY 0x601
162 #define NVREG_OFFLOAD_NORMAL 0x5ee
163 NvRegReceiverControl = 0x094,
164 #define NVREG_RCVCTL_START 0x01
165 NvRegReceiverStatus = 0x98,
166 #define NVREG_RCVSTAT_BUSY 0x01
168 NvRegRandomSeed = 0x9c,
169 #define NVREG_RNDSEED_MASK 0x00ff
170 #define NVREG_RNDSEED_FORCE 0x7f00
172 NvRegUnknownSetupReg1 = 0xA0,
173 #define NVREG_UNKSETUP1_VAL 0x16070f
174 NvRegUnknownSetupReg2 = 0xA4,
175 #define NVREG_UNKSETUP2_VAL 0x16
176 NvRegMacAddrA = 0xA8,
177 NvRegMacAddrB = 0xAC,
178 NvRegMulticastAddrA = 0xB0,
179 #define NVREG_MCASTADDRA_FORCE 0x01
180 NvRegMulticastAddrB = 0xB4,
181 NvRegMulticastMaskA = 0xB8,
182 NvRegMulticastMaskB = 0xBC,
184 NvRegTxRingPhysAddr = 0x100,
185 NvRegRxRingPhysAddr = 0x104,
186 NvRegRingSizes = 0x108,
187 #define NVREG_RINGSZ_TXSHIFT 0
188 #define NVREG_RINGSZ_RXSHIFT 16
189 NvRegUnknownTransmitterReg = 0x10c,
190 NvRegLinkSpeed = 0x110,
191 #define NVREG_LINKSPEED_FORCE 0x10000
192 #define NVREG_LINKSPEED_10 10
193 #define NVREG_LINKSPEED_100 100
194 #define NVREG_LINKSPEED_1000 1000
195 NvRegUnknownSetupReg5 = 0x130,
196 #define NVREG_UNKSETUP5_BIT31 (1<<31)
197 NvRegUnknownSetupReg3 = 0x134,
198 #define NVREG_UNKSETUP3_VAL1 0x200010
199 NvRegTxRxControl = 0x144,
200 #define NVREG_TXRXCTL_KICK 0x0001
201 #define NVREG_TXRXCTL_BIT1 0x0002
202 #define NVREG_TXRXCTL_BIT2 0x0004
203 #define NVREG_TXRXCTL_IDLE 0x0008
204 #define NVREG_TXRXCTL_RESET 0x0010
205 NvRegMIIStatus = 0x180,
206 #define NVREG_MIISTAT_ERROR 0x0001
207 #define NVREG_MIISTAT_LINKCHANGE 0x0008
208 #define NVREG_MIISTAT_MASK 0x000f
209 #define NVREG_MIISTAT_MASK2 0x000f
210 NvRegUnknownSetupReg4 = 0x184,
211 #define NVREG_UNKSETUP4_VAL 8
213 NvRegAdapterControl = 0x188,
214 #define NVREG_ADAPTCTL_START 0x02
215 #define NVREG_ADAPTCTL_LINKUP 0x04
216 #define NVREG_ADAPTCTL_PHYVALID 0x4000
217 #define NVREG_ADAPTCTL_RUNNING 0x100000
218 #define NVREG_ADAPTCTL_PHYSHIFT 24
219 NvRegMIISpeed = 0x18c,
220 #define NVREG_MIISPEED_BIT8 (1<<8)
221 #define NVREG_MIIDELAY 5
222 NvRegMIIControl = 0x190,
223 #define NVREG_MIICTL_INUSE 0x10000
224 #define NVREG_MIICTL_WRITE 0x08000
225 #define NVREG_MIICTL_ADDRSHIFT 5
226 NvRegMIIData = 0x194,
227 NvRegWakeUpFlags = 0x200,
228 #define NVREG_WAKEUPFLAGS_VAL 0x7770
229 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
230 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
231 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
232 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
233 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
234 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
235 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
236 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
237 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
238 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
240 NvRegPatternCRC = 0x204,
241 NvRegPatternMask = 0x208,
242 NvRegPowerCap = 0x268,
243 #define NVREG_POWERCAP_D3SUPP (1<<30)
244 #define NVREG_POWERCAP_D2SUPP (1<<26)
245 #define NVREG_POWERCAP_D1SUPP (1<<25)
246 NvRegPowerState = 0x26c,
247 #define NVREG_POWERSTATE_POWEREDUP 0x8000
248 #define NVREG_POWERSTATE_VALID 0x0100
249 #define NVREG_POWERSTATE_MASK 0x0003
250 #define NVREG_POWERSTATE_D0 0x0000
251 #define NVREG_POWERSTATE_D1 0x0001
252 #define NVREG_POWERSTATE_D2 0x0002
253 #define NVREG_POWERSTATE_D3 0x0003
262 #define NV_TX_LASTPACKET (1<<0)
263 #define NV_TX_RETRYERROR (1<<3)
264 #define NV_TX_LASTPACKET1 (1<<8)
265 #define NV_TX_DEFERRED (1<<10)
266 #define NV_TX_CARRIERLOST (1<<11)
267 #define NV_TX_LATECOLLISION (1<<12)
268 #define NV_TX_UNDERFLOW (1<<13)
269 #define NV_TX_ERROR (1<<14)
270 #define NV_TX_VALID (1<<15)
272 #define NV_RX_DESCRIPTORVALID (1<<0)
273 #define NV_RX_MISSEDFRAME (1<<1)
274 #define NV_RX_SUBSTRACT1 (1<<3)
275 #define NV_RX_ERROR1 (1<<7)
276 #define NV_RX_ERROR2 (1<<8)
277 #define NV_RX_ERROR3 (1<<9)
278 #define NV_RX_ERROR4 (1<<10)
279 #define NV_RX_CRCERR (1<<11)
280 #define NV_RX_OVERFLOW (1<<12)
281 #define NV_RX_FRAMINGERR (1<<13)
282 #define NV_RX_ERROR (1<<14)
283 #define NV_RX_AVAIL (1<<15)
285 /* Miscelaneous hardware related defines: */
286 #define NV_PCI_REGSZ 0x270
288 /* various timeout delays: all in usec */
289 #define NV_TXRX_RESET_DELAY 4
290 #define NV_TXSTOP_DELAY1 10
291 #define NV_TXSTOP_DELAY1MAX 500000
292 #define NV_TXSTOP_DELAY2 100
293 #define NV_RXSTOP_DELAY1 10
294 #define NV_RXSTOP_DELAY1MAX 500000
295 #define NV_RXSTOP_DELAY2 100
296 #define NV_SETUP5_DELAY 5
297 #define NV_SETUP5_DELAYMAX 50000
298 #define NV_POWERUP_DELAY 5
299 #define NV_POWERUP_DELAYMAX 5000
300 #define NV_MIIBUSY_DELAY 50
301 #define NV_MIIPHY_DELAY 10
302 #define NV_MIIPHY_DELAYMAX 10000
304 #define NV_WAKEUPPATTERNS 5
305 #define NV_WAKEUPMASKENTRIES 4
307 /* General driver defaults */
308 #define NV_WATCHDOG_TIMEO (5*HZ)
309 #define DEFAULT_MTU 1500 /* also maximum supported, at least for now */
313 /* limited to 1 packet until we understand NV_TX_LASTPACKET */
314 #define TX_LIMIT_STOP 10
315 #define TX_LIMIT_START 5
317 /* rx/tx mac addr + type + vlan + align + slack*/
318 #define RX_NIC_BUFSIZE (DEFAULT_MTU + 64)
319 /* even more slack */
320 #define RX_ALLOC_BUFSIZE (DEFAULT_MTU + 128)
322 #define OOM_REFILL (1+HZ/20)
323 #define POLL_WAIT (1+HZ/100)
327 * All hardware access under dev->priv->lock, except the performance
329 * - rx is (pseudo-) lockless: it relies on the single-threading provided
330 * by the arch code for interrupts.
331 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
332 * needs dev->priv->lock :-(
333 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
336 /* in dev: base, irq */
341 * Locking: spin_lock(&np->lock); */
342 struct net_device_stats stats;
349 /* General data: RO fields */
350 dma_addr_t ring_addr;
351 struct pci_dev *pci_dev;
355 /* rx specific fields.
356 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
358 struct ring_desc *rx_ring;
359 unsigned int cur_rx, refill_rx;
360 struct sk_buff *rx_skbuff[RX_RING];
361 dma_addr_t rx_dma[RX_RING];
362 unsigned int rx_buf_sz;
363 struct timer_list oom_kick;
364 struct timer_list nic_poll;
367 * tx specific fields.
369 struct ring_desc *tx_ring;
370 unsigned int next_tx, nic_tx;
371 struct sk_buff *tx_skbuff[TX_RING];
372 dma_addr_t tx_dma[TX_RING];
377 * Maximum number of loops until we assume that a bit in the irq mask
378 * is stuck. Overridable with module param.
380 static int max_interrupt_work = 5;
382 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
384 return (struct fe_priv *) dev->priv;
387 static inline u8 *get_hwbase(struct net_device *dev)
389 return (u8 *) dev->base_addr;
392 static inline void pci_push(u8 * base)
394 /* force out pending posted writes */
398 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
399 int delay, int delaymax, const char *msg)
401 u8 *base = get_hwbase(dev);
412 } while ((readl(base + offset) & mask) != target);
416 #define MII_READ (-1)
417 /* mii_rw: read/write a register on the PHY.
419 * Caller must guarantee serialization
421 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
423 u8 *base = get_hwbase(dev);
428 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
430 reg = readl(base + NvRegAdapterControl);
431 if (reg & NVREG_ADAPTCTL_RUNNING) {
433 writel(reg & ~NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
435 reg = readl(base + NvRegMIIControl);
436 if (reg & NVREG_MIICTL_INUSE) {
437 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
438 udelay(NV_MIIBUSY_DELAY);
441 reg = NVREG_MIICTL_INUSE | (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
442 if (value != MII_READ) {
443 writel(value, base + NvRegMIIData);
444 reg |= NVREG_MIICTL_WRITE;
446 writel(reg, base + NvRegMIIControl);
448 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
449 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
450 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
451 dev->name, miireg, addr);
453 } else if (value != MII_READ) {
454 /* it was a write operation - fewer failures are detectable */
455 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
456 dev->name, value, miireg, addr);
458 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
459 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
460 dev->name, miireg, addr);
463 /* FIXME: why is that required? */
465 retval = readl(base + NvRegMIIData);
466 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
467 dev->name, miireg, addr, retval);
470 reg = readl(base + NvRegAdapterControl);
471 writel(reg | NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
476 static void nv_start_rx(struct net_device *dev)
478 struct fe_priv *np = get_nvpriv(dev);
479 u8 *base = get_hwbase(dev);
481 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
482 /* Already running? Stop it. */
483 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
484 writel(0, base + NvRegReceiverControl);
487 writel(np->linkspeed, base + NvRegLinkSpeed);
489 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
493 static void nv_stop_rx(struct net_device *dev)
495 u8 *base = get_hwbase(dev);
497 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
498 writel(0, base + NvRegReceiverControl);
499 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
500 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
501 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
503 udelay(NV_RXSTOP_DELAY2);
504 writel(0, base + NvRegLinkSpeed);
507 static void nv_start_tx(struct net_device *dev)
509 u8 *base = get_hwbase(dev);
511 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
512 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
516 static void nv_stop_tx(struct net_device *dev)
518 u8 *base = get_hwbase(dev);
520 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
521 writel(0, base + NvRegTransmitterControl);
522 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
523 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
524 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
526 udelay(NV_TXSTOP_DELAY2);
527 writel(0, base + NvRegUnknownTransmitterReg);
530 static void nv_txrx_reset(struct net_device *dev)
532 u8 *base = get_hwbase(dev);
534 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
535 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET, base + NvRegTxRxControl);
537 udelay(NV_TXRX_RESET_DELAY);
538 writel(NVREG_TXRXCTL_BIT2, base + NvRegTxRxControl);
543 * nv_get_stats: dev->get_stats function
544 * Get latest stats value from the nic.
545 * Called with read_lock(&dev_base_lock) held for read -
546 * only synchronized against unregister_netdevice.
548 static struct net_device_stats *nv_get_stats(struct net_device *dev)
550 struct fe_priv *np = get_nvpriv(dev);
552 /* It seems that the nic always generates interrupts and doesn't
553 * accumulate errors internally. Thus the current values in np->stats
554 * are already up to date.
559 static int nv_ethtool_ioctl(struct net_device *dev, void __user *useraddr)
561 struct fe_priv *np = get_nvpriv(dev);
562 u8 *base = get_hwbase(dev);
565 if (copy_from_user(ðcmd, useraddr, sizeof (ethcmd)))
569 case ETHTOOL_GDRVINFO:
571 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
572 strcpy(info.driver, "forcedeth");
573 strcpy(info.version, FORCEDETH_VERSION);
574 strcpy(info.bus_info, pci_name(np->pci_dev));
575 if (copy_to_user(useraddr, &info, sizeof (info)))
581 struct ethtool_value edata = { ETHTOOL_GLINK };
583 edata.data = !!netif_carrier_ok(dev);
585 if (copy_to_user(useraddr, &edata, sizeof(edata)))
591 struct ethtool_wolinfo wolinfo;
592 memset(&wolinfo, 0, sizeof(wolinfo));
593 wolinfo.supported = WAKE_MAGIC;
595 spin_lock_irq(&np->lock);
597 wolinfo.wolopts = WAKE_MAGIC;
598 spin_unlock_irq(&np->lock);
600 if (copy_to_user(useraddr, &wolinfo, sizeof(wolinfo)))
606 struct ethtool_wolinfo wolinfo;
607 if (copy_from_user(&wolinfo, useraddr, sizeof(wolinfo)))
610 spin_lock_irq(&np->lock);
611 if (wolinfo.wolopts == 0) {
612 writel(0, base + NvRegWakeUpFlags);
615 if (wolinfo.wolopts & WAKE_MAGIC) {
616 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
619 spin_unlock_irq(&np->lock);
630 * nv_ioctl: dev->do_ioctl function
631 * Called with rtnl_lock held.
633 static int nv_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
637 return nv_ethtool_ioctl(dev, rq->ifr_data);
645 * nv_alloc_rx: fill rx ring entries.
646 * Return 1 if the allocations for the skbs failed and the
647 * rx engine is without Available descriptors
649 static int nv_alloc_rx(struct net_device *dev)
651 struct fe_priv *np = get_nvpriv(dev);
652 unsigned int refill_rx = np->refill_rx;
654 while (np->cur_rx != refill_rx) {
655 int nr = refill_rx % RX_RING;
658 if (np->rx_skbuff[nr] == NULL) {
660 skb = dev_alloc_skb(RX_ALLOC_BUFSIZE);
665 np->rx_skbuff[nr] = skb;
667 skb = np->rx_skbuff[nr];
669 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
671 np->rx_ring[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
672 np->rx_ring[nr].Length = cpu_to_le16(RX_NIC_BUFSIZE);
674 np->rx_ring[nr].Flags = cpu_to_le16(NV_RX_AVAIL);
675 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
676 dev->name, refill_rx);
679 np->refill_rx = refill_rx;
680 if (np->cur_rx - refill_rx == RX_RING)
685 static void nv_do_rx_refill(unsigned long data)
687 struct net_device *dev = (struct net_device *) data;
688 struct fe_priv *np = get_nvpriv(dev);
690 disable_irq(dev->irq);
691 if (nv_alloc_rx(dev)) {
692 spin_lock(&np->lock);
693 if (!np->in_shutdown)
694 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
695 spin_unlock(&np->lock);
697 enable_irq(dev->irq);
700 static int nv_init_ring(struct net_device *dev)
702 struct fe_priv *np = get_nvpriv(dev);
705 np->next_tx = np->nic_tx = 0;
706 for (i = 0; i < TX_RING; i++) {
707 np->tx_ring[i].Flags = 0;
710 np->cur_rx = RX_RING;
712 for (i = 0; i < RX_RING; i++) {
713 np->rx_ring[i].Flags = 0;
715 return nv_alloc_rx(dev);
718 static void nv_drain_tx(struct net_device *dev)
720 struct fe_priv *np = get_nvpriv(dev);
722 for (i = 0; i < TX_RING; i++) {
723 np->tx_ring[i].Flags = 0;
724 if (np->tx_skbuff[i]) {
725 pci_unmap_single(np->pci_dev, np->tx_dma[i],
726 np->tx_skbuff[i]->len,
728 dev_kfree_skb(np->tx_skbuff[i]);
729 np->tx_skbuff[i] = NULL;
730 np->stats.tx_dropped++;
735 static void nv_drain_rx(struct net_device *dev)
737 struct fe_priv *np = get_nvpriv(dev);
739 for (i = 0; i < RX_RING; i++) {
740 np->rx_ring[i].Flags = 0;
742 if (np->rx_skbuff[i]) {
743 pci_unmap_single(np->pci_dev, np->rx_dma[i],
744 np->rx_skbuff[i]->len,
746 dev_kfree_skb(np->rx_skbuff[i]);
747 np->rx_skbuff[i] = NULL;
752 static void drain_ring(struct net_device *dev)
759 * nv_start_xmit: dev->hard_start_xmit function
760 * Called with dev->xmit_lock held.
762 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
764 struct fe_priv *np = get_nvpriv(dev);
765 int nr = np->next_tx % TX_RING;
767 np->tx_skbuff[nr] = skb;
768 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data,skb->len,
771 np->tx_ring[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
772 np->tx_ring[nr].Length = cpu_to_le16(skb->len-1);
774 spin_lock_irq(&np->lock);
776 np->tx_ring[nr].Flags = np->tx_flags;
777 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission.\n",
778 dev->name, np->next_tx);
781 for (j=0; j<64; j++) {
783 dprintk("\n%03x:", j);
784 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
791 dev->trans_start = jiffies;
792 if (np->next_tx - np->nic_tx >= TX_LIMIT_STOP)
793 netif_stop_queue(dev);
794 spin_unlock_irq(&np->lock);
795 writel(NVREG_TXRXCTL_KICK, get_hwbase(dev) + NvRegTxRxControl);
796 pci_push(get_hwbase(dev));
801 * nv_tx_done: check for completed packets, release the skbs.
803 * Caller must own np->lock.
805 static void nv_tx_done(struct net_device *dev)
807 struct fe_priv *np = get_nvpriv(dev);
809 while (np->nic_tx < np->next_tx) {
810 struct ring_desc *prd;
811 int i = np->nic_tx % TX_RING;
813 prd = &np->tx_ring[i];
815 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
816 dev->name, np->nic_tx, prd->Flags);
817 if (prd->Flags & cpu_to_le16(NV_TX_VALID))
819 if (prd->Flags & cpu_to_le16(NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
820 NV_TX_UNDERFLOW|NV_TX_ERROR)) {
821 if (prd->Flags & cpu_to_le16(NV_TX_UNDERFLOW))
822 np->stats.tx_fifo_errors++;
823 if (prd->Flags & cpu_to_le16(NV_TX_CARRIERLOST))
824 np->stats.tx_carrier_errors++;
825 np->stats.tx_errors++;
827 np->stats.tx_packets++;
828 np->stats.tx_bytes += np->tx_skbuff[i]->len;
830 pci_unmap_single(np->pci_dev, np->tx_dma[i],
831 np->tx_skbuff[i]->len,
833 dev_kfree_skb_irq(np->tx_skbuff[i]);
834 np->tx_skbuff[i] = NULL;
837 if (np->next_tx - np->nic_tx < TX_LIMIT_START)
838 netif_wake_queue(dev);
842 * nv_tx_timeout: dev->tx_timeout function
843 * Called with dev->xmit_lock held.
845 static void nv_tx_timeout(struct net_device *dev)
847 struct fe_priv *np = get_nvpriv(dev);
848 u8 *base = get_hwbase(dev);
850 dprintk(KERN_DEBUG "%s: Got tx_timeout. irq: %08x\n", dev->name,
851 readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
853 spin_lock_irq(&np->lock);
855 /* 1) stop tx engine */
858 /* 2) check that the packets were not sent already: */
861 /* 3) if there are dead entries: clear everything */
862 if (np->next_tx != np->nic_tx) {
863 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
865 np->next_tx = np->nic_tx = 0;
866 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
867 netif_wake_queue(dev);
870 /* 4) restart tx engine */
872 spin_unlock_irq(&np->lock);
875 static void nv_rx_process(struct net_device *dev)
877 struct fe_priv *np = get_nvpriv(dev);
880 struct ring_desc *prd;
884 if (np->cur_rx - np->refill_rx >= RX_RING)
885 break; /* we scanned the whole ring - do not continue */
887 i = np->cur_rx % RX_RING;
888 prd = &np->rx_ring[i];
889 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
890 dev->name, np->cur_rx, prd->Flags);
892 if (prd->Flags & cpu_to_le16(NV_RX_AVAIL))
893 break; /* still owned by hardware, */
896 * the packet is for us - immediately tear down the pci mapping.
897 * TODO: check if a prefetch of the first cacheline improves
900 pci_unmap_single(np->pci_dev, np->rx_dma[i],
901 np->rx_skbuff[i]->len,
906 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",prd->Flags);
907 for (j=0; j<64; j++) {
909 dprintk("\n%03x:", j);
910 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
914 /* look at what we actually got: */
915 if (!(prd->Flags & cpu_to_le16(NV_RX_DESCRIPTORVALID)))
919 len = le16_to_cpu(prd->Length);
921 if (prd->Flags & cpu_to_le16(NV_RX_MISSEDFRAME)) {
922 np->stats.rx_missed_errors++;
923 np->stats.rx_errors++;
926 if (prd->Flags & cpu_to_le16(NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4)) {
927 np->stats.rx_errors++;
930 if (prd->Flags & cpu_to_le16(NV_RX_CRCERR)) {
931 np->stats.rx_crc_errors++;
932 np->stats.rx_errors++;
935 if (prd->Flags & cpu_to_le16(NV_RX_OVERFLOW)) {
936 np->stats.rx_over_errors++;
937 np->stats.rx_errors++;
940 if (prd->Flags & cpu_to_le16(NV_RX_ERROR)) {
941 /* framing errors are soft errors, the rest is fatal. */
942 if (prd->Flags & cpu_to_le16(NV_RX_FRAMINGERR)) {
943 if (prd->Flags & cpu_to_le16(NV_RX_SUBSTRACT1)) {
947 np->stats.rx_errors++;
951 /* got a valid packet - forward it to the network core */
952 skb = np->rx_skbuff[i];
953 np->rx_skbuff[i] = NULL;
956 skb->protocol = eth_type_trans(skb, dev);
957 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
958 dev->name, np->cur_rx, len, skb->protocol);
960 dev->last_rx = jiffies;
961 np->stats.rx_packets++;
962 np->stats.rx_bytes += len;
969 * nv_change_mtu: dev->change_mtu function
970 * Called with dev_base_lock held for read.
972 static int nv_change_mtu(struct net_device *dev, int new_mtu)
974 if (new_mtu > DEFAULT_MTU)
981 * nv_set_multicast: dev->set_multicast function
982 * Called with dev->xmit_lock held.
984 static void nv_set_multicast(struct net_device *dev)
986 struct fe_priv *np = get_nvpriv(dev);
987 u8 *base = get_hwbase(dev);
992 memset(addr, 0, sizeof(addr));
993 memset(mask, 0, sizeof(mask));
995 if (dev->flags & IFF_PROMISC) {
996 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
997 pff = NVREG_PFF_PROMISC;
999 pff = NVREG_PFF_MYADDR;
1001 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1005 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1006 if (dev->flags & IFF_ALLMULTI) {
1007 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1009 struct dev_mc_list *walk;
1011 walk = dev->mc_list;
1012 while (walk != NULL) {
1014 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1015 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1023 addr[0] = alwaysOn[0];
1024 addr[1] = alwaysOn[1];
1025 mask[0] = alwaysOn[0] | alwaysOff[0];
1026 mask[1] = alwaysOn[1] | alwaysOff[1];
1029 addr[0] |= NVREG_MCASTADDRA_FORCE;
1030 pff |= NVREG_PFF_ALWAYS;
1031 spin_lock_irq(&np->lock);
1033 writel(addr[0], base + NvRegMulticastAddrA);
1034 writel(addr[1], base + NvRegMulticastAddrB);
1035 writel(mask[0], base + NvRegMulticastMaskA);
1036 writel(mask[1], base + NvRegMulticastMaskB);
1037 writel(pff, base + NvRegPacketFilterFlags);
1039 spin_unlock_irq(&np->lock);
1042 static int nv_update_linkspeed(struct net_device *dev)
1044 struct fe_priv *np = get_nvpriv(dev);
1045 int adv, lpa, newls, newdup;
1047 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1048 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1049 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1050 dev->name, adv, lpa);
1052 /* FIXME: handle parallel detection properly, handle gigabit ethernet */
1054 if (lpa & LPA_100FULL) {
1055 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1057 } else if (lpa & LPA_100HALF) {
1058 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1060 } else if (lpa & LPA_10FULL) {
1061 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1063 } else if (lpa & LPA_10HALF) {
1064 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1067 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1068 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1071 if (np->duplex != newdup || np->linkspeed != newls) {
1072 np->duplex = newdup;
1073 np->linkspeed = newls;
1079 static void nv_link_irq(struct net_device *dev)
1081 struct fe_priv *np = get_nvpriv(dev);
1082 u8 *base = get_hwbase(dev);
1086 miistat = readl(base + NvRegMIIStatus);
1087 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1088 printk(KERN_DEBUG "%s: link change notification, status 0x%x.\n", dev->name, miistat);
1090 miival = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1091 if (miival & BMSR_ANEGCOMPLETE) {
1092 nv_update_linkspeed(dev);
1094 if (netif_carrier_ok(dev)) {
1097 netif_carrier_on(dev);
1098 printk(KERN_INFO "%s: link up.\n", dev->name);
1100 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1104 if (netif_carrier_ok(dev)) {
1105 netif_carrier_off(dev);
1106 printk(KERN_INFO "%s: link down.\n", dev->name);
1109 writel(np->linkspeed, base + NvRegLinkSpeed);
1114 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1116 struct net_device *dev = (struct net_device *) data;
1117 struct fe_priv *np = get_nvpriv(dev);
1118 u8 *base = get_hwbase(dev);
1122 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1125 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1126 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1128 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1129 if (!(events & np->irqmask))
1132 if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX2|NVREG_IRQ_TX_ERR)) {
1133 spin_lock(&np->lock);
1135 spin_unlock(&np->lock);
1138 if (events & (NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF)) {
1140 if (nv_alloc_rx(dev)) {
1141 spin_lock(&np->lock);
1142 if (!np->in_shutdown)
1143 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1144 spin_unlock(&np->lock);
1148 if (events & NVREG_IRQ_LINK) {
1149 spin_lock(&np->lock);
1151 spin_unlock(&np->lock);
1153 if (events & (NVREG_IRQ_TX_ERR)) {
1154 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1157 if (events & (NVREG_IRQ_UNKNOWN)) {
1158 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1161 if (i > max_interrupt_work) {
1162 spin_lock(&np->lock);
1163 /* disable interrupts on the nic */
1164 writel(0, base + NvRegIrqMask);
1167 if (!np->in_shutdown)
1168 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1169 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1170 spin_unlock(&np->lock);
1175 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1177 return IRQ_RETVAL(i);
1180 static void nv_do_nic_poll(unsigned long data)
1182 struct net_device *dev = (struct net_device *) data;
1183 struct fe_priv *np = get_nvpriv(dev);
1184 u8 *base = get_hwbase(dev);
1186 disable_irq(dev->irq);
1187 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1189 * reenable interrupts on the nic, we have to do this before calling
1190 * nv_nic_irq because that may decide to do otherwise
1192 writel(np->irqmask, base + NvRegIrqMask);
1194 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1195 enable_irq(dev->irq);
1198 static int nv_open(struct net_device *dev)
1200 struct fe_priv *np = get_nvpriv(dev);
1201 u8 *base = get_hwbase(dev);
1204 dprintk(KERN_DEBUG "nv_open: begin\n");
1206 /* 1) erase previous misconfiguration */
1207 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
1208 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1209 writel(0, base + NvRegMulticastAddrB);
1210 writel(0, base + NvRegMulticastMaskA);
1211 writel(0, base + NvRegMulticastMaskB);
1212 writel(0, base + NvRegPacketFilterFlags);
1213 writel(0, base + NvRegAdapterControl);
1214 writel(0, base + NvRegLinkSpeed);
1215 writel(0, base + NvRegUnknownTransmitterReg);
1217 writel(0, base + NvRegUnknownSetupReg6);
1219 /* 2) initialize descriptor rings */
1220 np->in_shutdown = 0;
1221 oom = nv_init_ring(dev);
1223 /* 3) set mac address */
1227 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1228 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1229 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1231 writel(mac[0], base + NvRegMacAddrA);
1232 writel(mac[1], base + NvRegMacAddrB);
1235 /* 4) continue setup */
1236 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1238 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
1239 writel(0, base + NvRegTxRxControl);
1241 writel(NVREG_TXRXCTL_BIT1, base + NvRegTxRxControl);
1242 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
1243 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
1244 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
1245 writel(0, base + NvRegUnknownSetupReg4);
1247 /* 5) Find a suitable PHY */
1248 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
1249 for (i = 1; i < 32; i++) {
1252 spin_lock_irq(&np->lock);
1253 id1 = mii_rw(dev, i, MII_PHYSID1, MII_READ);
1254 spin_unlock_irq(&np->lock);
1255 if (id1 < 0 || id1 == 0xffff)
1257 spin_lock_irq(&np->lock);
1258 id2 = mii_rw(dev, i, MII_PHYSID2, MII_READ);
1259 spin_unlock_irq(&np->lock);
1260 if (id2 < 0 || id2 == 0xffff)
1262 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
1263 dev->name, id1, id2, i);
1266 spin_lock_irq(&np->lock);
1267 nv_update_linkspeed(dev);
1268 spin_unlock_irq(&np->lock);
1273 printk(KERN_INFO "%s: open: failing due to lack of suitable PHY.\n",
1279 /* 6) continue setup */
1280 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1282 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
1283 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
1284 writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig);
1286 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
1287 get_random_bytes(&i, sizeof(i));
1288 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
1289 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
1290 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
1291 writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
1292 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
1293 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID,
1294 base + NvRegAdapterControl);
1295 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
1296 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
1298 /* 7) start packet processing */
1299 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1300 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1301 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1302 base + NvRegRingSizes);
1304 i = readl(base + NvRegPowerState);
1305 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
1306 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
1310 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
1311 writel(NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
1314 writel(0, base + NvRegIrqMask);
1316 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1318 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1319 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1322 ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
1326 writel(np->irqmask, base + NvRegIrqMask);
1328 spin_lock_irq(&np->lock);
1329 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1330 writel(0, base + NvRegMulticastAddrB);
1331 writel(0, base + NvRegMulticastMaskA);
1332 writel(0, base + NvRegMulticastMaskB);
1333 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
1336 netif_start_queue(dev);
1338 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1339 if (mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ) & BMSR_ANEGCOMPLETE) {
1340 netif_carrier_on(dev);
1342 printk("%s: no link during initialization.\n", dev->name);
1343 netif_carrier_off(dev);
1346 spin_unlock_irq(&np->lock);
1354 static int nv_close(struct net_device *dev)
1356 struct fe_priv *np = get_nvpriv(dev);
1359 spin_lock_irq(&np->lock);
1360 np->in_shutdown = 1;
1361 spin_unlock_irq(&np->lock);
1362 synchronize_irq(dev->irq);
1364 del_timer_sync(&np->oom_kick);
1365 del_timer_sync(&np->nic_poll);
1367 netif_stop_queue(dev);
1368 spin_lock_irq(&np->lock);
1371 base = get_hwbase(dev);
1373 /* disable interrupts on the nic or we will lock up */
1374 writel(0, base + NvRegIrqMask);
1376 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
1378 spin_unlock_irq(&np->lock);
1380 free_irq(dev->irq, dev);
1387 /* FIXME: power down nic */
1392 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
1394 struct net_device *dev;
1400 dev = alloc_etherdev(sizeof(struct fe_priv));
1405 np = get_nvpriv(dev);
1406 np->pci_dev = pci_dev;
1407 spin_lock_init(&np->lock);
1408 SET_MODULE_OWNER(dev);
1409 SET_NETDEV_DEV(dev, &pci_dev->dev);
1411 init_timer(&np->oom_kick);
1412 np->oom_kick.data = (unsigned long) dev;
1413 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
1414 init_timer(&np->nic_poll);
1415 np->nic_poll.data = (unsigned long) dev;
1416 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
1418 err = pci_enable_device(pci_dev);
1420 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
1421 err, pci_name(pci_dev));
1425 pci_set_master(pci_dev);
1427 err = pci_request_regions(pci_dev, dev->name);
1433 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1434 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
1435 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
1436 pci_resource_len(pci_dev, i),
1437 pci_resource_flags(pci_dev, i));
1438 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
1439 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
1440 addr = pci_resource_start(pci_dev, i);
1444 if (i == DEVICE_COUNT_RESOURCE) {
1445 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
1451 dev->base_addr = (unsigned long) ioremap(addr, NV_PCI_REGSZ);
1452 if (!dev->base_addr)
1454 dev->irq = pci_dev->irq;
1455 np->rx_ring = pci_alloc_consistent(pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
1459 np->tx_ring = &np->rx_ring[RX_RING];
1461 dev->open = nv_open;
1462 dev->stop = nv_close;
1463 dev->hard_start_xmit = nv_start_xmit;
1464 dev->get_stats = nv_get_stats;
1465 dev->change_mtu = nv_change_mtu;
1466 dev->set_multicast_list = nv_set_multicast;
1467 dev->do_ioctl = nv_ioctl;
1468 dev->tx_timeout = nv_tx_timeout;
1469 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
1471 pci_set_drvdata(pci_dev, dev);
1473 /* read the mac address */
1474 base = get_hwbase(dev);
1475 np->orig_mac[0] = readl(base + NvRegMacAddrA);
1476 np->orig_mac[1] = readl(base + NvRegMacAddrB);
1478 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
1479 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
1480 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
1481 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
1482 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
1483 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
1485 if (!is_valid_ether_addr(dev->dev_addr)) {
1487 * Bad mac address. At least one bios sets the mac address
1488 * to 01:23:45:67:89:ab
1490 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
1492 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1493 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1494 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
1495 dev->dev_addr[0] = 0x00;
1496 dev->dev_addr[1] = 0x00;
1497 dev->dev_addr[2] = 0x6c;
1498 get_random_bytes(&dev->dev_addr[3], 3);
1501 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
1502 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1503 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1506 writel(0, base + NvRegWakeUpFlags);
1509 np->tx_flags = cpu_to_le16(NV_TX_LASTPACKET|NV_TX_LASTPACKET1|NV_TX_VALID);
1510 if (id->driver_data & DEV_NEED_LASTPACKET1)
1511 np->tx_flags |= cpu_to_le16(NV_TX_LASTPACKET1);
1512 if (id->driver_data & DEV_IRQMASK_1)
1513 np->irqmask = NVREG_IRQMASK_WANTED_1;
1514 if (id->driver_data & DEV_IRQMASK_2)
1515 np->irqmask = NVREG_IRQMASK_WANTED_2;
1516 if (id->driver_data & DEV_NEED_TIMERIRQ)
1517 np->irqmask |= NVREG_IRQ_TIMER;
1519 err = register_netdev(dev);
1521 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
1524 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
1525 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
1531 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
1532 np->rx_ring, np->ring_addr);
1533 pci_set_drvdata(pci_dev, NULL);
1535 iounmap(get_hwbase(dev));
1537 pci_release_regions(pci_dev);
1539 pci_disable_device(pci_dev);
1546 static void __devexit nv_remove(struct pci_dev *pci_dev)
1548 struct net_device *dev = pci_get_drvdata(pci_dev);
1549 struct fe_priv *np = get_nvpriv(dev);
1550 u8 *base = get_hwbase(dev);
1552 unregister_netdev(dev);
1554 /* special op: write back the misordered MAC address - otherwise
1555 * the next nv_probe would see a wrong address.
1557 writel(np->orig_mac[0], base + NvRegMacAddrA);
1558 writel(np->orig_mac[1], base + NvRegMacAddrB);
1560 /* free all structures */
1561 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring, np->ring_addr);
1562 iounmap(get_hwbase(dev));
1563 pci_release_regions(pci_dev);
1564 pci_disable_device(pci_dev);
1566 pci_set_drvdata(pci_dev, NULL);
1569 static struct pci_device_id pci_tbl[] = {
1570 { /* nForce Ethernet Controller */
1571 .vendor = PCI_VENDOR_ID_NVIDIA,
1573 .subvendor = PCI_ANY_ID,
1574 .subdevice = PCI_ANY_ID,
1575 .driver_data = DEV_IRQMASK_1|DEV_NEED_TIMERIRQ,
1577 { /* nForce2 Ethernet Controller */
1578 .vendor = PCI_VENDOR_ID_NVIDIA,
1580 .subvendor = PCI_ANY_ID,
1581 .subdevice = PCI_ANY_ID,
1582 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1584 { /* nForce3 Ethernet Controller */
1585 .vendor = PCI_VENDOR_ID_NVIDIA,
1587 .subvendor = PCI_ANY_ID,
1588 .subdevice = PCI_ANY_ID,
1589 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1594 static struct pci_driver driver = {
1595 .name = "forcedeth",
1596 .id_table = pci_tbl,
1598 .remove = __devexit_p(nv_remove),
1602 static int __init init_nic(void)
1604 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
1605 return pci_module_init(&driver);
1608 static void __exit exit_nic(void)
1610 pci_unregister_driver(&driver);
1613 MODULE_PARM(max_interrupt_work, "i");
1614 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
1616 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
1617 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
1618 MODULE_LICENSE("GPL");
1620 MODULE_DEVICE_TABLE(pci, pci_tbl);
1622 module_init(init_nic);
1623 module_exit(exit_nic);