2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
13 * Copyright (C) 2003,4 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80 * into nv_close, otherwise reenabling for wol can
81 * cause DMA to kfree'd memory.
84 * We suspect that on some hardware no TX done interrupts are generated.
85 * This means recovery from netif_stop_queue only happens if the hw timer
86 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
87 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
88 * If your hardware reliably generates tx done interrupts, then you can remove
89 * DEV_NEED_TIMERIRQ from the driver_data flags.
90 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
91 * superfluous timer interrupts from the nic.
93 #define FORCEDETH_VERSION "0.30"
94 #define DRV_NAME "forcedeth"
96 #include <linux/module.h>
97 #include <linux/types.h>
98 #include <linux/pci.h>
99 #include <linux/interrupt.h>
100 #include <linux/netdevice.h>
101 #include <linux/etherdevice.h>
102 #include <linux/delay.h>
103 #include <linux/spinlock.h>
104 #include <linux/ethtool.h>
105 #include <linux/timer.h>
106 #include <linux/skbuff.h>
107 #include <linux/mii.h>
108 #include <linux/random.h>
109 #include <linux/init.h>
113 #include <asm/uaccess.h>
114 #include <asm/system.h>
117 #define dprintk printk
119 #define dprintk(x...) do { } while (0)
127 #define DEV_NEED_LASTPACKET1 0x0001 /* set LASTPACKET1 in tx flags */
128 #define DEV_IRQMASK_1 0x0002 /* use NVREG_IRQMASK_WANTED_1 for irq mask */
129 #define DEV_IRQMASK_2 0x0004 /* use NVREG_IRQMASK_WANTED_2 for irq mask */
130 #define DEV_NEED_TIMERIRQ 0x0008 /* set the timer irq flag in the irq mask */
131 #define DEV_NEED_LINKTIMER 0x0010 /* poll link settings. Relies on the timer irq */
134 NvRegIrqStatus = 0x000,
135 #define NVREG_IRQSTAT_MIIEVENT 0x040
136 #define NVREG_IRQSTAT_MASK 0x1ff
137 NvRegIrqMask = 0x004,
138 #define NVREG_IRQ_RX_ERROR 0x0001
139 #define NVREG_IRQ_RX 0x0002
140 #define NVREG_IRQ_RX_NOBUF 0x0004
141 #define NVREG_IRQ_TX_ERR 0x0008
142 #define NVREG_IRQ_TX2 0x0010
143 #define NVREG_IRQ_TIMER 0x0020
144 #define NVREG_IRQ_LINK 0x0040
145 #define NVREG_IRQ_TX1 0x0100
146 #define NVREG_IRQMASK_WANTED_1 0x005f
147 #define NVREG_IRQMASK_WANTED_2 0x0147
148 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
150 NvRegUnknownSetupReg6 = 0x008,
151 #define NVREG_UNKSETUP6_VAL 3
154 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
155 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
157 NvRegPollingInterval = 0x00c,
158 #define NVREG_POLL_DEFAULT 970
160 #define NVREG_MISC1_HD 0x02
161 #define NVREG_MISC1_FORCE 0x3b0f3c
163 NvRegTransmitterControl = 0x084,
164 #define NVREG_XMITCTL_START 0x01
165 NvRegTransmitterStatus = 0x088,
166 #define NVREG_XMITSTAT_BUSY 0x01
168 NvRegPacketFilterFlags = 0x8c,
169 #define NVREG_PFF_ALWAYS 0x7F0008
170 #define NVREG_PFF_PROMISC 0x80
171 #define NVREG_PFF_MYADDR 0x20
173 NvRegOffloadConfig = 0x90,
174 #define NVREG_OFFLOAD_HOMEPHY 0x601
175 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
176 NvRegReceiverControl = 0x094,
177 #define NVREG_RCVCTL_START 0x01
178 NvRegReceiverStatus = 0x98,
179 #define NVREG_RCVSTAT_BUSY 0x01
181 NvRegRandomSeed = 0x9c,
182 #define NVREG_RNDSEED_MASK 0x00ff
183 #define NVREG_RNDSEED_FORCE 0x7f00
184 #define NVREG_RNDSEED_FORCE2 0x2d00
185 #define NVREG_RNDSEED_FORCE3 0x7400
187 NvRegUnknownSetupReg1 = 0xA0,
188 #define NVREG_UNKSETUP1_VAL 0x16070f
189 NvRegUnknownSetupReg2 = 0xA4,
190 #define NVREG_UNKSETUP2_VAL 0x16
191 NvRegMacAddrA = 0xA8,
192 NvRegMacAddrB = 0xAC,
193 NvRegMulticastAddrA = 0xB0,
194 #define NVREG_MCASTADDRA_FORCE 0x01
195 NvRegMulticastAddrB = 0xB4,
196 NvRegMulticastMaskA = 0xB8,
197 NvRegMulticastMaskB = 0xBC,
199 NvRegPhyInterface = 0xC0,
200 #define PHY_RGMII 0x10000000
202 NvRegTxRingPhysAddr = 0x100,
203 NvRegRxRingPhysAddr = 0x104,
204 NvRegRingSizes = 0x108,
205 #define NVREG_RINGSZ_TXSHIFT 0
206 #define NVREG_RINGSZ_RXSHIFT 16
207 NvRegUnknownTransmitterReg = 0x10c,
208 NvRegLinkSpeed = 0x110,
209 #define NVREG_LINKSPEED_FORCE 0x10000
210 #define NVREG_LINKSPEED_10 1000
211 #define NVREG_LINKSPEED_100 100
212 #define NVREG_LINKSPEED_1000 50
213 NvRegUnknownSetupReg5 = 0x130,
214 #define NVREG_UNKSETUP5_BIT31 (1<<31)
215 NvRegUnknownSetupReg3 = 0x13c,
216 #define NVREG_UNKSETUP3_VAL1 0x200010
217 NvRegTxRxControl = 0x144,
218 #define NVREG_TXRXCTL_KICK 0x0001
219 #define NVREG_TXRXCTL_BIT1 0x0002
220 #define NVREG_TXRXCTL_BIT2 0x0004
221 #define NVREG_TXRXCTL_IDLE 0x0008
222 #define NVREG_TXRXCTL_RESET 0x0010
223 #define NVREG_TXRXCTL_RXCHECK 0x0400
224 NvRegMIIStatus = 0x180,
225 #define NVREG_MIISTAT_ERROR 0x0001
226 #define NVREG_MIISTAT_LINKCHANGE 0x0008
227 #define NVREG_MIISTAT_MASK 0x000f
228 #define NVREG_MIISTAT_MASK2 0x000f
229 NvRegUnknownSetupReg4 = 0x184,
230 #define NVREG_UNKSETUP4_VAL 8
232 NvRegAdapterControl = 0x188,
233 #define NVREG_ADAPTCTL_START 0x02
234 #define NVREG_ADAPTCTL_LINKUP 0x04
235 #define NVREG_ADAPTCTL_PHYVALID 0x40000
236 #define NVREG_ADAPTCTL_RUNNING 0x100000
237 #define NVREG_ADAPTCTL_PHYSHIFT 24
238 NvRegMIISpeed = 0x18c,
239 #define NVREG_MIISPEED_BIT8 (1<<8)
240 #define NVREG_MIIDELAY 5
241 NvRegMIIControl = 0x190,
242 #define NVREG_MIICTL_INUSE 0x08000
243 #define NVREG_MIICTL_WRITE 0x00400
244 #define NVREG_MIICTL_ADDRSHIFT 5
245 NvRegMIIData = 0x194,
246 NvRegWakeUpFlags = 0x200,
247 #define NVREG_WAKEUPFLAGS_VAL 0x7770
248 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
249 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
250 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
251 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
252 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
253 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
254 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
255 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
256 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
257 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
259 NvRegPatternCRC = 0x204,
260 NvRegPatternMask = 0x208,
261 NvRegPowerCap = 0x268,
262 #define NVREG_POWERCAP_D3SUPP (1<<30)
263 #define NVREG_POWERCAP_D2SUPP (1<<26)
264 #define NVREG_POWERCAP_D1SUPP (1<<25)
265 NvRegPowerState = 0x26c,
266 #define NVREG_POWERSTATE_POWEREDUP 0x8000
267 #define NVREG_POWERSTATE_VALID 0x0100
268 #define NVREG_POWERSTATE_MASK 0x0003
269 #define NVREG_POWERSTATE_D0 0x0000
270 #define NVREG_POWERSTATE_D1 0x0001
271 #define NVREG_POWERSTATE_D2 0x0002
272 #define NVREG_POWERSTATE_D3 0x0003
275 /* Big endian: should work, but is untested */
281 #define FLAG_MASK_V1 0xffff0000
282 #define FLAG_MASK_V2 0xffffc000
283 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
284 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
286 #define NV_TX_LASTPACKET (1<<16)
287 #define NV_TX_RETRYERROR (1<<19)
288 #define NV_TX_LASTPACKET1 (1<<24)
289 #define NV_TX_DEFERRED (1<<26)
290 #define NV_TX_CARRIERLOST (1<<27)
291 #define NV_TX_LATECOLLISION (1<<28)
292 #define NV_TX_UNDERFLOW (1<<29)
293 #define NV_TX_ERROR (1<<30)
294 #define NV_TX_VALID (1<<31)
296 #define NV_TX2_LASTPACKET (1<<29)
297 #define NV_TX2_RETRYERROR (1<<18)
298 #define NV_TX2_LASTPACKET1 (1<<23)
299 #define NV_TX2_DEFERRED (1<<25)
300 #define NV_TX2_CARRIERLOST (1<<26)
301 #define NV_TX2_LATECOLLISION (1<<27)
302 #define NV_TX2_UNDERFLOW (1<<28)
303 /* error and valid are the same for both */
304 #define NV_TX2_ERROR (1<<30)
305 #define NV_TX2_VALID (1<<31)
307 #define NV_RX_DESCRIPTORVALID (1<<16)
308 #define NV_RX_MISSEDFRAME (1<<17)
309 #define NV_RX_SUBSTRACT1 (1<<18)
310 #define NV_RX_ERROR1 (1<<23)
311 #define NV_RX_ERROR2 (1<<24)
312 #define NV_RX_ERROR3 (1<<25)
313 #define NV_RX_ERROR4 (1<<26)
314 #define NV_RX_CRCERR (1<<27)
315 #define NV_RX_OVERFLOW (1<<28)
316 #define NV_RX_FRAMINGERR (1<<29)
317 #define NV_RX_ERROR (1<<30)
318 #define NV_RX_AVAIL (1<<31)
320 #define NV_RX2_CHECKSUMMASK (0x1C000000)
321 #define NV_RX2_CHECKSUMOK1 (0x10000000)
322 #define NV_RX2_CHECKSUMOK2 (0x14000000)
323 #define NV_RX2_CHECKSUMOK3 (0x18000000)
324 #define NV_RX2_DESCRIPTORVALID (1<<29)
325 #define NV_RX2_SUBSTRACT1 (1<<25)
326 #define NV_RX2_ERROR1 (1<<18)
327 #define NV_RX2_ERROR2 (1<<19)
328 #define NV_RX2_ERROR3 (1<<20)
329 #define NV_RX2_ERROR4 (1<<21)
330 #define NV_RX2_CRCERR (1<<22)
331 #define NV_RX2_OVERFLOW (1<<23)
332 #define NV_RX2_FRAMINGERR (1<<24)
333 /* error and avail are the same for both */
334 #define NV_RX2_ERROR (1<<30)
335 #define NV_RX2_AVAIL (1<<31)
337 /* Miscelaneous hardware related defines: */
338 #define NV_PCI_REGSZ 0x270
340 /* various timeout delays: all in usec */
341 #define NV_TXRX_RESET_DELAY 4
342 #define NV_TXSTOP_DELAY1 10
343 #define NV_TXSTOP_DELAY1MAX 500000
344 #define NV_TXSTOP_DELAY2 100
345 #define NV_RXSTOP_DELAY1 10
346 #define NV_RXSTOP_DELAY1MAX 500000
347 #define NV_RXSTOP_DELAY2 100
348 #define NV_SETUP5_DELAY 5
349 #define NV_SETUP5_DELAYMAX 50000
350 #define NV_POWERUP_DELAY 5
351 #define NV_POWERUP_DELAYMAX 5000
352 #define NV_MIIBUSY_DELAY 50
353 #define NV_MIIPHY_DELAY 10
354 #define NV_MIIPHY_DELAYMAX 10000
356 #define NV_WAKEUPPATTERNS 5
357 #define NV_WAKEUPMASKENTRIES 4
359 /* General driver defaults */
360 #define NV_WATCHDOG_TIMEO (5*HZ)
365 * If your nic mysteriously hangs then try to reduce the limits
366 * to 1/0: It might be required to set NV_TX_LASTPACKET in the
367 * last valid ring entry. But this would be impossible to
368 * implement - probably a disassembly error.
370 #define TX_LIMIT_STOP 63
371 #define TX_LIMIT_START 62
373 /* rx/tx mac addr + type + vlan + align + slack*/
374 #define RX_NIC_BUFSIZE (ETH_DATA_LEN + 64)
375 /* even more slack */
376 #define RX_ALLOC_BUFSIZE (ETH_DATA_LEN + 128)
378 #define OOM_REFILL (1+HZ/20)
379 #define POLL_WAIT (1+HZ/100)
380 #define LINK_TIMEOUT (3*HZ)
384 * This field has two purposes:
385 * - Newer nics uses a different ring layout. The layout is selected by
386 * comparing np->desc_ver with DESC_VER_xy.
387 * - It contains bits that are forced on when writing to NvRegTxRxControl.
389 #define DESC_VER_1 0x0
390 #define DESC_VER_2 (0x02100|NVREG_TXRXCTL_RXCHECK)
393 #define PHY_OUI_MARVELL 0x5043
394 #define PHY_OUI_CICADA 0x03f1
395 #define PHYID1_OUI_MASK 0x03ff
396 #define PHYID1_OUI_SHFT 6
397 #define PHYID2_OUI_MASK 0xfc00
398 #define PHYID2_OUI_SHFT 10
399 #define PHY_INIT1 0x0f000
400 #define PHY_INIT2 0x0e00
401 #define PHY_INIT3 0x01000
402 #define PHY_INIT4 0x0200
403 #define PHY_INIT5 0x0004
404 #define PHY_INIT6 0x02000
405 #define PHY_GIGABIT 0x0100
407 #define PHY_TIMEOUT 0x1
408 #define PHY_ERROR 0x2
412 #define PHY_HALF 0x100
414 /* FIXME: MII defines that should be added to <linux/mii.h> */
415 #define MII_1000BT_CR 0x09
416 #define MII_1000BT_SR 0x0a
417 #define ADVERTISE_1000FULL 0x0200
418 #define ADVERTISE_1000HALF 0x0100
419 #define LPA_1000FULL 0x0800
420 #define LPA_1000HALF 0x0400
425 * All hardware access under dev->priv->lock, except the performance
427 * - rx is (pseudo-) lockless: it relies on the single-threading provided
428 * by the arch code for interrupts.
429 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
430 * needs dev->priv->lock :-(
431 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
434 /* in dev: base, irq */
439 * Locking: spin_lock(&np->lock); */
440 struct net_device_stats stats;
446 unsigned int phy_oui;
449 /* General data: RO fields */
450 dma_addr_t ring_addr;
451 struct pci_dev *pci_dev;
456 /* rx specific fields.
457 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
459 struct ring_desc *rx_ring;
460 unsigned int cur_rx, refill_rx;
461 struct sk_buff *rx_skbuff[RX_RING];
462 dma_addr_t rx_dma[RX_RING];
463 unsigned int rx_buf_sz;
464 struct timer_list oom_kick;
465 struct timer_list nic_poll;
467 /* media detection workaround.
468 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
471 unsigned long link_timeout;
473 * tx specific fields.
475 struct ring_desc *tx_ring;
476 unsigned int next_tx, nic_tx;
477 struct sk_buff *tx_skbuff[TX_RING];
478 dma_addr_t tx_dma[TX_RING];
483 * Maximum number of loops until we assume that a bit in the irq mask
484 * is stuck. Overridable with module param.
486 static int max_interrupt_work = 5;
488 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
490 return (struct fe_priv *) dev->priv;
493 static inline u8 *get_hwbase(struct net_device *dev)
495 return (u8 *) dev->base_addr;
498 static inline void pci_push(u8 * base)
500 /* force out pending posted writes */
504 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
506 return le32_to_cpu(prd->FlagLen)
507 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
510 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
511 int delay, int delaymax, const char *msg)
513 u8 *base = get_hwbase(dev);
524 } while ((readl(base + offset) & mask) != target);
528 #define MII_READ (-1)
529 /* mii_rw: read/write a register on the PHY.
531 * Caller must guarantee serialization
533 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
535 u8 *base = get_hwbase(dev);
539 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
541 reg = readl(base + NvRegMIIControl);
542 if (reg & NVREG_MIICTL_INUSE) {
543 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
544 udelay(NV_MIIBUSY_DELAY);
547 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
548 if (value != MII_READ) {
549 writel(value, base + NvRegMIIData);
550 reg |= NVREG_MIICTL_WRITE;
552 writel(reg, base + NvRegMIIControl);
554 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
555 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
556 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
557 dev->name, miireg, addr);
559 } else if (value != MII_READ) {
560 /* it was a write operation - fewer failures are detectable */
561 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
562 dev->name, value, miireg, addr);
564 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
565 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
566 dev->name, miireg, addr);
569 retval = readl(base + NvRegMIIData);
570 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
571 dev->name, miireg, addr, retval);
577 static int phy_reset(struct net_device *dev)
579 struct fe_priv *np = get_nvpriv(dev);
581 unsigned int tries = 0;
583 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
584 miicontrol |= BMCR_RESET;
585 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
592 /* must wait till reset is deasserted */
593 while (miicontrol & BMCR_RESET) {
595 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
596 /* FIXME: 100 tries seem excessive */
603 static int phy_init(struct net_device *dev)
605 struct fe_priv *np = get_nvpriv(dev);
606 u8 *base = get_hwbase(dev);
607 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
609 /* set advertise register */
610 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
611 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
612 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
613 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
617 /* get phy interface type */
618 phyinterface = readl(base + NvRegPhyInterface);
620 /* see if gigabit phy */
621 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
622 if (mii_status & PHY_GIGABIT) {
623 np->gigabit = PHY_GIGABIT;
624 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
625 mii_control_1000 &= ~ADVERTISE_1000HALF;
626 if (phyinterface & PHY_RGMII)
627 mii_control_1000 |= ADVERTISE_1000FULL;
629 mii_control_1000 &= ~ADVERTISE_1000FULL;
631 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
632 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
640 if (phy_reset(dev)) {
641 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
645 /* phy vendor specific configuration */
646 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
647 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
648 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
649 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
650 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
651 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
654 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
655 phy_reserved |= PHY_INIT5;
656 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
657 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
661 if (np->phy_oui == PHY_OUI_CICADA) {
662 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
663 phy_reserved |= PHY_INIT6;
664 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
665 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
670 /* restart auto negotiation */
671 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
672 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
673 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
680 static void nv_start_rx(struct net_device *dev)
682 struct fe_priv *np = get_nvpriv(dev);
683 u8 *base = get_hwbase(dev);
685 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
686 /* Already running? Stop it. */
687 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
688 writel(0, base + NvRegReceiverControl);
691 writel(np->linkspeed, base + NvRegLinkSpeed);
693 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
694 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
695 dev->name, np->duplex, np->linkspeed);
699 static void nv_stop_rx(struct net_device *dev)
701 u8 *base = get_hwbase(dev);
703 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
704 writel(0, base + NvRegReceiverControl);
705 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
706 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
707 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
709 udelay(NV_RXSTOP_DELAY2);
710 writel(0, base + NvRegLinkSpeed);
713 static void nv_start_tx(struct net_device *dev)
715 u8 *base = get_hwbase(dev);
717 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
718 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
722 static void nv_stop_tx(struct net_device *dev)
724 u8 *base = get_hwbase(dev);
726 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
727 writel(0, base + NvRegTransmitterControl);
728 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
729 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
730 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
732 udelay(NV_TXSTOP_DELAY2);
733 writel(0, base + NvRegUnknownTransmitterReg);
736 static void nv_txrx_reset(struct net_device *dev)
738 struct fe_priv *np = get_nvpriv(dev);
739 u8 *base = get_hwbase(dev);
741 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
742 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->desc_ver, base + NvRegTxRxControl);
744 udelay(NV_TXRX_RESET_DELAY);
745 writel(NVREG_TXRXCTL_BIT2 | np->desc_ver, base + NvRegTxRxControl);
750 * nv_get_stats: dev->get_stats function
751 * Get latest stats value from the nic.
752 * Called with read_lock(&dev_base_lock) held for read -
753 * only synchronized against unregister_netdevice.
755 static struct net_device_stats *nv_get_stats(struct net_device *dev)
757 struct fe_priv *np = get_nvpriv(dev);
759 /* It seems that the nic always generates interrupts and doesn't
760 * accumulate errors internally. Thus the current values in np->stats
761 * are already up to date.
766 static int nv_ethtool_ioctl(struct net_device *dev, void __user *useraddr)
768 struct fe_priv *np = get_nvpriv(dev);
769 u8 *base = get_hwbase(dev);
772 if (copy_from_user(ðcmd, useraddr, sizeof (ethcmd)))
776 case ETHTOOL_GDRVINFO:
778 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
779 strcpy(info.driver, "forcedeth");
780 strcpy(info.version, FORCEDETH_VERSION);
781 strcpy(info.bus_info, pci_name(np->pci_dev));
782 if (copy_to_user(useraddr, &info, sizeof (info)))
788 struct ethtool_value edata = { ETHTOOL_GLINK };
790 edata.data = !!netif_carrier_ok(dev);
792 if (copy_to_user(useraddr, &edata, sizeof(edata)))
798 struct ethtool_wolinfo wolinfo;
799 memset(&wolinfo, 0, sizeof(wolinfo));
800 wolinfo.supported = WAKE_MAGIC;
802 spin_lock_irq(&np->lock);
804 wolinfo.wolopts = WAKE_MAGIC;
805 spin_unlock_irq(&np->lock);
807 if (copy_to_user(useraddr, &wolinfo, sizeof(wolinfo)))
813 struct ethtool_wolinfo wolinfo;
814 if (copy_from_user(&wolinfo, useraddr, sizeof(wolinfo)))
817 spin_lock_irq(&np->lock);
818 if (wolinfo.wolopts == 0) {
819 writel(0, base + NvRegWakeUpFlags);
822 if (wolinfo.wolopts & WAKE_MAGIC) {
823 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
826 spin_unlock_irq(&np->lock);
837 * nv_ioctl: dev->do_ioctl function
838 * Called with rtnl_lock held.
840 static int nv_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
844 return nv_ethtool_ioctl(dev, rq->ifr_data);
852 * nv_alloc_rx: fill rx ring entries.
853 * Return 1 if the allocations for the skbs failed and the
854 * rx engine is without Available descriptors
856 static int nv_alloc_rx(struct net_device *dev)
858 struct fe_priv *np = get_nvpriv(dev);
859 unsigned int refill_rx = np->refill_rx;
862 while (np->cur_rx != refill_rx) {
865 nr = refill_rx % RX_RING;
866 if (np->rx_skbuff[nr] == NULL) {
868 skb = dev_alloc_skb(RX_ALLOC_BUFSIZE);
873 np->rx_skbuff[nr] = skb;
875 skb = np->rx_skbuff[nr];
877 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
879 np->rx_ring[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
881 np->rx_ring[nr].FlagLen = cpu_to_le32(RX_NIC_BUFSIZE | NV_RX_AVAIL);
882 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
883 dev->name, refill_rx);
886 np->refill_rx = refill_rx;
887 if (np->cur_rx - refill_rx == RX_RING)
892 static void nv_do_rx_refill(unsigned long data)
894 struct net_device *dev = (struct net_device *) data;
895 struct fe_priv *np = get_nvpriv(dev);
897 disable_irq(dev->irq);
898 if (nv_alloc_rx(dev)) {
899 spin_lock(&np->lock);
900 if (!np->in_shutdown)
901 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
902 spin_unlock(&np->lock);
904 enable_irq(dev->irq);
907 static int nv_init_ring(struct net_device *dev)
909 struct fe_priv *np = get_nvpriv(dev);
912 np->next_tx = np->nic_tx = 0;
913 for (i = 0; i < TX_RING; i++)
914 np->tx_ring[i].FlagLen = 0;
916 np->cur_rx = RX_RING;
918 for (i = 0; i < RX_RING; i++)
919 np->rx_ring[i].FlagLen = 0;
920 return nv_alloc_rx(dev);
923 static void nv_drain_tx(struct net_device *dev)
925 struct fe_priv *np = get_nvpriv(dev);
927 for (i = 0; i < TX_RING; i++) {
928 np->tx_ring[i].FlagLen = 0;
929 if (np->tx_skbuff[i]) {
930 pci_unmap_single(np->pci_dev, np->tx_dma[i],
931 np->tx_skbuff[i]->len,
933 dev_kfree_skb(np->tx_skbuff[i]);
934 np->tx_skbuff[i] = NULL;
935 np->stats.tx_dropped++;
940 static void nv_drain_rx(struct net_device *dev)
942 struct fe_priv *np = get_nvpriv(dev);
944 for (i = 0; i < RX_RING; i++) {
945 np->rx_ring[i].FlagLen = 0;
947 if (np->rx_skbuff[i]) {
948 pci_unmap_single(np->pci_dev, np->rx_dma[i],
949 np->rx_skbuff[i]->len,
951 dev_kfree_skb(np->rx_skbuff[i]);
952 np->rx_skbuff[i] = NULL;
957 static void drain_ring(struct net_device *dev)
964 * nv_start_xmit: dev->hard_start_xmit function
965 * Called with dev->xmit_lock held.
967 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
969 struct fe_priv *np = get_nvpriv(dev);
970 int nr = np->next_tx % TX_RING;
972 np->tx_skbuff[nr] = skb;
973 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data,skb->len,
976 np->tx_ring[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
978 spin_lock_irq(&np->lock);
980 np->tx_ring[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags );
981 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission.\n",
982 dev->name, np->next_tx);
985 for (j=0; j<64; j++) {
987 dprintk("\n%03x:", j);
988 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
995 dev->trans_start = jiffies;
996 if (np->next_tx - np->nic_tx >= TX_LIMIT_STOP)
997 netif_stop_queue(dev);
998 spin_unlock_irq(&np->lock);
999 writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl);
1000 pci_push(get_hwbase(dev));
1005 * nv_tx_done: check for completed packets, release the skbs.
1007 * Caller must own np->lock.
1009 static void nv_tx_done(struct net_device *dev)
1011 struct fe_priv *np = get_nvpriv(dev);
1015 while (np->nic_tx != np->next_tx) {
1016 i = np->nic_tx % TX_RING;
1018 Flags = le32_to_cpu(np->tx_ring[i].FlagLen);
1020 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1021 dev->name, np->nic_tx, Flags);
1022 if (Flags & NV_TX_VALID)
1024 if (np->desc_ver == DESC_VER_1) {
1025 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1026 NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1027 if (Flags & NV_TX_UNDERFLOW)
1028 np->stats.tx_fifo_errors++;
1029 if (Flags & NV_TX_CARRIERLOST)
1030 np->stats.tx_carrier_errors++;
1031 np->stats.tx_errors++;
1033 np->stats.tx_packets++;
1034 np->stats.tx_bytes += np->tx_skbuff[i]->len;
1037 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1038 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1039 if (Flags & NV_TX2_UNDERFLOW)
1040 np->stats.tx_fifo_errors++;
1041 if (Flags & NV_TX2_CARRIERLOST)
1042 np->stats.tx_carrier_errors++;
1043 np->stats.tx_errors++;
1045 np->stats.tx_packets++;
1046 np->stats.tx_bytes += np->tx_skbuff[i]->len;
1049 pci_unmap_single(np->pci_dev, np->tx_dma[i],
1050 np->tx_skbuff[i]->len,
1052 dev_kfree_skb_irq(np->tx_skbuff[i]);
1053 np->tx_skbuff[i] = NULL;
1056 if (np->next_tx - np->nic_tx < TX_LIMIT_START)
1057 netif_wake_queue(dev);
1061 * nv_tx_timeout: dev->tx_timeout function
1062 * Called with dev->xmit_lock held.
1064 static void nv_tx_timeout(struct net_device *dev)
1066 struct fe_priv *np = get_nvpriv(dev);
1067 u8 *base = get_hwbase(dev);
1069 dprintk(KERN_DEBUG "%s: Got tx_timeout. irq: %08x\n", dev->name,
1070 readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
1072 spin_lock_irq(&np->lock);
1074 /* 1) stop tx engine */
1077 /* 2) check that the packets were not sent already: */
1080 /* 3) if there are dead entries: clear everything */
1081 if (np->next_tx != np->nic_tx) {
1082 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1084 np->next_tx = np->nic_tx = 0;
1085 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1086 netif_wake_queue(dev);
1089 /* 4) restart tx engine */
1091 spin_unlock_irq(&np->lock);
1094 static void nv_rx_process(struct net_device *dev)
1096 struct fe_priv *np = get_nvpriv(dev);
1100 struct sk_buff *skb;
1103 if (np->cur_rx - np->refill_rx >= RX_RING)
1104 break; /* we scanned the whole ring - do not continue */
1106 i = np->cur_rx % RX_RING;
1107 Flags = le32_to_cpu(np->rx_ring[i].FlagLen);
1108 len = nv_descr_getlength(&np->rx_ring[i], np->desc_ver);
1110 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1111 dev->name, np->cur_rx, Flags);
1113 if (Flags & NV_RX_AVAIL)
1114 break; /* still owned by hardware, */
1117 * the packet is for us - immediately tear down the pci mapping.
1118 * TODO: check if a prefetch of the first cacheline improves
1121 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1122 np->rx_skbuff[i]->len,
1123 PCI_DMA_FROMDEVICE);
1127 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1128 for (j=0; j<64; j++) {
1130 dprintk("\n%03x:", j);
1131 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1135 /* look at what we actually got: */
1136 if (np->desc_ver == DESC_VER_1) {
1137 if (!(Flags & NV_RX_DESCRIPTORVALID))
1140 if (Flags & NV_RX_MISSEDFRAME) {
1141 np->stats.rx_missed_errors++;
1142 np->stats.rx_errors++;
1145 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4)) {
1146 np->stats.rx_errors++;
1149 if (Flags & NV_RX_CRCERR) {
1150 np->stats.rx_crc_errors++;
1151 np->stats.rx_errors++;
1154 if (Flags & NV_RX_OVERFLOW) {
1155 np->stats.rx_over_errors++;
1156 np->stats.rx_errors++;
1159 if (Flags & NV_RX_ERROR) {
1160 /* framing errors are soft errors, the rest is fatal. */
1161 if (Flags & NV_RX_FRAMINGERR) {
1162 if (Flags & NV_RX_SUBSTRACT1) {
1166 np->stats.rx_errors++;
1171 if (!(Flags & NV_RX2_DESCRIPTORVALID))
1174 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4)) {
1175 np->stats.rx_errors++;
1178 if (Flags & NV_RX2_CRCERR) {
1179 np->stats.rx_crc_errors++;
1180 np->stats.rx_errors++;
1183 if (Flags & NV_RX2_OVERFLOW) {
1184 np->stats.rx_over_errors++;
1185 np->stats.rx_errors++;
1188 if (Flags & NV_RX2_ERROR) {
1189 /* framing errors are soft errors, the rest is fatal. */
1190 if (Flags & NV_RX2_FRAMINGERR) {
1191 if (Flags & NV_RX2_SUBSTRACT1) {
1195 np->stats.rx_errors++;
1199 Flags &= NV_RX2_CHECKSUMMASK;
1200 if (Flags == NV_RX2_CHECKSUMOK1 ||
1201 Flags == NV_RX2_CHECKSUMOK2 ||
1202 Flags == NV_RX2_CHECKSUMOK3) {
1203 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1204 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1206 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1209 /* got a valid packet - forward it to the network core */
1210 skb = np->rx_skbuff[i];
1211 np->rx_skbuff[i] = NULL;
1214 skb->protocol = eth_type_trans(skb, dev);
1215 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1216 dev->name, np->cur_rx, len, skb->protocol);
1218 dev->last_rx = jiffies;
1219 np->stats.rx_packets++;
1220 np->stats.rx_bytes += len;
1227 * nv_change_mtu: dev->change_mtu function
1228 * Called with dev_base_lock held for read.
1230 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1232 if (new_mtu > ETH_DATA_LEN)
1239 * nv_set_multicast: dev->set_multicast function
1240 * Called with dev->xmit_lock held.
1242 static void nv_set_multicast(struct net_device *dev)
1244 struct fe_priv *np = get_nvpriv(dev);
1245 u8 *base = get_hwbase(dev);
1250 memset(addr, 0, sizeof(addr));
1251 memset(mask, 0, sizeof(mask));
1253 if (dev->flags & IFF_PROMISC) {
1254 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1255 pff = NVREG_PFF_PROMISC;
1257 pff = NVREG_PFF_MYADDR;
1259 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1263 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1264 if (dev->flags & IFF_ALLMULTI) {
1265 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1267 struct dev_mc_list *walk;
1269 walk = dev->mc_list;
1270 while (walk != NULL) {
1272 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1273 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1281 addr[0] = alwaysOn[0];
1282 addr[1] = alwaysOn[1];
1283 mask[0] = alwaysOn[0] | alwaysOff[0];
1284 mask[1] = alwaysOn[1] | alwaysOff[1];
1287 addr[0] |= NVREG_MCASTADDRA_FORCE;
1288 pff |= NVREG_PFF_ALWAYS;
1289 spin_lock_irq(&np->lock);
1291 writel(addr[0], base + NvRegMulticastAddrA);
1292 writel(addr[1], base + NvRegMulticastAddrB);
1293 writel(mask[0], base + NvRegMulticastMaskA);
1294 writel(mask[1], base + NvRegMulticastMaskB);
1295 writel(pff, base + NvRegPacketFilterFlags);
1296 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1299 spin_unlock_irq(&np->lock);
1302 static int nv_update_linkspeed(struct net_device *dev)
1304 struct fe_priv *np = get_nvpriv(dev);
1305 u8 *base = get_hwbase(dev);
1307 int newls = np->linkspeed;
1308 int newdup = np->duplex;
1311 u32 control_1000, status_1000, phyreg;
1313 /* BMSR_LSTATUS is latched, read it twice:
1314 * we want the current value.
1316 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1317 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1319 if (!(mii_status & BMSR_LSTATUS)) {
1320 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1322 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1328 /* check auto negotiation is complete */
1329 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1330 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1331 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1334 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1339 if (np->gigabit == PHY_GIGABIT) {
1340 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1341 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1343 if ((control_1000 & ADVERTISE_1000FULL) &&
1344 (status_1000 & LPA_1000FULL)) {
1345 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1347 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1353 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1354 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1355 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1356 dev->name, adv, lpa);
1358 /* FIXME: handle parallel detection properly */
1360 if (lpa & LPA_100FULL) {
1361 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1363 } else if (lpa & LPA_100HALF) {
1364 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1366 } else if (lpa & LPA_10FULL) {
1367 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1369 } else if (lpa & LPA_10HALF) {
1370 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1373 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1374 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1379 if (np->duplex == newdup && np->linkspeed == newls)
1382 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1383 dev->name, np->linkspeed, np->duplex, newls, newdup);
1385 np->duplex = newdup;
1386 np->linkspeed = newls;
1388 if (np->gigabit == PHY_GIGABIT) {
1389 phyreg = readl(base + NvRegRandomSeed);
1390 phyreg &= ~(0x3FF00);
1391 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1392 phyreg |= NVREG_RNDSEED_FORCE3;
1393 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1394 phyreg |= NVREG_RNDSEED_FORCE2;
1395 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1396 phyreg |= NVREG_RNDSEED_FORCE;
1397 writel(phyreg, base + NvRegRandomSeed);
1400 phyreg = readl(base + NvRegPhyInterface);
1401 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1402 if (np->duplex == 0)
1404 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1406 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1408 writel(phyreg, base + NvRegPhyInterface);
1410 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1413 writel(np->linkspeed, base + NvRegLinkSpeed);
1419 static void nv_linkchange(struct net_device *dev)
1421 if (nv_update_linkspeed(dev)) {
1422 if (netif_carrier_ok(dev)) {
1425 netif_carrier_on(dev);
1426 printk(KERN_INFO "%s: link up.\n", dev->name);
1430 if (netif_carrier_ok(dev)) {
1431 netif_carrier_off(dev);
1432 printk(KERN_INFO "%s: link down.\n", dev->name);
1438 static void nv_link_irq(struct net_device *dev)
1440 u8 *base = get_hwbase(dev);
1443 miistat = readl(base + NvRegMIIStatus);
1444 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1445 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
1447 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
1449 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1452 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1454 struct net_device *dev = (struct net_device *) data;
1455 struct fe_priv *np = get_nvpriv(dev);
1456 u8 *base = get_hwbase(dev);
1460 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1463 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1464 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1466 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1467 if (!(events & np->irqmask))
1470 if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX2|NVREG_IRQ_TX_ERR)) {
1471 spin_lock(&np->lock);
1473 spin_unlock(&np->lock);
1476 if (events & (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF)) {
1478 if (nv_alloc_rx(dev)) {
1479 spin_lock(&np->lock);
1480 if (!np->in_shutdown)
1481 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1482 spin_unlock(&np->lock);
1486 if (events & NVREG_IRQ_LINK) {
1487 spin_lock(&np->lock);
1489 spin_unlock(&np->lock);
1491 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
1492 spin_lock(&np->lock);
1494 spin_unlock(&np->lock);
1495 np->link_timeout = jiffies + LINK_TIMEOUT;
1497 if (events & (NVREG_IRQ_TX_ERR)) {
1498 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1501 if (events & (NVREG_IRQ_UNKNOWN)) {
1502 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1505 if (i > max_interrupt_work) {
1506 spin_lock(&np->lock);
1507 /* disable interrupts on the nic */
1508 writel(0, base + NvRegIrqMask);
1511 if (!np->in_shutdown)
1512 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1513 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1514 spin_unlock(&np->lock);
1519 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1521 return IRQ_RETVAL(i);
1524 static void nv_do_nic_poll(unsigned long data)
1526 struct net_device *dev = (struct net_device *) data;
1527 struct fe_priv *np = get_nvpriv(dev);
1528 u8 *base = get_hwbase(dev);
1530 disable_irq(dev->irq);
1531 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1533 * reenable interrupts on the nic, we have to do this before calling
1534 * nv_nic_irq because that may decide to do otherwise
1536 writel(np->irqmask, base + NvRegIrqMask);
1538 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1539 enable_irq(dev->irq);
1542 static int nv_open(struct net_device *dev)
1544 struct fe_priv *np = get_nvpriv(dev);
1545 u8 *base = get_hwbase(dev);
1548 dprintk(KERN_DEBUG "nv_open: begin\n");
1550 /* 1) erase previous misconfiguration */
1551 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
1552 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1553 writel(0, base + NvRegMulticastAddrB);
1554 writel(0, base + NvRegMulticastMaskA);
1555 writel(0, base + NvRegMulticastMaskB);
1556 writel(0, base + NvRegPacketFilterFlags);
1558 writel(0, base + NvRegTransmitterControl);
1559 writel(0, base + NvRegReceiverControl);
1561 writel(0, base + NvRegAdapterControl);
1563 /* 2) initialize descriptor rings */
1564 oom = nv_init_ring(dev);
1566 writel(0, base + NvRegLinkSpeed);
1567 writel(0, base + NvRegUnknownTransmitterReg);
1569 writel(0, base + NvRegUnknownSetupReg6);
1571 np->in_shutdown = 0;
1573 /* 3) set mac address */
1577 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1578 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1579 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1581 writel(mac[0], base + NvRegMacAddrA);
1582 writel(mac[1], base + NvRegMacAddrB);
1585 /* 4) give hw rings */
1586 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1587 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1588 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1589 base + NvRegRingSizes);
1591 /* 5) continue setup */
1592 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1595 writel(np->linkspeed, base + NvRegLinkSpeed);
1596 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
1597 writel(np->desc_ver, base + NvRegTxRxControl);
1599 writel(NVREG_TXRXCTL_BIT1|np->desc_ver, base + NvRegTxRxControl);
1600 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
1601 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
1602 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
1604 writel(0, base + NvRegUnknownSetupReg4);
1605 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1606 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1608 /* 6) continue setup */
1609 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
1610 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
1611 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
1612 writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig);
1614 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
1615 get_random_bytes(&i, sizeof(i));
1616 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
1617 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
1618 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
1619 writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
1620 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
1621 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
1622 base + NvRegAdapterControl);
1623 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
1624 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
1625 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
1627 i = readl(base + NvRegPowerState);
1628 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
1629 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
1633 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
1635 writel(0, base + NvRegIrqMask);
1637 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1638 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1641 ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
1645 /* ask for interrupts */
1646 writel(np->irqmask, base + NvRegIrqMask);
1648 spin_lock_irq(&np->lock);
1649 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1650 writel(0, base + NvRegMulticastAddrB);
1651 writel(0, base + NvRegMulticastMaskA);
1652 writel(0, base + NvRegMulticastMaskB);
1653 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
1654 /* One manual link speed update: Interrupts are enabled, future link
1655 * speed changes cause interrupts and are handled by nv_link_irq().
1659 miistat = readl(base + NvRegMIIStatus);
1660 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1661 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
1663 ret = nv_update_linkspeed(dev);
1666 netif_start_queue(dev);
1668 netif_carrier_on(dev);
1670 printk("%s: no link during initialization.\n", dev->name);
1671 netif_carrier_off(dev);
1674 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1675 spin_unlock_irq(&np->lock);
1683 static int nv_close(struct net_device *dev)
1685 struct fe_priv *np = get_nvpriv(dev);
1688 spin_lock_irq(&np->lock);
1689 np->in_shutdown = 1;
1690 spin_unlock_irq(&np->lock);
1691 synchronize_irq(dev->irq);
1693 del_timer_sync(&np->oom_kick);
1694 del_timer_sync(&np->nic_poll);
1696 netif_stop_queue(dev);
1697 spin_lock_irq(&np->lock);
1702 /* disable interrupts on the nic or we will lock up */
1703 base = get_hwbase(dev);
1704 writel(0, base + NvRegIrqMask);
1706 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
1708 spin_unlock_irq(&np->lock);
1710 free_irq(dev->irq, dev);
1717 /* FIXME: power down nic */
1722 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
1724 struct net_device *dev;
1730 dev = alloc_etherdev(sizeof(struct fe_priv));
1735 np = get_nvpriv(dev);
1736 np->pci_dev = pci_dev;
1737 spin_lock_init(&np->lock);
1738 SET_MODULE_OWNER(dev);
1739 SET_NETDEV_DEV(dev, &pci_dev->dev);
1741 init_timer(&np->oom_kick);
1742 np->oom_kick.data = (unsigned long) dev;
1743 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
1744 init_timer(&np->nic_poll);
1745 np->nic_poll.data = (unsigned long) dev;
1746 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
1748 err = pci_enable_device(pci_dev);
1750 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
1751 err, pci_name(pci_dev));
1755 pci_set_master(pci_dev);
1757 err = pci_request_regions(pci_dev, DRV_NAME);
1763 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1764 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
1765 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
1766 pci_resource_len(pci_dev, i),
1767 pci_resource_flags(pci_dev, i));
1768 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
1769 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
1770 addr = pci_resource_start(pci_dev, i);
1774 if (i == DEVICE_COUNT_RESOURCE) {
1775 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
1780 /* handle different descriptor versions */
1781 if (pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_1 ||
1782 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_2 ||
1783 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_3)
1784 np->desc_ver = DESC_VER_1;
1786 np->desc_ver = DESC_VER_2;
1789 dev->base_addr = (unsigned long) ioremap(addr, NV_PCI_REGSZ);
1790 if (!dev->base_addr)
1792 dev->irq = pci_dev->irq;
1793 np->rx_ring = pci_alloc_consistent(pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
1797 np->tx_ring = &np->rx_ring[RX_RING];
1799 dev->open = nv_open;
1800 dev->stop = nv_close;
1801 dev->hard_start_xmit = nv_start_xmit;
1802 dev->get_stats = nv_get_stats;
1803 dev->change_mtu = nv_change_mtu;
1804 dev->set_multicast_list = nv_set_multicast;
1805 dev->do_ioctl = nv_ioctl;
1806 dev->tx_timeout = nv_tx_timeout;
1807 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
1809 pci_set_drvdata(pci_dev, dev);
1811 /* read the mac address */
1812 base = get_hwbase(dev);
1813 np->orig_mac[0] = readl(base + NvRegMacAddrA);
1814 np->orig_mac[1] = readl(base + NvRegMacAddrB);
1816 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
1817 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
1818 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
1819 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
1820 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
1821 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
1823 if (!is_valid_ether_addr(dev->dev_addr)) {
1825 * Bad mac address. At least one bios sets the mac address
1826 * to 01:23:45:67:89:ab
1828 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
1830 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1831 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1832 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
1833 dev->dev_addr[0] = 0x00;
1834 dev->dev_addr[1] = 0x00;
1835 dev->dev_addr[2] = 0x6c;
1836 get_random_bytes(&dev->dev_addr[3], 3);
1839 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
1840 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1841 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1844 writel(0, base + NvRegWakeUpFlags);
1847 if (np->desc_ver == DESC_VER_1) {
1848 np->tx_flags = NV_TX_LASTPACKET|NV_TX_VALID;
1849 if (id->driver_data & DEV_NEED_LASTPACKET1)
1850 np->tx_flags |= NV_TX_LASTPACKET1;
1852 np->tx_flags = NV_TX2_LASTPACKET|NV_TX2_VALID;
1853 if (id->driver_data & DEV_NEED_LASTPACKET1)
1854 np->tx_flags |= NV_TX2_LASTPACKET1;
1856 if (id->driver_data & DEV_IRQMASK_1)
1857 np->irqmask = NVREG_IRQMASK_WANTED_1;
1858 if (id->driver_data & DEV_IRQMASK_2)
1859 np->irqmask = NVREG_IRQMASK_WANTED_2;
1860 if (id->driver_data & DEV_NEED_TIMERIRQ)
1861 np->irqmask |= NVREG_IRQ_TIMER;
1862 if (id->driver_data & DEV_NEED_LINKTIMER) {
1863 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
1864 np->need_linktimer = 1;
1865 np->link_timeout = jiffies + LINK_TIMEOUT;
1867 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
1868 np->need_linktimer = 0;
1871 /* find a suitable phy */
1872 for (i = 1; i < 32; i++) {
1875 spin_lock_irq(&np->lock);
1876 id1 = mii_rw(dev, i, MII_PHYSID1, MII_READ);
1877 spin_unlock_irq(&np->lock);
1878 if (id1 < 0 || id1 == 0xffff)
1880 spin_lock_irq(&np->lock);
1881 id2 = mii_rw(dev, i, MII_PHYSID2, MII_READ);
1882 spin_unlock_irq(&np->lock);
1883 if (id2 < 0 || id2 == 0xffff)
1886 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
1887 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
1888 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
1889 pci_name(pci_dev), id1, id2, i);
1891 np->phy_oui = id1 | id2;
1895 /* PHY in isolate mode? No phy attached and user wants to
1896 * test loopback? Very odd, but can be correct.
1898 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
1907 err = register_netdev(dev);
1909 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
1912 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
1913 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
1919 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
1920 np->rx_ring, np->ring_addr);
1921 pci_set_drvdata(pci_dev, NULL);
1923 iounmap(get_hwbase(dev));
1925 pci_release_regions(pci_dev);
1927 pci_disable_device(pci_dev);
1934 static void __devexit nv_remove(struct pci_dev *pci_dev)
1936 struct net_device *dev = pci_get_drvdata(pci_dev);
1937 struct fe_priv *np = get_nvpriv(dev);
1938 u8 *base = get_hwbase(dev);
1940 unregister_netdev(dev);
1942 /* special op: write back the misordered MAC address - otherwise
1943 * the next nv_probe would see a wrong address.
1945 writel(np->orig_mac[0], base + NvRegMacAddrA);
1946 writel(np->orig_mac[1], base + NvRegMacAddrB);
1948 /* free all structures */
1949 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring, np->ring_addr);
1950 iounmap(get_hwbase(dev));
1951 pci_release_regions(pci_dev);
1952 pci_disable_device(pci_dev);
1954 pci_set_drvdata(pci_dev, NULL);
1957 static struct pci_device_id pci_tbl[] = {
1958 { /* nForce Ethernet Controller */
1959 .vendor = PCI_VENDOR_ID_NVIDIA,
1960 .device = PCI_DEVICE_ID_NVIDIA_NVENET_1,
1961 .subvendor = PCI_ANY_ID,
1962 .subdevice = PCI_ANY_ID,
1963 .driver_data = DEV_IRQMASK_1|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
1965 { /* nForce2 Ethernet Controller */
1966 .vendor = PCI_VENDOR_ID_NVIDIA,
1967 .device = PCI_DEVICE_ID_NVIDIA_NVENET_2,
1968 .subvendor = PCI_ANY_ID,
1969 .subdevice = PCI_ANY_ID,
1970 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
1972 { /* nForce3 Ethernet Controller */
1973 .vendor = PCI_VENDOR_ID_NVIDIA,
1974 .device = PCI_DEVICE_ID_NVIDIA_NVENET_3,
1975 .subvendor = PCI_ANY_ID,
1976 .subdevice = PCI_ANY_ID,
1977 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
1979 { /* nForce3 Ethernet Controller */
1980 .vendor = PCI_VENDOR_ID_NVIDIA,
1981 .device = PCI_DEVICE_ID_NVIDIA_NVENET_4,
1982 .subvendor = PCI_ANY_ID,
1983 .subdevice = PCI_ANY_ID,
1984 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1986 { /* nForce3 Ethernet Controller */
1987 .vendor = PCI_VENDOR_ID_NVIDIA,
1988 .device = PCI_DEVICE_ID_NVIDIA_NVENET_5,
1989 .subvendor = PCI_ANY_ID,
1990 .subdevice = PCI_ANY_ID,
1991 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1993 { /* nForce3 Ethernet Controller */
1994 .vendor = PCI_VENDOR_ID_NVIDIA,
1995 .device = PCI_DEVICE_ID_NVIDIA_NVENET_6,
1996 .subvendor = PCI_ANY_ID,
1997 .subdevice = PCI_ANY_ID,
1998 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
2000 { /* nForce3 Ethernet Controller */
2001 .vendor = PCI_VENDOR_ID_NVIDIA,
2002 .device = PCI_DEVICE_ID_NVIDIA_NVENET_7,
2003 .subvendor = PCI_ANY_ID,
2004 .subdevice = PCI_ANY_ID,
2005 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
2007 { /* CK804 Ethernet Controller */
2008 .vendor = PCI_VENDOR_ID_NVIDIA,
2009 .device = PCI_DEVICE_ID_NVIDIA_NVENET_8,
2010 .subvendor = PCI_ANY_ID,
2011 .subdevice = PCI_ANY_ID,
2012 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
2014 { /* CK804 Ethernet Controller */
2015 .vendor = PCI_VENDOR_ID_NVIDIA,
2016 .device = PCI_DEVICE_ID_NVIDIA_NVENET_9,
2017 .subvendor = PCI_ANY_ID,
2018 .subdevice = PCI_ANY_ID,
2019 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
2021 { /* MCP04 Ethernet Controller */
2022 .vendor = PCI_VENDOR_ID_NVIDIA,
2023 .device = PCI_DEVICE_ID_NVIDIA_NVENET_10,
2024 .subvendor = PCI_ANY_ID,
2025 .subdevice = PCI_ANY_ID,
2026 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
2028 { /* MCP04 Ethernet Controller */
2029 .vendor = PCI_VENDOR_ID_NVIDIA,
2030 .device = PCI_DEVICE_ID_NVIDIA_NVENET_11,
2031 .subvendor = PCI_ANY_ID,
2032 .subdevice = PCI_ANY_ID,
2033 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
2038 static struct pci_driver driver = {
2039 .name = "forcedeth",
2040 .id_table = pci_tbl,
2042 .remove = __devexit_p(nv_remove),
2046 static int __init init_nic(void)
2048 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
2049 return pci_module_init(&driver);
2052 static void __exit exit_nic(void)
2054 pci_unregister_driver(&driver);
2057 module_param(max_interrupt_work, int, 0);
2058 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2060 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2061 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2062 MODULE_LICENSE("GPL");
2064 MODULE_DEVICE_TABLE(pci, pci_tbl);
2066 module_init(init_nic);
2067 module_exit(exit_nic);