2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
13 * Copyright (C) 2003,4,5 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80 * into nv_close, otherwise reenabling for wol can
81 * cause DMA to kfree'd memory.
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
85 * 0.33: 16 May 2005: Support for MCP51 added.
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
87 * 0.35: 26 Jun 2005: Support for MCP55 added.
88 * 0.36: 28 Jun 2005: Add jumbo frame support.
89 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
90 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
92 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
93 * 0.40: 19 Jul 2005: Add support for mac address change.
94 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
96 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
97 * in the second (and later) nv_open call
98 * 0.43: 10 Aug 2005: Add support for tx checksum.
99 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
100 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
101 * 0.46: 20 Oct 2005: Add irq optimization modes.
102 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
103 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
104 * 0.49: 10 Dec 2005: Fix tso for large buffers.
105 * 0.50: 20 Jan 2006: Add 8021pq tagging support.
106 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
107 * 0.52: 20 Jan 2006: Add MSI/MSIX support.
108 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
109 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
110 * 0.55: 22 Mar 2006: Add flow control (pause frame).
111 * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
114 * We suspect that on some hardware no TX done interrupts are generated.
115 * This means recovery from netif_stop_queue only happens if the hw timer
116 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
117 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
118 * If your hardware reliably generates tx done interrupts, then you can remove
119 * DEV_NEED_TIMERIRQ from the driver_data flags.
120 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
121 * superfluous timer interrupts from the nic.
123 #define FORCEDETH_VERSION "0.56"
124 #define DRV_NAME "forcedeth"
126 #include <linux/module.h>
127 #include <linux/types.h>
128 #include <linux/pci.h>
129 #include <linux/interrupt.h>
130 #include <linux/netdevice.h>
131 #include <linux/etherdevice.h>
132 #include <linux/delay.h>
133 #include <linux/spinlock.h>
134 #include <linux/ethtool.h>
135 #include <linux/timer.h>
136 #include <linux/skbuff.h>
137 #include <linux/mii.h>
138 #include <linux/random.h>
139 #include <linux/init.h>
140 #include <linux/if_vlan.h>
141 #include <linux/dma-mapping.h>
145 #include <asm/uaccess.h>
146 #include <asm/system.h>
149 #define dprintk printk
151 #define dprintk(x...) do { } while (0)
159 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
160 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
161 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
162 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
163 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
164 #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */
165 #define DEV_HAS_MSI 0x0040 /* device supports MSI */
166 #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
167 #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
168 #define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
169 #define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */
170 #define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */
173 NvRegIrqStatus = 0x000,
174 #define NVREG_IRQSTAT_MIIEVENT 0x040
175 #define NVREG_IRQSTAT_MASK 0x1ff
176 NvRegIrqMask = 0x004,
177 #define NVREG_IRQ_RX_ERROR 0x0001
178 #define NVREG_IRQ_RX 0x0002
179 #define NVREG_IRQ_RX_NOBUF 0x0004
180 #define NVREG_IRQ_TX_ERR 0x0008
181 #define NVREG_IRQ_TX_OK 0x0010
182 #define NVREG_IRQ_TIMER 0x0020
183 #define NVREG_IRQ_LINK 0x0040
184 #define NVREG_IRQ_RX_FORCED 0x0080
185 #define NVREG_IRQ_TX_FORCED 0x0100
186 #define NVREG_IRQMASK_THROUGHPUT 0x00df
187 #define NVREG_IRQMASK_CPU 0x0040
188 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
189 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
190 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK)
192 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
193 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
194 NVREG_IRQ_TX_FORCED))
196 NvRegUnknownSetupReg6 = 0x008,
197 #define NVREG_UNKSETUP6_VAL 3
200 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
201 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
203 NvRegPollingInterval = 0x00c,
204 #define NVREG_POLL_DEFAULT_THROUGHPUT 970
205 #define NVREG_POLL_DEFAULT_CPU 13
206 NvRegMSIMap0 = 0x020,
207 NvRegMSIMap1 = 0x024,
208 NvRegMSIIrqMask = 0x030,
209 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
211 #define NVREG_MISC1_PAUSE_TX 0x01
212 #define NVREG_MISC1_HD 0x02
213 #define NVREG_MISC1_FORCE 0x3b0f3c
215 NvRegMacReset = 0x3c,
216 #define NVREG_MAC_RESET_ASSERT 0x0F3
217 NvRegTransmitterControl = 0x084,
218 #define NVREG_XMITCTL_START 0x01
219 NvRegTransmitterStatus = 0x088,
220 #define NVREG_XMITSTAT_BUSY 0x01
222 NvRegPacketFilterFlags = 0x8c,
223 #define NVREG_PFF_PAUSE_RX 0x08
224 #define NVREG_PFF_ALWAYS 0x7F0000
225 #define NVREG_PFF_PROMISC 0x80
226 #define NVREG_PFF_MYADDR 0x20
227 #define NVREG_PFF_LOOPBACK 0x10
229 NvRegOffloadConfig = 0x90,
230 #define NVREG_OFFLOAD_HOMEPHY 0x601
231 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
232 NvRegReceiverControl = 0x094,
233 #define NVREG_RCVCTL_START 0x01
234 NvRegReceiverStatus = 0x98,
235 #define NVREG_RCVSTAT_BUSY 0x01
237 NvRegRandomSeed = 0x9c,
238 #define NVREG_RNDSEED_MASK 0x00ff
239 #define NVREG_RNDSEED_FORCE 0x7f00
240 #define NVREG_RNDSEED_FORCE2 0x2d00
241 #define NVREG_RNDSEED_FORCE3 0x7400
243 NvRegTxDeferral = 0xA0,
244 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
245 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
246 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
247 NvRegRxDeferral = 0xA4,
248 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
249 NvRegMacAddrA = 0xA8,
250 NvRegMacAddrB = 0xAC,
251 NvRegMulticastAddrA = 0xB0,
252 #define NVREG_MCASTADDRA_FORCE 0x01
253 NvRegMulticastAddrB = 0xB4,
254 NvRegMulticastMaskA = 0xB8,
255 NvRegMulticastMaskB = 0xBC,
257 NvRegPhyInterface = 0xC0,
258 #define PHY_RGMII 0x10000000
260 NvRegTxRingPhysAddr = 0x100,
261 NvRegRxRingPhysAddr = 0x104,
262 NvRegRingSizes = 0x108,
263 #define NVREG_RINGSZ_TXSHIFT 0
264 #define NVREG_RINGSZ_RXSHIFT 16
265 NvRegUnknownTransmitterReg = 0x10c,
266 NvRegLinkSpeed = 0x110,
267 #define NVREG_LINKSPEED_FORCE 0x10000
268 #define NVREG_LINKSPEED_10 1000
269 #define NVREG_LINKSPEED_100 100
270 #define NVREG_LINKSPEED_1000 50
271 #define NVREG_LINKSPEED_MASK (0xFFF)
272 NvRegUnknownSetupReg5 = 0x130,
273 #define NVREG_UNKSETUP5_BIT31 (1<<31)
274 NvRegTxWatermark = 0x13c,
275 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
276 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
277 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
278 NvRegTxRxControl = 0x144,
279 #define NVREG_TXRXCTL_KICK 0x0001
280 #define NVREG_TXRXCTL_BIT1 0x0002
281 #define NVREG_TXRXCTL_BIT2 0x0004
282 #define NVREG_TXRXCTL_IDLE 0x0008
283 #define NVREG_TXRXCTL_RESET 0x0010
284 #define NVREG_TXRXCTL_RXCHECK 0x0400
285 #define NVREG_TXRXCTL_DESC_1 0
286 #define NVREG_TXRXCTL_DESC_2 0x02100
287 #define NVREG_TXRXCTL_DESC_3 0x02200
288 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
289 #define NVREG_TXRXCTL_VLANINS 0x00080
290 NvRegTxRingPhysAddrHigh = 0x148,
291 NvRegRxRingPhysAddrHigh = 0x14C,
292 NvRegTxPauseFrame = 0x170,
293 #define NVREG_TX_PAUSEFRAME_DISABLE 0x1ff0080
294 #define NVREG_TX_PAUSEFRAME_ENABLE 0x0c00030
295 NvRegMIIStatus = 0x180,
296 #define NVREG_MIISTAT_ERROR 0x0001
297 #define NVREG_MIISTAT_LINKCHANGE 0x0008
298 #define NVREG_MIISTAT_MASK 0x000f
299 #define NVREG_MIISTAT_MASK2 0x000f
300 NvRegUnknownSetupReg4 = 0x184,
301 #define NVREG_UNKSETUP4_VAL 8
303 NvRegAdapterControl = 0x188,
304 #define NVREG_ADAPTCTL_START 0x02
305 #define NVREG_ADAPTCTL_LINKUP 0x04
306 #define NVREG_ADAPTCTL_PHYVALID 0x40000
307 #define NVREG_ADAPTCTL_RUNNING 0x100000
308 #define NVREG_ADAPTCTL_PHYSHIFT 24
309 NvRegMIISpeed = 0x18c,
310 #define NVREG_MIISPEED_BIT8 (1<<8)
311 #define NVREG_MIIDELAY 5
312 NvRegMIIControl = 0x190,
313 #define NVREG_MIICTL_INUSE 0x08000
314 #define NVREG_MIICTL_WRITE 0x00400
315 #define NVREG_MIICTL_ADDRSHIFT 5
316 NvRegMIIData = 0x194,
317 NvRegWakeUpFlags = 0x200,
318 #define NVREG_WAKEUPFLAGS_VAL 0x7770
319 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
320 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
321 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
322 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
323 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
324 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
325 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
326 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
327 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
328 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
330 NvRegPatternCRC = 0x204,
331 NvRegPatternMask = 0x208,
332 NvRegPowerCap = 0x268,
333 #define NVREG_POWERCAP_D3SUPP (1<<30)
334 #define NVREG_POWERCAP_D2SUPP (1<<26)
335 #define NVREG_POWERCAP_D1SUPP (1<<25)
336 NvRegPowerState = 0x26c,
337 #define NVREG_POWERSTATE_POWEREDUP 0x8000
338 #define NVREG_POWERSTATE_VALID 0x0100
339 #define NVREG_POWERSTATE_MASK 0x0003
340 #define NVREG_POWERSTATE_D0 0x0000
341 #define NVREG_POWERSTATE_D1 0x0001
342 #define NVREG_POWERSTATE_D2 0x0002
343 #define NVREG_POWERSTATE_D3 0x0003
345 NvRegTxZeroReXmt = 0x284,
346 NvRegTxOneReXmt = 0x288,
347 NvRegTxManyReXmt = 0x28c,
348 NvRegTxLateCol = 0x290,
349 NvRegTxUnderflow = 0x294,
350 NvRegTxLossCarrier = 0x298,
351 NvRegTxExcessDef = 0x29c,
352 NvRegTxRetryErr = 0x2a0,
353 NvRegRxFrameErr = 0x2a4,
354 NvRegRxExtraByte = 0x2a8,
355 NvRegRxLateCol = 0x2ac,
357 NvRegRxFrameTooLong = 0x2b4,
358 NvRegRxOverflow = 0x2b8,
359 NvRegRxFCSErr = 0x2bc,
360 NvRegRxFrameAlignErr = 0x2c0,
361 NvRegRxLenErr = 0x2c4,
362 NvRegRxUnicast = 0x2c8,
363 NvRegRxMulticast = 0x2cc,
364 NvRegRxBroadcast = 0x2d0,
366 NvRegTxFrame = 0x2d8,
368 NvRegTxPause = 0x2e0,
369 NvRegRxPause = 0x2e4,
370 NvRegRxDropFrame = 0x2e8,
371 NvRegVlanControl = 0x300,
372 #define NVREG_VLANCONTROL_ENABLE 0x2000
373 NvRegMSIXMap0 = 0x3e0,
374 NvRegMSIXMap1 = 0x3e4,
375 NvRegMSIXIrqStatus = 0x3f0,
377 NvRegPowerState2 = 0x600,
378 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
379 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
382 /* Big endian: should work, but is untested */
388 struct ring_desc_ex {
389 u32 PacketBufferHigh;
395 typedef union _ring_type {
396 struct ring_desc* orig;
397 struct ring_desc_ex* ex;
400 #define FLAG_MASK_V1 0xffff0000
401 #define FLAG_MASK_V2 0xffffc000
402 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
403 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
405 #define NV_TX_LASTPACKET (1<<16)
406 #define NV_TX_RETRYERROR (1<<19)
407 #define NV_TX_FORCED_INTERRUPT (1<<24)
408 #define NV_TX_DEFERRED (1<<26)
409 #define NV_TX_CARRIERLOST (1<<27)
410 #define NV_TX_LATECOLLISION (1<<28)
411 #define NV_TX_UNDERFLOW (1<<29)
412 #define NV_TX_ERROR (1<<30)
413 #define NV_TX_VALID (1<<31)
415 #define NV_TX2_LASTPACKET (1<<29)
416 #define NV_TX2_RETRYERROR (1<<18)
417 #define NV_TX2_FORCED_INTERRUPT (1<<30)
418 #define NV_TX2_DEFERRED (1<<25)
419 #define NV_TX2_CARRIERLOST (1<<26)
420 #define NV_TX2_LATECOLLISION (1<<27)
421 #define NV_TX2_UNDERFLOW (1<<28)
422 /* error and valid are the same for both */
423 #define NV_TX2_ERROR (1<<30)
424 #define NV_TX2_VALID (1<<31)
425 #define NV_TX2_TSO (1<<28)
426 #define NV_TX2_TSO_SHIFT 14
427 #define NV_TX2_TSO_MAX_SHIFT 14
428 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
429 #define NV_TX2_CHECKSUM_L3 (1<<27)
430 #define NV_TX2_CHECKSUM_L4 (1<<26)
432 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
434 #define NV_RX_DESCRIPTORVALID (1<<16)
435 #define NV_RX_MISSEDFRAME (1<<17)
436 #define NV_RX_SUBSTRACT1 (1<<18)
437 #define NV_RX_ERROR1 (1<<23)
438 #define NV_RX_ERROR2 (1<<24)
439 #define NV_RX_ERROR3 (1<<25)
440 #define NV_RX_ERROR4 (1<<26)
441 #define NV_RX_CRCERR (1<<27)
442 #define NV_RX_OVERFLOW (1<<28)
443 #define NV_RX_FRAMINGERR (1<<29)
444 #define NV_RX_ERROR (1<<30)
445 #define NV_RX_AVAIL (1<<31)
447 #define NV_RX2_CHECKSUMMASK (0x1C000000)
448 #define NV_RX2_CHECKSUMOK1 (0x10000000)
449 #define NV_RX2_CHECKSUMOK2 (0x14000000)
450 #define NV_RX2_CHECKSUMOK3 (0x18000000)
451 #define NV_RX2_DESCRIPTORVALID (1<<29)
452 #define NV_RX2_SUBSTRACT1 (1<<25)
453 #define NV_RX2_ERROR1 (1<<18)
454 #define NV_RX2_ERROR2 (1<<19)
455 #define NV_RX2_ERROR3 (1<<20)
456 #define NV_RX2_ERROR4 (1<<21)
457 #define NV_RX2_CRCERR (1<<22)
458 #define NV_RX2_OVERFLOW (1<<23)
459 #define NV_RX2_FRAMINGERR (1<<24)
460 /* error and avail are the same for both */
461 #define NV_RX2_ERROR (1<<30)
462 #define NV_RX2_AVAIL (1<<31)
464 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
465 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
467 /* Miscelaneous hardware related defines: */
468 #define NV_PCI_REGSZ_VER1 0x270
469 #define NV_PCI_REGSZ_VER2 0x604
471 /* various timeout delays: all in usec */
472 #define NV_TXRX_RESET_DELAY 4
473 #define NV_TXSTOP_DELAY1 10
474 #define NV_TXSTOP_DELAY1MAX 500000
475 #define NV_TXSTOP_DELAY2 100
476 #define NV_RXSTOP_DELAY1 10
477 #define NV_RXSTOP_DELAY1MAX 500000
478 #define NV_RXSTOP_DELAY2 100
479 #define NV_SETUP5_DELAY 5
480 #define NV_SETUP5_DELAYMAX 50000
481 #define NV_POWERUP_DELAY 5
482 #define NV_POWERUP_DELAYMAX 5000
483 #define NV_MIIBUSY_DELAY 50
484 #define NV_MIIPHY_DELAY 10
485 #define NV_MIIPHY_DELAYMAX 10000
486 #define NV_MAC_RESET_DELAY 64
488 #define NV_WAKEUPPATTERNS 5
489 #define NV_WAKEUPMASKENTRIES 4
491 /* General driver defaults */
492 #define NV_WATCHDOG_TIMEO (5*HZ)
494 #define RX_RING_DEFAULT 128
495 #define TX_RING_DEFAULT 256
496 #define RX_RING_MIN 128
497 #define TX_RING_MIN 64
498 #define RING_MAX_DESC_VER_1 1024
499 #define RING_MAX_DESC_VER_2_3 16384
501 * Difference between the get and put pointers for the tx ring.
502 * This is used to throttle the amount of data outstanding in the
505 #define TX_LIMIT_DIFFERENCE 1
507 /* rx/tx mac addr + type + vlan + align + slack*/
508 #define NV_RX_HEADERS (64)
509 /* even more slack. */
510 #define NV_RX_ALLOC_PAD (64)
512 /* maximum mtu size */
513 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
514 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
516 #define OOM_REFILL (1+HZ/20)
517 #define POLL_WAIT (1+HZ/100)
518 #define LINK_TIMEOUT (3*HZ)
519 #define STATS_INTERVAL (10*HZ)
523 * The nic supports three different descriptor types:
524 * - DESC_VER_1: Original
525 * - DESC_VER_2: support for jumbo frames.
526 * - DESC_VER_3: 64-bit format.
533 #define PHY_OUI_MARVELL 0x5043
534 #define PHY_OUI_CICADA 0x03f1
535 #define PHYID1_OUI_MASK 0x03ff
536 #define PHYID1_OUI_SHFT 6
537 #define PHYID2_OUI_MASK 0xfc00
538 #define PHYID2_OUI_SHFT 10
539 #define PHY_INIT1 0x0f000
540 #define PHY_INIT2 0x0e00
541 #define PHY_INIT3 0x01000
542 #define PHY_INIT4 0x0200
543 #define PHY_INIT5 0x0004
544 #define PHY_INIT6 0x02000
545 #define PHY_GIGABIT 0x0100
547 #define PHY_TIMEOUT 0x1
548 #define PHY_ERROR 0x2
552 #define PHY_HALF 0x100
554 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
555 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
556 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
557 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
558 #define NV_PAUSEFRAME_RX_REQ 0x0010
559 #define NV_PAUSEFRAME_TX_REQ 0x0020
560 #define NV_PAUSEFRAME_AUTONEG 0x0040
562 /* MSI/MSI-X defines */
563 #define NV_MSI_X_MAX_VECTORS 8
564 #define NV_MSI_X_VECTORS_MASK 0x000f
565 #define NV_MSI_CAPABLE 0x0010
566 #define NV_MSI_X_CAPABLE 0x0020
567 #define NV_MSI_ENABLED 0x0040
568 #define NV_MSI_X_ENABLED 0x0080
570 #define NV_MSI_X_VECTOR_ALL 0x0
571 #define NV_MSI_X_VECTOR_RX 0x0
572 #define NV_MSI_X_VECTOR_TX 0x1
573 #define NV_MSI_X_VECTOR_OTHER 0x2
576 struct nv_ethtool_str {
577 char name[ETH_GSTRING_LEN];
580 static const struct nv_ethtool_str nv_estats_str[] = {
585 { "tx_late_collision" },
586 { "tx_fifo_errors" },
587 { "tx_carrier_errors" },
588 { "tx_excess_deferral" },
589 { "tx_retry_error" },
593 { "rx_frame_error" },
595 { "rx_late_collision" },
597 { "rx_frame_too_long" },
598 { "rx_over_errors" },
600 { "rx_frame_align_error" },
601 { "rx_length_error" },
609 { "rx_errors_total" }
612 struct nv_ethtool_stats {
617 u64 tx_late_collision;
619 u64 tx_carrier_errors;
620 u64 tx_excess_deferral;
627 u64 rx_late_collision;
629 u64 rx_frame_too_long;
632 u64 rx_frame_align_error;
645 #define NV_TEST_COUNT_BASE 3
646 #define NV_TEST_COUNT_EXTENDED 4
648 static const struct nv_ethtool_str nv_etests_str[] = {
649 { "link (online/offline)" },
650 { "register (offline) " },
651 { "interrupt (offline) " },
652 { "loopback (offline) " }
655 struct register_test {
660 static const struct register_test nv_registers_test[] = {
661 { NvRegUnknownSetupReg6, 0x01 },
662 { NvRegMisc1, 0x03c },
663 { NvRegOffloadConfig, 0x03ff },
664 { NvRegMulticastAddrA, 0xffffffff },
665 { NvRegTxWatermark, 0x0ff },
666 { NvRegWakeUpFlags, 0x07777 },
672 * All hardware access under dev->priv->lock, except the performance
674 * - rx is (pseudo-) lockless: it relies on the single-threading provided
675 * by the arch code for interrupts.
676 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
677 * needs dev->priv->lock :-(
678 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
681 /* in dev: base, irq */
686 * Locking: spin_lock(&np->lock); */
687 struct net_device_stats stats;
688 struct nv_ethtool_stats estats;
696 unsigned int phy_oui;
700 /* General data: RO fields */
701 dma_addr_t ring_addr;
702 struct pci_dev *pci_dev;
713 /* rx specific fields.
714 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
717 unsigned int cur_rx, refill_rx;
718 struct sk_buff **rx_skbuff;
720 unsigned int rx_buf_sz;
721 unsigned int pkt_limit;
722 struct timer_list oom_kick;
723 struct timer_list nic_poll;
724 struct timer_list stats_poll;
728 /* media detection workaround.
729 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
732 unsigned long link_timeout;
734 * tx specific fields.
737 unsigned int next_tx, nic_tx;
738 struct sk_buff **tx_skbuff;
740 unsigned int *tx_dma_len;
747 struct vlan_group *vlangrp;
749 /* msi/msi-x fields */
751 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
758 * Maximum number of loops until we assume that a bit in the irq mask
759 * is stuck. Overridable with module param.
761 static int max_interrupt_work = 5;
764 * Optimization can be either throuput mode or cpu mode
766 * Throughput Mode: Every tx and rx packet will generate an interrupt.
767 * CPU Mode: Interrupts are controlled by a timer.
770 NV_OPTIMIZATION_MODE_THROUGHPUT,
771 NV_OPTIMIZATION_MODE_CPU
773 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
776 * Poll interval for timer irq
778 * This interval determines how frequent an interrupt is generated.
779 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
780 * Min = 0, and Max = 65535
782 static int poll_interval = -1;
791 static int msi = NV_MSI_INT_ENABLED;
797 NV_MSIX_INT_DISABLED,
800 static int msix = NV_MSIX_INT_ENABLED;
806 NV_DMA_64BIT_DISABLED,
809 static int dma_64bit = NV_DMA_64BIT_ENABLED;
811 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
813 return netdev_priv(dev);
816 static inline u8 __iomem *get_hwbase(struct net_device *dev)
818 return ((struct fe_priv *)netdev_priv(dev))->base;
821 static inline void pci_push(u8 __iomem *base)
823 /* force out pending posted writes */
827 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
829 return le32_to_cpu(prd->FlagLen)
830 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
833 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
835 return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
838 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
839 int delay, int delaymax, const char *msg)
841 u8 __iomem *base = get_hwbase(dev);
852 } while ((readl(base + offset) & mask) != target);
856 #define NV_SETUP_RX_RING 0x01
857 #define NV_SETUP_TX_RING 0x02
859 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
861 struct fe_priv *np = get_nvpriv(dev);
862 u8 __iomem *base = get_hwbase(dev);
864 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
865 if (rxtx_flags & NV_SETUP_RX_RING) {
866 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
868 if (rxtx_flags & NV_SETUP_TX_RING) {
869 writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
872 if (rxtx_flags & NV_SETUP_RX_RING) {
873 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
874 writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
876 if (rxtx_flags & NV_SETUP_TX_RING) {
877 writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
878 writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
883 static void free_rings(struct net_device *dev)
885 struct fe_priv *np = get_nvpriv(dev);
887 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
889 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
890 np->rx_ring.orig, np->ring_addr);
893 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
894 np->rx_ring.ex, np->ring_addr);
897 kfree(np->rx_skbuff);
901 kfree(np->tx_skbuff);
905 kfree(np->tx_dma_len);
908 static int using_multi_irqs(struct net_device *dev)
910 struct fe_priv *np = get_nvpriv(dev);
912 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
913 ((np->msi_flags & NV_MSI_X_ENABLED) &&
914 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
920 static void nv_enable_irq(struct net_device *dev)
922 struct fe_priv *np = get_nvpriv(dev);
924 if (!using_multi_irqs(dev)) {
925 if (np->msi_flags & NV_MSI_X_ENABLED)
926 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
928 enable_irq(dev->irq);
930 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
931 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
932 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
936 static void nv_disable_irq(struct net_device *dev)
938 struct fe_priv *np = get_nvpriv(dev);
940 if (!using_multi_irqs(dev)) {
941 if (np->msi_flags & NV_MSI_X_ENABLED)
942 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
944 disable_irq(dev->irq);
946 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
947 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
948 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
952 /* In MSIX mode, a write to irqmask behaves as XOR */
953 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
955 u8 __iomem *base = get_hwbase(dev);
957 writel(mask, base + NvRegIrqMask);
960 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
962 struct fe_priv *np = get_nvpriv(dev);
963 u8 __iomem *base = get_hwbase(dev);
965 if (np->msi_flags & NV_MSI_X_ENABLED) {
966 writel(mask, base + NvRegIrqMask);
968 if (np->msi_flags & NV_MSI_ENABLED)
969 writel(0, base + NvRegMSIIrqMask);
970 writel(0, base + NvRegIrqMask);
974 #define MII_READ (-1)
975 /* mii_rw: read/write a register on the PHY.
977 * Caller must guarantee serialization
979 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
981 u8 __iomem *base = get_hwbase(dev);
985 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
987 reg = readl(base + NvRegMIIControl);
988 if (reg & NVREG_MIICTL_INUSE) {
989 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
990 udelay(NV_MIIBUSY_DELAY);
993 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
994 if (value != MII_READ) {
995 writel(value, base + NvRegMIIData);
996 reg |= NVREG_MIICTL_WRITE;
998 writel(reg, base + NvRegMIIControl);
1000 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1001 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1002 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1003 dev->name, miireg, addr);
1005 } else if (value != MII_READ) {
1006 /* it was a write operation - fewer failures are detectable */
1007 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1008 dev->name, value, miireg, addr);
1010 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1011 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1012 dev->name, miireg, addr);
1015 retval = readl(base + NvRegMIIData);
1016 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1017 dev->name, miireg, addr, retval);
1023 static int phy_reset(struct net_device *dev)
1025 struct fe_priv *np = netdev_priv(dev);
1027 unsigned int tries = 0;
1029 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1030 miicontrol |= BMCR_RESET;
1031 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1035 /* wait for 500ms */
1038 /* must wait till reset is deasserted */
1039 while (miicontrol & BMCR_RESET) {
1041 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1042 /* FIXME: 100 tries seem excessive */
1049 static int phy_init(struct net_device *dev)
1051 struct fe_priv *np = get_nvpriv(dev);
1052 u8 __iomem *base = get_hwbase(dev);
1053 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1055 /* set advertise register */
1056 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1057 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1058 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1059 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1063 /* get phy interface type */
1064 phyinterface = readl(base + NvRegPhyInterface);
1066 /* see if gigabit phy */
1067 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1068 if (mii_status & PHY_GIGABIT) {
1069 np->gigabit = PHY_GIGABIT;
1070 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1071 mii_control_1000 &= ~ADVERTISE_1000HALF;
1072 if (phyinterface & PHY_RGMII)
1073 mii_control_1000 |= ADVERTISE_1000FULL;
1075 mii_control_1000 &= ~ADVERTISE_1000FULL;
1077 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1078 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1086 if (phy_reset(dev)) {
1087 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1091 /* phy vendor specific configuration */
1092 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1093 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1094 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1095 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1096 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1097 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1100 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1101 phy_reserved |= PHY_INIT5;
1102 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1103 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1107 if (np->phy_oui == PHY_OUI_CICADA) {
1108 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1109 phy_reserved |= PHY_INIT6;
1110 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1111 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1115 /* some phys clear out pause advertisment on reset, set it back */
1116 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1118 /* restart auto negotiation */
1119 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1120 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1121 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1128 static void nv_start_rx(struct net_device *dev)
1130 struct fe_priv *np = netdev_priv(dev);
1131 u8 __iomem *base = get_hwbase(dev);
1133 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1134 /* Already running? Stop it. */
1135 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
1136 writel(0, base + NvRegReceiverControl);
1139 writel(np->linkspeed, base + NvRegLinkSpeed);
1141 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
1142 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1143 dev->name, np->duplex, np->linkspeed);
1147 static void nv_stop_rx(struct net_device *dev)
1149 u8 __iomem *base = get_hwbase(dev);
1151 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1152 writel(0, base + NvRegReceiverControl);
1153 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1154 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1155 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1157 udelay(NV_RXSTOP_DELAY2);
1158 writel(0, base + NvRegLinkSpeed);
1161 static void nv_start_tx(struct net_device *dev)
1163 u8 __iomem *base = get_hwbase(dev);
1165 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1166 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
1170 static void nv_stop_tx(struct net_device *dev)
1172 u8 __iomem *base = get_hwbase(dev);
1174 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1175 writel(0, base + NvRegTransmitterControl);
1176 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1177 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1178 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1180 udelay(NV_TXSTOP_DELAY2);
1181 writel(0, base + NvRegUnknownTransmitterReg);
1184 static void nv_txrx_reset(struct net_device *dev)
1186 struct fe_priv *np = netdev_priv(dev);
1187 u8 __iomem *base = get_hwbase(dev);
1189 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1190 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1192 udelay(NV_TXRX_RESET_DELAY);
1193 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1197 static void nv_mac_reset(struct net_device *dev)
1199 struct fe_priv *np = netdev_priv(dev);
1200 u8 __iomem *base = get_hwbase(dev);
1202 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1203 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1205 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1207 udelay(NV_MAC_RESET_DELAY);
1208 writel(0, base + NvRegMacReset);
1210 udelay(NV_MAC_RESET_DELAY);
1211 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1216 * nv_get_stats: dev->get_stats function
1217 * Get latest stats value from the nic.
1218 * Called with read_lock(&dev_base_lock) held for read -
1219 * only synchronized against unregister_netdevice.
1221 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1223 struct fe_priv *np = netdev_priv(dev);
1225 /* It seems that the nic always generates interrupts and doesn't
1226 * accumulate errors internally. Thus the current values in np->stats
1227 * are already up to date.
1233 * nv_alloc_rx: fill rx ring entries.
1234 * Return 1 if the allocations for the skbs failed and the
1235 * rx engine is without Available descriptors
1237 static int nv_alloc_rx(struct net_device *dev)
1239 struct fe_priv *np = netdev_priv(dev);
1240 unsigned int refill_rx = np->refill_rx;
1243 while (np->cur_rx != refill_rx) {
1244 struct sk_buff *skb;
1246 nr = refill_rx % np->rx_ring_size;
1247 if (np->rx_skbuff[nr] == NULL) {
1249 skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1254 np->rx_skbuff[nr] = skb;
1256 skb = np->rx_skbuff[nr];
1258 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
1259 skb->end-skb->data, PCI_DMA_FROMDEVICE);
1260 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1261 np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
1263 np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1265 np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
1266 np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
1268 np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1270 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
1271 dev->name, refill_rx);
1274 np->refill_rx = refill_rx;
1275 if (np->cur_rx - refill_rx == np->rx_ring_size)
1280 static void nv_do_rx_refill(unsigned long data)
1282 struct net_device *dev = (struct net_device *) data;
1283 struct fe_priv *np = netdev_priv(dev);
1285 if (!using_multi_irqs(dev)) {
1286 if (np->msi_flags & NV_MSI_X_ENABLED)
1287 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1289 disable_irq(dev->irq);
1291 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1293 if (nv_alloc_rx(dev)) {
1294 spin_lock_irq(&np->lock);
1295 if (!np->in_shutdown)
1296 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1297 spin_unlock_irq(&np->lock);
1299 if (!using_multi_irqs(dev)) {
1300 if (np->msi_flags & NV_MSI_X_ENABLED)
1301 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1303 enable_irq(dev->irq);
1305 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1309 static void nv_init_rx(struct net_device *dev)
1311 struct fe_priv *np = netdev_priv(dev);
1314 np->cur_rx = np->rx_ring_size;
1316 for (i = 0; i < np->rx_ring_size; i++)
1317 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1318 np->rx_ring.orig[i].FlagLen = 0;
1320 np->rx_ring.ex[i].FlagLen = 0;
1323 static void nv_init_tx(struct net_device *dev)
1325 struct fe_priv *np = netdev_priv(dev);
1328 np->next_tx = np->nic_tx = 0;
1329 for (i = 0; i < np->tx_ring_size; i++) {
1330 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1331 np->tx_ring.orig[i].FlagLen = 0;
1333 np->tx_ring.ex[i].FlagLen = 0;
1334 np->tx_skbuff[i] = NULL;
1339 static int nv_init_ring(struct net_device *dev)
1343 return nv_alloc_rx(dev);
1346 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
1348 struct fe_priv *np = netdev_priv(dev);
1350 dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
1353 if (np->tx_dma[skbnr]) {
1354 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
1355 np->tx_dma_len[skbnr],
1357 np->tx_dma[skbnr] = 0;
1360 if (np->tx_skbuff[skbnr]) {
1361 dev_kfree_skb_any(np->tx_skbuff[skbnr]);
1362 np->tx_skbuff[skbnr] = NULL;
1369 static void nv_drain_tx(struct net_device *dev)
1371 struct fe_priv *np = netdev_priv(dev);
1374 for (i = 0; i < np->tx_ring_size; i++) {
1375 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1376 np->tx_ring.orig[i].FlagLen = 0;
1378 np->tx_ring.ex[i].FlagLen = 0;
1379 if (nv_release_txskb(dev, i))
1380 np->stats.tx_dropped++;
1384 static void nv_drain_rx(struct net_device *dev)
1386 struct fe_priv *np = netdev_priv(dev);
1388 for (i = 0; i < np->rx_ring_size; i++) {
1389 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1390 np->rx_ring.orig[i].FlagLen = 0;
1392 np->rx_ring.ex[i].FlagLen = 0;
1394 if (np->rx_skbuff[i]) {
1395 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1396 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1397 PCI_DMA_FROMDEVICE);
1398 dev_kfree_skb(np->rx_skbuff[i]);
1399 np->rx_skbuff[i] = NULL;
1404 static void drain_ring(struct net_device *dev)
1411 * nv_start_xmit: dev->hard_start_xmit function
1412 * Called with netif_tx_lock held.
1414 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1416 struct fe_priv *np = netdev_priv(dev);
1418 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1419 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1420 unsigned int nr = (np->next_tx - 1) % np->tx_ring_size;
1421 unsigned int start_nr = np->next_tx % np->tx_ring_size;
1425 u32 size = skb->len-skb->data_len;
1426 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1427 u32 tx_flags_vlan = 0;
1429 /* add fragments to entries count */
1430 for (i = 0; i < fragments; i++) {
1431 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1432 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1435 spin_lock_irq(&np->lock);
1437 if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) {
1438 spin_unlock_irq(&np->lock);
1439 netif_stop_queue(dev);
1440 return NETDEV_TX_BUSY;
1443 /* setup the header buffer */
1445 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1446 nr = (nr + 1) % np->tx_ring_size;
1448 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1450 np->tx_dma_len[nr] = bcnt;
1452 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1453 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1454 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1456 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1457 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1458 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1460 tx_flags = np->tx_flags;
1465 /* setup the fragments */
1466 for (i = 0; i < fragments; i++) {
1467 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1468 u32 size = frag->size;
1472 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1473 nr = (nr + 1) % np->tx_ring_size;
1475 np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1477 np->tx_dma_len[nr] = bcnt;
1479 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1480 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1481 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1483 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1484 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1485 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1492 /* set last fragment flag */
1493 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1494 np->tx_ring.orig[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1496 np->tx_ring.ex[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1499 np->tx_skbuff[nr] = skb;
1502 if (skb_is_gso(skb))
1503 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1506 tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
1509 if (np->vlangrp && vlan_tx_tag_present(skb)) {
1510 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1514 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1515 np->tx_ring.orig[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1517 np->tx_ring.ex[start_nr].TxVlan = cpu_to_le32(tx_flags_vlan);
1518 np->tx_ring.ex[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1521 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1522 dev->name, np->next_tx, entries, tx_flags_extra);
1525 for (j=0; j<64; j++) {
1527 dprintk("\n%03x:", j);
1528 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1533 np->next_tx += entries;
1535 dev->trans_start = jiffies;
1536 spin_unlock_irq(&np->lock);
1537 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1538 pci_push(get_hwbase(dev));
1539 return NETDEV_TX_OK;
1543 * nv_tx_done: check for completed packets, release the skbs.
1545 * Caller must own np->lock.
1547 static void nv_tx_done(struct net_device *dev)
1549 struct fe_priv *np = netdev_priv(dev);
1552 struct sk_buff *skb;
1554 while (np->nic_tx != np->next_tx) {
1555 i = np->nic_tx % np->tx_ring_size;
1557 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1558 Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1560 Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
1562 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1563 dev->name, np->nic_tx, Flags);
1564 if (Flags & NV_TX_VALID)
1566 if (np->desc_ver == DESC_VER_1) {
1567 if (Flags & NV_TX_LASTPACKET) {
1568 skb = np->tx_skbuff[i];
1569 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1570 NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1571 if (Flags & NV_TX_UNDERFLOW)
1572 np->stats.tx_fifo_errors++;
1573 if (Flags & NV_TX_CARRIERLOST)
1574 np->stats.tx_carrier_errors++;
1575 np->stats.tx_errors++;
1577 np->stats.tx_packets++;
1578 np->stats.tx_bytes += skb->len;
1582 if (Flags & NV_TX2_LASTPACKET) {
1583 skb = np->tx_skbuff[i];
1584 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1585 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1586 if (Flags & NV_TX2_UNDERFLOW)
1587 np->stats.tx_fifo_errors++;
1588 if (Flags & NV_TX2_CARRIERLOST)
1589 np->stats.tx_carrier_errors++;
1590 np->stats.tx_errors++;
1592 np->stats.tx_packets++;
1593 np->stats.tx_bytes += skb->len;
1597 nv_release_txskb(dev, i);
1600 if (np->next_tx - np->nic_tx < np->tx_limit_start)
1601 netif_wake_queue(dev);
1605 * nv_tx_timeout: dev->tx_timeout function
1606 * Called with netif_tx_lock held.
1608 static void nv_tx_timeout(struct net_device *dev)
1610 struct fe_priv *np = netdev_priv(dev);
1611 u8 __iomem *base = get_hwbase(dev);
1614 if (np->msi_flags & NV_MSI_X_ENABLED)
1615 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1617 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1619 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1624 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1625 dev->name, (unsigned long)np->ring_addr,
1626 np->next_tx, np->nic_tx);
1627 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1628 for (i=0;i<=np->register_size;i+= 32) {
1629 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1631 readl(base + i + 0), readl(base + i + 4),
1632 readl(base + i + 8), readl(base + i + 12),
1633 readl(base + i + 16), readl(base + i + 20),
1634 readl(base + i + 24), readl(base + i + 28));
1636 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1637 for (i=0;i<np->tx_ring_size;i+= 4) {
1638 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1639 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1641 le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1642 le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1643 le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1644 le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1645 le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1646 le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1647 le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1648 le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1650 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1652 le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1653 le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1654 le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1655 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1656 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1657 le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1658 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1659 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1660 le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1661 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1662 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1663 le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1668 spin_lock_irq(&np->lock);
1670 /* 1) stop tx engine */
1673 /* 2) check that the packets were not sent already: */
1676 /* 3) if there are dead entries: clear everything */
1677 if (np->next_tx != np->nic_tx) {
1678 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1680 np->next_tx = np->nic_tx = 0;
1681 setup_hw_rings(dev, NV_SETUP_TX_RING);
1682 netif_wake_queue(dev);
1685 /* 4) restart tx engine */
1687 spin_unlock_irq(&np->lock);
1691 * Called when the nic notices a mismatch between the actual data len on the
1692 * wire and the len indicated in the 802 header
1694 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1696 int hdrlen; /* length of the 802 header */
1697 int protolen; /* length as stored in the proto field */
1699 /* 1) calculate len according to header */
1700 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1701 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1704 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1707 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1708 dev->name, datalen, protolen, hdrlen);
1709 if (protolen > ETH_DATA_LEN)
1710 return datalen; /* Value in proto field not a len, no checks possible */
1713 /* consistency checks: */
1714 if (datalen > ETH_ZLEN) {
1715 if (datalen >= protolen) {
1716 /* more data on wire than in 802 header, trim of
1719 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1720 dev->name, protolen);
1723 /* less data on wire than mentioned in header.
1724 * Discard the packet.
1726 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1731 /* short packet. Accept only if 802 values are also short */
1732 if (protolen > ETH_ZLEN) {
1733 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1737 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1738 dev->name, datalen);
1743 static void nv_rx_process(struct net_device *dev)
1745 struct fe_priv *np = netdev_priv(dev);
1750 struct sk_buff *skb;
1753 if (np->cur_rx - np->refill_rx >= np->rx_ring_size)
1754 break; /* we scanned the whole ring - do not continue */
1756 i = np->cur_rx % np->rx_ring_size;
1757 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1758 Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1759 len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1761 Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1762 len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1763 vlanflags = le32_to_cpu(np->rx_ring.ex[i].PacketBufferLow);
1766 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1767 dev->name, np->cur_rx, Flags);
1769 if (Flags & NV_RX_AVAIL)
1770 break; /* still owned by hardware, */
1773 * the packet is for us - immediately tear down the pci mapping.
1774 * TODO: check if a prefetch of the first cacheline improves
1777 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1778 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1779 PCI_DMA_FROMDEVICE);
1783 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1784 for (j=0; j<64; j++) {
1786 dprintk("\n%03x:", j);
1787 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1791 /* look at what we actually got: */
1792 if (np->desc_ver == DESC_VER_1) {
1793 if (!(Flags & NV_RX_DESCRIPTORVALID))
1796 if (Flags & NV_RX_ERROR) {
1797 if (Flags & NV_RX_MISSEDFRAME) {
1798 np->stats.rx_missed_errors++;
1799 np->stats.rx_errors++;
1802 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1803 np->stats.rx_errors++;
1806 if (Flags & NV_RX_CRCERR) {
1807 np->stats.rx_crc_errors++;
1808 np->stats.rx_errors++;
1811 if (Flags & NV_RX_OVERFLOW) {
1812 np->stats.rx_over_errors++;
1813 np->stats.rx_errors++;
1816 if (Flags & NV_RX_ERROR4) {
1817 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1819 np->stats.rx_errors++;
1823 /* framing errors are soft errors. */
1824 if (Flags & NV_RX_FRAMINGERR) {
1825 if (Flags & NV_RX_SUBSTRACT1) {
1831 if (!(Flags & NV_RX2_DESCRIPTORVALID))
1834 if (Flags & NV_RX2_ERROR) {
1835 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1836 np->stats.rx_errors++;
1839 if (Flags & NV_RX2_CRCERR) {
1840 np->stats.rx_crc_errors++;
1841 np->stats.rx_errors++;
1844 if (Flags & NV_RX2_OVERFLOW) {
1845 np->stats.rx_over_errors++;
1846 np->stats.rx_errors++;
1849 if (Flags & NV_RX2_ERROR4) {
1850 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1852 np->stats.rx_errors++;
1856 /* framing errors are soft errors */
1857 if (Flags & NV_RX2_FRAMINGERR) {
1858 if (Flags & NV_RX2_SUBSTRACT1) {
1863 if (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) {
1864 Flags &= NV_RX2_CHECKSUMMASK;
1865 if (Flags == NV_RX2_CHECKSUMOK1 ||
1866 Flags == NV_RX2_CHECKSUMOK2 ||
1867 Flags == NV_RX2_CHECKSUMOK3) {
1868 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1869 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1871 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1875 /* got a valid packet - forward it to the network core */
1876 skb = np->rx_skbuff[i];
1877 np->rx_skbuff[i] = NULL;
1880 skb->protocol = eth_type_trans(skb, dev);
1881 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1882 dev->name, np->cur_rx, len, skb->protocol);
1883 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT)) {
1884 vlan_hwaccel_rx(skb, np->vlangrp, vlanflags & NV_RX3_VLAN_TAG_MASK);
1888 dev->last_rx = jiffies;
1889 np->stats.rx_packets++;
1890 np->stats.rx_bytes += len;
1896 static void set_bufsize(struct net_device *dev)
1898 struct fe_priv *np = netdev_priv(dev);
1900 if (dev->mtu <= ETH_DATA_LEN)
1901 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1903 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1907 * nv_change_mtu: dev->change_mtu function
1908 * Called with dev_base_lock held for read.
1910 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1912 struct fe_priv *np = netdev_priv(dev);
1915 if (new_mtu < 64 || new_mtu > np->pkt_limit)
1921 /* return early if the buffer sizes will not change */
1922 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1924 if (old_mtu == new_mtu)
1927 /* synchronized against open : rtnl_lock() held by caller */
1928 if (netif_running(dev)) {
1929 u8 __iomem *base = get_hwbase(dev);
1931 * It seems that the nic preloads valid ring entries into an
1932 * internal buffer. The procedure for flushing everything is
1933 * guessed, there is probably a simpler approach.
1934 * Changing the MTU is a rare event, it shouldn't matter.
1936 nv_disable_irq(dev);
1937 netif_tx_lock_bh(dev);
1938 spin_lock(&np->lock);
1943 /* drain rx queue */
1946 /* reinit driver view of the rx queue */
1948 if (nv_init_ring(dev)) {
1949 if (!np->in_shutdown)
1950 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1952 /* reinit nic view of the rx queue */
1953 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1954 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
1955 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
1956 base + NvRegRingSizes);
1958 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1961 /* restart rx engine */
1964 spin_unlock(&np->lock);
1965 netif_tx_unlock_bh(dev);
1971 static void nv_copy_mac_to_hw(struct net_device *dev)
1973 u8 __iomem *base = get_hwbase(dev);
1976 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1977 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1978 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1980 writel(mac[0], base + NvRegMacAddrA);
1981 writel(mac[1], base + NvRegMacAddrB);
1985 * nv_set_mac_address: dev->set_mac_address function
1986 * Called with rtnl_lock() held.
1988 static int nv_set_mac_address(struct net_device *dev, void *addr)
1990 struct fe_priv *np = netdev_priv(dev);
1991 struct sockaddr *macaddr = (struct sockaddr*)addr;
1993 if(!is_valid_ether_addr(macaddr->sa_data))
1994 return -EADDRNOTAVAIL;
1996 /* synchronized against open : rtnl_lock() held by caller */
1997 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1999 if (netif_running(dev)) {
2000 netif_tx_lock_bh(dev);
2001 spin_lock_irq(&np->lock);
2003 /* stop rx engine */
2006 /* set mac address */
2007 nv_copy_mac_to_hw(dev);
2009 /* restart rx engine */
2011 spin_unlock_irq(&np->lock);
2012 netif_tx_unlock_bh(dev);
2014 nv_copy_mac_to_hw(dev);
2020 * nv_set_multicast: dev->set_multicast function
2021 * Called with netif_tx_lock held.
2023 static void nv_set_multicast(struct net_device *dev)
2025 struct fe_priv *np = netdev_priv(dev);
2026 u8 __iomem *base = get_hwbase(dev);
2029 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2031 memset(addr, 0, sizeof(addr));
2032 memset(mask, 0, sizeof(mask));
2034 if (dev->flags & IFF_PROMISC) {
2035 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
2036 pff |= NVREG_PFF_PROMISC;
2038 pff |= NVREG_PFF_MYADDR;
2040 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2044 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2045 if (dev->flags & IFF_ALLMULTI) {
2046 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2048 struct dev_mc_list *walk;
2050 walk = dev->mc_list;
2051 while (walk != NULL) {
2053 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2054 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2062 addr[0] = alwaysOn[0];
2063 addr[1] = alwaysOn[1];
2064 mask[0] = alwaysOn[0] | alwaysOff[0];
2065 mask[1] = alwaysOn[1] | alwaysOff[1];
2068 addr[0] |= NVREG_MCASTADDRA_FORCE;
2069 pff |= NVREG_PFF_ALWAYS;
2070 spin_lock_irq(&np->lock);
2072 writel(addr[0], base + NvRegMulticastAddrA);
2073 writel(addr[1], base + NvRegMulticastAddrB);
2074 writel(mask[0], base + NvRegMulticastMaskA);
2075 writel(mask[1], base + NvRegMulticastMaskB);
2076 writel(pff, base + NvRegPacketFilterFlags);
2077 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2080 spin_unlock_irq(&np->lock);
2083 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2085 struct fe_priv *np = netdev_priv(dev);
2086 u8 __iomem *base = get_hwbase(dev);
2088 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2090 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2091 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2092 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2093 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2094 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2096 writel(pff, base + NvRegPacketFilterFlags);
2099 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2100 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2101 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2102 writel(NVREG_TX_PAUSEFRAME_ENABLE, base + NvRegTxPauseFrame);
2103 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2104 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2106 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
2107 writel(regmisc, base + NvRegMisc1);
2113 * nv_update_linkspeed: Setup the MAC according to the link partner
2114 * @dev: Network device to be configured
2116 * The function queries the PHY and checks if there is a link partner.
2117 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2118 * set to 10 MBit HD.
2120 * The function returns 0 if there is no link partner and 1 if there is
2121 * a good link partner.
2123 static int nv_update_linkspeed(struct net_device *dev)
2125 struct fe_priv *np = netdev_priv(dev);
2126 u8 __iomem *base = get_hwbase(dev);
2129 int adv_lpa, adv_pause, lpa_pause;
2130 int newls = np->linkspeed;
2131 int newdup = np->duplex;
2134 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2136 /* BMSR_LSTATUS is latched, read it twice:
2137 * we want the current value.
2139 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2140 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2142 if (!(mii_status & BMSR_LSTATUS)) {
2143 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2145 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2151 if (np->autoneg == 0) {
2152 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2153 dev->name, np->fixed_mode);
2154 if (np->fixed_mode & LPA_100FULL) {
2155 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2157 } else if (np->fixed_mode & LPA_100HALF) {
2158 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2160 } else if (np->fixed_mode & LPA_10FULL) {
2161 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2164 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2170 /* check auto negotiation is complete */
2171 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2172 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2173 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2176 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2180 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2181 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2182 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2183 dev->name, adv, lpa);
2186 if (np->gigabit == PHY_GIGABIT) {
2187 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2188 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2190 if ((control_1000 & ADVERTISE_1000FULL) &&
2191 (status_1000 & LPA_1000FULL)) {
2192 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2194 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2200 /* FIXME: handle parallel detection properly */
2201 adv_lpa = lpa & adv;
2202 if (adv_lpa & LPA_100FULL) {
2203 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2205 } else if (adv_lpa & LPA_100HALF) {
2206 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2208 } else if (adv_lpa & LPA_10FULL) {
2209 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2211 } else if (adv_lpa & LPA_10HALF) {
2212 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2215 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2216 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2221 if (np->duplex == newdup && np->linkspeed == newls)
2224 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2225 dev->name, np->linkspeed, np->duplex, newls, newdup);
2227 np->duplex = newdup;
2228 np->linkspeed = newls;
2230 if (np->gigabit == PHY_GIGABIT) {
2231 phyreg = readl(base + NvRegRandomSeed);
2232 phyreg &= ~(0x3FF00);
2233 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2234 phyreg |= NVREG_RNDSEED_FORCE3;
2235 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2236 phyreg |= NVREG_RNDSEED_FORCE2;
2237 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2238 phyreg |= NVREG_RNDSEED_FORCE;
2239 writel(phyreg, base + NvRegRandomSeed);
2242 phyreg = readl(base + NvRegPhyInterface);
2243 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2244 if (np->duplex == 0)
2246 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2248 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2250 writel(phyreg, base + NvRegPhyInterface);
2252 if (phyreg & PHY_RGMII) {
2253 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2254 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2256 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2258 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2260 writel(txreg, base + NvRegTxDeferral);
2262 if (np->desc_ver == DESC_VER_1) {
2263 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2265 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2266 txreg = NVREG_TX_WM_DESC2_3_1000;
2268 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2270 writel(txreg, base + NvRegTxWatermark);
2272 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2275 writel(np->linkspeed, base + NvRegLinkSpeed);
2279 /* setup pause frame */
2280 if (np->duplex != 0) {
2281 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2282 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2283 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2285 switch (adv_pause) {
2286 case (ADVERTISE_PAUSE_CAP):
2287 if (lpa_pause & LPA_PAUSE_CAP) {
2288 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2289 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2290 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2293 case (ADVERTISE_PAUSE_ASYM):
2294 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2296 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2299 case (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM):
2300 if (lpa_pause & LPA_PAUSE_CAP)
2302 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2303 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2304 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2306 if (lpa_pause == LPA_PAUSE_ASYM)
2308 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2313 pause_flags = np->pause_flags;
2316 nv_update_pause(dev, pause_flags);
2321 static void nv_linkchange(struct net_device *dev)
2323 if (nv_update_linkspeed(dev)) {
2324 if (!netif_carrier_ok(dev)) {
2325 netif_carrier_on(dev);
2326 printk(KERN_INFO "%s: link up.\n", dev->name);
2330 if (netif_carrier_ok(dev)) {
2331 netif_carrier_off(dev);
2332 printk(KERN_INFO "%s: link down.\n", dev->name);
2338 static void nv_link_irq(struct net_device *dev)
2340 u8 __iomem *base = get_hwbase(dev);
2343 miistat = readl(base + NvRegMIIStatus);
2344 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2345 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2347 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2349 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2352 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
2354 struct net_device *dev = (struct net_device *) data;
2355 struct fe_priv *np = netdev_priv(dev);
2356 u8 __iomem *base = get_hwbase(dev);
2360 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2363 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2364 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2365 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2367 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2368 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2371 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2372 if (!(events & np->irqmask))
2375 spin_lock(&np->lock);
2377 spin_unlock(&np->lock);
2380 if (nv_alloc_rx(dev)) {
2381 spin_lock(&np->lock);
2382 if (!np->in_shutdown)
2383 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2384 spin_unlock(&np->lock);
2387 if (events & NVREG_IRQ_LINK) {
2388 spin_lock(&np->lock);
2390 spin_unlock(&np->lock);
2392 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2393 spin_lock(&np->lock);
2395 spin_unlock(&np->lock);
2396 np->link_timeout = jiffies + LINK_TIMEOUT;
2398 if (events & (NVREG_IRQ_TX_ERR)) {
2399 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2402 if (events & (NVREG_IRQ_UNKNOWN)) {
2403 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2406 if (i > max_interrupt_work) {
2407 spin_lock(&np->lock);
2408 /* disable interrupts on the nic */
2409 if (!(np->msi_flags & NV_MSI_X_ENABLED))
2410 writel(0, base + NvRegIrqMask);
2412 writel(np->irqmask, base + NvRegIrqMask);
2415 if (!np->in_shutdown) {
2416 np->nic_poll_irq = np->irqmask;
2417 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2419 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2420 spin_unlock(&np->lock);
2425 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2427 return IRQ_RETVAL(i);
2430 static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs)
2432 struct net_device *dev = (struct net_device *) data;
2433 struct fe_priv *np = netdev_priv(dev);
2434 u8 __iomem *base = get_hwbase(dev);
2437 unsigned long flags;
2439 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
2442 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2443 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2445 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2446 if (!(events & np->irqmask))
2449 spin_lock_irqsave(&np->lock, flags);
2451 spin_unlock_irqrestore(&np->lock, flags);
2453 if (events & (NVREG_IRQ_TX_ERR)) {
2454 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2457 if (i > max_interrupt_work) {
2458 spin_lock_irqsave(&np->lock, flags);
2459 /* disable interrupts on the nic */
2460 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
2463 if (!np->in_shutdown) {
2464 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
2465 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2467 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
2468 spin_unlock_irqrestore(&np->lock, flags);
2473 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
2475 return IRQ_RETVAL(i);
2478 static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
2480 struct net_device *dev = (struct net_device *) data;
2481 struct fe_priv *np = netdev_priv(dev);
2482 u8 __iomem *base = get_hwbase(dev);
2485 unsigned long flags;
2487 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
2490 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2491 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2493 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
2494 if (!(events & np->irqmask))
2498 if (nv_alloc_rx(dev)) {
2499 spin_lock_irqsave(&np->lock, flags);
2500 if (!np->in_shutdown)
2501 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2502 spin_unlock_irqrestore(&np->lock, flags);
2505 if (i > max_interrupt_work) {
2506 spin_lock_irqsave(&np->lock, flags);
2507 /* disable interrupts on the nic */
2508 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2511 if (!np->in_shutdown) {
2512 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
2513 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2515 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
2516 spin_unlock_irqrestore(&np->lock, flags);
2521 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
2523 return IRQ_RETVAL(i);
2526 static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs)
2528 struct net_device *dev = (struct net_device *) data;
2529 struct fe_priv *np = netdev_priv(dev);
2530 u8 __iomem *base = get_hwbase(dev);
2533 unsigned long flags;
2535 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
2538 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
2539 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
2541 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2542 if (!(events & np->irqmask))
2545 if (events & NVREG_IRQ_LINK) {
2546 spin_lock_irqsave(&np->lock, flags);
2548 spin_unlock_irqrestore(&np->lock, flags);
2550 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2551 spin_lock_irqsave(&np->lock, flags);
2553 spin_unlock_irqrestore(&np->lock, flags);
2554 np->link_timeout = jiffies + LINK_TIMEOUT;
2556 if (events & (NVREG_IRQ_UNKNOWN)) {
2557 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2560 if (i > max_interrupt_work) {
2561 spin_lock_irqsave(&np->lock, flags);
2562 /* disable interrupts on the nic */
2563 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2566 if (!np->in_shutdown) {
2567 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2568 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2570 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
2571 spin_unlock_irqrestore(&np->lock, flags);
2576 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
2578 return IRQ_RETVAL(i);
2581 static irqreturn_t nv_nic_irq_test(int foo, void *data, struct pt_regs *regs)
2583 struct net_device *dev = (struct net_device *) data;
2584 struct fe_priv *np = netdev_priv(dev);
2585 u8 __iomem *base = get_hwbase(dev);
2588 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
2590 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2591 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2592 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
2594 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2595 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
2598 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2599 if (!(events & NVREG_IRQ_TIMER))
2600 return IRQ_RETVAL(0);
2602 spin_lock(&np->lock);
2604 spin_unlock(&np->lock);
2606 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
2608 return IRQ_RETVAL(1);
2611 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
2613 u8 __iomem *base = get_hwbase(dev);
2617 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2618 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2619 * the remaining 8 interrupts.
2621 for (i = 0; i < 8; i++) {
2622 if ((irqmask >> i) & 0x1) {
2623 msixmap |= vector << (i << 2);
2626 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
2629 for (i = 0; i < 8; i++) {
2630 if ((irqmask >> (i + 8)) & 0x1) {
2631 msixmap |= vector << (i << 2);
2634 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
2637 static int nv_request_irq(struct net_device *dev, int intr_test)
2639 struct fe_priv *np = get_nvpriv(dev);
2640 u8 __iomem *base = get_hwbase(dev);
2644 if (np->msi_flags & NV_MSI_X_CAPABLE) {
2645 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2646 np->msi_x_entry[i].entry = i;
2648 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
2649 np->msi_flags |= NV_MSI_X_ENABLED;
2650 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
2651 /* Request irq for rx handling */
2652 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
2653 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
2654 pci_disable_msix(np->pci_dev);
2655 np->msi_flags &= ~NV_MSI_X_ENABLED;
2658 /* Request irq for tx handling */
2659 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
2660 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
2661 pci_disable_msix(np->pci_dev);
2662 np->msi_flags &= ~NV_MSI_X_ENABLED;
2665 /* Request irq for link and timer handling */
2666 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
2667 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
2668 pci_disable_msix(np->pci_dev);
2669 np->msi_flags &= ~NV_MSI_X_ENABLED;
2672 /* map interrupts to their respective vector */
2673 writel(0, base + NvRegMSIXMap0);
2674 writel(0, base + NvRegMSIXMap1);
2675 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
2676 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
2677 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
2679 /* Request irq for all interrupts */
2681 request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2683 request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2684 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2685 pci_disable_msix(np->pci_dev);
2686 np->msi_flags &= ~NV_MSI_X_ENABLED;
2690 /* map interrupts to vector 0 */
2691 writel(0, base + NvRegMSIXMap0);
2692 writel(0, base + NvRegMSIXMap1);
2696 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
2697 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
2698 pci_intx(np->pci_dev, 0);
2699 np->msi_flags |= NV_MSI_ENABLED;
2700 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2701 (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2702 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2703 pci_disable_msi(np->pci_dev);
2704 pci_intx(np->pci_dev, 1);
2705 np->msi_flags &= ~NV_MSI_ENABLED;
2709 /* map interrupts to vector 0 */
2710 writel(0, base + NvRegMSIMap0);
2711 writel(0, base + NvRegMSIMap1);
2712 /* enable msi vector 0 */
2713 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
2717 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2718 (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0))
2725 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
2727 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
2732 static void nv_free_irq(struct net_device *dev)
2734 struct fe_priv *np = get_nvpriv(dev);
2737 if (np->msi_flags & NV_MSI_X_ENABLED) {
2738 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2739 free_irq(np->msi_x_entry[i].vector, dev);
2741 pci_disable_msix(np->pci_dev);
2742 np->msi_flags &= ~NV_MSI_X_ENABLED;
2744 free_irq(np->pci_dev->irq, dev);
2745 if (np->msi_flags & NV_MSI_ENABLED) {
2746 pci_disable_msi(np->pci_dev);
2747 pci_intx(np->pci_dev, 1);
2748 np->msi_flags &= ~NV_MSI_ENABLED;
2753 static void nv_do_nic_poll(unsigned long data)
2755 struct net_device *dev = (struct net_device *) data;
2756 struct fe_priv *np = netdev_priv(dev);
2757 u8 __iomem *base = get_hwbase(dev);
2761 * First disable irq(s) and then
2762 * reenable interrupts on the nic, we have to do this before calling
2763 * nv_nic_irq because that may decide to do otherwise
2766 if (!using_multi_irqs(dev)) {
2767 if (np->msi_flags & NV_MSI_X_ENABLED)
2768 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2770 disable_irq_lockdep(dev->irq);
2773 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2774 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2775 mask |= NVREG_IRQ_RX_ALL;
2777 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2778 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2779 mask |= NVREG_IRQ_TX_ALL;
2781 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2782 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2783 mask |= NVREG_IRQ_OTHER;
2786 np->nic_poll_irq = 0;
2788 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
2790 writel(mask, base + NvRegIrqMask);
2793 if (!using_multi_irqs(dev)) {
2794 nv_nic_irq(0, dev, NULL);
2795 if (np->msi_flags & NV_MSI_X_ENABLED)
2796 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2798 enable_irq_lockdep(dev->irq);
2800 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2801 nv_nic_irq_rx(0, dev, NULL);
2802 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2804 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2805 nv_nic_irq_tx(0, dev, NULL);
2806 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2808 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2809 nv_nic_irq_other(0, dev, NULL);
2810 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2815 #ifdef CONFIG_NET_POLL_CONTROLLER
2816 static void nv_poll_controller(struct net_device *dev)
2818 nv_do_nic_poll((unsigned long) dev);
2822 static void nv_do_stats_poll(unsigned long data)
2824 struct net_device *dev = (struct net_device *) data;
2825 struct fe_priv *np = netdev_priv(dev);
2826 u8 __iomem *base = get_hwbase(dev);
2828 np->estats.tx_bytes += readl(base + NvRegTxCnt);
2829 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
2830 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
2831 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
2832 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
2833 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
2834 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
2835 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
2836 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
2837 np->estats.tx_deferral += readl(base + NvRegTxDef);
2838 np->estats.tx_packets += readl(base + NvRegTxFrame);
2839 np->estats.tx_pause += readl(base + NvRegTxPause);
2840 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
2841 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
2842 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
2843 np->estats.rx_runt += readl(base + NvRegRxRunt);
2844 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
2845 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
2846 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
2847 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
2848 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
2849 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
2850 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
2851 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
2852 np->estats.rx_bytes += readl(base + NvRegRxCnt);
2853 np->estats.rx_pause += readl(base + NvRegRxPause);
2854 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
2855 np->estats.rx_packets =
2856 np->estats.rx_unicast +
2857 np->estats.rx_multicast +
2858 np->estats.rx_broadcast;
2859 np->estats.rx_errors_total =
2860 np->estats.rx_crc_errors +
2861 np->estats.rx_over_errors +
2862 np->estats.rx_frame_error +
2863 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
2864 np->estats.rx_late_collision +
2865 np->estats.rx_runt +
2866 np->estats.rx_frame_too_long;
2868 if (!np->in_shutdown)
2869 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
2872 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2874 struct fe_priv *np = netdev_priv(dev);
2875 strcpy(info->driver, "forcedeth");
2876 strcpy(info->version, FORCEDETH_VERSION);
2877 strcpy(info->bus_info, pci_name(np->pci_dev));
2880 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2882 struct fe_priv *np = netdev_priv(dev);
2883 wolinfo->supported = WAKE_MAGIC;
2885 spin_lock_irq(&np->lock);
2887 wolinfo->wolopts = WAKE_MAGIC;
2888 spin_unlock_irq(&np->lock);
2891 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2893 struct fe_priv *np = netdev_priv(dev);
2894 u8 __iomem *base = get_hwbase(dev);
2897 if (wolinfo->wolopts == 0) {
2899 } else if (wolinfo->wolopts & WAKE_MAGIC) {
2901 flags = NVREG_WAKEUPFLAGS_ENABLE;
2903 if (netif_running(dev)) {
2904 spin_lock_irq(&np->lock);
2905 writel(flags, base + NvRegWakeUpFlags);
2906 spin_unlock_irq(&np->lock);
2911 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2913 struct fe_priv *np = netdev_priv(dev);
2916 spin_lock_irq(&np->lock);
2917 ecmd->port = PORT_MII;
2918 if (!netif_running(dev)) {
2919 /* We do not track link speed / duplex setting if the
2920 * interface is disabled. Force a link check */
2921 if (nv_update_linkspeed(dev)) {
2922 if (!netif_carrier_ok(dev))
2923 netif_carrier_on(dev);
2925 if (netif_carrier_ok(dev))
2926 netif_carrier_off(dev);
2930 if (netif_carrier_ok(dev)) {
2931 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
2932 case NVREG_LINKSPEED_10:
2933 ecmd->speed = SPEED_10;
2935 case NVREG_LINKSPEED_100:
2936 ecmd->speed = SPEED_100;
2938 case NVREG_LINKSPEED_1000:
2939 ecmd->speed = SPEED_1000;
2942 ecmd->duplex = DUPLEX_HALF;
2944 ecmd->duplex = DUPLEX_FULL;
2950 ecmd->autoneg = np->autoneg;
2952 ecmd->advertising = ADVERTISED_MII;
2954 ecmd->advertising |= ADVERTISED_Autoneg;
2955 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2956 if (adv & ADVERTISE_10HALF)
2957 ecmd->advertising |= ADVERTISED_10baseT_Half;
2958 if (adv & ADVERTISE_10FULL)
2959 ecmd->advertising |= ADVERTISED_10baseT_Full;
2960 if (adv & ADVERTISE_100HALF)
2961 ecmd->advertising |= ADVERTISED_100baseT_Half;
2962 if (adv & ADVERTISE_100FULL)
2963 ecmd->advertising |= ADVERTISED_100baseT_Full;
2964 if (np->gigabit == PHY_GIGABIT) {
2965 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2966 if (adv & ADVERTISE_1000FULL)
2967 ecmd->advertising |= ADVERTISED_1000baseT_Full;
2970 ecmd->supported = (SUPPORTED_Autoneg |
2971 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2972 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2974 if (np->gigabit == PHY_GIGABIT)
2975 ecmd->supported |= SUPPORTED_1000baseT_Full;
2977 ecmd->phy_address = np->phyaddr;
2978 ecmd->transceiver = XCVR_EXTERNAL;
2980 /* ignore maxtxpkt, maxrxpkt for now */
2981 spin_unlock_irq(&np->lock);
2985 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2987 struct fe_priv *np = netdev_priv(dev);
2989 if (ecmd->port != PORT_MII)
2991 if (ecmd->transceiver != XCVR_EXTERNAL)
2993 if (ecmd->phy_address != np->phyaddr) {
2994 /* TODO: support switching between multiple phys. Should be
2995 * trivial, but not enabled due to lack of test hardware. */
2998 if (ecmd->autoneg == AUTONEG_ENABLE) {
3001 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3002 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3003 if (np->gigabit == PHY_GIGABIT)
3004 mask |= ADVERTISED_1000baseT_Full;
3006 if ((ecmd->advertising & mask) == 0)
3009 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3010 /* Note: autonegotiation disable, speed 1000 intentionally
3011 * forbidden - noone should need that. */
3013 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3015 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3021 netif_carrier_off(dev);
3022 if (netif_running(dev)) {
3023 nv_disable_irq(dev);
3024 netif_tx_lock_bh(dev);
3025 spin_lock(&np->lock);
3029 spin_unlock(&np->lock);
3030 netif_tx_unlock_bh(dev);
3033 if (ecmd->autoneg == AUTONEG_ENABLE) {
3038 /* advertise only what has been requested */
3039 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3040 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3041 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3042 adv |= ADVERTISE_10HALF;
3043 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3044 adv |= ADVERTISE_10FULL;
3045 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3046 adv |= ADVERTISE_100HALF;
3047 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3048 adv |= ADVERTISE_100FULL;
3049 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3050 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3051 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3052 adv |= ADVERTISE_PAUSE_ASYM;
3053 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3055 if (np->gigabit == PHY_GIGABIT) {
3056 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3057 adv &= ~ADVERTISE_1000FULL;
3058 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3059 adv |= ADVERTISE_1000FULL;
3060 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3063 if (netif_running(dev))
3064 printk(KERN_INFO "%s: link down.\n", dev->name);
3065 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3066 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3067 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3074 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3075 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3076 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3077 adv |= ADVERTISE_10HALF;
3078 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3079 adv |= ADVERTISE_10FULL;
3080 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3081 adv |= ADVERTISE_100HALF;
3082 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3083 adv |= ADVERTISE_100FULL;
3084 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3085 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3086 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3087 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3089 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3090 adv |= ADVERTISE_PAUSE_ASYM;
3091 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3093 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3094 np->fixed_mode = adv;
3096 if (np->gigabit == PHY_GIGABIT) {
3097 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3098 adv &= ~ADVERTISE_1000FULL;
3099 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3102 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3103 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3104 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3105 bmcr |= BMCR_FULLDPLX;
3106 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3107 bmcr |= BMCR_SPEED100;
3108 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3109 if (np->phy_oui == PHY_OUI_MARVELL) {
3111 if (phy_reset(dev)) {
3112 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3115 } else if (netif_running(dev)) {
3116 /* Wait a bit and then reconfigure the nic. */
3122 if (netif_running(dev)) {
3131 #define FORCEDETH_REGS_VER 1
3133 static int nv_get_regs_len(struct net_device *dev)
3135 struct fe_priv *np = netdev_priv(dev);
3136 return np->register_size;
3139 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3141 struct fe_priv *np = netdev_priv(dev);
3142 u8 __iomem *base = get_hwbase(dev);
3146 regs->version = FORCEDETH_REGS_VER;
3147 spin_lock_irq(&np->lock);
3148 for (i = 0;i <= np->register_size/sizeof(u32); i++)
3149 rbuf[i] = readl(base + i*sizeof(u32));
3150 spin_unlock_irq(&np->lock);
3153 static int nv_nway_reset(struct net_device *dev)
3155 struct fe_priv *np = netdev_priv(dev);
3161 netif_carrier_off(dev);
3162 if (netif_running(dev)) {
3163 nv_disable_irq(dev);
3164 netif_tx_lock_bh(dev);
3165 spin_lock(&np->lock);
3169 spin_unlock(&np->lock);
3170 netif_tx_unlock_bh(dev);
3171 printk(KERN_INFO "%s: link down.\n", dev->name);
3174 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3175 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3176 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3178 if (netif_running(dev)) {
3191 static int nv_set_tso(struct net_device *dev, u32 value)
3193 struct fe_priv *np = netdev_priv(dev);
3195 if ((np->driver_data & DEV_HAS_CHECKSUM))
3196 return ethtool_op_set_tso(dev, value);
3201 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3203 struct fe_priv *np = netdev_priv(dev);
3205 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3206 ring->rx_mini_max_pending = 0;
3207 ring->rx_jumbo_max_pending = 0;
3208 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3210 ring->rx_pending = np->rx_ring_size;
3211 ring->rx_mini_pending = 0;
3212 ring->rx_jumbo_pending = 0;
3213 ring->tx_pending = np->tx_ring_size;
3216 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3218 struct fe_priv *np = netdev_priv(dev);
3219 u8 __iomem *base = get_hwbase(dev);
3220 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff, *rx_dma, *tx_dma, *tx_dma_len;
3221 dma_addr_t ring_addr;
3223 if (ring->rx_pending < RX_RING_MIN ||
3224 ring->tx_pending < TX_RING_MIN ||
3225 ring->rx_mini_pending != 0 ||
3226 ring->rx_jumbo_pending != 0 ||
3227 (np->desc_ver == DESC_VER_1 &&
3228 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3229 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3230 (np->desc_ver != DESC_VER_1 &&
3231 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3232 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3236 /* allocate new rings */
3237 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3238 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3239 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3242 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3243 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3246 rx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->rx_pending, GFP_KERNEL);
3247 rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL);
3248 tx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->tx_pending, GFP_KERNEL);
3249 tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL);
3250 tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL);
3251 if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) {
3252 /* fall back to old rings */
3253 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3255 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3256 rxtx_ring, ring_addr);
3259 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3260 rxtx_ring, ring_addr);
3275 if (netif_running(dev)) {
3276 nv_disable_irq(dev);
3277 netif_tx_lock_bh(dev);
3278 spin_lock(&np->lock);
3290 /* set new values */
3291 np->rx_ring_size = ring->rx_pending;
3292 np->tx_ring_size = ring->tx_pending;
3293 np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE;
3294 np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1;
3295 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3296 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
3297 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3299 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
3300 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3302 np->rx_skbuff = (struct sk_buff**)rx_skbuff;
3303 np->rx_dma = (dma_addr_t*)rx_dma;
3304 np->tx_skbuff = (struct sk_buff**)tx_skbuff;
3305 np->tx_dma = (dma_addr_t*)tx_dma;
3306 np->tx_dma_len = (unsigned int*)tx_dma_len;
3307 np->ring_addr = ring_addr;
3309 memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
3310 memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
3311 memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
3312 memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
3313 memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
3315 if (netif_running(dev)) {
3316 /* reinit driver view of the queues */
3318 if (nv_init_ring(dev)) {
3319 if (!np->in_shutdown)
3320 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3323 /* reinit nic view of the queues */
3324 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3325 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3326 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3327 base + NvRegRingSizes);
3329 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3332 /* restart engines */
3335 spin_unlock(&np->lock);
3336 netif_tx_unlock_bh(dev);
3344 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3346 struct fe_priv *np = netdev_priv(dev);
3348 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
3349 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
3350 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
3353 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3355 struct fe_priv *np = netdev_priv(dev);
3358 if ((!np->autoneg && np->duplex == 0) ||
3359 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
3360 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
3364 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
3365 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
3369 netif_carrier_off(dev);
3370 if (netif_running(dev)) {
3371 nv_disable_irq(dev);
3372 netif_tx_lock_bh(dev);
3373 spin_lock(&np->lock);
3377 spin_unlock(&np->lock);
3378 netif_tx_unlock_bh(dev);
3381 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
3382 if (pause->rx_pause)
3383 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
3384 if (pause->tx_pause)
3385 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
3387 if (np->autoneg && pause->autoneg) {
3388 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
3390 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3391 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3392 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3393 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3394 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3395 adv |= ADVERTISE_PAUSE_ASYM;
3396 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3398 if (netif_running(dev))
3399 printk(KERN_INFO "%s: link down.\n", dev->name);
3400 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3401 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3402 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3404 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3405 if (pause->rx_pause)
3406 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3407 if (pause->tx_pause)
3408 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3410 if (!netif_running(dev))
3411 nv_update_linkspeed(dev);
3413 nv_update_pause(dev, np->pause_flags);
3416 if (netif_running(dev)) {
3424 static u32 nv_get_rx_csum(struct net_device *dev)
3426 struct fe_priv *np = netdev_priv(dev);
3427 return (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) != 0;
3430 static int nv_set_rx_csum(struct net_device *dev, u32 data)
3432 struct fe_priv *np = netdev_priv(dev);
3433 u8 __iomem *base = get_hwbase(dev);
3436 if (np->driver_data & DEV_HAS_CHECKSUM) {
3438 if (((np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && data) ||
3439 (!(np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && !data)) {
3440 /* already set or unset */
3445 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3446 } else if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) {
3447 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3449 printk(KERN_INFO "Can not disable rx checksum if vlan is enabled\n");
3453 if (netif_running(dev)) {
3454 spin_lock_irq(&np->lock);
3455 writel(np->txrxctl_bits, base + NvRegTxRxControl);
3456 spin_unlock_irq(&np->lock);
3465 static int nv_set_tx_csum(struct net_device *dev, u32 data)
3467 struct fe_priv *np = netdev_priv(dev);
3469 if (np->driver_data & DEV_HAS_CHECKSUM)
3470 return ethtool_op_set_tx_hw_csum(dev, data);
3475 static int nv_set_sg(struct net_device *dev, u32 data)
3477 struct fe_priv *np = netdev_priv(dev);
3479 if (np->driver_data & DEV_HAS_CHECKSUM)
3480 return ethtool_op_set_sg(dev, data);
3485 static int nv_get_stats_count(struct net_device *dev)
3487 struct fe_priv *np = netdev_priv(dev);
3489 if (np->driver_data & DEV_HAS_STATISTICS)
3490 return (sizeof(struct nv_ethtool_stats)/sizeof(u64));
3495 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
3497 struct fe_priv *np = netdev_priv(dev);
3500 nv_do_stats_poll((unsigned long)dev);
3502 memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
3505 static int nv_self_test_count(struct net_device *dev)
3507 struct fe_priv *np = netdev_priv(dev);
3509 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
3510 return NV_TEST_COUNT_EXTENDED;
3512 return NV_TEST_COUNT_BASE;
3515 static int nv_link_test(struct net_device *dev)
3517 struct fe_priv *np = netdev_priv(dev);
3520 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3521 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3523 /* check phy link status */
3524 if (!(mii_status & BMSR_LSTATUS))
3530 static int nv_register_test(struct net_device *dev)
3532 u8 __iomem *base = get_hwbase(dev);
3534 u32 orig_read, new_read;
3537 orig_read = readl(base + nv_registers_test[i].reg);
3539 /* xor with mask to toggle bits */
3540 orig_read ^= nv_registers_test[i].mask;
3542 writel(orig_read, base + nv_registers_test[i].reg);
3544 new_read = readl(base + nv_registers_test[i].reg);
3546 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
3549 /* restore original value */
3550 orig_read ^= nv_registers_test[i].mask;
3551 writel(orig_read, base + nv_registers_test[i].reg);
3553 } while (nv_registers_test[++i].reg != 0);
3558 static int nv_interrupt_test(struct net_device *dev)
3560 struct fe_priv *np = netdev_priv(dev);
3561 u8 __iomem *base = get_hwbase(dev);
3564 u32 save_msi_flags, save_poll_interval = 0;
3566 if (netif_running(dev)) {
3567 /* free current irq */
3569 save_poll_interval = readl(base+NvRegPollingInterval);
3572 /* flag to test interrupt handler */
3575 /* setup test irq */
3576 save_msi_flags = np->msi_flags;
3577 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
3578 np->msi_flags |= 0x001; /* setup 1 vector */
3579 if (nv_request_irq(dev, 1))
3582 /* setup timer interrupt */
3583 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3584 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3586 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3588 /* wait for at least one interrupt */
3591 spin_lock_irq(&np->lock);
3593 /* flag should be set within ISR */
3594 testcnt = np->intr_test;
3598 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3599 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3600 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3602 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3604 spin_unlock_irq(&np->lock);
3608 np->msi_flags = save_msi_flags;
3610 if (netif_running(dev)) {
3611 writel(save_poll_interval, base + NvRegPollingInterval);
3612 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3613 /* restore original irq */
3614 if (nv_request_irq(dev, 0))
3621 static int nv_loopback_test(struct net_device *dev)
3623 struct fe_priv *np = netdev_priv(dev);
3624 u8 __iomem *base = get_hwbase(dev);
3625 struct sk_buff *tx_skb, *rx_skb;
3626 dma_addr_t test_dma_addr;
3627 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
3629 int len, i, pkt_len;
3631 u32 filter_flags = 0;
3632 u32 misc1_flags = 0;
3635 if (netif_running(dev)) {
3636 nv_disable_irq(dev);
3637 filter_flags = readl(base + NvRegPacketFilterFlags);
3638 misc1_flags = readl(base + NvRegMisc1);
3643 /* reinit driver view of the rx queue */
3647 /* setup hardware for loopback */
3648 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
3649 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
3651 /* reinit nic view of the rx queue */
3652 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3653 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3654 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3655 base + NvRegRingSizes);
3658 /* restart rx engine */
3662 /* setup packet for tx */
3663 pkt_len = ETH_DATA_LEN;
3664 tx_skb = dev_alloc_skb(pkt_len);
3665 pkt_data = skb_put(tx_skb, pkt_len);
3666 for (i = 0; i < pkt_len; i++)
3667 pkt_data[i] = (u8)(i & 0xff);
3668 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
3669 tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
3671 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3672 np->tx_ring.orig[0].PacketBuffer = cpu_to_le32(test_dma_addr);
3673 np->tx_ring.orig[0].FlagLen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3675 np->tx_ring.ex[0].PacketBufferHigh = cpu_to_le64(test_dma_addr) >> 32;
3676 np->tx_ring.ex[0].PacketBufferLow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
3677 np->tx_ring.ex[0].FlagLen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3679 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3680 pci_push(get_hwbase(dev));
3684 /* check for rx of the packet */
3685 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3686 Flags = le32_to_cpu(np->rx_ring.orig[0].FlagLen);
3687 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
3690 Flags = le32_to_cpu(np->rx_ring.ex[0].FlagLen);
3691 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
3694 if (Flags & NV_RX_AVAIL) {
3696 } else if (np->desc_ver == DESC_VER_1) {
3697 if (Flags & NV_RX_ERROR)
3700 if (Flags & NV_RX2_ERROR) {
3706 if (len != pkt_len) {
3708 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
3709 dev->name, len, pkt_len);
3711 rx_skb = np->rx_skbuff[0];
3712 for (i = 0; i < pkt_len; i++) {
3713 if (rx_skb->data[i] != (u8)(i & 0xff)) {
3715 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
3722 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
3725 pci_unmap_page(np->pci_dev, test_dma_addr,
3726 tx_skb->end-tx_skb->data,
3728 dev_kfree_skb_any(tx_skb);
3734 /* drain rx queue */
3738 if (netif_running(dev)) {
3739 writel(misc1_flags, base + NvRegMisc1);
3740 writel(filter_flags, base + NvRegPacketFilterFlags);
3747 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
3749 struct fe_priv *np = netdev_priv(dev);
3750 u8 __iomem *base = get_hwbase(dev);
3752 memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
3754 if (!nv_link_test(dev)) {
3755 test->flags |= ETH_TEST_FL_FAILED;
3759 if (test->flags & ETH_TEST_FL_OFFLINE) {
3760 if (netif_running(dev)) {
3761 netif_stop_queue(dev);
3762 netif_tx_lock_bh(dev);
3763 spin_lock_irq(&np->lock);
3764 nv_disable_hw_interrupts(dev, np->irqmask);
3765 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3766 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3768 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3774 /* drain rx queue */
3777 spin_unlock_irq(&np->lock);
3778 netif_tx_unlock_bh(dev);
3781 if (!nv_register_test(dev)) {
3782 test->flags |= ETH_TEST_FL_FAILED;
3786 result = nv_interrupt_test(dev);
3788 test->flags |= ETH_TEST_FL_FAILED;
3796 if (!nv_loopback_test(dev)) {
3797 test->flags |= ETH_TEST_FL_FAILED;
3801 if (netif_running(dev)) {
3802 /* reinit driver view of the rx queue */
3804 if (nv_init_ring(dev)) {
3805 if (!np->in_shutdown)
3806 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3808 /* reinit nic view of the rx queue */
3809 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3810 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3811 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3812 base + NvRegRingSizes);
3814 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3816 /* restart rx engine */
3819 netif_start_queue(dev);
3820 nv_enable_hw_interrupts(dev, np->irqmask);
3825 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
3827 switch (stringset) {
3829 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
3832 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
3837 static struct ethtool_ops ops = {
3838 .get_drvinfo = nv_get_drvinfo,
3839 .get_link = ethtool_op_get_link,
3840 .get_wol = nv_get_wol,
3841 .set_wol = nv_set_wol,
3842 .get_settings = nv_get_settings,
3843 .set_settings = nv_set_settings,
3844 .get_regs_len = nv_get_regs_len,
3845 .get_regs = nv_get_regs,
3846 .nway_reset = nv_nway_reset,
3847 .get_perm_addr = ethtool_op_get_perm_addr,
3848 .get_tso = ethtool_op_get_tso,
3849 .set_tso = nv_set_tso,
3850 .get_ringparam = nv_get_ringparam,
3851 .set_ringparam = nv_set_ringparam,
3852 .get_pauseparam = nv_get_pauseparam,
3853 .set_pauseparam = nv_set_pauseparam,
3854 .get_rx_csum = nv_get_rx_csum,
3855 .set_rx_csum = nv_set_rx_csum,
3856 .get_tx_csum = ethtool_op_get_tx_csum,
3857 .set_tx_csum = nv_set_tx_csum,
3858 .get_sg = ethtool_op_get_sg,
3859 .set_sg = nv_set_sg,
3860 .get_strings = nv_get_strings,
3861 .get_stats_count = nv_get_stats_count,
3862 .get_ethtool_stats = nv_get_ethtool_stats,
3863 .self_test_count = nv_self_test_count,
3864 .self_test = nv_self_test,
3867 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
3869 struct fe_priv *np = get_nvpriv(dev);
3871 spin_lock_irq(&np->lock);
3873 /* save vlan group */
3877 /* enable vlan on MAC */
3878 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
3880 /* disable vlan on MAC */
3881 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
3882 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
3885 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3887 spin_unlock_irq(&np->lock);
3890 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
3895 static int nv_open(struct net_device *dev)
3897 struct fe_priv *np = netdev_priv(dev);
3898 u8 __iomem *base = get_hwbase(dev);
3902 dprintk(KERN_DEBUG "nv_open: begin\n");
3904 /* 1) erase previous misconfiguration */
3905 if (np->driver_data & DEV_HAS_POWER_CNTRL)
3907 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
3908 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
3909 writel(0, base + NvRegMulticastAddrB);
3910 writel(0, base + NvRegMulticastMaskA);
3911 writel(0, base + NvRegMulticastMaskB);
3912 writel(0, base + NvRegPacketFilterFlags);
3914 writel(0, base + NvRegTransmitterControl);
3915 writel(0, base + NvRegReceiverControl);
3917 writel(0, base + NvRegAdapterControl);
3919 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
3920 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3922 /* 2) initialize descriptor rings */
3924 oom = nv_init_ring(dev);
3926 writel(0, base + NvRegLinkSpeed);
3927 writel(0, base + NvRegUnknownTransmitterReg);
3929 writel(0, base + NvRegUnknownSetupReg6);
3931 np->in_shutdown = 0;
3933 /* 3) set mac address */
3934 nv_copy_mac_to_hw(dev);
3936 /* 4) give hw rings */
3937 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3938 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3939 base + NvRegRingSizes);
3941 /* 5) continue setup */
3942 writel(np->linkspeed, base + NvRegLinkSpeed);
3943 if (np->desc_ver == DESC_VER_1)
3944 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
3946 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
3947 writel(np->txrxctl_bits, base + NvRegTxRxControl);
3948 writel(np->vlanctl_bits, base + NvRegVlanControl);
3950 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
3951 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
3952 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
3953 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
3955 writel(0, base + NvRegUnknownSetupReg4);
3956 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3957 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
3959 /* 6) continue setup */
3960 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
3961 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
3962 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
3963 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3965 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
3966 get_random_bytes(&i, sizeof(i));
3967 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
3968 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
3969 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
3970 if (poll_interval == -1) {
3971 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
3972 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
3974 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3977 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
3978 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3979 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
3980 base + NvRegAdapterControl);
3981 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
3982 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
3984 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
3986 i = readl(base + NvRegPowerState);
3987 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
3988 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
3992 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
3994 nv_disable_hw_interrupts(dev, np->irqmask);
3996 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
3997 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4000 if (nv_request_irq(dev, 0)) {
4004 /* ask for interrupts */
4005 nv_enable_hw_interrupts(dev, np->irqmask);
4007 spin_lock_irq(&np->lock);
4008 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4009 writel(0, base + NvRegMulticastAddrB);
4010 writel(0, base + NvRegMulticastMaskA);
4011 writel(0, base + NvRegMulticastMaskB);
4012 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4013 /* One manual link speed update: Interrupts are enabled, future link
4014 * speed changes cause interrupts and are handled by nv_link_irq().
4018 miistat = readl(base + NvRegMIIStatus);
4019 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4020 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4022 /* set linkspeed to invalid value, thus force nv_update_linkspeed
4025 ret = nv_update_linkspeed(dev);
4028 netif_start_queue(dev);
4030 netif_carrier_on(dev);
4032 printk("%s: no link during initialization.\n", dev->name);
4033 netif_carrier_off(dev);
4036 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4038 /* start statistics timer */
4039 if (np->driver_data & DEV_HAS_STATISTICS)
4040 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4042 spin_unlock_irq(&np->lock);
4050 static int nv_close(struct net_device *dev)
4052 struct fe_priv *np = netdev_priv(dev);
4055 spin_lock_irq(&np->lock);
4056 np->in_shutdown = 1;
4057 spin_unlock_irq(&np->lock);
4058 synchronize_irq(dev->irq);
4060 del_timer_sync(&np->oom_kick);
4061 del_timer_sync(&np->nic_poll);
4062 del_timer_sync(&np->stats_poll);
4064 netif_stop_queue(dev);
4065 spin_lock_irq(&np->lock);
4070 /* disable interrupts on the nic or we will lock up */
4071 base = get_hwbase(dev);
4072 nv_disable_hw_interrupts(dev, np->irqmask);
4074 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4076 spin_unlock_irq(&np->lock);
4085 /* special op: write back the misordered MAC address - otherwise
4086 * the next nv_probe would see a wrong address.
4088 writel(np->orig_mac[0], base + NvRegMacAddrA);
4089 writel(np->orig_mac[1], base + NvRegMacAddrB);
4091 /* FIXME: power down nic */
4096 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4098 struct net_device *dev;
4105 dev = alloc_etherdev(sizeof(struct fe_priv));
4110 np = netdev_priv(dev);
4111 np->pci_dev = pci_dev;
4112 spin_lock_init(&np->lock);
4113 SET_MODULE_OWNER(dev);
4114 SET_NETDEV_DEV(dev, &pci_dev->dev);
4116 init_timer(&np->oom_kick);
4117 np->oom_kick.data = (unsigned long) dev;
4118 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
4119 init_timer(&np->nic_poll);
4120 np->nic_poll.data = (unsigned long) dev;
4121 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
4122 init_timer(&np->stats_poll);
4123 np->stats_poll.data = (unsigned long) dev;
4124 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
4126 err = pci_enable_device(pci_dev);
4128 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4129 err, pci_name(pci_dev));
4133 pci_set_master(pci_dev);
4135 err = pci_request_regions(pci_dev, DRV_NAME);
4139 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
4140 np->register_size = NV_PCI_REGSZ_VER2;
4142 np->register_size = NV_PCI_REGSZ_VER1;
4146 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4147 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4148 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4149 pci_resource_len(pci_dev, i),
4150 pci_resource_flags(pci_dev, i));
4151 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4152 pci_resource_len(pci_dev, i) >= np->register_size) {
4153 addr = pci_resource_start(pci_dev, i);
4157 if (i == DEVICE_COUNT_RESOURCE) {
4158 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4163 /* copy of driver data */
4164 np->driver_data = id->driver_data;
4166 /* handle different descriptor versions */
4167 if (id->driver_data & DEV_HAS_HIGH_DMA) {
4168 /* packet format 3: supports 40-bit addressing */
4169 np->desc_ver = DESC_VER_3;
4170 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4172 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4173 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4176 dev->features |= NETIF_F_HIGHDMA;
4177 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4179 if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4180 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4184 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4185 /* packet format 2: supports jumbo frames */
4186 np->desc_ver = DESC_VER_2;
4187 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4189 /* original packet format */
4190 np->desc_ver = DESC_VER_1;
4191 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4194 np->pkt_limit = NV_PKTLIMIT_1;
4195 if (id->driver_data & DEV_HAS_LARGEDESC)
4196 np->pkt_limit = NV_PKTLIMIT_2;
4198 if (id->driver_data & DEV_HAS_CHECKSUM) {
4199 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4200 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4202 dev->features |= NETIF_F_TSO;
4206 np->vlanctl_bits = 0;
4207 if (id->driver_data & DEV_HAS_VLAN) {
4208 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4209 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4210 dev->vlan_rx_register = nv_vlan_rx_register;
4211 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4215 if ((id->driver_data & DEV_HAS_MSI) && msi) {
4216 np->msi_flags |= NV_MSI_CAPABLE;
4218 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4219 np->msi_flags |= NV_MSI_X_CAPABLE;
4222 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4223 if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4224 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4229 np->base = ioremap(addr, np->register_size);
4232 dev->base_addr = (unsigned long)np->base;
4234 dev->irq = pci_dev->irq;
4236 np->rx_ring_size = RX_RING_DEFAULT;
4237 np->tx_ring_size = TX_RING_DEFAULT;
4238 np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE;
4239 np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1;
4241 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4242 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4243 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4245 if (!np->rx_ring.orig)
4247 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4249 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4250 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4252 if (!np->rx_ring.ex)
4254 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4256 np->rx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->rx_ring_size, GFP_KERNEL);
4257 np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL);
4258 np->tx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->tx_ring_size, GFP_KERNEL);
4259 np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL);
4260 np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL);
4261 if (!np->rx_skbuff || !np->rx_dma || !np->tx_skbuff || !np->tx_dma || !np->tx_dma_len)
4263 memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
4264 memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
4265 memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
4266 memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
4267 memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
4269 dev->open = nv_open;
4270 dev->stop = nv_close;
4271 dev->hard_start_xmit = nv_start_xmit;
4272 dev->get_stats = nv_get_stats;
4273 dev->change_mtu = nv_change_mtu;
4274 dev->set_mac_address = nv_set_mac_address;
4275 dev->set_multicast_list = nv_set_multicast;
4276 #ifdef CONFIG_NET_POLL_CONTROLLER
4277 dev->poll_controller = nv_poll_controller;
4279 SET_ETHTOOL_OPS(dev, &ops);
4280 dev->tx_timeout = nv_tx_timeout;
4281 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
4283 pci_set_drvdata(pci_dev, dev);
4285 /* read the mac address */
4286 base = get_hwbase(dev);
4287 np->orig_mac[0] = readl(base + NvRegMacAddrA);
4288 np->orig_mac[1] = readl(base + NvRegMacAddrB);
4290 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
4291 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
4292 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
4293 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
4294 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
4295 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
4296 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4298 if (!is_valid_ether_addr(dev->perm_addr)) {
4300 * Bad mac address. At least one bios sets the mac address
4301 * to 01:23:45:67:89:ab
4303 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
4305 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4306 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4307 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
4308 dev->dev_addr[0] = 0x00;
4309 dev->dev_addr[1] = 0x00;
4310 dev->dev_addr[2] = 0x6c;
4311 get_random_bytes(&dev->dev_addr[3], 3);
4314 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
4315 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4316 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4319 writel(0, base + NvRegWakeUpFlags);
4322 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
4324 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
4326 /* take phy and nic out of low power mode */
4327 powerstate = readl(base + NvRegPowerState2);
4328 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
4329 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
4330 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
4331 revision_id >= 0xA3)
4332 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
4333 writel(powerstate, base + NvRegPowerState2);
4336 if (np->desc_ver == DESC_VER_1) {
4337 np->tx_flags = NV_TX_VALID;
4339 np->tx_flags = NV_TX2_VALID;
4341 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
4342 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
4343 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4344 np->msi_flags |= 0x0003;
4346 np->irqmask = NVREG_IRQMASK_CPU;
4347 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4348 np->msi_flags |= 0x0001;
4351 if (id->driver_data & DEV_NEED_TIMERIRQ)
4352 np->irqmask |= NVREG_IRQ_TIMER;
4353 if (id->driver_data & DEV_NEED_LINKTIMER) {
4354 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
4355 np->need_linktimer = 1;
4356 np->link_timeout = jiffies + LINK_TIMEOUT;
4358 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
4359 np->need_linktimer = 0;
4362 /* find a suitable phy */
4363 for (i = 1; i <= 32; i++) {
4365 int phyaddr = i & 0x1F;
4367 spin_lock_irq(&np->lock);
4368 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
4369 spin_unlock_irq(&np->lock);
4370 if (id1 < 0 || id1 == 0xffff)
4372 spin_lock_irq(&np->lock);
4373 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
4374 spin_unlock_irq(&np->lock);
4375 if (id2 < 0 || id2 == 0xffff)
4378 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
4379 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
4380 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
4381 pci_name(pci_dev), id1, id2, phyaddr);
4382 np->phyaddr = phyaddr;
4383 np->phy_oui = id1 | id2;
4387 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
4395 /* set default link speed settings */
4396 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
4400 err = register_netdev(dev);
4402 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
4405 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
4406 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
4412 pci_set_drvdata(pci_dev, NULL);
4416 iounmap(get_hwbase(dev));
4418 pci_release_regions(pci_dev);
4420 pci_disable_device(pci_dev);
4427 static void __devexit nv_remove(struct pci_dev *pci_dev)
4429 struct net_device *dev = pci_get_drvdata(pci_dev);
4431 unregister_netdev(dev);
4433 /* free all structures */
4435 iounmap(get_hwbase(dev));
4436 pci_release_regions(pci_dev);
4437 pci_disable_device(pci_dev);
4439 pci_set_drvdata(pci_dev, NULL);
4445 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
4447 struct net_device *dev = pci_get_drvdata(pdev);
4448 struct fe_priv *np = netdev_priv(dev);
4450 if (!netif_running(dev))
4453 netif_device_detach(dev);
4458 pci_save_state(pdev);
4459 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
4460 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4465 static int nv_resume(struct pci_dev *pdev)
4467 struct net_device *dev = pci_get_drvdata(pdev);
4470 if (!netif_running(dev))
4473 netif_device_attach(dev);
4475 pci_set_power_state(pdev, PCI_D0);
4476 pci_restore_state(pdev);
4477 pci_enable_wake(pdev, PCI_D0, 0);
4484 #endif /* CONFIG_PM */
4486 static struct pci_device_id pci_tbl[] = {
4487 { /* nForce Ethernet Controller */
4488 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
4489 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4491 { /* nForce2 Ethernet Controller */
4492 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
4493 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4495 { /* nForce3 Ethernet Controller */
4496 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
4497 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4499 { /* nForce3 Ethernet Controller */
4500 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
4501 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4503 { /* nForce3 Ethernet Controller */
4504 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
4505 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4507 { /* nForce3 Ethernet Controller */
4508 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
4509 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4511 { /* nForce3 Ethernet Controller */
4512 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
4513 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4515 { /* CK804 Ethernet Controller */
4516 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
4517 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4519 { /* CK804 Ethernet Controller */
4520 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
4521 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4523 { /* MCP04 Ethernet Controller */
4524 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
4525 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4527 { /* MCP04 Ethernet Controller */
4528 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
4529 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4531 { /* MCP51 Ethernet Controller */
4532 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
4533 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4535 { /* MCP51 Ethernet Controller */
4536 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
4537 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4539 { /* MCP55 Ethernet Controller */
4540 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
4541 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4543 { /* MCP55 Ethernet Controller */
4544 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
4545 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4547 { /* MCP61 Ethernet Controller */
4548 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
4549 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4551 { /* MCP61 Ethernet Controller */
4552 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
4553 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4555 { /* MCP61 Ethernet Controller */
4556 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
4557 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4559 { /* MCP61 Ethernet Controller */
4560 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
4561 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4563 { /* MCP65 Ethernet Controller */
4564 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
4565 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4567 { /* MCP65 Ethernet Controller */
4568 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
4569 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4571 { /* MCP65 Ethernet Controller */
4572 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
4573 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4575 { /* MCP65 Ethernet Controller */
4576 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
4577 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4582 static struct pci_driver driver = {
4583 .name = "forcedeth",
4584 .id_table = pci_tbl,
4586 .remove = __devexit_p(nv_remove),
4588 .suspend = nv_suspend,
4589 .resume = nv_resume,
4594 static int __init init_nic(void)
4596 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
4597 return pci_module_init(&driver);
4600 static void __exit exit_nic(void)
4602 pci_unregister_driver(&driver);
4605 module_param(max_interrupt_work, int, 0);
4606 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
4607 module_param(optimization_mode, int, 0);
4608 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
4609 module_param(poll_interval, int, 0);
4610 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
4611 module_param(msi, int, 0);
4612 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
4613 module_param(msix, int, 0);
4614 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
4615 module_param(dma_64bit, int, 0);
4616 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
4618 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
4619 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
4620 MODULE_LICENSE("GPL");
4622 MODULE_DEVICE_TABLE(pci, pci_tbl);
4624 module_init(init_nic);
4625 module_exit(exit_nic);