2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
13 * Copyright (C) 2003,4 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80 * into nv_close, otherwise reenabling for wol can
81 * cause DMA to kfree'd memory.
84 * We suspect that on some hardware no TX done interrupts are generated.
85 * This means recovery from netif_stop_queue only happens if the hw timer
86 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
87 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
88 * If your hardware reliably generates tx done interrupts, then you can remove
89 * DEV_NEED_TIMERIRQ from the driver_data flags.
90 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
91 * superfluous timer interrupts from the nic.
93 #define FORCEDETH_VERSION "0.30"
94 #define DRV_NAME "forcedeth"
96 #include <linux/module.h>
97 #include <linux/types.h>
98 #include <linux/pci.h>
99 #include <linux/interrupt.h>
100 #include <linux/netdevice.h>
101 #include <linux/etherdevice.h>
102 #include <linux/delay.h>
103 #include <linux/spinlock.h>
104 #include <linux/ethtool.h>
105 #include <linux/timer.h>
106 #include <linux/skbuff.h>
107 #include <linux/mii.h>
108 #include <linux/random.h>
109 #include <linux/init.h>
113 #include <asm/uaccess.h>
114 #include <asm/system.h>
117 #define dprintk printk
119 #define dprintk(x...) do { } while (0)
127 #define DEV_NEED_LASTPACKET1 0x0001 /* set LASTPACKET1 in tx flags */
128 #define DEV_IRQMASK_1 0x0002 /* use NVREG_IRQMASK_WANTED_1 for irq mask */
129 #define DEV_IRQMASK_2 0x0004 /* use NVREG_IRQMASK_WANTED_2 for irq mask */
130 #define DEV_NEED_TIMERIRQ 0x0008 /* set the timer irq flag in the irq mask */
131 #define DEV_NEED_LINKTIMER 0x0010 /* poll link settings. Relies on the timer irq */
134 NvRegIrqStatus = 0x000,
135 #define NVREG_IRQSTAT_MIIEVENT 0x040
136 #define NVREG_IRQSTAT_MASK 0x1ff
137 NvRegIrqMask = 0x004,
138 #define NVREG_IRQ_RX_ERROR 0x0001
139 #define NVREG_IRQ_RX 0x0002
140 #define NVREG_IRQ_RX_NOBUF 0x0004
141 #define NVREG_IRQ_TX_ERR 0x0008
142 #define NVREG_IRQ_TX2 0x0010
143 #define NVREG_IRQ_TIMER 0x0020
144 #define NVREG_IRQ_LINK 0x0040
145 #define NVREG_IRQ_TX1 0x0100
146 #define NVREG_IRQMASK_WANTED_1 0x005f
147 #define NVREG_IRQMASK_WANTED_2 0x0147
148 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
150 NvRegUnknownSetupReg6 = 0x008,
151 #define NVREG_UNKSETUP6_VAL 3
154 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
155 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
157 NvRegPollingInterval = 0x00c,
158 #define NVREG_POLL_DEFAULT 970
160 #define NVREG_MISC1_HD 0x02
161 #define NVREG_MISC1_FORCE 0x3b0f3c
163 NvRegTransmitterControl = 0x084,
164 #define NVREG_XMITCTL_START 0x01
165 NvRegTransmitterStatus = 0x088,
166 #define NVREG_XMITSTAT_BUSY 0x01
168 NvRegPacketFilterFlags = 0x8c,
169 #define NVREG_PFF_ALWAYS 0x7F0008
170 #define NVREG_PFF_PROMISC 0x80
171 #define NVREG_PFF_MYADDR 0x20
173 NvRegOffloadConfig = 0x90,
174 #define NVREG_OFFLOAD_HOMEPHY 0x601
175 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
176 NvRegReceiverControl = 0x094,
177 #define NVREG_RCVCTL_START 0x01
178 NvRegReceiverStatus = 0x98,
179 #define NVREG_RCVSTAT_BUSY 0x01
181 NvRegRandomSeed = 0x9c,
182 #define NVREG_RNDSEED_MASK 0x00ff
183 #define NVREG_RNDSEED_FORCE 0x7f00
184 #define NVREG_RNDSEED_FORCE2 0x2d00
185 #define NVREG_RNDSEED_FORCE3 0x7400
187 NvRegUnknownSetupReg1 = 0xA0,
188 #define NVREG_UNKSETUP1_VAL 0x16070f
189 NvRegUnknownSetupReg2 = 0xA4,
190 #define NVREG_UNKSETUP2_VAL 0x16
191 NvRegMacAddrA = 0xA8,
192 NvRegMacAddrB = 0xAC,
193 NvRegMulticastAddrA = 0xB0,
194 #define NVREG_MCASTADDRA_FORCE 0x01
195 NvRegMulticastAddrB = 0xB4,
196 NvRegMulticastMaskA = 0xB8,
197 NvRegMulticastMaskB = 0xBC,
199 NvRegPhyInterface = 0xC0,
200 #define PHY_RGMII 0x10000000
202 NvRegTxRingPhysAddr = 0x100,
203 NvRegRxRingPhysAddr = 0x104,
204 NvRegRingSizes = 0x108,
205 #define NVREG_RINGSZ_TXSHIFT 0
206 #define NVREG_RINGSZ_RXSHIFT 16
207 NvRegUnknownTransmitterReg = 0x10c,
208 NvRegLinkSpeed = 0x110,
209 #define NVREG_LINKSPEED_FORCE 0x10000
210 #define NVREG_LINKSPEED_10 1000
211 #define NVREG_LINKSPEED_100 100
212 #define NVREG_LINKSPEED_1000 50
213 NvRegUnknownSetupReg5 = 0x130,
214 #define NVREG_UNKSETUP5_BIT31 (1<<31)
215 NvRegUnknownSetupReg3 = 0x13c,
216 #define NVREG_UNKSETUP3_VAL1 0x200010
217 NvRegTxRxControl = 0x144,
218 #define NVREG_TXRXCTL_KICK 0x0001
219 #define NVREG_TXRXCTL_BIT1 0x0002
220 #define NVREG_TXRXCTL_BIT2 0x0004
221 #define NVREG_TXRXCTL_IDLE 0x0008
222 #define NVREG_TXRXCTL_RESET 0x0010
223 #define NVREG_TXRXCTL_RXCHECK 0x0400
224 NvRegMIIStatus = 0x180,
225 #define NVREG_MIISTAT_ERROR 0x0001
226 #define NVREG_MIISTAT_LINKCHANGE 0x0008
227 #define NVREG_MIISTAT_MASK 0x000f
228 #define NVREG_MIISTAT_MASK2 0x000f
229 NvRegUnknownSetupReg4 = 0x184,
230 #define NVREG_UNKSETUP4_VAL 8
232 NvRegAdapterControl = 0x188,
233 #define NVREG_ADAPTCTL_START 0x02
234 #define NVREG_ADAPTCTL_LINKUP 0x04
235 #define NVREG_ADAPTCTL_PHYVALID 0x40000
236 #define NVREG_ADAPTCTL_RUNNING 0x100000
237 #define NVREG_ADAPTCTL_PHYSHIFT 24
238 NvRegMIISpeed = 0x18c,
239 #define NVREG_MIISPEED_BIT8 (1<<8)
240 #define NVREG_MIIDELAY 5
241 NvRegMIIControl = 0x190,
242 #define NVREG_MIICTL_INUSE 0x08000
243 #define NVREG_MIICTL_WRITE 0x00400
244 #define NVREG_MIICTL_ADDRSHIFT 5
245 NvRegMIIData = 0x194,
246 NvRegWakeUpFlags = 0x200,
247 #define NVREG_WAKEUPFLAGS_VAL 0x7770
248 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
249 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
250 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
251 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
252 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
253 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
254 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
255 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
256 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
257 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
259 NvRegPatternCRC = 0x204,
260 NvRegPatternMask = 0x208,
261 NvRegPowerCap = 0x268,
262 #define NVREG_POWERCAP_D3SUPP (1<<30)
263 #define NVREG_POWERCAP_D2SUPP (1<<26)
264 #define NVREG_POWERCAP_D1SUPP (1<<25)
265 NvRegPowerState = 0x26c,
266 #define NVREG_POWERSTATE_POWEREDUP 0x8000
267 #define NVREG_POWERSTATE_VALID 0x0100
268 #define NVREG_POWERSTATE_MASK 0x0003
269 #define NVREG_POWERSTATE_D0 0x0000
270 #define NVREG_POWERSTATE_D1 0x0001
271 #define NVREG_POWERSTATE_D2 0x0002
272 #define NVREG_POWERSTATE_D3 0x0003
275 /* Big endian: should work, but is untested */
281 #define FLAG_MASK_V1 0xffff0000
282 #define FLAG_MASK_V2 0xffffc000
283 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
284 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
286 #define NV_TX_LASTPACKET (1<<16)
287 #define NV_TX_RETRYERROR (1<<19)
288 #define NV_TX_LASTPACKET1 (1<<24)
289 #define NV_TX_DEFERRED (1<<26)
290 #define NV_TX_CARRIERLOST (1<<27)
291 #define NV_TX_LATECOLLISION (1<<28)
292 #define NV_TX_UNDERFLOW (1<<29)
293 #define NV_TX_ERROR (1<<30)
294 #define NV_TX_VALID (1<<31)
296 #define NV_TX2_LASTPACKET (1<<29)
297 #define NV_TX2_RETRYERROR (1<<18)
298 #define NV_TX2_LASTPACKET1 (1<<23)
299 #define NV_TX2_DEFERRED (1<<25)
300 #define NV_TX2_CARRIERLOST (1<<26)
301 #define NV_TX2_LATECOLLISION (1<<27)
302 #define NV_TX2_UNDERFLOW (1<<28)
303 /* error and valid are the same for both */
304 #define NV_TX2_ERROR (1<<30)
305 #define NV_TX2_VALID (1<<31)
307 #define NV_RX_DESCRIPTORVALID (1<<16)
308 #define NV_RX_MISSEDFRAME (1<<17)
309 #define NV_RX_SUBSTRACT1 (1<<18)
310 #define NV_RX_ERROR1 (1<<23)
311 #define NV_RX_ERROR2 (1<<24)
312 #define NV_RX_ERROR3 (1<<25)
313 #define NV_RX_ERROR4 (1<<26)
314 #define NV_RX_CRCERR (1<<27)
315 #define NV_RX_OVERFLOW (1<<28)
316 #define NV_RX_FRAMINGERR (1<<29)
317 #define NV_RX_ERROR (1<<30)
318 #define NV_RX_AVAIL (1<<31)
320 #define NV_RX2_CHECKSUMMASK (0x1C000000)
321 #define NV_RX2_CHECKSUMOK1 (0x10000000)
322 #define NV_RX2_CHECKSUMOK2 (0x14000000)
323 #define NV_RX2_CHECKSUMOK3 (0x18000000)
324 #define NV_RX2_DESCRIPTORVALID (1<<29)
325 #define NV_RX2_SUBSTRACT1 (1<<25)
326 #define NV_RX2_ERROR1 (1<<18)
327 #define NV_RX2_ERROR2 (1<<19)
328 #define NV_RX2_ERROR3 (1<<20)
329 #define NV_RX2_ERROR4 (1<<21)
330 #define NV_RX2_CRCERR (1<<22)
331 #define NV_RX2_OVERFLOW (1<<23)
332 #define NV_RX2_FRAMINGERR (1<<24)
333 /* error and avail are the same for both */
334 #define NV_RX2_ERROR (1<<30)
335 #define NV_RX2_AVAIL (1<<31)
337 /* Miscelaneous hardware related defines: */
338 #define NV_PCI_REGSZ 0x270
340 /* various timeout delays: all in usec */
341 #define NV_TXRX_RESET_DELAY 4
342 #define NV_TXSTOP_DELAY1 10
343 #define NV_TXSTOP_DELAY1MAX 500000
344 #define NV_TXSTOP_DELAY2 100
345 #define NV_RXSTOP_DELAY1 10
346 #define NV_RXSTOP_DELAY1MAX 500000
347 #define NV_RXSTOP_DELAY2 100
348 #define NV_SETUP5_DELAY 5
349 #define NV_SETUP5_DELAYMAX 50000
350 #define NV_POWERUP_DELAY 5
351 #define NV_POWERUP_DELAYMAX 5000
352 #define NV_MIIBUSY_DELAY 50
353 #define NV_MIIPHY_DELAY 10
354 #define NV_MIIPHY_DELAYMAX 10000
356 #define NV_WAKEUPPATTERNS 5
357 #define NV_WAKEUPMASKENTRIES 4
359 /* General driver defaults */
360 #define NV_WATCHDOG_TIMEO (5*HZ)
365 * If your nic mysteriously hangs then try to reduce the limits
366 * to 1/0: It might be required to set NV_TX_LASTPACKET in the
367 * last valid ring entry. But this would be impossible to
368 * implement - probably a disassembly error.
370 #define TX_LIMIT_STOP 63
371 #define TX_LIMIT_START 62
373 /* rx/tx mac addr + type + vlan + align + slack*/
374 #define RX_NIC_BUFSIZE (ETH_DATA_LEN + 64)
375 /* even more slack */
376 #define RX_ALLOC_BUFSIZE (ETH_DATA_LEN + 128)
378 #define OOM_REFILL (1+HZ/20)
379 #define POLL_WAIT (1+HZ/100)
380 #define LINK_TIMEOUT (3*HZ)
384 * This field has two purposes:
385 * - Newer nics uses a different ring layout. The layout is selected by
386 * comparing np->desc_ver with DESC_VER_xy.
387 * - It contains bits that are forced on when writing to NvRegTxRxControl.
389 #define DESC_VER_1 0x0
390 #define DESC_VER_2 (0x02100|NVREG_TXRXCTL_RXCHECK)
393 #define PHY_OUI_MARVELL 0x5043
394 #define PHY_OUI_CICADA 0x03f1
395 #define PHYID1_OUI_MASK 0x03ff
396 #define PHYID1_OUI_SHFT 6
397 #define PHYID2_OUI_MASK 0xfc00
398 #define PHYID2_OUI_SHFT 10
399 #define PHY_INIT1 0x0f000
400 #define PHY_INIT2 0x0e00
401 #define PHY_INIT3 0x01000
402 #define PHY_INIT4 0x0200
403 #define PHY_INIT5 0x0004
404 #define PHY_INIT6 0x02000
405 #define PHY_GIGABIT 0x0100
407 #define PHY_TIMEOUT 0x1
408 #define PHY_ERROR 0x2
412 #define PHY_HALF 0x100
414 /* FIXME: MII defines that should be added to <linux/mii.h> */
415 #define MII_1000BT_CR 0x09
416 #define MII_1000BT_SR 0x0a
417 #define ADVERTISE_1000FULL 0x0200
418 #define ADVERTISE_1000HALF 0x0100
419 #define LPA_1000FULL 0x0800
420 #define LPA_1000HALF 0x0400
425 * All hardware access under dev->priv->lock, except the performance
427 * - rx is (pseudo-) lockless: it relies on the single-threading provided
428 * by the arch code for interrupts.
429 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
430 * needs dev->priv->lock :-(
431 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
434 /* in dev: base, irq */
439 * Locking: spin_lock(&np->lock); */
440 struct net_device_stats stats;
446 unsigned int phy_oui;
449 /* General data: RO fields */
450 dma_addr_t ring_addr;
451 struct pci_dev *pci_dev;
458 /* rx specific fields.
459 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
461 struct ring_desc *rx_ring;
462 unsigned int cur_rx, refill_rx;
463 struct sk_buff *rx_skbuff[RX_RING];
464 dma_addr_t rx_dma[RX_RING];
465 unsigned int rx_buf_sz;
466 struct timer_list oom_kick;
467 struct timer_list nic_poll;
469 /* media detection workaround.
470 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
473 unsigned long link_timeout;
475 * tx specific fields.
477 struct ring_desc *tx_ring;
478 unsigned int next_tx, nic_tx;
479 struct sk_buff *tx_skbuff[TX_RING];
480 dma_addr_t tx_dma[TX_RING];
485 * Maximum number of loops until we assume that a bit in the irq mask
486 * is stuck. Overridable with module param.
488 static int max_interrupt_work = 5;
490 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
492 return netdev_priv(dev);
495 static inline u8 __iomem *get_hwbase(struct net_device *dev)
497 return get_nvpriv(dev)->base;
500 static inline void pci_push(u8 __iomem *base)
502 /* force out pending posted writes */
506 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
508 return le32_to_cpu(prd->FlagLen)
509 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
512 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
513 int delay, int delaymax, const char *msg)
515 u8 __iomem *base = get_hwbase(dev);
526 } while ((readl(base + offset) & mask) != target);
530 #define MII_READ (-1)
531 /* mii_rw: read/write a register on the PHY.
533 * Caller must guarantee serialization
535 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
537 u8 __iomem *base = get_hwbase(dev);
541 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
543 reg = readl(base + NvRegMIIControl);
544 if (reg & NVREG_MIICTL_INUSE) {
545 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
546 udelay(NV_MIIBUSY_DELAY);
549 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
550 if (value != MII_READ) {
551 writel(value, base + NvRegMIIData);
552 reg |= NVREG_MIICTL_WRITE;
554 writel(reg, base + NvRegMIIControl);
556 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
557 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
558 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
559 dev->name, miireg, addr);
561 } else if (value != MII_READ) {
562 /* it was a write operation - fewer failures are detectable */
563 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
564 dev->name, value, miireg, addr);
566 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
567 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
568 dev->name, miireg, addr);
571 retval = readl(base + NvRegMIIData);
572 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
573 dev->name, miireg, addr, retval);
579 static int phy_reset(struct net_device *dev)
581 struct fe_priv *np = get_nvpriv(dev);
583 unsigned int tries = 0;
585 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
586 miicontrol |= BMCR_RESET;
587 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
594 /* must wait till reset is deasserted */
595 while (miicontrol & BMCR_RESET) {
597 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
598 /* FIXME: 100 tries seem excessive */
605 static int phy_init(struct net_device *dev)
607 struct fe_priv *np = get_nvpriv(dev);
608 u8 __iomem *base = get_hwbase(dev);
609 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
611 /* set advertise register */
612 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
613 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
614 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
615 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
619 /* get phy interface type */
620 phyinterface = readl(base + NvRegPhyInterface);
622 /* see if gigabit phy */
623 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
624 if (mii_status & PHY_GIGABIT) {
625 np->gigabit = PHY_GIGABIT;
626 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
627 mii_control_1000 &= ~ADVERTISE_1000HALF;
628 if (phyinterface & PHY_RGMII)
629 mii_control_1000 |= ADVERTISE_1000FULL;
631 mii_control_1000 &= ~ADVERTISE_1000FULL;
633 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
634 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
642 if (phy_reset(dev)) {
643 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
647 /* phy vendor specific configuration */
648 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
649 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
650 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
651 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
652 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
653 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
656 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
657 phy_reserved |= PHY_INIT5;
658 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
659 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
663 if (np->phy_oui == PHY_OUI_CICADA) {
664 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
665 phy_reserved |= PHY_INIT6;
666 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
667 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
672 /* restart auto negotiation */
673 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
674 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
675 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
682 static void nv_start_rx(struct net_device *dev)
684 struct fe_priv *np = get_nvpriv(dev);
685 u8 __iomem *base = get_hwbase(dev);
687 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
688 /* Already running? Stop it. */
689 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
690 writel(0, base + NvRegReceiverControl);
693 writel(np->linkspeed, base + NvRegLinkSpeed);
695 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
696 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
697 dev->name, np->duplex, np->linkspeed);
701 static void nv_stop_rx(struct net_device *dev)
703 u8 __iomem *base = get_hwbase(dev);
705 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
706 writel(0, base + NvRegReceiverControl);
707 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
708 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
709 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
711 udelay(NV_RXSTOP_DELAY2);
712 writel(0, base + NvRegLinkSpeed);
715 static void nv_start_tx(struct net_device *dev)
717 u8 __iomem *base = get_hwbase(dev);
719 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
720 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
724 static void nv_stop_tx(struct net_device *dev)
726 u8 __iomem *base = get_hwbase(dev);
728 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
729 writel(0, base + NvRegTransmitterControl);
730 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
731 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
732 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
734 udelay(NV_TXSTOP_DELAY2);
735 writel(0, base + NvRegUnknownTransmitterReg);
738 static void nv_txrx_reset(struct net_device *dev)
740 struct fe_priv *np = get_nvpriv(dev);
741 u8 __iomem *base = get_hwbase(dev);
743 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
744 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->desc_ver, base + NvRegTxRxControl);
746 udelay(NV_TXRX_RESET_DELAY);
747 writel(NVREG_TXRXCTL_BIT2 | np->desc_ver, base + NvRegTxRxControl);
752 * nv_get_stats: dev->get_stats function
753 * Get latest stats value from the nic.
754 * Called with read_lock(&dev_base_lock) held for read -
755 * only synchronized against unregister_netdevice.
757 static struct net_device_stats *nv_get_stats(struct net_device *dev)
759 struct fe_priv *np = get_nvpriv(dev);
761 /* It seems that the nic always generates interrupts and doesn't
762 * accumulate errors internally. Thus the current values in np->stats
763 * are already up to date.
768 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
770 struct fe_priv *np = get_nvpriv(dev);
771 strcpy(info->driver, "forcedeth");
772 strcpy(info->version, FORCEDETH_VERSION);
773 strcpy(info->bus_info, pci_name(np->pci_dev));
776 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
778 struct fe_priv *np = get_nvpriv(dev);
779 wolinfo->supported = WAKE_MAGIC;
781 spin_lock_irq(&np->lock);
783 wolinfo->wolopts = WAKE_MAGIC;
784 spin_unlock_irq(&np->lock);
787 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
789 struct fe_priv *np = get_nvpriv(dev);
790 u8 __iomem *base = get_hwbase(dev);
792 spin_lock_irq(&np->lock);
793 if (wolinfo->wolopts == 0) {
794 writel(0, base + NvRegWakeUpFlags);
797 if (wolinfo->wolopts & WAKE_MAGIC) {
798 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
801 spin_unlock_irq(&np->lock);
805 static struct ethtool_ops ops = {
806 .get_drvinfo = nv_get_drvinfo,
807 .get_link = ethtool_op_get_link,
808 .get_wol = nv_get_wol,
809 .set_wol = nv_set_wol,
813 * nv_alloc_rx: fill rx ring entries.
814 * Return 1 if the allocations for the skbs failed and the
815 * rx engine is without Available descriptors
817 static int nv_alloc_rx(struct net_device *dev)
819 struct fe_priv *np = get_nvpriv(dev);
820 unsigned int refill_rx = np->refill_rx;
823 while (np->cur_rx != refill_rx) {
826 nr = refill_rx % RX_RING;
827 if (np->rx_skbuff[nr] == NULL) {
829 skb = dev_alloc_skb(RX_ALLOC_BUFSIZE);
834 np->rx_skbuff[nr] = skb;
836 skb = np->rx_skbuff[nr];
838 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
840 np->rx_ring[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
842 np->rx_ring[nr].FlagLen = cpu_to_le32(RX_NIC_BUFSIZE | NV_RX_AVAIL);
843 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
844 dev->name, refill_rx);
847 np->refill_rx = refill_rx;
848 if (np->cur_rx - refill_rx == RX_RING)
853 static void nv_do_rx_refill(unsigned long data)
855 struct net_device *dev = (struct net_device *) data;
856 struct fe_priv *np = get_nvpriv(dev);
858 disable_irq(dev->irq);
859 if (nv_alloc_rx(dev)) {
860 spin_lock(&np->lock);
861 if (!np->in_shutdown)
862 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
863 spin_unlock(&np->lock);
865 enable_irq(dev->irq);
868 static int nv_init_ring(struct net_device *dev)
870 struct fe_priv *np = get_nvpriv(dev);
873 np->next_tx = np->nic_tx = 0;
874 for (i = 0; i < TX_RING; i++)
875 np->tx_ring[i].FlagLen = 0;
877 np->cur_rx = RX_RING;
879 for (i = 0; i < RX_RING; i++)
880 np->rx_ring[i].FlagLen = 0;
881 return nv_alloc_rx(dev);
884 static void nv_drain_tx(struct net_device *dev)
886 struct fe_priv *np = get_nvpriv(dev);
888 for (i = 0; i < TX_RING; i++) {
889 np->tx_ring[i].FlagLen = 0;
890 if (np->tx_skbuff[i]) {
891 pci_unmap_single(np->pci_dev, np->tx_dma[i],
892 np->tx_skbuff[i]->len,
894 dev_kfree_skb(np->tx_skbuff[i]);
895 np->tx_skbuff[i] = NULL;
896 np->stats.tx_dropped++;
901 static void nv_drain_rx(struct net_device *dev)
903 struct fe_priv *np = get_nvpriv(dev);
905 for (i = 0; i < RX_RING; i++) {
906 np->rx_ring[i].FlagLen = 0;
908 if (np->rx_skbuff[i]) {
909 pci_unmap_single(np->pci_dev, np->rx_dma[i],
910 np->rx_skbuff[i]->len,
912 dev_kfree_skb(np->rx_skbuff[i]);
913 np->rx_skbuff[i] = NULL;
918 static void drain_ring(struct net_device *dev)
925 * nv_start_xmit: dev->hard_start_xmit function
926 * Called with dev->xmit_lock held.
928 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
930 struct fe_priv *np = get_nvpriv(dev);
931 int nr = np->next_tx % TX_RING;
933 np->tx_skbuff[nr] = skb;
934 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data,skb->len,
937 np->tx_ring[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
939 spin_lock_irq(&np->lock);
941 np->tx_ring[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags );
942 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission.\n",
943 dev->name, np->next_tx);
946 for (j=0; j<64; j++) {
948 dprintk("\n%03x:", j);
949 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
956 dev->trans_start = jiffies;
957 if (np->next_tx - np->nic_tx >= TX_LIMIT_STOP)
958 netif_stop_queue(dev);
959 spin_unlock_irq(&np->lock);
960 writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl);
961 pci_push(get_hwbase(dev));
966 * nv_tx_done: check for completed packets, release the skbs.
968 * Caller must own np->lock.
970 static void nv_tx_done(struct net_device *dev)
972 struct fe_priv *np = get_nvpriv(dev);
976 while (np->nic_tx != np->next_tx) {
977 i = np->nic_tx % TX_RING;
979 Flags = le32_to_cpu(np->tx_ring[i].FlagLen);
981 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
982 dev->name, np->nic_tx, Flags);
983 if (Flags & NV_TX_VALID)
985 if (np->desc_ver == DESC_VER_1) {
986 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
987 NV_TX_UNDERFLOW|NV_TX_ERROR)) {
988 if (Flags & NV_TX_UNDERFLOW)
989 np->stats.tx_fifo_errors++;
990 if (Flags & NV_TX_CARRIERLOST)
991 np->stats.tx_carrier_errors++;
992 np->stats.tx_errors++;
994 np->stats.tx_packets++;
995 np->stats.tx_bytes += np->tx_skbuff[i]->len;
998 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
999 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1000 if (Flags & NV_TX2_UNDERFLOW)
1001 np->stats.tx_fifo_errors++;
1002 if (Flags & NV_TX2_CARRIERLOST)
1003 np->stats.tx_carrier_errors++;
1004 np->stats.tx_errors++;
1006 np->stats.tx_packets++;
1007 np->stats.tx_bytes += np->tx_skbuff[i]->len;
1010 pci_unmap_single(np->pci_dev, np->tx_dma[i],
1011 np->tx_skbuff[i]->len,
1013 dev_kfree_skb_irq(np->tx_skbuff[i]);
1014 np->tx_skbuff[i] = NULL;
1017 if (np->next_tx - np->nic_tx < TX_LIMIT_START)
1018 netif_wake_queue(dev);
1022 * nv_tx_timeout: dev->tx_timeout function
1023 * Called with dev->xmit_lock held.
1025 static void nv_tx_timeout(struct net_device *dev)
1027 struct fe_priv *np = get_nvpriv(dev);
1028 u8 __iomem *base = get_hwbase(dev);
1030 dprintk(KERN_DEBUG "%s: Got tx_timeout. irq: %08x\n", dev->name,
1031 readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
1033 spin_lock_irq(&np->lock);
1035 /* 1) stop tx engine */
1038 /* 2) check that the packets were not sent already: */
1041 /* 3) if there are dead entries: clear everything */
1042 if (np->next_tx != np->nic_tx) {
1043 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1045 np->next_tx = np->nic_tx = 0;
1046 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1047 netif_wake_queue(dev);
1050 /* 4) restart tx engine */
1052 spin_unlock_irq(&np->lock);
1055 static void nv_rx_process(struct net_device *dev)
1057 struct fe_priv *np = get_nvpriv(dev);
1061 struct sk_buff *skb;
1064 if (np->cur_rx - np->refill_rx >= RX_RING)
1065 break; /* we scanned the whole ring - do not continue */
1067 i = np->cur_rx % RX_RING;
1068 Flags = le32_to_cpu(np->rx_ring[i].FlagLen);
1069 len = nv_descr_getlength(&np->rx_ring[i], np->desc_ver);
1071 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1072 dev->name, np->cur_rx, Flags);
1074 if (Flags & NV_RX_AVAIL)
1075 break; /* still owned by hardware, */
1078 * the packet is for us - immediately tear down the pci mapping.
1079 * TODO: check if a prefetch of the first cacheline improves
1082 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1083 np->rx_skbuff[i]->len,
1084 PCI_DMA_FROMDEVICE);
1088 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1089 for (j=0; j<64; j++) {
1091 dprintk("\n%03x:", j);
1092 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1096 /* look at what we actually got: */
1097 if (np->desc_ver == DESC_VER_1) {
1098 if (!(Flags & NV_RX_DESCRIPTORVALID))
1101 if (Flags & NV_RX_MISSEDFRAME) {
1102 np->stats.rx_missed_errors++;
1103 np->stats.rx_errors++;
1106 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4)) {
1107 np->stats.rx_errors++;
1110 if (Flags & NV_RX_CRCERR) {
1111 np->stats.rx_crc_errors++;
1112 np->stats.rx_errors++;
1115 if (Flags & NV_RX_OVERFLOW) {
1116 np->stats.rx_over_errors++;
1117 np->stats.rx_errors++;
1120 if (Flags & NV_RX_ERROR) {
1121 /* framing errors are soft errors, the rest is fatal. */
1122 if (Flags & NV_RX_FRAMINGERR) {
1123 if (Flags & NV_RX_SUBSTRACT1) {
1127 np->stats.rx_errors++;
1132 if (!(Flags & NV_RX2_DESCRIPTORVALID))
1135 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4)) {
1136 np->stats.rx_errors++;
1139 if (Flags & NV_RX2_CRCERR) {
1140 np->stats.rx_crc_errors++;
1141 np->stats.rx_errors++;
1144 if (Flags & NV_RX2_OVERFLOW) {
1145 np->stats.rx_over_errors++;
1146 np->stats.rx_errors++;
1149 if (Flags & NV_RX2_ERROR) {
1150 /* framing errors are soft errors, the rest is fatal. */
1151 if (Flags & NV_RX2_FRAMINGERR) {
1152 if (Flags & NV_RX2_SUBSTRACT1) {
1156 np->stats.rx_errors++;
1160 Flags &= NV_RX2_CHECKSUMMASK;
1161 if (Flags == NV_RX2_CHECKSUMOK1 ||
1162 Flags == NV_RX2_CHECKSUMOK2 ||
1163 Flags == NV_RX2_CHECKSUMOK3) {
1164 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1165 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1167 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1170 /* got a valid packet - forward it to the network core */
1171 skb = np->rx_skbuff[i];
1172 np->rx_skbuff[i] = NULL;
1175 skb->protocol = eth_type_trans(skb, dev);
1176 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1177 dev->name, np->cur_rx, len, skb->protocol);
1179 dev->last_rx = jiffies;
1180 np->stats.rx_packets++;
1181 np->stats.rx_bytes += len;
1188 * nv_change_mtu: dev->change_mtu function
1189 * Called with dev_base_lock held for read.
1191 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1193 if (new_mtu > ETH_DATA_LEN)
1200 * nv_set_multicast: dev->set_multicast function
1201 * Called with dev->xmit_lock held.
1203 static void nv_set_multicast(struct net_device *dev)
1205 struct fe_priv *np = get_nvpriv(dev);
1206 u8 __iomem *base = get_hwbase(dev);
1211 memset(addr, 0, sizeof(addr));
1212 memset(mask, 0, sizeof(mask));
1214 if (dev->flags & IFF_PROMISC) {
1215 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1216 pff = NVREG_PFF_PROMISC;
1218 pff = NVREG_PFF_MYADDR;
1220 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1224 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1225 if (dev->flags & IFF_ALLMULTI) {
1226 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1228 struct dev_mc_list *walk;
1230 walk = dev->mc_list;
1231 while (walk != NULL) {
1233 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1234 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1242 addr[0] = alwaysOn[0];
1243 addr[1] = alwaysOn[1];
1244 mask[0] = alwaysOn[0] | alwaysOff[0];
1245 mask[1] = alwaysOn[1] | alwaysOff[1];
1248 addr[0] |= NVREG_MCASTADDRA_FORCE;
1249 pff |= NVREG_PFF_ALWAYS;
1250 spin_lock_irq(&np->lock);
1252 writel(addr[0], base + NvRegMulticastAddrA);
1253 writel(addr[1], base + NvRegMulticastAddrB);
1254 writel(mask[0], base + NvRegMulticastMaskA);
1255 writel(mask[1], base + NvRegMulticastMaskB);
1256 writel(pff, base + NvRegPacketFilterFlags);
1257 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1260 spin_unlock_irq(&np->lock);
1263 static int nv_update_linkspeed(struct net_device *dev)
1265 struct fe_priv *np = get_nvpriv(dev);
1266 u8 __iomem *base = get_hwbase(dev);
1268 int newls = np->linkspeed;
1269 int newdup = np->duplex;
1272 u32 control_1000, status_1000, phyreg;
1274 /* BMSR_LSTATUS is latched, read it twice:
1275 * we want the current value.
1277 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1278 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1280 if (!(mii_status & BMSR_LSTATUS)) {
1281 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1283 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1289 /* check auto negotiation is complete */
1290 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1291 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1292 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1295 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1300 if (np->gigabit == PHY_GIGABIT) {
1301 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1302 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1304 if ((control_1000 & ADVERTISE_1000FULL) &&
1305 (status_1000 & LPA_1000FULL)) {
1306 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1308 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1314 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1315 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1316 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1317 dev->name, adv, lpa);
1319 /* FIXME: handle parallel detection properly */
1321 if (lpa & LPA_100FULL) {
1322 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1324 } else if (lpa & LPA_100HALF) {
1325 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1327 } else if (lpa & LPA_10FULL) {
1328 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1330 } else if (lpa & LPA_10HALF) {
1331 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1334 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1335 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1340 if (np->duplex == newdup && np->linkspeed == newls)
1343 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1344 dev->name, np->linkspeed, np->duplex, newls, newdup);
1346 np->duplex = newdup;
1347 np->linkspeed = newls;
1349 if (np->gigabit == PHY_GIGABIT) {
1350 phyreg = readl(base + NvRegRandomSeed);
1351 phyreg &= ~(0x3FF00);
1352 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1353 phyreg |= NVREG_RNDSEED_FORCE3;
1354 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1355 phyreg |= NVREG_RNDSEED_FORCE2;
1356 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1357 phyreg |= NVREG_RNDSEED_FORCE;
1358 writel(phyreg, base + NvRegRandomSeed);
1361 phyreg = readl(base + NvRegPhyInterface);
1362 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1363 if (np->duplex == 0)
1365 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1367 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1369 writel(phyreg, base + NvRegPhyInterface);
1371 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1374 writel(np->linkspeed, base + NvRegLinkSpeed);
1380 static void nv_linkchange(struct net_device *dev)
1382 if (nv_update_linkspeed(dev)) {
1383 if (netif_carrier_ok(dev)) {
1386 netif_carrier_on(dev);
1387 printk(KERN_INFO "%s: link up.\n", dev->name);
1391 if (netif_carrier_ok(dev)) {
1392 netif_carrier_off(dev);
1393 printk(KERN_INFO "%s: link down.\n", dev->name);
1399 static void nv_link_irq(struct net_device *dev)
1401 u8 __iomem *base = get_hwbase(dev);
1404 miistat = readl(base + NvRegMIIStatus);
1405 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1406 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
1408 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
1410 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1413 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1415 struct net_device *dev = (struct net_device *) data;
1416 struct fe_priv *np = get_nvpriv(dev);
1417 u8 __iomem *base = get_hwbase(dev);
1421 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1424 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1425 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1427 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1428 if (!(events & np->irqmask))
1431 if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX2|NVREG_IRQ_TX_ERR)) {
1432 spin_lock(&np->lock);
1434 spin_unlock(&np->lock);
1437 if (events & (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF)) {
1439 if (nv_alloc_rx(dev)) {
1440 spin_lock(&np->lock);
1441 if (!np->in_shutdown)
1442 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1443 spin_unlock(&np->lock);
1447 if (events & NVREG_IRQ_LINK) {
1448 spin_lock(&np->lock);
1450 spin_unlock(&np->lock);
1452 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
1453 spin_lock(&np->lock);
1455 spin_unlock(&np->lock);
1456 np->link_timeout = jiffies + LINK_TIMEOUT;
1458 if (events & (NVREG_IRQ_TX_ERR)) {
1459 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1462 if (events & (NVREG_IRQ_UNKNOWN)) {
1463 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1466 if (i > max_interrupt_work) {
1467 spin_lock(&np->lock);
1468 /* disable interrupts on the nic */
1469 writel(0, base + NvRegIrqMask);
1472 if (!np->in_shutdown)
1473 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1474 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1475 spin_unlock(&np->lock);
1480 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1482 return IRQ_RETVAL(i);
1485 static void nv_do_nic_poll(unsigned long data)
1487 struct net_device *dev = (struct net_device *) data;
1488 struct fe_priv *np = get_nvpriv(dev);
1489 u8 __iomem *base = get_hwbase(dev);
1491 disable_irq(dev->irq);
1492 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1494 * reenable interrupts on the nic, we have to do this before calling
1495 * nv_nic_irq because that may decide to do otherwise
1497 writel(np->irqmask, base + NvRegIrqMask);
1499 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1500 enable_irq(dev->irq);
1503 static int nv_open(struct net_device *dev)
1505 struct fe_priv *np = get_nvpriv(dev);
1506 u8 __iomem *base = get_hwbase(dev);
1509 dprintk(KERN_DEBUG "nv_open: begin\n");
1511 /* 1) erase previous misconfiguration */
1512 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
1513 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1514 writel(0, base + NvRegMulticastAddrB);
1515 writel(0, base + NvRegMulticastMaskA);
1516 writel(0, base + NvRegMulticastMaskB);
1517 writel(0, base + NvRegPacketFilterFlags);
1519 writel(0, base + NvRegTransmitterControl);
1520 writel(0, base + NvRegReceiverControl);
1522 writel(0, base + NvRegAdapterControl);
1524 /* 2) initialize descriptor rings */
1525 oom = nv_init_ring(dev);
1527 writel(0, base + NvRegLinkSpeed);
1528 writel(0, base + NvRegUnknownTransmitterReg);
1530 writel(0, base + NvRegUnknownSetupReg6);
1532 np->in_shutdown = 0;
1534 /* 3) set mac address */
1538 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1539 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1540 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1542 writel(mac[0], base + NvRegMacAddrA);
1543 writel(mac[1], base + NvRegMacAddrB);
1546 /* 4) give hw rings */
1547 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1548 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1549 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1550 base + NvRegRingSizes);
1552 /* 5) continue setup */
1553 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1556 writel(np->linkspeed, base + NvRegLinkSpeed);
1557 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
1558 writel(np->desc_ver, base + NvRegTxRxControl);
1560 writel(NVREG_TXRXCTL_BIT1|np->desc_ver, base + NvRegTxRxControl);
1561 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
1562 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
1563 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
1565 writel(0, base + NvRegUnknownSetupReg4);
1566 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1567 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1569 /* 6) continue setup */
1570 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
1571 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
1572 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
1573 writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig);
1575 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
1576 get_random_bytes(&i, sizeof(i));
1577 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
1578 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
1579 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
1580 writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
1581 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
1582 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
1583 base + NvRegAdapterControl);
1584 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
1585 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
1586 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
1588 i = readl(base + NvRegPowerState);
1589 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
1590 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
1594 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
1596 writel(0, base + NvRegIrqMask);
1598 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1599 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1602 ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
1606 /* ask for interrupts */
1607 writel(np->irqmask, base + NvRegIrqMask);
1609 spin_lock_irq(&np->lock);
1610 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1611 writel(0, base + NvRegMulticastAddrB);
1612 writel(0, base + NvRegMulticastMaskA);
1613 writel(0, base + NvRegMulticastMaskB);
1614 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
1615 /* One manual link speed update: Interrupts are enabled, future link
1616 * speed changes cause interrupts and are handled by nv_link_irq().
1620 miistat = readl(base + NvRegMIIStatus);
1621 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1622 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
1624 ret = nv_update_linkspeed(dev);
1627 netif_start_queue(dev);
1629 netif_carrier_on(dev);
1631 printk("%s: no link during initialization.\n", dev->name);
1632 netif_carrier_off(dev);
1635 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1636 spin_unlock_irq(&np->lock);
1644 static int nv_close(struct net_device *dev)
1646 struct fe_priv *np = get_nvpriv(dev);
1649 spin_lock_irq(&np->lock);
1650 np->in_shutdown = 1;
1651 spin_unlock_irq(&np->lock);
1652 synchronize_irq(dev->irq);
1654 del_timer_sync(&np->oom_kick);
1655 del_timer_sync(&np->nic_poll);
1657 netif_stop_queue(dev);
1658 spin_lock_irq(&np->lock);
1663 /* disable interrupts on the nic or we will lock up */
1664 base = get_hwbase(dev);
1665 writel(0, base + NvRegIrqMask);
1667 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
1669 spin_unlock_irq(&np->lock);
1671 free_irq(dev->irq, dev);
1678 /* FIXME: power down nic */
1683 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
1685 struct net_device *dev;
1691 dev = alloc_etherdev(sizeof(struct fe_priv));
1696 np = get_nvpriv(dev);
1697 np->pci_dev = pci_dev;
1698 spin_lock_init(&np->lock);
1699 SET_MODULE_OWNER(dev);
1700 SET_NETDEV_DEV(dev, &pci_dev->dev);
1702 init_timer(&np->oom_kick);
1703 np->oom_kick.data = (unsigned long) dev;
1704 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
1705 init_timer(&np->nic_poll);
1706 np->nic_poll.data = (unsigned long) dev;
1707 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
1709 err = pci_enable_device(pci_dev);
1711 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
1712 err, pci_name(pci_dev));
1716 pci_set_master(pci_dev);
1718 err = pci_request_regions(pci_dev, DRV_NAME);
1724 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1725 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
1726 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
1727 pci_resource_len(pci_dev, i),
1728 pci_resource_flags(pci_dev, i));
1729 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
1730 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
1731 addr = pci_resource_start(pci_dev, i);
1735 if (i == DEVICE_COUNT_RESOURCE) {
1736 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
1741 /* handle different descriptor versions */
1742 if (pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_1 ||
1743 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_2 ||
1744 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_3)
1745 np->desc_ver = DESC_VER_1;
1747 np->desc_ver = DESC_VER_2;
1750 np->base = ioremap(addr, NV_PCI_REGSZ);
1753 dev->base_addr = (unsigned long)np->base;
1754 dev->irq = pci_dev->irq;
1755 np->rx_ring = pci_alloc_consistent(pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
1759 np->tx_ring = &np->rx_ring[RX_RING];
1761 dev->open = nv_open;
1762 dev->stop = nv_close;
1763 dev->hard_start_xmit = nv_start_xmit;
1764 dev->get_stats = nv_get_stats;
1765 dev->change_mtu = nv_change_mtu;
1766 dev->set_multicast_list = nv_set_multicast;
1767 SET_ETHTOOL_OPS(dev, &ops);
1768 dev->tx_timeout = nv_tx_timeout;
1769 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
1771 pci_set_drvdata(pci_dev, dev);
1773 /* read the mac address */
1774 base = get_hwbase(dev);
1775 np->orig_mac[0] = readl(base + NvRegMacAddrA);
1776 np->orig_mac[1] = readl(base + NvRegMacAddrB);
1778 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
1779 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
1780 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
1781 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
1782 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
1783 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
1785 if (!is_valid_ether_addr(dev->dev_addr)) {
1787 * Bad mac address. At least one bios sets the mac address
1788 * to 01:23:45:67:89:ab
1790 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
1792 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1793 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1794 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
1795 dev->dev_addr[0] = 0x00;
1796 dev->dev_addr[1] = 0x00;
1797 dev->dev_addr[2] = 0x6c;
1798 get_random_bytes(&dev->dev_addr[3], 3);
1801 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
1802 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1803 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1806 writel(0, base + NvRegWakeUpFlags);
1809 if (np->desc_ver == DESC_VER_1) {
1810 np->tx_flags = NV_TX_LASTPACKET|NV_TX_VALID;
1811 if (id->driver_data & DEV_NEED_LASTPACKET1)
1812 np->tx_flags |= NV_TX_LASTPACKET1;
1814 np->tx_flags = NV_TX2_LASTPACKET|NV_TX2_VALID;
1815 if (id->driver_data & DEV_NEED_LASTPACKET1)
1816 np->tx_flags |= NV_TX2_LASTPACKET1;
1818 if (id->driver_data & DEV_IRQMASK_1)
1819 np->irqmask = NVREG_IRQMASK_WANTED_1;
1820 if (id->driver_data & DEV_IRQMASK_2)
1821 np->irqmask = NVREG_IRQMASK_WANTED_2;
1822 if (id->driver_data & DEV_NEED_TIMERIRQ)
1823 np->irqmask |= NVREG_IRQ_TIMER;
1824 if (id->driver_data & DEV_NEED_LINKTIMER) {
1825 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
1826 np->need_linktimer = 1;
1827 np->link_timeout = jiffies + LINK_TIMEOUT;
1829 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
1830 np->need_linktimer = 0;
1833 /* find a suitable phy */
1834 for (i = 1; i < 32; i++) {
1837 spin_lock_irq(&np->lock);
1838 id1 = mii_rw(dev, i, MII_PHYSID1, MII_READ);
1839 spin_unlock_irq(&np->lock);
1840 if (id1 < 0 || id1 == 0xffff)
1842 spin_lock_irq(&np->lock);
1843 id2 = mii_rw(dev, i, MII_PHYSID2, MII_READ);
1844 spin_unlock_irq(&np->lock);
1845 if (id2 < 0 || id2 == 0xffff)
1848 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
1849 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
1850 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
1851 pci_name(pci_dev), id1, id2, i);
1853 np->phy_oui = id1 | id2;
1857 /* PHY in isolate mode? No phy attached and user wants to
1858 * test loopback? Very odd, but can be correct.
1860 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
1869 err = register_netdev(dev);
1871 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
1874 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
1875 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
1881 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
1882 np->rx_ring, np->ring_addr);
1883 pci_set_drvdata(pci_dev, NULL);
1885 iounmap(get_hwbase(dev));
1887 pci_release_regions(pci_dev);
1889 pci_disable_device(pci_dev);
1896 static void __devexit nv_remove(struct pci_dev *pci_dev)
1898 struct net_device *dev = pci_get_drvdata(pci_dev);
1899 struct fe_priv *np = get_nvpriv(dev);
1900 u8 __iomem *base = get_hwbase(dev);
1902 unregister_netdev(dev);
1904 /* special op: write back the misordered MAC address - otherwise
1905 * the next nv_probe would see a wrong address.
1907 writel(np->orig_mac[0], base + NvRegMacAddrA);
1908 writel(np->orig_mac[1], base + NvRegMacAddrB);
1910 /* free all structures */
1911 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring, np->ring_addr);
1912 iounmap(get_hwbase(dev));
1913 pci_release_regions(pci_dev);
1914 pci_disable_device(pci_dev);
1916 pci_set_drvdata(pci_dev, NULL);
1919 static struct pci_device_id pci_tbl[] = {
1920 { /* nForce Ethernet Controller */
1921 .vendor = PCI_VENDOR_ID_NVIDIA,
1922 .device = PCI_DEVICE_ID_NVIDIA_NVENET_1,
1923 .subvendor = PCI_ANY_ID,
1924 .subdevice = PCI_ANY_ID,
1925 .driver_data = DEV_IRQMASK_1|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
1927 { /* nForce2 Ethernet Controller */
1928 .vendor = PCI_VENDOR_ID_NVIDIA,
1929 .device = PCI_DEVICE_ID_NVIDIA_NVENET_2,
1930 .subvendor = PCI_ANY_ID,
1931 .subdevice = PCI_ANY_ID,
1932 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
1934 { /* nForce3 Ethernet Controller */
1935 .vendor = PCI_VENDOR_ID_NVIDIA,
1936 .device = PCI_DEVICE_ID_NVIDIA_NVENET_3,
1937 .subvendor = PCI_ANY_ID,
1938 .subdevice = PCI_ANY_ID,
1939 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
1941 { /* nForce3 Ethernet Controller */
1942 .vendor = PCI_VENDOR_ID_NVIDIA,
1943 .device = PCI_DEVICE_ID_NVIDIA_NVENET_4,
1944 .subvendor = PCI_ANY_ID,
1945 .subdevice = PCI_ANY_ID,
1946 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1948 { /* nForce3 Ethernet Controller */
1949 .vendor = PCI_VENDOR_ID_NVIDIA,
1950 .device = PCI_DEVICE_ID_NVIDIA_NVENET_5,
1951 .subvendor = PCI_ANY_ID,
1952 .subdevice = PCI_ANY_ID,
1953 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1955 { /* nForce3 Ethernet Controller */
1956 .vendor = PCI_VENDOR_ID_NVIDIA,
1957 .device = PCI_DEVICE_ID_NVIDIA_NVENET_6,
1958 .subvendor = PCI_ANY_ID,
1959 .subdevice = PCI_ANY_ID,
1960 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1962 { /* nForce3 Ethernet Controller */
1963 .vendor = PCI_VENDOR_ID_NVIDIA,
1964 .device = PCI_DEVICE_ID_NVIDIA_NVENET_7,
1965 .subvendor = PCI_ANY_ID,
1966 .subdevice = PCI_ANY_ID,
1967 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1969 { /* CK804 Ethernet Controller */
1970 .vendor = PCI_VENDOR_ID_NVIDIA,
1971 .device = PCI_DEVICE_ID_NVIDIA_NVENET_8,
1972 .subvendor = PCI_ANY_ID,
1973 .subdevice = PCI_ANY_ID,
1974 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1976 { /* CK804 Ethernet Controller */
1977 .vendor = PCI_VENDOR_ID_NVIDIA,
1978 .device = PCI_DEVICE_ID_NVIDIA_NVENET_9,
1979 .subvendor = PCI_ANY_ID,
1980 .subdevice = PCI_ANY_ID,
1981 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1983 { /* MCP04 Ethernet Controller */
1984 .vendor = PCI_VENDOR_ID_NVIDIA,
1985 .device = PCI_DEVICE_ID_NVIDIA_NVENET_10,
1986 .subvendor = PCI_ANY_ID,
1987 .subdevice = PCI_ANY_ID,
1988 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1990 { /* MCP04 Ethernet Controller */
1991 .vendor = PCI_VENDOR_ID_NVIDIA,
1992 .device = PCI_DEVICE_ID_NVIDIA_NVENET_11,
1993 .subvendor = PCI_ANY_ID,
1994 .subdevice = PCI_ANY_ID,
1995 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
2000 static struct pci_driver driver = {
2001 .name = "forcedeth",
2002 .id_table = pci_tbl,
2004 .remove = __devexit_p(nv_remove),
2008 static int __init init_nic(void)
2010 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
2011 return pci_module_init(&driver);
2014 static void __exit exit_nic(void)
2016 pci_unregister_driver(&driver);
2019 module_param(max_interrupt_work, int, 0);
2020 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2022 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2023 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2024 MODULE_LICENSE("GPL");
2026 MODULE_DEVICE_TABLE(pci, pci_tbl);
2028 module_init(init_nic);
2029 module_exit(exit_nic);