drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey. It's neither supported nor endorsed
   7  *      by NVIDIA Corp. Use at your own risk.
   8  *
   9  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  10  * trademarks of NVIDIA Corporation in the United States and other
  11  * countries.
  12  *
  13  * Copyright (C) 2003,4,5 Manfred Spraul
  14  * Copyright (C) 2004 Andrew de Quincey (wol support)
  15  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  16  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  17  * Copyright (c) 2004 NVIDIA Corporation
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  32  *
  33  * Changelog:
  34  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  35  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  36  *                         Check all PCI BARs for the register window.
  37  *                         udelay added to mii_rw.
  38  *      0.03: 06 Oct 2003: Initialize dev->irq.
  39  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  40  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  41  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  42  *                         irq mask updated
  43  *      0.07: 14 Oct 2003: Further irq mask updates.
  44  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  45  *                         added into irq handler, NULL check for drain_ring.
  46  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  47  *                         requested interrupt sources.
  48  *      0.10: 20 Oct 2003: First cleanup for release.
  49  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  50  *                         MAC Address init fix, set_multicast cleanup.
  51  *      0.12: 23 Oct 2003: Cleanups for release.
  52  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  53  *                         Set link speed correctly. start rx before starting
  54  *                         tx (nv_start_rx sets the link speed).
  55  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  56  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  57  *                         open.
  58  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  59  *                         increased to 1628 bytes.
  60  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  61  *                         the tx length.
  62  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  63  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  64  *                         addresses, really stop rx if already running
  65  *                         in nv_start_rx, clean up a bit.
  66  *      0.20: 07 Dec 2003: alloc fixes
  67  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  68  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  69  *                         on close.
  70  *      0.23: 26 Jan 2004: various small cleanups
  71  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  72  *      0.25: 09 Mar 2004: wol support
  73  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  74  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  75  *                         added CK804/MCP04 device IDs, code fixes
  76  *                         for registers, link status and other minor fixes.
  77  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  78  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  79  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  80  *                         into nv_close, otherwise reenabling for wol can
  81  *                         cause DMA to kfree'd memory.
  82  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  83  *                         capabilities.
  84  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  85  *      0.33: 16 May 2005: Support for MCP51 added.
  86  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  87  *      0.35: 26 Jun 2005: Support for MCP55 added.
  88  *      0.36: 28 Jun 2005: Add jumbo frame support.
  89  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  90  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  91  *                         per-packet flags.
  92  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  93  *      0.40: 19 Jul 2005: Add support for mac address change.
  94  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  95  *                         of nv_remove
  96  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  97  *                         in the second (and later) nv_open call
  98  *      0.43: 10 Aug 2005: Add support for tx checksum.
  99  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
 100  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 101  *      0.46: 20 Oct 2005: Add irq optimization modes.
 102  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 103  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 104  *      0.49: 10 Dec 2005: Fix tso for large buffers.
 105  *
 106  * Known bugs:
 107  * We suspect that on some hardware no TX done interrupts are generated.
 108  * This means recovery from netif_stop_queue only happens if the hw timer
 109  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 110  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 111  * If your hardware reliably generates tx done interrupts, then you can remove
 112  * DEV_NEED_TIMERIRQ from the driver_data flags.
 113  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 114  * superfluous timer interrupts from the nic.
 115  */
 116 #define FORCEDETH_VERSION               "0.49"
 117 #define DRV_NAME                        "forcedeth"
 118
 119 #include <linux/module.h>
 120 #include <linux/types.h>
 121 #include <linux/pci.h>
 122 #include <linux/interrupt.h>
 123 #include <linux/netdevice.h>
 124 #include <linux/etherdevice.h>
 125 #include <linux/delay.h>
 126 #include <linux/spinlock.h>
 127 #include <linux/ethtool.h>
 128 #include <linux/timer.h>
 129 #include <linux/skbuff.h>
 130 #include <linux/mii.h>
 131 #include <linux/random.h>
 132 #include <linux/init.h>
 133 #include <linux/if_vlan.h>
 134
 135 #include <asm/irq.h>
 136 #include <asm/io.h>
 137 #include <asm/uaccess.h>
 138 #include <asm/system.h>
 139
 140 #if 0
 141 #define dprintk                 printk
 142 #else
 143 #define dprintk(x...)           do { } while (0)
 144 #endif
 145
 146
 147 /*
 148  * Hardware access:
 149  */
 150
 151 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 152 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 153 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 154 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 155 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 156
 157 enum {
 158         NvRegIrqStatus = 0x000,
 159 #define NVREG_IRQSTAT_MIIEVENT  0x040
 160 #define NVREG_IRQSTAT_MASK              0x1ff
 161         NvRegIrqMask = 0x004,
 162 #define NVREG_IRQ_RX_ERROR              0x0001
 163 #define NVREG_IRQ_RX                    0x0002
 164 #define NVREG_IRQ_RX_NOBUF              0x0004
 165 #define NVREG_IRQ_TX_ERR                0x0008
 166 #define NVREG_IRQ_TX_OK                 0x0010
 167 #define NVREG_IRQ_TIMER                 0x0020
 168 #define NVREG_IRQ_LINK                  0x0040
 169 #define NVREG_IRQ_TX_ERROR              0x0080
 170 #define NVREG_IRQ_TX1                   0x0100
 171 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 172 #define NVREG_IRQMASK_CPU               0x0040
 173
 174 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 175                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX_ERROR| \
 176                                         NVREG_IRQ_TX1))
 177
 178         NvRegUnknownSetupReg6 = 0x008,
 179 #define NVREG_UNKSETUP6_VAL             3
 180
 181 /*
 182  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 183  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 184  */
 185         NvRegPollingInterval = 0x00c,
 186 #define NVREG_POLL_DEFAULT_THROUGHPUT   970
 187 #define NVREG_POLL_DEFAULT_CPU  13
 188         NvRegMisc1 = 0x080,
 189 #define NVREG_MISC1_HD          0x02
 190 #define NVREG_MISC1_FORCE       0x3b0f3c
 191
 192         NvRegTransmitterControl = 0x084,
 193 #define NVREG_XMITCTL_START     0x01
 194         NvRegTransmitterStatus = 0x088,
 195 #define NVREG_XMITSTAT_BUSY     0x01
 196
 197         NvRegPacketFilterFlags = 0x8c,
 198 #define NVREG_PFF_ALWAYS        0x7F0008
 199 #define NVREG_PFF_PROMISC       0x80
 200 #define NVREG_PFF_MYADDR        0x20
 201
 202         NvRegOffloadConfig = 0x90,
 203 #define NVREG_OFFLOAD_HOMEPHY   0x601
 204 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 205         NvRegReceiverControl = 0x094,
 206 #define NVREG_RCVCTL_START      0x01
 207         NvRegReceiverStatus = 0x98,
 208 #define NVREG_RCVSTAT_BUSY      0x01
 209
 210         NvRegRandomSeed = 0x9c,
 211 #define NVREG_RNDSEED_MASK      0x00ff
 212 #define NVREG_RNDSEED_FORCE     0x7f00
 213 #define NVREG_RNDSEED_FORCE2    0x2d00
 214 #define NVREG_RNDSEED_FORCE3    0x7400
 215
 216         NvRegUnknownSetupReg1 = 0xA0,
 217 #define NVREG_UNKSETUP1_VAL     0x16070f
 218         NvRegUnknownSetupReg2 = 0xA4,
 219 #define NVREG_UNKSETUP2_VAL     0x16
 220         NvRegMacAddrA = 0xA8,
 221         NvRegMacAddrB = 0xAC,
 222         NvRegMulticastAddrA = 0xB0,
 223 #define NVREG_MCASTADDRA_FORCE  0x01
 224         NvRegMulticastAddrB = 0xB4,
 225         NvRegMulticastMaskA = 0xB8,
 226         NvRegMulticastMaskB = 0xBC,
 227
 228         NvRegPhyInterface = 0xC0,
 229 #define PHY_RGMII               0x10000000
 230
 231         NvRegTxRingPhysAddr = 0x100,
 232         NvRegRxRingPhysAddr = 0x104,
 233         NvRegRingSizes = 0x108,
 234 #define NVREG_RINGSZ_TXSHIFT 0
 235 #define NVREG_RINGSZ_RXSHIFT 16
 236         NvRegUnknownTransmitterReg = 0x10c,
 237         NvRegLinkSpeed = 0x110,
 238 #define NVREG_LINKSPEED_FORCE 0x10000
 239 #define NVREG_LINKSPEED_10      1000
 240 #define NVREG_LINKSPEED_100     100
 241 #define NVREG_LINKSPEED_1000    50
 242 #define NVREG_LINKSPEED_MASK    (0xFFF)
 243         NvRegUnknownSetupReg5 = 0x130,
 244 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 245         NvRegUnknownSetupReg3 = 0x13c,
 246 #define NVREG_UNKSETUP3_VAL1    0x200010
 247         NvRegTxRxControl = 0x144,
 248 #define NVREG_TXRXCTL_KICK      0x0001
 249 #define NVREG_TXRXCTL_BIT1      0x0002
 250 #define NVREG_TXRXCTL_BIT2      0x0004
 251 #define NVREG_TXRXCTL_IDLE      0x0008
 252 #define NVREG_TXRXCTL_RESET     0x0010
 253 #define NVREG_TXRXCTL_RXCHECK   0x0400
 254 #define NVREG_TXRXCTL_DESC_1    0
 255 #define NVREG_TXRXCTL_DESC_2    0x02100
 256 #define NVREG_TXRXCTL_DESC_3    0x02200
 257         NvRegMIIStatus = 0x180,
 258 #define NVREG_MIISTAT_ERROR             0x0001
 259 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 260 #define NVREG_MIISTAT_MASK              0x000f
 261 #define NVREG_MIISTAT_MASK2             0x000f
 262         NvRegUnknownSetupReg4 = 0x184,
 263 #define NVREG_UNKSETUP4_VAL     8
 264
 265         NvRegAdapterControl = 0x188,
 266 #define NVREG_ADAPTCTL_START    0x02
 267 #define NVREG_ADAPTCTL_LINKUP   0x04
 268 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 269 #define NVREG_ADAPTCTL_RUNNING  0x100000
 270 #define NVREG_ADAPTCTL_PHYSHIFT 24
 271         NvRegMIISpeed = 0x18c,
 272 #define NVREG_MIISPEED_BIT8     (1<<8)
 273 #define NVREG_MIIDELAY  5
 274         NvRegMIIControl = 0x190,
 275 #define NVREG_MIICTL_INUSE      0x08000
 276 #define NVREG_MIICTL_WRITE      0x00400
 277 #define NVREG_MIICTL_ADDRSHIFT  5
 278         NvRegMIIData = 0x194,
 279         NvRegWakeUpFlags = 0x200,
 280 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 281 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 282 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 283 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 284 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 285 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 286 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 287 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 288 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 289 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 290 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 291
 292         NvRegPatternCRC = 0x204,
 293         NvRegPatternMask = 0x208,
 294         NvRegPowerCap = 0x268,
 295 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 296 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 297 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 298         NvRegPowerState = 0x26c,
 299 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 300 #define NVREG_POWERSTATE_VALID          0x0100
 301 #define NVREG_POWERSTATE_MASK           0x0003
 302 #define NVREG_POWERSTATE_D0             0x0000
 303 #define NVREG_POWERSTATE_D1             0x0001
 304 #define NVREG_POWERSTATE_D2             0x0002
 305 #define NVREG_POWERSTATE_D3             0x0003
 306 };
 307
 308 /* Big endian: should work, but is untested */
 309 struct ring_desc {
 310         u32 PacketBuffer;
 311         u32 FlagLen;
 312 };
 313
 314 struct ring_desc_ex {
 315         u32 PacketBufferHigh;
 316         u32 PacketBufferLow;
 317         u32 Reserved;
 318         u32 FlagLen;
 319 };
 320
 321 typedef union _ring_type {
 322         struct ring_desc* orig;
 323         struct ring_desc_ex* ex;
 324 } ring_type;
 325
 326 #define FLAG_MASK_V1 0xffff0000
 327 #define FLAG_MASK_V2 0xffffc000
 328 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 329 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 330
 331 #define NV_TX_LASTPACKET        (1<<16)
 332 #define NV_TX_RETRYERROR        (1<<19)
 333 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 334 #define NV_TX_DEFERRED          (1<<26)
 335 #define NV_TX_CARRIERLOST       (1<<27)
 336 #define NV_TX_LATECOLLISION     (1<<28)
 337 #define NV_TX_UNDERFLOW         (1<<29)
 338 #define NV_TX_ERROR             (1<<30)
 339 #define NV_TX_VALID             (1<<31)
 340
 341 #define NV_TX2_LASTPACKET       (1<<29)
 342 #define NV_TX2_RETRYERROR       (1<<18)
 343 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 344 #define NV_TX2_DEFERRED         (1<<25)
 345 #define NV_TX2_CARRIERLOST      (1<<26)
 346 #define NV_TX2_LATECOLLISION    (1<<27)
 347 #define NV_TX2_UNDERFLOW        (1<<28)
 348 /* error and valid are the same for both */
 349 #define NV_TX2_ERROR            (1<<30)
 350 #define NV_TX2_VALID            (1<<31)
 351 #define NV_TX2_TSO              (1<<28)
 352 #define NV_TX2_TSO_SHIFT        14
 353 #define NV_TX2_TSO_MAX_SHIFT    14
 354 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 355 #define NV_TX2_CHECKSUM_L3      (1<<27)
 356 #define NV_TX2_CHECKSUM_L4      (1<<26)
 357
 358 #define NV_RX_DESCRIPTORVALID   (1<<16)
 359 #define NV_RX_MISSEDFRAME       (1<<17)
 360 #define NV_RX_SUBSTRACT1        (1<<18)
 361 #define NV_RX_ERROR1            (1<<23)
 362 #define NV_RX_ERROR2            (1<<24)
 363 #define NV_RX_ERROR3            (1<<25)
 364 #define NV_RX_ERROR4            (1<<26)
 365 #define NV_RX_CRCERR            (1<<27)
 366 #define NV_RX_OVERFLOW          (1<<28)
 367 #define NV_RX_FRAMINGERR        (1<<29)
 368 #define NV_RX_ERROR             (1<<30)
 369 #define NV_RX_AVAIL             (1<<31)
 370
 371 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 372 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 373 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 374 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 375 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 376 #define NV_RX2_SUBSTRACT1       (1<<25)
 377 #define NV_RX2_ERROR1           (1<<18)
 378 #define NV_RX2_ERROR2           (1<<19)
 379 #define NV_RX2_ERROR3           (1<<20)
 380 #define NV_RX2_ERROR4           (1<<21)
 381 #define NV_RX2_CRCERR           (1<<22)
 382 #define NV_RX2_OVERFLOW         (1<<23)
 383 #define NV_RX2_FRAMINGERR       (1<<24)
 384 /* error and avail are the same for both */
 385 #define NV_RX2_ERROR            (1<<30)
 386 #define NV_RX2_AVAIL            (1<<31)
 387
 388 /* Miscelaneous hardware related defines: */
 389 #define NV_PCI_REGSZ            0x270
 390
 391 /* various timeout delays: all in usec */
 392 #define NV_TXRX_RESET_DELAY     4
 393 #define NV_TXSTOP_DELAY1        10
 394 #define NV_TXSTOP_DELAY1MAX     500000
 395 #define NV_TXSTOP_DELAY2        100
 396 #define NV_RXSTOP_DELAY1        10
 397 #define NV_RXSTOP_DELAY1MAX     500000
 398 #define NV_RXSTOP_DELAY2        100
 399 #define NV_SETUP5_DELAY         5
 400 #define NV_SETUP5_DELAYMAX      50000
 401 #define NV_POWERUP_DELAY        5
 402 #define NV_POWERUP_DELAYMAX     5000
 403 #define NV_MIIBUSY_DELAY        50
 404 #define NV_MIIPHY_DELAY 10
 405 #define NV_MIIPHY_DELAYMAX      10000
 406
 407 #define NV_WAKEUPPATTERNS       5
 408 #define NV_WAKEUPMASKENTRIES    4
 409
 410 /* General driver defaults */
 411 #define NV_WATCHDOG_TIMEO       (5*HZ)
 412
 413 #define RX_RING         128
 414 #define TX_RING         256
 415 /*
 416  * If your nic mysteriously hangs then try to reduce the limits
 417  * to 1/0: It might be required to set NV_TX_LASTPACKET in the
 418  * last valid ring entry. But this would be impossible to
 419  * implement - probably a disassembly error.
 420  */
 421 #define TX_LIMIT_STOP   255
 422 #define TX_LIMIT_START  254
 423
 424 /* rx/tx mac addr + type + vlan + align + slack*/
 425 #define NV_RX_HEADERS           (64)
 426 /* even more slack. */
 427 #define NV_RX_ALLOC_PAD         (64)
 428
 429 /* maximum mtu size */
 430 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 431 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 432
 433 #define OOM_REFILL      (1+HZ/20)
 434 #define POLL_WAIT       (1+HZ/100)
 435 #define LINK_TIMEOUT    (3*HZ)
 436
 437 /*
 438  * desc_ver values:
 439  * The nic supports three different descriptor types:
 440  * - DESC_VER_1: Original
 441  * - DESC_VER_2: support for jumbo frames.
 442  * - DESC_VER_3: 64-bit format.
 443  */
 444 #define DESC_VER_1      1
 445 #define DESC_VER_2      2
 446 #define DESC_VER_3      3
 447
 448 /* PHY defines */
 449 #define PHY_OUI_MARVELL 0x5043
 450 #define PHY_OUI_CICADA  0x03f1
 451 #define PHYID1_OUI_MASK 0x03ff
 452 #define PHYID1_OUI_SHFT 6
 453 #define PHYID2_OUI_MASK 0xfc00
 454 #define PHYID2_OUI_SHFT 10
 455 #define PHY_INIT1       0x0f000
 456 #define PHY_INIT2       0x0e00
 457 #define PHY_INIT3       0x01000
 458 #define PHY_INIT4       0x0200
 459 #define PHY_INIT5       0x0004
 460 #define PHY_INIT6       0x02000
 461 #define PHY_GIGABIT     0x0100
 462
 463 #define PHY_TIMEOUT     0x1
 464 #define PHY_ERROR       0x2
 465
 466 #define PHY_100 0x1
 467 #define PHY_1000        0x2
 468 #define PHY_HALF        0x100
 469
 470 /* FIXME: MII defines that should be added to <linux/mii.h> */
 471 #define MII_1000BT_CR   0x09
 472 #define MII_1000BT_SR   0x0a
 473 #define ADVERTISE_1000FULL      0x0200
 474 #define ADVERTISE_1000HALF      0x0100
 475 #define LPA_1000FULL    0x0800
 476 #define LPA_1000HALF    0x0400
 477
 478
 479 /*
 480  * SMP locking:
 481  * All hardware access under dev->priv->lock, except the performance
 482  * critical parts:
 483  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 484  *      by the arch code for interrupts.
 485  * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
 486  *      needs dev->priv->lock :-(
 487  * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
 488  */
 489
 490 /* in dev: base, irq */
 491 struct fe_priv {
 492         spinlock_t lock;
 493
 494         /* General data:
 495          * Locking: spin_lock(&np->lock); */
 496         struct net_device_stats stats;
 497         int in_shutdown;
 498         u32 linkspeed;
 499         int duplex;
 500         int autoneg;
 501         int fixed_mode;
 502         int phyaddr;
 503         int wolenabled;
 504         unsigned int phy_oui;
 505         u16 gigabit;
 506
 507         /* General data: RO fields */
 508         dma_addr_t ring_addr;
 509         struct pci_dev *pci_dev;
 510         u32 orig_mac[2];
 511         u32 irqmask;
 512         u32 desc_ver;
 513         u32 txrxctl_bits;
 514
 515         void __iomem *base;
 516
 517         /* rx specific fields.
 518          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 519          */
 520         ring_type rx_ring;
 521         unsigned int cur_rx, refill_rx;
 522         struct sk_buff *rx_skbuff[RX_RING];
 523         dma_addr_t rx_dma[RX_RING];
 524         unsigned int rx_buf_sz;
 525         unsigned int pkt_limit;
 526         struct timer_list oom_kick;
 527         struct timer_list nic_poll;
 528
 529         /* media detection workaround.
 530          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 531          */
 532         int need_linktimer;
 533         unsigned long link_timeout;
 534         /*
 535          * tx specific fields.
 536          */
 537         ring_type tx_ring;
 538         unsigned int next_tx, nic_tx;
 539         struct sk_buff *tx_skbuff[TX_RING];
 540         dma_addr_t tx_dma[TX_RING];
 541         unsigned int tx_dma_len[TX_RING];
 542         u32 tx_flags;
 543 };
 544
 545 /*
 546  * Maximum number of loops until we assume that a bit in the irq mask
 547  * is stuck. Overridable with module param.
 548  */
 549 static int max_interrupt_work = 5;
 550
 551 /*
 552  * Optimization can be either throuput mode or cpu mode
 553  *
 554  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 555  * CPU Mode: Interrupts are controlled by a timer.
 556  */
 557 #define NV_OPTIMIZATION_MODE_THROUGHPUT 0
 558 #define NV_OPTIMIZATION_MODE_CPU        1
 559 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 560
 561 /*
 562  * Poll interval for timer irq
 563  *
 564  * This interval determines how frequent an interrupt is generated.
 565  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 566  * Min = 0, and Max = 65535
 567  */
 568 static int poll_interval = -1;
 569
 570 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 571 {
 572         return netdev_priv(dev);
 573 }
 574
 575 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 576 {
 577         return ((struct fe_priv *)netdev_priv(dev))->base;
 578 }
 579
 580 static inline void pci_push(u8 __iomem *base)
 581 {
 582         /* force out pending posted writes */
 583         readl(base);
 584 }
 585
 586 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 587 {
 588         return le32_to_cpu(prd->FlagLen)
 589                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 590 }
 591
 592 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 593 {
 594         return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
 595 }
 596
 597 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 598                                 int delay, int delaymax, const char *msg)
 599 {
 600         u8 __iomem *base = get_hwbase(dev);
 601
 602         pci_push(base);
 603         do {
 604                 udelay(delay);
 605                 delaymax -= delay;
 606                 if (delaymax < 0) {
 607                         if (msg)
 608                                 printk(msg);
 609                         return 1;
 610                 }
 611         } while ((readl(base + offset) & mask) != target);
 612         return 0;
 613 }
 614
 615 #define MII_READ        (-1)
 616 /* mii_rw: read/write a register on the PHY.
 617  *
 618  * Caller must guarantee serialization
 619  */
 620 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
 621 {
 622         u8 __iomem *base = get_hwbase(dev);
 623         u32 reg;
 624         int retval;
 625
 626         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
 627
 628         reg = readl(base + NvRegMIIControl);
 629         if (reg & NVREG_MIICTL_INUSE) {
 630                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
 631                 udelay(NV_MIIBUSY_DELAY);
 632         }
 633
 634         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
 635         if (value != MII_READ) {
 636                 writel(value, base + NvRegMIIData);
 637                 reg |= NVREG_MIICTL_WRITE;
 638         }
 639         writel(reg, base + NvRegMIIControl);
 640
 641         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
 642                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
 643                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
 644                                 dev->name, miireg, addr);
 645                 retval = -1;
 646         } else if (value != MII_READ) {
 647                 /* it was a write operation - fewer failures are detectable */
 648                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
 649                                 dev->name, value, miireg, addr);
 650                 retval = 0;
 651         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
 652                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
 653                                 dev->name, miireg, addr);
 654                 retval = -1;
 655         } else {
 656                 retval = readl(base + NvRegMIIData);
 657                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
 658                                 dev->name, miireg, addr, retval);
 659         }
 660
 661         return retval;
 662 }
 663
 664 static int phy_reset(struct net_device *dev)
 665 {
 666         struct fe_priv *np = netdev_priv(dev);
 667         u32 miicontrol;
 668         unsigned int tries = 0;
 669
 670         miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 671         miicontrol |= BMCR_RESET;
 672         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
 673                 return -1;
 674         }
 675
 676         /* wait for 500ms */
 677         msleep(500);
 678
 679         /* must wait till reset is deasserted */
 680         while (miicontrol & BMCR_RESET) {
 681                 msleep(10);
 682                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 683                 /* FIXME: 100 tries seem excessive */
 684                 if (tries++ > 100)
 685                         return -1;
 686         }
 687         return 0;
 688 }
 689
 690 static int phy_init(struct net_device *dev)
 691 {
 692         struct fe_priv *np = get_nvpriv(dev);
 693         u8 __iomem *base = get_hwbase(dev);
 694         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
 695
 696         /* set advertise register */
 697         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
 698         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
 699         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
 700                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
 701                 return PHY_ERROR;
 702         }
 703
 704         /* get phy interface type */
 705         phyinterface = readl(base + NvRegPhyInterface);
 706
 707         /* see if gigabit phy */
 708         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
 709         if (mii_status & PHY_GIGABIT) {
 710                 np->gigabit = PHY_GIGABIT;
 711                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
 712                 mii_control_1000 &= ~ADVERTISE_1000HALF;
 713                 if (phyinterface & PHY_RGMII)
 714                         mii_control_1000 |= ADVERTISE_1000FULL;
 715                 else
 716                         mii_control_1000 &= ~ADVERTISE_1000FULL;
 717
 718                 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
 719                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 720                         return PHY_ERROR;
 721                 }
 722         }
 723         else
 724                 np->gigabit = 0;
 725
 726         /* reset the phy */
 727         if (phy_reset(dev)) {
 728                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
 729                 return PHY_ERROR;
 730         }
 731
 732         /* phy vendor specific configuration */
 733         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
 734                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
 735                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
 736                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
 737                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
 738                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 739                         return PHY_ERROR;
 740                 }
 741                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
 742                 phy_reserved |= PHY_INIT5;
 743                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
 744                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 745                         return PHY_ERROR;
 746                 }
 747         }
 748         if (np->phy_oui == PHY_OUI_CICADA) {
 749                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
 750                 phy_reserved |= PHY_INIT6;
 751                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
 752                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 753                         return PHY_ERROR;
 754                 }
 755         }
 756
 757         /* restart auto negotiation */
 758         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 759         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
 760         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
 761                 return PHY_ERROR;
 762         }
 763
 764         return 0;
 765 }
 766
 767 static void nv_start_rx(struct net_device *dev)
 768 {
 769         struct fe_priv *np = netdev_priv(dev);
 770         u8 __iomem *base = get_hwbase(dev);
 771
 772         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
 773         /* Already running? Stop it. */
 774         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
 775                 writel(0, base + NvRegReceiverControl);
 776                 pci_push(base);
 777         }
 778         writel(np->linkspeed, base + NvRegLinkSpeed);
 779         pci_push(base);
 780         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
 781         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
 782                                 dev->name, np->duplex, np->linkspeed);
 783         pci_push(base);
 784 }
 785
 786 static void nv_stop_rx(struct net_device *dev)
 787 {
 788         u8 __iomem *base = get_hwbase(dev);
 789
 790         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
 791         writel(0, base + NvRegReceiverControl);
 792         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
 793                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
 794                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
 795
 796         udelay(NV_RXSTOP_DELAY2);
 797         writel(0, base + NvRegLinkSpeed);
 798 }
 799
 800 static void nv_start_tx(struct net_device *dev)
 801 {
 802         u8 __iomem *base = get_hwbase(dev);
 803
 804         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
 805         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
 806         pci_push(base);
 807 }
 808
 809 static void nv_stop_tx(struct net_device *dev)
 810 {
 811         u8 __iomem *base = get_hwbase(dev);
 812
 813         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
 814         writel(0, base + NvRegTransmitterControl);
 815         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
 816                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
 817                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
 818
 819         udelay(NV_TXSTOP_DELAY2);
 820         writel(0, base + NvRegUnknownTransmitterReg);
 821 }
 822
 823 static void nv_txrx_reset(struct net_device *dev)
 824 {
 825         struct fe_priv *np = netdev_priv(dev);
 826         u8 __iomem *base = get_hwbase(dev);
 827
 828         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
 829         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
 830         pci_push(base);
 831         udelay(NV_TXRX_RESET_DELAY);
 832         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
 833         pci_push(base);
 834 }
 835
 836 /*
 837  * nv_get_stats: dev->get_stats function
 838  * Get latest stats value from the nic.
 839  * Called with read_lock(&dev_base_lock) held for read -
 840  * only synchronized against unregister_netdevice.
 841  */
 842 static struct net_device_stats *nv_get_stats(struct net_device *dev)
 843 {
 844         struct fe_priv *np = netdev_priv(dev);
 845
 846         /* It seems that the nic always generates interrupts and doesn't
 847          * accumulate errors internally. Thus the current values in np->stats
 848          * are already up to date.
 849          */
 850         return &np->stats;
 851 }
 852
 853 /*
 854  * nv_alloc_rx: fill rx ring entries.
 855  * Return 1 if the allocations for the skbs failed and the
 856  * rx engine is without Available descriptors
 857  */
 858 static int nv_alloc_rx(struct net_device *dev)
 859 {
 860         struct fe_priv *np = netdev_priv(dev);
 861         unsigned int refill_rx = np->refill_rx;
 862         int nr;
 863
 864         while (np->cur_rx != refill_rx) {
 865                 struct sk_buff *skb;
 866
 867                 nr = refill_rx % RX_RING;
 868                 if (np->rx_skbuff[nr] == NULL) {
 869
 870                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
 871                         if (!skb)
 872                                 break;
 873
 874                         skb->dev = dev;
 875                         np->rx_skbuff[nr] = skb;
 876                 } else {
 877                         skb = np->rx_skbuff[nr];
 878                 }
 879                 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
 880                                         skb->end-skb->data, PCI_DMA_FROMDEVICE);
 881                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 882                         np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
 883                         wmb();
 884                         np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
 885                 } else {
 886                         np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
 887                         np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
 888                         wmb();
 889                         np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
 890                 }
 891                 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
 892                                         dev->name, refill_rx);
 893                 refill_rx++;
 894         }
 895         np->refill_rx = refill_rx;
 896         if (np->cur_rx - refill_rx == RX_RING)
 897                 return 1;
 898         return 0;
 899 }
 900
 901 static void nv_do_rx_refill(unsigned long data)
 902 {
 903         struct net_device *dev = (struct net_device *) data;
 904         struct fe_priv *np = netdev_priv(dev);
 905
 906         disable_irq(dev->irq);
 907         if (nv_alloc_rx(dev)) {
 908                 spin_lock(&np->lock);
 909                 if (!np->in_shutdown)
 910                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
 911                 spin_unlock(&np->lock);
 912         }
 913         enable_irq(dev->irq);
 914 }
 915
 916 static void nv_init_rx(struct net_device *dev)
 917 {
 918         struct fe_priv *np = netdev_priv(dev);
 919         int i;
 920
 921         np->cur_rx = RX_RING;
 922         np->refill_rx = 0;
 923         for (i = 0; i < RX_RING; i++)
 924                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 925                         np->rx_ring.orig[i].FlagLen = 0;
 926                 else
 927                         np->rx_ring.ex[i].FlagLen = 0;
 928 }
 929
 930 static void nv_init_tx(struct net_device *dev)
 931 {
 932         struct fe_priv *np = netdev_priv(dev);
 933         int i;
 934
 935         np->next_tx = np->nic_tx = 0;
 936         for (i = 0; i < TX_RING; i++) {
 937                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 938                         np->tx_ring.orig[i].FlagLen = 0;
 939                 else
 940                         np->tx_ring.ex[i].FlagLen = 0;
 941                 np->tx_skbuff[i] = NULL;
 942                 np->tx_dma[i] = 0;
 943         }
 944 }
 945
 946 static int nv_init_ring(struct net_device *dev)
 947 {
 948         nv_init_tx(dev);
 949         nv_init_rx(dev);
 950         return nv_alloc_rx(dev);
 951 }
 952
 953 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
 954 {
 955         struct fe_priv *np = netdev_priv(dev);
 956
 957         dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
 958                 dev->name, skbnr);
 959
 960         if (np->tx_dma[skbnr]) {
 961                 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
 962                                np->tx_dma_len[skbnr],
 963                                PCI_DMA_TODEVICE);
 964                 np->tx_dma[skbnr] = 0;
 965         }
 966
 967         if (np->tx_skbuff[skbnr]) {
 968                 dev_kfree_skb_irq(np->tx_skbuff[skbnr]);
 969                 np->tx_skbuff[skbnr] = NULL;
 970                 return 1;
 971         } else {
 972                 return 0;
 973         }
 974 }
 975
 976 static void nv_drain_tx(struct net_device *dev)
 977 {
 978         struct fe_priv *np = netdev_priv(dev);
 979         unsigned int i;
 980
 981         for (i = 0; i < TX_RING; i++) {
 982                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 983                         np->tx_ring.orig[i].FlagLen = 0;
 984                 else
 985                         np->tx_ring.ex[i].FlagLen = 0;
 986                 if (nv_release_txskb(dev, i))
 987                         np->stats.tx_dropped++;
 988         }
 989 }
 990
 991 static void nv_drain_rx(struct net_device *dev)
 992 {
 993         struct fe_priv *np = netdev_priv(dev);
 994         int i;
 995         for (i = 0; i < RX_RING; i++) {
 996                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 997                         np->rx_ring.orig[i].FlagLen = 0;
 998                 else
 999                         np->rx_ring.ex[i].FlagLen = 0;
1000                 wmb();
1001                 if (np->rx_skbuff[i]) {
1002                         pci_unmap_single(np->pci_dev, np->rx_dma[i],
1003                                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1004                                                 PCI_DMA_FROMDEVICE);
1005                         dev_kfree_skb(np->rx_skbuff[i]);
1006                         np->rx_skbuff[i] = NULL;
1007                 }
1008         }
1009 }
1010
1011 static void drain_ring(struct net_device *dev)
1012 {
1013         nv_drain_tx(dev);
1014         nv_drain_rx(dev);
1015 }
1016
1017 /*
1018  * nv_start_xmit: dev->hard_start_xmit function
1019  * Called with dev->xmit_lock held.
1020  */
1021 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1022 {
1023         struct fe_priv *np = netdev_priv(dev);
1024         u32 tx_flags = 0;
1025         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1026         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1027         unsigned int nr = (np->next_tx - 1) % TX_RING;
1028         unsigned int start_nr = np->next_tx % TX_RING;
1029         unsigned int i;
1030         u32 offset = 0;
1031         u32 bcnt;
1032         u32 size = skb->len-skb->data_len;
1033         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1034
1035         /* add fragments to entries count */
1036         for (i = 0; i < fragments; i++) {
1037                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1038                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1039         }
1040
1041         spin_lock_irq(&np->lock);
1042
1043         if ((np->next_tx - np->nic_tx + entries - 1) > TX_LIMIT_STOP) {
1044                 spin_unlock_irq(&np->lock);
1045                 netif_stop_queue(dev);
1046                 return NETDEV_TX_BUSY;
1047         }
1048
1049         /* setup the header buffer */
1050         do {
1051                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1052                 nr = (nr + 1) % TX_RING;
1053
1054                 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1055                                                 PCI_DMA_TODEVICE);
1056                 np->tx_dma_len[nr] = bcnt;
1057
1058                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1059                         np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1060                         np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1061                 } else {
1062                         np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1063                         np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1064                         np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1065                 }
1066                 tx_flags = np->tx_flags;
1067                 offset += bcnt;
1068                 size -= bcnt;
1069         } while(size);
1070
1071         /* setup the fragments */
1072         for (i = 0; i < fragments; i++) {
1073                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1074                 u32 size = frag->size;
1075                 offset = 0;
1076
1077                 do {
1078                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1079                         nr = (nr + 1) % TX_RING;
1080
1081                         np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1082                                                       PCI_DMA_TODEVICE);
1083                         np->tx_dma_len[nr] = bcnt;
1084
1085                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1086                                 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1087                                 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1088                         } else {
1089                                 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1090                                 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1091                                 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1092                         }
1093                         offset += bcnt;
1094                         size -= bcnt;
1095                 } while (size);
1096         }
1097
1098         /* set last fragment flag  */
1099         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1100                 np->tx_ring.orig[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1101         } else {
1102                 np->tx_ring.ex[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1103         }
1104
1105         np->tx_skbuff[nr] = skb;
1106
1107 #ifdef NETIF_F_TSO
1108         if (skb_shinfo(skb)->tso_size)
1109                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->tso_size << NV_TX2_TSO_SHIFT);
1110         else
1111 #endif
1112         tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
1113
1114         /* set tx flags */
1115         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1116                 np->tx_ring.orig[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1117         } else {
1118                 np->tx_ring.ex[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1119         }
1120
1121         dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1122                 dev->name, np->next_tx, entries, tx_flags_extra);
1123         {
1124                 int j;
1125                 for (j=0; j<64; j++) {
1126                         if ((j%16) == 0)
1127                                 dprintk("\n%03x:", j);
1128                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1129                 }
1130                 dprintk("\n");
1131         }
1132
1133         np->next_tx += entries;
1134
1135         dev->trans_start = jiffies;
1136         spin_unlock_irq(&np->lock);
1137         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1138         pci_push(get_hwbase(dev));
1139         return NETDEV_TX_OK;
1140 }
1141
1142 /*
1143  * nv_tx_done: check for completed packets, release the skbs.
1144  *
1145  * Caller must own np->lock.
1146  */
1147 static void nv_tx_done(struct net_device *dev)
1148 {
1149         struct fe_priv *np = netdev_priv(dev);
1150         u32 Flags;
1151         unsigned int i;
1152         struct sk_buff *skb;
1153
1154         while (np->nic_tx != np->next_tx) {
1155                 i = np->nic_tx % TX_RING;
1156
1157                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1158                         Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1159                 else
1160                         Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
1161
1162                 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1163                                         dev->name, np->nic_tx, Flags);
1164                 if (Flags & NV_TX_VALID)
1165                         break;
1166                 if (np->desc_ver == DESC_VER_1) {
1167                         if (Flags & NV_TX_LASTPACKET) {
1168                                 skb = np->tx_skbuff[i];
1169                                 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1170                                              NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1171                                         if (Flags & NV_TX_UNDERFLOW)
1172                                                 np->stats.tx_fifo_errors++;
1173                                         if (Flags & NV_TX_CARRIERLOST)
1174                                                 np->stats.tx_carrier_errors++;
1175                                         np->stats.tx_errors++;
1176                                 } else {
1177                                         np->stats.tx_packets++;
1178                                         np->stats.tx_bytes += skb->len;
1179                                 }
1180                         }
1181                 } else {
1182                         if (Flags & NV_TX2_LASTPACKET) {
1183                                 skb = np->tx_skbuff[i];
1184                                 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1185                                              NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1186                                         if (Flags & NV_TX2_UNDERFLOW)
1187                                                 np->stats.tx_fifo_errors++;
1188                                         if (Flags & NV_TX2_CARRIERLOST)
1189                                                 np->stats.tx_carrier_errors++;
1190                                         np->stats.tx_errors++;
1191                                 } else {
1192                                         np->stats.tx_packets++;
1193                                         np->stats.tx_bytes += skb->len;
1194                                 }
1195                         }
1196                 }
1197                 nv_release_txskb(dev, i);
1198                 np->nic_tx++;
1199         }
1200         if (np->next_tx - np->nic_tx < TX_LIMIT_START)
1201                 netif_wake_queue(dev);
1202 }
1203
1204 /*
1205  * nv_tx_timeout: dev->tx_timeout function
1206  * Called with dev->xmit_lock held.
1207  */
1208 static void nv_tx_timeout(struct net_device *dev)
1209 {
1210         struct fe_priv *np = netdev_priv(dev);
1211         u8 __iomem *base = get_hwbase(dev);
1212
1213         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name,
1214                         readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
1215
1216         {
1217                 int i;
1218
1219                 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1220                                 dev->name, (unsigned long)np->ring_addr,
1221                                 np->next_tx, np->nic_tx);
1222                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1223                 for (i=0;i<0x400;i+= 32) {
1224                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1225                                         i,
1226                                         readl(base + i + 0), readl(base + i + 4),
1227                                         readl(base + i + 8), readl(base + i + 12),
1228                                         readl(base + i + 16), readl(base + i + 20),
1229                                         readl(base + i + 24), readl(base + i + 28));
1230                 }
1231                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1232                 for (i=0;i<TX_RING;i+= 4) {
1233                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1234                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1235                                        i,
1236                                        le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1237                                        le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1238                                        le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1239                                        le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1240                                        le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1241                                        le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1242                                        le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1243                                        le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1244                         } else {
1245                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1246                                        i,
1247                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1248                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1249                                        le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1250                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1251                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1252                                        le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1253                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1254                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1255                                        le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1256                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1257                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1258                                        le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1259                         }
1260                 }
1261         }
1262
1263         spin_lock_irq(&np->lock);
1264
1265         /* 1) stop tx engine */
1266         nv_stop_tx(dev);
1267
1268         /* 2) check that the packets were not sent already: */
1269         nv_tx_done(dev);
1270
1271         /* 3) if there are dead entries: clear everything */
1272         if (np->next_tx != np->nic_tx) {
1273                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1274                 nv_drain_tx(dev);
1275                 np->next_tx = np->nic_tx = 0;
1276                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1277                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1278                 else
1279                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1280                 netif_wake_queue(dev);
1281         }
1282
1283         /* 4) restart tx engine */
1284         nv_start_tx(dev);
1285         spin_unlock_irq(&np->lock);
1286 }
1287
1288 /*
1289  * Called when the nic notices a mismatch between the actual data len on the
1290  * wire and the len indicated in the 802 header
1291  */
1292 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1293 {
1294         int hdrlen;     /* length of the 802 header */
1295         int protolen;   /* length as stored in the proto field */
1296
1297         /* 1) calculate len according to header */
1298         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1299                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1300                 hdrlen = VLAN_HLEN;
1301         } else {
1302                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1303                 hdrlen = ETH_HLEN;
1304         }
1305         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1306                                 dev->name, datalen, protolen, hdrlen);
1307         if (protolen > ETH_DATA_LEN)
1308                 return datalen; /* Value in proto field not a len, no checks possible */
1309
1310         protolen += hdrlen;
1311         /* consistency checks: */
1312         if (datalen > ETH_ZLEN) {
1313                 if (datalen >= protolen) {
1314                         /* more data on wire than in 802 header, trim of
1315                          * additional data.
1316                          */
1317                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1318                                         dev->name, protolen);
1319                         return protolen;
1320                 } else {
1321                         /* less data on wire than mentioned in header.
1322                          * Discard the packet.
1323                          */
1324                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1325                                         dev->name);
1326                         return -1;
1327                 }
1328         } else {
1329                 /* short packet. Accept only if 802 values are also short */
1330                 if (protolen > ETH_ZLEN) {
1331                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1332                                         dev->name);
1333                         return -1;
1334                 }
1335                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1336                                 dev->name, datalen);
1337                 return datalen;
1338         }
1339 }
1340
1341 static void nv_rx_process(struct net_device *dev)
1342 {
1343         struct fe_priv *np = netdev_priv(dev);
1344         u32 Flags;
1345
1346         for (;;) {
1347                 struct sk_buff *skb;
1348                 int len;
1349                 int i;
1350                 if (np->cur_rx - np->refill_rx >= RX_RING)
1351                         break;  /* we scanned the whole ring - do not continue */
1352
1353                 i = np->cur_rx % RX_RING;
1354                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1355                         Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1356                         len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1357                 } else {
1358                         Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1359                         len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1360                 }
1361
1362                 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1363                                         dev->name, np->cur_rx, Flags);
1364
1365                 if (Flags & NV_RX_AVAIL)
1366                         break;  /* still owned by hardware, */
1367
1368                 /*
1369                  * the packet is for us - immediately tear down the pci mapping.
1370                  * TODO: check if a prefetch of the first cacheline improves
1371                  * the performance.
1372                  */
1373                 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1374                                 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1375                                 PCI_DMA_FROMDEVICE);
1376
1377                 {
1378                         int j;
1379                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1380                         for (j=0; j<64; j++) {
1381                                 if ((j%16) == 0)
1382                                         dprintk("\n%03x:", j);
1383                                 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1384                         }
1385                         dprintk("\n");
1386                 }
1387                 /* look at what we actually got: */
1388                 if (np->desc_ver == DESC_VER_1) {
1389                         if (!(Flags & NV_RX_DESCRIPTORVALID))
1390                                 goto next_pkt;
1391
1392                         if (Flags & NV_RX_ERROR) {
1393                                 if (Flags & NV_RX_MISSEDFRAME) {
1394                                         np->stats.rx_missed_errors++;
1395                                         np->stats.rx_errors++;
1396                                         goto next_pkt;
1397                                 }
1398                                 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1399                                         np->stats.rx_errors++;
1400                                         goto next_pkt;
1401                                 }
1402                                 if (Flags & NV_RX_CRCERR) {
1403                                         np->stats.rx_crc_errors++;
1404                                         np->stats.rx_errors++;
1405                                         goto next_pkt;
1406                                 }
1407                                 if (Flags & NV_RX_OVERFLOW) {
1408                                         np->stats.rx_over_errors++;
1409                                         np->stats.rx_errors++;
1410                                         goto next_pkt;
1411                                 }
1412                                 if (Flags & NV_RX_ERROR4) {
1413                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1414                                         if (len < 0) {
1415                                                 np->stats.rx_errors++;
1416                                                 goto next_pkt;
1417                                         }
1418                                 }
1419                                 /* framing errors are soft errors. */
1420                                 if (Flags & NV_RX_FRAMINGERR) {
1421                                         if (Flags & NV_RX_SUBSTRACT1) {
1422                                                 len--;
1423                                         }
1424                                 }
1425                         }
1426                 } else {
1427                         if (!(Flags & NV_RX2_DESCRIPTORVALID))
1428                                 goto next_pkt;
1429
1430                         if (Flags & NV_RX2_ERROR) {
1431                                 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1432                                         np->stats.rx_errors++;
1433                                         goto next_pkt;
1434                                 }
1435                                 if (Flags & NV_RX2_CRCERR) {
1436                                         np->stats.rx_crc_errors++;
1437                                         np->stats.rx_errors++;
1438                                         goto next_pkt;
1439                                 }
1440                                 if (Flags & NV_RX2_OVERFLOW) {
1441                                         np->stats.rx_over_errors++;
1442                                         np->stats.rx_errors++;
1443                                         goto next_pkt;
1444                                 }
1445                                 if (Flags & NV_RX2_ERROR4) {
1446                                         len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1447                                         if (len < 0) {
1448                                                 np->stats.rx_errors++;
1449                                                 goto next_pkt;
1450                                         }
1451                                 }
1452                                 /* framing errors are soft errors */
1453                                 if (Flags & NV_RX2_FRAMINGERR) {
1454                                         if (Flags & NV_RX2_SUBSTRACT1) {
1455                                                 len--;
1456                                         }
1457                                 }
1458                         }
1459                         Flags &= NV_RX2_CHECKSUMMASK;
1460                         if (Flags == NV_RX2_CHECKSUMOK1 ||
1461                                         Flags == NV_RX2_CHECKSUMOK2 ||
1462                                         Flags == NV_RX2_CHECKSUMOK3) {
1463                                 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1464                                 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1465                         } else {
1466                                 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1467                         }
1468                 }
1469                 /* got a valid packet - forward it to the network core */
1470                 skb = np->rx_skbuff[i];
1471                 np->rx_skbuff[i] = NULL;
1472
1473                 skb_put(skb, len);
1474                 skb->protocol = eth_type_trans(skb, dev);
1475                 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1476                                         dev->name, np->cur_rx, len, skb->protocol);
1477                 netif_rx(skb);
1478                 dev->last_rx = jiffies;
1479                 np->stats.rx_packets++;
1480                 np->stats.rx_bytes += len;
1481 next_pkt:
1482                 np->cur_rx++;
1483         }
1484 }
1485
1486 static void set_bufsize(struct net_device *dev)
1487 {
1488         struct fe_priv *np = netdev_priv(dev);
1489
1490         if (dev->mtu <= ETH_DATA_LEN)
1491                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1492         else
1493                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1494 }
1495
1496 /*
1497  * nv_change_mtu: dev->change_mtu function
1498  * Called with dev_base_lock held for read.
1499  */
1500 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1501 {
1502         struct fe_priv *np = netdev_priv(dev);
1503         int old_mtu;
1504
1505         if (new_mtu < 64 || new_mtu > np->pkt_limit)
1506                 return -EINVAL;
1507
1508         old_mtu = dev->mtu;
1509         dev->mtu = new_mtu;
1510
1511         /* return early if the buffer sizes will not change */
1512         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1513                 return 0;
1514         if (old_mtu == new_mtu)
1515                 return 0;
1516
1517         /* synchronized against open : rtnl_lock() held by caller */
1518         if (netif_running(dev)) {
1519                 u8 __iomem *base = get_hwbase(dev);
1520                 /*
1521                  * It seems that the nic preloads valid ring entries into an
1522                  * internal buffer. The procedure for flushing everything is
1523                  * guessed, there is probably a simpler approach.
1524                  * Changing the MTU is a rare event, it shouldn't matter.
1525                  */
1526                 disable_irq(dev->irq);
1527                 spin_lock_bh(&dev->xmit_lock);
1528                 spin_lock(&np->lock);
1529                 /* stop engines */
1530                 nv_stop_rx(dev);
1531                 nv_stop_tx(dev);
1532                 nv_txrx_reset(dev);
1533                 /* drain rx queue */
1534                 nv_drain_rx(dev);
1535                 nv_drain_tx(dev);
1536                 /* reinit driver view of the rx queue */
1537                 nv_init_rx(dev);
1538                 nv_init_tx(dev);
1539                 /* alloc new rx buffers */
1540                 set_bufsize(dev);
1541                 if (nv_alloc_rx(dev)) {
1542                         if (!np->in_shutdown)
1543                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1544                 }
1545                 /* reinit nic view of the rx queue */
1546                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1547                 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1548                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1549                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1550                 else
1551                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1552                 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1553                         base + NvRegRingSizes);
1554                 pci_push(base);
1555                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1556                 pci_push(base);
1557
1558                 /* restart rx engine */
1559                 nv_start_rx(dev);
1560                 nv_start_tx(dev);
1561                 spin_unlock(&np->lock);
1562                 spin_unlock_bh(&dev->xmit_lock);
1563                 enable_irq(dev->irq);
1564         }
1565         return 0;
1566 }
1567
1568 static void nv_copy_mac_to_hw(struct net_device *dev)
1569 {
1570         u8 __iomem *base = get_hwbase(dev);
1571         u32 mac[2];
1572
1573         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1574                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1575         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1576
1577         writel(mac[0], base + NvRegMacAddrA);
1578         writel(mac[1], base + NvRegMacAddrB);
1579 }
1580
1581 /*
1582  * nv_set_mac_address: dev->set_mac_address function
1583  * Called with rtnl_lock() held.
1584  */
1585 static int nv_set_mac_address(struct net_device *dev, void *addr)
1586 {
1587         struct fe_priv *np = netdev_priv(dev);
1588         struct sockaddr *macaddr = (struct sockaddr*)addr;
1589
1590         if(!is_valid_ether_addr(macaddr->sa_data))
1591                 return -EADDRNOTAVAIL;
1592
1593         /* synchronized against open : rtnl_lock() held by caller */
1594         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1595
1596         if (netif_running(dev)) {
1597                 spin_lock_bh(&dev->xmit_lock);
1598                 spin_lock_irq(&np->lock);
1599
1600                 /* stop rx engine */
1601                 nv_stop_rx(dev);
1602
1603                 /* set mac address */
1604                 nv_copy_mac_to_hw(dev);
1605
1606                 /* restart rx engine */
1607                 nv_start_rx(dev);
1608                 spin_unlock_irq(&np->lock);
1609                 spin_unlock_bh(&dev->xmit_lock);
1610         } else {
1611                 nv_copy_mac_to_hw(dev);
1612         }
1613         return 0;
1614 }
1615
1616 /*
1617  * nv_set_multicast: dev->set_multicast function
1618  * Called with dev->xmit_lock held.
1619  */
1620 static void nv_set_multicast(struct net_device *dev)
1621 {
1622         struct fe_priv *np = netdev_priv(dev);
1623         u8 __iomem *base = get_hwbase(dev);
1624         u32 addr[2];
1625         u32 mask[2];
1626         u32 pff;
1627
1628         memset(addr, 0, sizeof(addr));
1629         memset(mask, 0, sizeof(mask));
1630
1631         if (dev->flags & IFF_PROMISC) {
1632                 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1633                 pff = NVREG_PFF_PROMISC;
1634         } else {
1635                 pff = NVREG_PFF_MYADDR;
1636
1637                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1638                         u32 alwaysOff[2];
1639                         u32 alwaysOn[2];
1640
1641                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1642                         if (dev->flags & IFF_ALLMULTI) {
1643                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1644                         } else {
1645                                 struct dev_mc_list *walk;
1646
1647                                 walk = dev->mc_list;
1648                                 while (walk != NULL) {
1649                                         u32 a, b;
1650                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1651                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1652                                         alwaysOn[0] &= a;
1653                                         alwaysOff[0] &= ~a;
1654                                         alwaysOn[1] &= b;
1655                                         alwaysOff[1] &= ~b;
1656                                         walk = walk->next;
1657                                 }
1658                         }
1659                         addr[0] = alwaysOn[0];
1660                         addr[1] = alwaysOn[1];
1661                         mask[0] = alwaysOn[0] | alwaysOff[0];
1662                         mask[1] = alwaysOn[1] | alwaysOff[1];
1663                 }
1664         }
1665         addr[0] |= NVREG_MCASTADDRA_FORCE;
1666         pff |= NVREG_PFF_ALWAYS;
1667         spin_lock_irq(&np->lock);
1668         nv_stop_rx(dev);
1669         writel(addr[0], base + NvRegMulticastAddrA);
1670         writel(addr[1], base + NvRegMulticastAddrB);
1671         writel(mask[0], base + NvRegMulticastMaskA);
1672         writel(mask[1], base + NvRegMulticastMaskB);
1673         writel(pff, base + NvRegPacketFilterFlags);
1674         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1675                 dev->name);
1676         nv_start_rx(dev);
1677         spin_unlock_irq(&np->lock);
1678 }
1679
1680 /**
1681  * nv_update_linkspeed: Setup the MAC according to the link partner
1682  * @dev: Network device to be configured
1683  *
1684  * The function queries the PHY and checks if there is a link partner.
1685  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
1686  * set to 10 MBit HD.
1687  *
1688  * The function returns 0 if there is no link partner and 1 if there is
1689  * a good link partner.
1690  */
1691 static int nv_update_linkspeed(struct net_device *dev)
1692 {
1693         struct fe_priv *np = netdev_priv(dev);
1694         u8 __iomem *base = get_hwbase(dev);
1695         int adv, lpa;
1696         int newls = np->linkspeed;
1697         int newdup = np->duplex;
1698         int mii_status;
1699         int retval = 0;
1700         u32 control_1000, status_1000, phyreg;
1701
1702         /* BMSR_LSTATUS is latched, read it twice:
1703          * we want the current value.
1704          */
1705         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1706         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1707
1708         if (!(mii_status & BMSR_LSTATUS)) {
1709                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1710                                 dev->name);
1711                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1712                 newdup = 0;
1713                 retval = 0;
1714                 goto set_speed;
1715         }
1716
1717         if (np->autoneg == 0) {
1718                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1719                                 dev->name, np->fixed_mode);
1720                 if (np->fixed_mode & LPA_100FULL) {
1721                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1722                         newdup = 1;
1723                 } else if (np->fixed_mode & LPA_100HALF) {
1724                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1725                         newdup = 0;
1726                 } else if (np->fixed_mode & LPA_10FULL) {
1727                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1728                         newdup = 1;
1729                 } else {
1730                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1731                         newdup = 0;
1732                 }
1733                 retval = 1;
1734                 goto set_speed;
1735         }
1736         /* check auto negotiation is complete */
1737         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1738                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1739                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1740                 newdup = 0;
1741                 retval = 0;
1742                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1743                 goto set_speed;
1744         }
1745
1746         retval = 1;
1747         if (np->gigabit == PHY_GIGABIT) {
1748                 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1749                 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1750
1751                 if ((control_1000 & ADVERTISE_1000FULL) &&
1752                         (status_1000 & LPA_1000FULL)) {
1753                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1754                                 dev->name);
1755                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1756                         newdup = 1;
1757                         goto set_speed;
1758                 }
1759         }
1760
1761         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1762         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1763         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1764                                 dev->name, adv, lpa);
1765
1766         /* FIXME: handle parallel detection properly */
1767         lpa = lpa & adv;
1768         if (lpa & LPA_100FULL) {
1769                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1770                 newdup = 1;
1771         } else if (lpa & LPA_100HALF) {
1772                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1773                 newdup = 0;
1774         } else if (lpa & LPA_10FULL) {
1775                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1776                 newdup = 1;
1777         } else if (lpa & LPA_10HALF) {
1778                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1779                 newdup = 0;
1780         } else {
1781                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1782                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1783                 newdup = 0;
1784         }
1785
1786 set_speed:
1787         if (np->duplex == newdup && np->linkspeed == newls)
1788                 return retval;
1789
1790         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1791                         dev->name, np->linkspeed, np->duplex, newls, newdup);
1792
1793         np->duplex = newdup;
1794         np->linkspeed = newls;
1795
1796         if (np->gigabit == PHY_GIGABIT) {
1797                 phyreg = readl(base + NvRegRandomSeed);
1798                 phyreg &= ~(0x3FF00);
1799                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1800                         phyreg |= NVREG_RNDSEED_FORCE3;
1801                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1802                         phyreg |= NVREG_RNDSEED_FORCE2;
1803                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1804                         phyreg |= NVREG_RNDSEED_FORCE;
1805                 writel(phyreg, base + NvRegRandomSeed);
1806         }
1807
1808         phyreg = readl(base + NvRegPhyInterface);
1809         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1810         if (np->duplex == 0)
1811                 phyreg |= PHY_HALF;
1812         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
1813                 phyreg |= PHY_100;
1814         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
1815                 phyreg |= PHY_1000;
1816         writel(phyreg, base + NvRegPhyInterface);
1817
1818         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1819                 base + NvRegMisc1);
1820         pci_push(base);
1821         writel(np->linkspeed, base + NvRegLinkSpeed);
1822         pci_push(base);
1823
1824         return retval;
1825 }
1826
1827 static void nv_linkchange(struct net_device *dev)
1828 {
1829         if (nv_update_linkspeed(dev)) {
1830                 if (!netif_carrier_ok(dev)) {
1831                         netif_carrier_on(dev);
1832                         printk(KERN_INFO "%s: link up.\n", dev->name);
1833                         nv_start_rx(dev);
1834                 }
1835         } else {
1836                 if (netif_carrier_ok(dev)) {
1837                         netif_carrier_off(dev);
1838                         printk(KERN_INFO "%s: link down.\n", dev->name);
1839                         nv_stop_rx(dev);
1840                 }
1841         }
1842 }
1843
1844 static void nv_link_irq(struct net_device *dev)
1845 {
1846         u8 __iomem *base = get_hwbase(dev);
1847         u32 miistat;
1848
1849         miistat = readl(base + NvRegMIIStatus);
1850         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1851         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
1852
1853         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
1854                 nv_linkchange(dev);
1855         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1856 }
1857
1858 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1859 {
1860         struct net_device *dev = (struct net_device *) data;
1861         struct fe_priv *np = netdev_priv(dev);
1862         u8 __iomem *base = get_hwbase(dev);
1863         u32 events;
1864         int i;
1865
1866         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1867
1868         for (i=0; ; i++) {
1869                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1870                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1871                 pci_push(base);
1872                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1873                 if (!(events & np->irqmask))
1874                         break;
1875
1876                 spin_lock(&np->lock);
1877                 nv_tx_done(dev);
1878                 spin_unlock(&np->lock);
1879
1880                 nv_rx_process(dev);
1881                 if (nv_alloc_rx(dev)) {
1882                         spin_lock(&np->lock);
1883                         if (!np->in_shutdown)
1884                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1885                         spin_unlock(&np->lock);
1886                 }
1887
1888                 if (events & NVREG_IRQ_LINK) {
1889                         spin_lock(&np->lock);
1890                         nv_link_irq(dev);
1891                         spin_unlock(&np->lock);
1892                 }
1893                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
1894                         spin_lock(&np->lock);
1895                         nv_linkchange(dev);
1896                         spin_unlock(&np->lock);
1897                         np->link_timeout = jiffies + LINK_TIMEOUT;
1898                 }
1899                 if (events & (NVREG_IRQ_TX_ERR)) {
1900                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1901                                                 dev->name, events);
1902                 }
1903                 if (events & (NVREG_IRQ_UNKNOWN)) {
1904                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1905                                                 dev->name, events);
1906                 }
1907                 if (i > max_interrupt_work) {
1908                         spin_lock(&np->lock);
1909                         /* disable interrupts on the nic */
1910                         writel(0, base + NvRegIrqMask);
1911                         pci_push(base);
1912
1913                         if (!np->in_shutdown)
1914                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1915                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1916                         spin_unlock(&np->lock);
1917                         break;
1918                 }
1919
1920         }
1921         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1922
1923         return IRQ_RETVAL(i);
1924 }
1925
1926 static void nv_do_nic_poll(unsigned long data)
1927 {
1928         struct net_device *dev = (struct net_device *) data;
1929         struct fe_priv *np = netdev_priv(dev);
1930         u8 __iomem *base = get_hwbase(dev);
1931
1932         disable_irq(dev->irq);
1933         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1934         /*
1935          * reenable interrupts on the nic, we have to do this before calling
1936          * nv_nic_irq because that may decide to do otherwise
1937          */
1938         writel(np->irqmask, base + NvRegIrqMask);
1939         pci_push(base);
1940         nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1941         enable_irq(dev->irq);
1942 }
1943
1944 #ifdef CONFIG_NET_POLL_CONTROLLER
1945 static void nv_poll_controller(struct net_device *dev)
1946 {
1947         nv_do_nic_poll((unsigned long) dev);
1948 }
1949 #endif
1950
1951 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1952 {
1953         struct fe_priv *np = netdev_priv(dev);
1954         strcpy(info->driver, "forcedeth");
1955         strcpy(info->version, FORCEDETH_VERSION);
1956         strcpy(info->bus_info, pci_name(np->pci_dev));
1957 }
1958
1959 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1960 {
1961         struct fe_priv *np = netdev_priv(dev);
1962         wolinfo->supported = WAKE_MAGIC;
1963
1964         spin_lock_irq(&np->lock);
1965         if (np->wolenabled)
1966                 wolinfo->wolopts = WAKE_MAGIC;
1967         spin_unlock_irq(&np->lock);
1968 }
1969
1970 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1971 {
1972         struct fe_priv *np = netdev_priv(dev);
1973         u8 __iomem *base = get_hwbase(dev);
1974
1975         spin_lock_irq(&np->lock);
1976         if (wolinfo->wolopts == 0) {
1977                 writel(0, base + NvRegWakeUpFlags);
1978                 np->wolenabled = 0;
1979         }
1980         if (wolinfo->wolopts & WAKE_MAGIC) {
1981                 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
1982                 np->wolenabled = 1;
1983         }
1984         spin_unlock_irq(&np->lock);
1985         return 0;
1986 }
1987
1988 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1989 {
1990         struct fe_priv *np = netdev_priv(dev);
1991         int adv;
1992
1993         spin_lock_irq(&np->lock);
1994         ecmd->port = PORT_MII;
1995         if (!netif_running(dev)) {
1996                 /* We do not track link speed / duplex setting if the
1997                  * interface is disabled. Force a link check */
1998                 nv_update_linkspeed(dev);
1999         }
2000         switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
2001                 case NVREG_LINKSPEED_10:
2002                         ecmd->speed = SPEED_10;
2003                         break;
2004                 case NVREG_LINKSPEED_100:
2005                         ecmd->speed = SPEED_100;
2006                         break;
2007                 case NVREG_LINKSPEED_1000:
2008                         ecmd->speed = SPEED_1000;
2009                         break;
2010         }
2011         ecmd->duplex = DUPLEX_HALF;
2012         if (np->duplex)
2013                 ecmd->duplex = DUPLEX_FULL;
2014
2015         ecmd->autoneg = np->autoneg;
2016
2017         ecmd->advertising = ADVERTISED_MII;
2018         if (np->autoneg) {
2019                 ecmd->advertising |= ADVERTISED_Autoneg;
2020                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2021         } else {
2022                 adv = np->fixed_mode;
2023         }
2024         if (adv & ADVERTISE_10HALF)
2025                 ecmd->advertising |= ADVERTISED_10baseT_Half;
2026         if (adv & ADVERTISE_10FULL)
2027                 ecmd->advertising |= ADVERTISED_10baseT_Full;
2028         if (adv & ADVERTISE_100HALF)
2029                 ecmd->advertising |= ADVERTISED_100baseT_Half;
2030         if (adv & ADVERTISE_100FULL)
2031                 ecmd->advertising |= ADVERTISED_100baseT_Full;
2032         if (np->autoneg && np->gigabit == PHY_GIGABIT) {
2033                 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2034                 if (adv & ADVERTISE_1000FULL)
2035                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
2036         }
2037
2038         ecmd->supported = (SUPPORTED_Autoneg |
2039                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2040                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2041                 SUPPORTED_MII);
2042         if (np->gigabit == PHY_GIGABIT)
2043                 ecmd->supported |= SUPPORTED_1000baseT_Full;
2044
2045         ecmd->phy_address = np->phyaddr;
2046         ecmd->transceiver = XCVR_EXTERNAL;
2047
2048         /* ignore maxtxpkt, maxrxpkt for now */
2049         spin_unlock_irq(&np->lock);
2050         return 0;
2051 }
2052
2053 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2054 {
2055         struct fe_priv *np = netdev_priv(dev);
2056
2057         if (ecmd->port != PORT_MII)
2058                 return -EINVAL;
2059         if (ecmd->transceiver != XCVR_EXTERNAL)
2060                 return -EINVAL;
2061         if (ecmd->phy_address != np->phyaddr) {
2062                 /* TODO: support switching between multiple phys. Should be
2063                  * trivial, but not enabled due to lack of test hardware. */
2064                 return -EINVAL;
2065         }
2066         if (ecmd->autoneg == AUTONEG_ENABLE) {
2067                 u32 mask;
2068
2069                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2070                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
2071                 if (np->gigabit == PHY_GIGABIT)
2072                         mask |= ADVERTISED_1000baseT_Full;
2073
2074                 if ((ecmd->advertising & mask) == 0)
2075                         return -EINVAL;
2076
2077         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2078                 /* Note: autonegotiation disable, speed 1000 intentionally
2079                  * forbidden - noone should need that. */
2080
2081                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2082                         return -EINVAL;
2083                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2084                         return -EINVAL;
2085         } else {
2086                 return -EINVAL;
2087         }
2088
2089         spin_lock_irq(&np->lock);
2090         if (ecmd->autoneg == AUTONEG_ENABLE) {
2091                 int adv, bmcr;
2092
2093                 np->autoneg = 1;
2094
2095                 /* advertise only what has been requested */
2096                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2097                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2098                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2099                         adv |= ADVERTISE_10HALF;
2100                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2101                         adv |= ADVERTISE_10FULL;
2102                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2103                         adv |= ADVERTISE_100HALF;
2104                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2105                         adv |= ADVERTISE_100FULL;
2106                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2107
2108                 if (np->gigabit == PHY_GIGABIT) {
2109                         adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2110                         adv &= ~ADVERTISE_1000FULL;
2111                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
2112                                 adv |= ADVERTISE_1000FULL;
2113                         mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
2114                 }
2115
2116                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2117                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2118                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2119
2120         } else {
2121                 int adv, bmcr;
2122
2123                 np->autoneg = 0;
2124
2125                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2126                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2127                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
2128                         adv |= ADVERTISE_10HALF;
2129                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
2130                         adv |= ADVERTISE_10FULL;
2131                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
2132                         adv |= ADVERTISE_100HALF;
2133                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
2134                         adv |= ADVERTISE_100FULL;
2135                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2136                 np->fixed_mode = adv;
2137
2138                 if (np->gigabit == PHY_GIGABIT) {
2139                         adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2140                         adv &= ~ADVERTISE_1000FULL;
2141                         mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
2142                 }
2143
2144                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2145                 bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX);
2146                 if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL))
2147                         bmcr |= BMCR_FULLDPLX;
2148                 if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL))
2149                         bmcr |= BMCR_SPEED100;
2150                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2151
2152                 if (netif_running(dev)) {
2153                         /* Wait a bit and then reconfigure the nic. */
2154                         udelay(10);
2155                         nv_linkchange(dev);
2156                 }
2157         }
2158         spin_unlock_irq(&np->lock);
2159
2160         return 0;
2161 }
2162
2163 #define FORCEDETH_REGS_VER      1
2164 #define FORCEDETH_REGS_SIZE     0x400 /* 256 32-bit registers */
2165
2166 static int nv_get_regs_len(struct net_device *dev)
2167 {
2168         return FORCEDETH_REGS_SIZE;
2169 }
2170
2171 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2172 {
2173         struct fe_priv *np = netdev_priv(dev);
2174         u8 __iomem *base = get_hwbase(dev);
2175         u32 *rbuf = buf;
2176         int i;
2177
2178         regs->version = FORCEDETH_REGS_VER;
2179         spin_lock_irq(&np->lock);
2180         for (i=0;i<FORCEDETH_REGS_SIZE/sizeof(u32);i++)
2181                 rbuf[i] = readl(base + i*sizeof(u32));
2182         spin_unlock_irq(&np->lock);
2183 }
2184
2185 static int nv_nway_reset(struct net_device *dev)
2186 {
2187         struct fe_priv *np = netdev_priv(dev);
2188         int ret;
2189
2190         spin_lock_irq(&np->lock);
2191         if (np->autoneg) {
2192                 int bmcr;
2193
2194                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2195                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2196                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2197
2198                 ret = 0;
2199         } else {
2200                 ret = -EINVAL;
2201         }
2202         spin_unlock_irq(&np->lock);
2203
2204         return ret;
2205 }
2206
2207 static struct ethtool_ops ops = {
2208         .get_drvinfo = nv_get_drvinfo,
2209         .get_link = ethtool_op_get_link,
2210         .get_wol = nv_get_wol,
2211         .set_wol = nv_set_wol,
2212         .get_settings = nv_get_settings,
2213         .set_settings = nv_set_settings,
2214         .get_regs_len = nv_get_regs_len,
2215         .get_regs = nv_get_regs,
2216         .nway_reset = nv_nway_reset,
2217         .get_perm_addr = ethtool_op_get_perm_addr,
2218 };
2219
2220 static int nv_open(struct net_device *dev)
2221 {
2222         struct fe_priv *np = netdev_priv(dev);
2223         u8 __iomem *base = get_hwbase(dev);
2224         int ret, oom, i;
2225
2226         dprintk(KERN_DEBUG "nv_open: begin\n");
2227
2228         /* 1) erase previous misconfiguration */
2229         /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
2230         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2231         writel(0, base + NvRegMulticastAddrB);
2232         writel(0, base + NvRegMulticastMaskA);
2233         writel(0, base + NvRegMulticastMaskB);
2234         writel(0, base + NvRegPacketFilterFlags);
2235
2236         writel(0, base + NvRegTransmitterControl);
2237         writel(0, base + NvRegReceiverControl);
2238
2239         writel(0, base + NvRegAdapterControl);
2240
2241         /* 2) initialize descriptor rings */
2242         set_bufsize(dev);
2243         oom = nv_init_ring(dev);
2244
2245         writel(0, base + NvRegLinkSpeed);
2246         writel(0, base + NvRegUnknownTransmitterReg);
2247         nv_txrx_reset(dev);
2248         writel(0, base + NvRegUnknownSetupReg6);
2249
2250         np->in_shutdown = 0;
2251
2252         /* 3) set mac address */
2253         nv_copy_mac_to_hw(dev);
2254
2255         /* 4) give hw rings */
2256         writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
2257         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2258                 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
2259         else
2260                 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
2261         writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
2262                 base + NvRegRingSizes);
2263
2264         /* 5) continue setup */
2265         writel(np->linkspeed, base + NvRegLinkSpeed);
2266         writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
2267         writel(np->txrxctl_bits, base + NvRegTxRxControl);
2268         pci_push(base);
2269         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
2270         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
2271                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
2272                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
2273
2274         writel(0, base + NvRegUnknownSetupReg4);
2275         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2276         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2277
2278         /* 6) continue setup */
2279         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
2280         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
2281         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
2282         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2283
2284         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
2285         get_random_bytes(&i, sizeof(i));
2286         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
2287         writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
2288         writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
2289         if (poll_interval == -1) {
2290                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
2291                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
2292                 else
2293                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
2294         }
2295         else
2296                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
2297         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
2298         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
2299                         base + NvRegAdapterControl);
2300         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
2301         writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
2302         writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
2303
2304         i = readl(base + NvRegPowerState);
2305         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
2306                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
2307
2308         pci_push(base);
2309         udelay(10);
2310         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
2311
2312         writel(0, base + NvRegIrqMask);
2313         pci_push(base);
2314         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2315         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2316         pci_push(base);
2317
2318         ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
2319         if (ret)
2320                 goto out_drain;
2321
2322         /* ask for interrupts */
2323         writel(np->irqmask, base + NvRegIrqMask);
2324
2325         spin_lock_irq(&np->lock);
2326         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2327         writel(0, base + NvRegMulticastAddrB);
2328         writel(0, base + NvRegMulticastMaskA);
2329         writel(0, base + NvRegMulticastMaskB);
2330         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
2331         /* One manual link speed update: Interrupts are enabled, future link
2332          * speed changes cause interrupts and are handled by nv_link_irq().
2333          */
2334         {
2335                 u32 miistat;
2336                 miistat = readl(base + NvRegMIIStatus);
2337                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2338                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
2339         }
2340         /* set linkspeed to invalid value, thus force nv_update_linkspeed
2341          * to init hw */
2342         np->linkspeed = 0;
2343         ret = nv_update_linkspeed(dev);
2344         nv_start_rx(dev);
2345         nv_start_tx(dev);
2346         netif_start_queue(dev);
2347         if (ret) {
2348                 netif_carrier_on(dev);
2349         } else {
2350                 printk("%s: no link during initialization.\n", dev->name);
2351                 netif_carrier_off(dev);
2352         }
2353         if (oom)
2354                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2355         spin_unlock_irq(&np->lock);
2356
2357         return 0;
2358 out_drain:
2359         drain_ring(dev);
2360         return ret;
2361 }
2362
2363 static int nv_close(struct net_device *dev)
2364 {
2365         struct fe_priv *np = netdev_priv(dev);
2366         u8 __iomem *base;
2367
2368         spin_lock_irq(&np->lock);
2369         np->in_shutdown = 1;
2370         spin_unlock_irq(&np->lock);
2371         synchronize_irq(dev->irq);
2372
2373         del_timer_sync(&np->oom_kick);
2374         del_timer_sync(&np->nic_poll);
2375
2376         netif_stop_queue(dev);
2377         spin_lock_irq(&np->lock);
2378         nv_stop_tx(dev);
2379         nv_stop_rx(dev);
2380         nv_txrx_reset(dev);
2381
2382         /* disable interrupts on the nic or we will lock up */
2383         base = get_hwbase(dev);
2384         writel(0, base + NvRegIrqMask);
2385         pci_push(base);
2386         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
2387
2388         spin_unlock_irq(&np->lock);
2389
2390         free_irq(dev->irq, dev);
2391
2392         drain_ring(dev);
2393
2394         if (np->wolenabled)
2395                 nv_start_rx(dev);
2396
2397         /* special op: write back the misordered MAC address - otherwise
2398          * the next nv_probe would see a wrong address.
2399          */
2400         writel(np->orig_mac[0], base + NvRegMacAddrA);
2401         writel(np->orig_mac[1], base + NvRegMacAddrB);
2402
2403         /* FIXME: power down nic */
2404
2405         return 0;
2406 }
2407
2408 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
2409 {
2410         struct net_device *dev;
2411         struct fe_priv *np;
2412         unsigned long addr;
2413         u8 __iomem *base;
2414         int err, i;
2415
2416         dev = alloc_etherdev(sizeof(struct fe_priv));
2417         err = -ENOMEM;
2418         if (!dev)
2419                 goto out;
2420
2421         np = netdev_priv(dev);
2422         np->pci_dev = pci_dev;
2423         spin_lock_init(&np->lock);
2424         SET_MODULE_OWNER(dev);
2425         SET_NETDEV_DEV(dev, &pci_dev->dev);
2426
2427         init_timer(&np->oom_kick);
2428         np->oom_kick.data = (unsigned long) dev;
2429         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
2430         init_timer(&np->nic_poll);
2431         np->nic_poll.data = (unsigned long) dev;
2432         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
2433
2434         err = pci_enable_device(pci_dev);
2435         if (err) {
2436                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
2437                                 err, pci_name(pci_dev));
2438                 goto out_free;
2439         }
2440
2441         pci_set_master(pci_dev);
2442
2443         err = pci_request_regions(pci_dev, DRV_NAME);
2444         if (err < 0)
2445                 goto out_disable;
2446
2447         err = -EINVAL;
2448         addr = 0;
2449         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2450                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
2451                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
2452                                 pci_resource_len(pci_dev, i),
2453                                 pci_resource_flags(pci_dev, i));
2454                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
2455                                 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
2456                         addr = pci_resource_start(pci_dev, i);
2457                         break;
2458                 }
2459         }
2460         if (i == DEVICE_COUNT_RESOURCE) {
2461                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
2462                                         pci_name(pci_dev));
2463                 goto out_relreg;
2464         }
2465
2466         /* handle different descriptor versions */
2467         if (id->driver_data & DEV_HAS_HIGH_DMA) {
2468                 /* packet format 3: supports 40-bit addressing */
2469                 np->desc_ver = DESC_VER_3;
2470                 if (pci_set_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
2471                         printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
2472                                         pci_name(pci_dev));
2473                 } else {
2474                         dev->features |= NETIF_F_HIGHDMA;
2475                 }
2476                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
2477         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
2478                 /* packet format 2: supports jumbo frames */
2479                 np->desc_ver = DESC_VER_2;
2480                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
2481         } else {
2482                 /* original packet format */
2483                 np->desc_ver = DESC_VER_1;
2484                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
2485         }
2486
2487         np->pkt_limit = NV_PKTLIMIT_1;
2488         if (id->driver_data & DEV_HAS_LARGEDESC)
2489                 np->pkt_limit = NV_PKTLIMIT_2;
2490
2491         if (id->driver_data & DEV_HAS_CHECKSUM) {
2492                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
2493                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
2494 #ifdef NETIF_F_TSO
2495                 dev->features |= NETIF_F_TSO;
2496 #endif
2497         }
2498
2499         err = -ENOMEM;
2500         np->base = ioremap(addr, NV_PCI_REGSZ);
2501         if (!np->base)
2502                 goto out_relreg;
2503         dev->base_addr = (unsigned long)np->base;
2504
2505         dev->irq = pci_dev->irq;
2506
2507         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2508                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
2509                                         sizeof(struct ring_desc) * (RX_RING + TX_RING),
2510                                         &np->ring_addr);
2511                 if (!np->rx_ring.orig)
2512                         goto out_unmap;
2513                 np->tx_ring.orig = &np->rx_ring.orig[RX_RING];
2514         } else {
2515                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
2516                                         sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2517                                         &np->ring_addr);
2518                 if (!np->rx_ring.ex)
2519                         goto out_unmap;
2520                 np->tx_ring.ex = &np->rx_ring.ex[RX_RING];
2521         }
2522
2523         dev->open = nv_open;
2524         dev->stop = nv_close;
2525         dev->hard_start_xmit = nv_start_xmit;
2526         dev->get_stats = nv_get_stats;
2527         dev->change_mtu = nv_change_mtu;
2528         dev->set_mac_address = nv_set_mac_address;
2529         dev->set_multicast_list = nv_set_multicast;
2530 #ifdef CONFIG_NET_POLL_CONTROLLER
2531         dev->poll_controller = nv_poll_controller;
2532 #endif
2533         SET_ETHTOOL_OPS(dev, &ops);
2534         dev->tx_timeout = nv_tx_timeout;
2535         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
2536
2537         pci_set_drvdata(pci_dev, dev);
2538
2539         /* read the mac address */
2540         base = get_hwbase(dev);
2541         np->orig_mac[0] = readl(base + NvRegMacAddrA);
2542         np->orig_mac[1] = readl(base + NvRegMacAddrB);
2543
2544         dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
2545         dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
2546         dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
2547         dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
2548         dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
2549         dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
2550         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2551
2552         if (!is_valid_ether_addr(dev->perm_addr)) {
2553                 /*
2554                  * Bad mac address. At least one bios sets the mac address
2555                  * to 01:23:45:67:89:ab
2556                  */
2557                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
2558                         pci_name(pci_dev),
2559                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2560                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2561                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
2562                 dev->dev_addr[0] = 0x00;
2563                 dev->dev_addr[1] = 0x00;
2564                 dev->dev_addr[2] = 0x6c;
2565                 get_random_bytes(&dev->dev_addr[3], 3);
2566         }
2567
2568         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
2569                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2570                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2571
2572         /* disable WOL */
2573         writel(0, base + NvRegWakeUpFlags);
2574         np->wolenabled = 0;
2575
2576         if (np->desc_ver == DESC_VER_1) {
2577                 np->tx_flags = NV_TX_VALID;
2578         } else {
2579                 np->tx_flags = NV_TX2_VALID;
2580         }
2581         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
2582                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
2583         else
2584                 np->irqmask = NVREG_IRQMASK_CPU;
2585
2586         if (id->driver_data & DEV_NEED_TIMERIRQ)
2587                 np->irqmask |= NVREG_IRQ_TIMER;
2588         if (id->driver_data & DEV_NEED_LINKTIMER) {
2589                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
2590                 np->need_linktimer = 1;
2591                 np->link_timeout = jiffies + LINK_TIMEOUT;
2592         } else {
2593                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
2594                 np->need_linktimer = 0;
2595         }
2596
2597         /* find a suitable phy */
2598         for (i = 1; i <= 32; i++) {
2599                 int id1, id2;
2600                 int phyaddr = i & 0x1F;
2601
2602                 spin_lock_irq(&np->lock);
2603                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
2604                 spin_unlock_irq(&np->lock);
2605                 if (id1 < 0 || id1 == 0xffff)
2606                         continue;
2607                 spin_lock_irq(&np->lock);
2608                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
2609                 spin_unlock_irq(&np->lock);
2610                 if (id2 < 0 || id2 == 0xffff)
2611                         continue;
2612
2613                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
2614                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
2615                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
2616                         pci_name(pci_dev), id1, id2, phyaddr);
2617                 np->phyaddr = phyaddr;
2618                 np->phy_oui = id1 | id2;
2619                 break;
2620         }
2621         if (i == 33) {
2622                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
2623                        pci_name(pci_dev));
2624                 goto out_freering;
2625         }
2626
2627         /* reset it */
2628         phy_init(dev);
2629
2630         /* set default link speed settings */
2631         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2632         np->duplex = 0;
2633         np->autoneg = 1;
2634
2635         err = register_netdev(dev);
2636         if (err) {
2637                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
2638                 goto out_freering;
2639         }
2640         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
2641                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
2642                         pci_name(pci_dev));
2643
2644         return 0;
2645
2646 out_freering:
2647         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2648                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2649                                     np->rx_ring.orig, np->ring_addr);
2650         else
2651                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2652                                     np->rx_ring.ex, np->ring_addr);
2653         pci_set_drvdata(pci_dev, NULL);
2654 out_unmap:
2655         iounmap(get_hwbase(dev));
2656 out_relreg:
2657         pci_release_regions(pci_dev);
2658 out_disable:
2659         pci_disable_device(pci_dev);
2660 out_free:
2661         free_netdev(dev);
2662 out:
2663         return err;
2664 }
2665
2666 static void __devexit nv_remove(struct pci_dev *pci_dev)
2667 {
2668         struct net_device *dev = pci_get_drvdata(pci_dev);
2669         struct fe_priv *np = netdev_priv(dev);
2670
2671         unregister_netdev(dev);
2672
2673         /* free all structures */
2674         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2675                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring.orig, np->ring_addr);
2676         else
2677                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), np->rx_ring.ex, np->ring_addr);
2678         iounmap(get_hwbase(dev));
2679         pci_release_regions(pci_dev);
2680         pci_disable_device(pci_dev);
2681         free_netdev(dev);
2682         pci_set_drvdata(pci_dev, NULL);
2683 }
2684
2685 static struct pci_device_id pci_tbl[] = {
2686         {       /* nForce Ethernet Controller */
2687                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
2688                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2689         },
2690         {       /* nForce2 Ethernet Controller */
2691                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
2692                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2693         },
2694         {       /* nForce3 Ethernet Controller */
2695                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
2696                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2697         },
2698         {       /* nForce3 Ethernet Controller */
2699                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
2700                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2701         },
2702         {       /* nForce3 Ethernet Controller */
2703                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
2704                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2705         },
2706         {       /* nForce3 Ethernet Controller */
2707                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
2708                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2709         },
2710         {       /* nForce3 Ethernet Controller */
2711                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
2712                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2713         },
2714         {       /* CK804 Ethernet Controller */
2715                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
2716                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2717         },
2718         {       /* CK804 Ethernet Controller */
2719                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
2720                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2721         },
2722         {       /* MCP04 Ethernet Controller */
2723                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
2724                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2725         },
2726         {       /* MCP04 Ethernet Controller */
2727                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
2728                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2729         },
2730         {       /* MCP51 Ethernet Controller */
2731                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
2732                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2733         },
2734         {       /* MCP51 Ethernet Controller */
2735                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
2736                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2737         },
2738         {       /* MCP55 Ethernet Controller */
2739                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
2740                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2741         },
2742         {       /* MCP55 Ethernet Controller */
2743                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
2744                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2745         },
2746         {0,},
2747 };
2748
2749 static struct pci_driver driver = {
2750         .name = "forcedeth",
2751         .id_table = pci_tbl,
2752         .probe = nv_probe,
2753         .remove = __devexit_p(nv_remove),
2754 };
2755
2756
2757 static int __init init_nic(void)
2758 {
2759         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
2760         return pci_module_init(&driver);
2761 }
2762
2763 static void __exit exit_nic(void)
2764 {
2765         pci_unregister_driver(&driver);
2766 }
2767
2768 module_param(max_interrupt_work, int, 0);
2769 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2770 module_param(optimization_mode, int, 0);
2771 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
2772 module_param(poll_interval, int, 0);
2773 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
2774
2775 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2776 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2777 MODULE_LICENSE("GPL");
2778
2779 MODULE_DEVICE_TABLE(pci, pci_tbl);
2780
2781 module_init(init_nic);
2782 module_exit(exit_nic);