2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
13 * Copyright (C) 2003 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 * 0.01: 05 Oct 2003: First release that compiles without warnings.
32 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
33 * Check all PCI BARs for the register window.
34 * udelay added to mii_rw.
35 * 0.03: 06 Oct 2003: Initialize dev->irq.
36 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
37 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
38 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
40 * 0.07: 14 Oct 2003: Further irq mask updates.
41 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
42 * added into irq handler, NULL check for drain_ring.
43 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
44 * requested interrupt sources.
45 * 0.10: 20 Oct 2003: First cleanup for release.
46 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
47 * MAC Address init fix, set_multicast cleanup.
48 * 0.12: 23 Oct 2003: Cleanups for release.
49 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
50 * Set link speed correctly. start rx before starting
51 * tx (nv_start_rx sets the link speed).
52 * 0.14: 25 Oct 2003: Nic dependant irq mask.
53 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
55 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
56 * increased to 1628 bytes.
57 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
59 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
60 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
61 * addresses, really stop rx if already running
62 * in nv_start_rx, clean up a bit.
63 * (C) Carl-Daniel Hailfinger
64 * 0.20: 07 Dec 2003: alloc fixes
65 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
66 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
68 * (C) Carl-Daniel Hailfinger, Manfred Spraul
69 * 0.23: 26 Jan 2004: various small cleanups
70 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
71 * 0.25: 09 Mar 2004: wol support
74 * We suspect that on some hardware no TX done interrupts are generated.
75 * This means recovery from netif_stop_queue only happens if the hw timer
76 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
77 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
78 * If your hardware reliably generates tx done interrupts, then you can remove
79 * DEV_NEED_TIMERIRQ from the driver_data flags.
80 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
81 * superfluous timer interrupts from the nic.
83 #define FORCEDETH_VERSION "0.25"
84 #define DRV_NAME "forcedeth"
86 #include <linux/module.h>
87 #include <linux/types.h>
88 #include <linux/pci.h>
89 #include <linux/interrupt.h>
90 #include <linux/netdevice.h>
91 #include <linux/etherdevice.h>
92 #include <linux/delay.h>
93 #include <linux/spinlock.h>
94 #include <linux/ethtool.h>
95 #include <linux/timer.h>
96 #include <linux/skbuff.h>
97 #include <linux/mii.h>
98 #include <linux/random.h>
99 #include <linux/init.h>
103 #include <asm/uaccess.h>
104 #include <asm/system.h>
107 #define dprintk printk
109 #define dprintk(x...) do { } while (0)
117 #define DEV_NEED_LASTPACKET1 0x0001
118 #define DEV_IRQMASK_1 0x0002
119 #define DEV_IRQMASK_2 0x0004
120 #define DEV_NEED_TIMERIRQ 0x0008
123 NvRegIrqStatus = 0x000,
124 #define NVREG_IRQSTAT_MIIEVENT 0x040
125 #define NVREG_IRQSTAT_MASK 0x1ff
126 NvRegIrqMask = 0x004,
127 #define NVREG_IRQ_RX 0x0002
128 #define NVREG_IRQ_RX_NOBUF 0x0004
129 #define NVREG_IRQ_TX_ERR 0x0008
130 #define NVREG_IRQ_TX2 0x0010
131 #define NVREG_IRQ_TIMER 0x0020
132 #define NVREG_IRQ_LINK 0x0040
133 #define NVREG_IRQ_TX1 0x0100
134 #define NVREG_IRQMASK_WANTED_1 0x005f
135 #define NVREG_IRQMASK_WANTED_2 0x0147
136 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
138 NvRegUnknownSetupReg6 = 0x008,
139 #define NVREG_UNKSETUP6_VAL 3
142 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
143 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
145 NvRegPollingInterval = 0x00c,
146 #define NVREG_POLL_DEFAULT 970
148 #define NVREG_MISC1_HD 0x02
149 #define NVREG_MISC1_FORCE 0x3b0f3c
151 NvRegTransmitterControl = 0x084,
152 #define NVREG_XMITCTL_START 0x01
153 NvRegTransmitterStatus = 0x088,
154 #define NVREG_XMITSTAT_BUSY 0x01
156 NvRegPacketFilterFlags = 0x8c,
157 #define NVREG_PFF_ALWAYS 0x7F0008
158 #define NVREG_PFF_PROMISC 0x80
159 #define NVREG_PFF_MYADDR 0x20
161 NvRegOffloadConfig = 0x90,
162 #define NVREG_OFFLOAD_HOMEPHY 0x601
163 #define NVREG_OFFLOAD_NORMAL 0x5ee
164 NvRegReceiverControl = 0x094,
165 #define NVREG_RCVCTL_START 0x01
166 NvRegReceiverStatus = 0x98,
167 #define NVREG_RCVSTAT_BUSY 0x01
169 NvRegRandomSeed = 0x9c,
170 #define NVREG_RNDSEED_MASK 0x00ff
171 #define NVREG_RNDSEED_FORCE 0x7f00
173 NvRegUnknownSetupReg1 = 0xA0,
174 #define NVREG_UNKSETUP1_VAL 0x16070f
175 NvRegUnknownSetupReg2 = 0xA4,
176 #define NVREG_UNKSETUP2_VAL 0x16
177 NvRegMacAddrA = 0xA8,
178 NvRegMacAddrB = 0xAC,
179 NvRegMulticastAddrA = 0xB0,
180 #define NVREG_MCASTADDRA_FORCE 0x01
181 NvRegMulticastAddrB = 0xB4,
182 NvRegMulticastMaskA = 0xB8,
183 NvRegMulticastMaskB = 0xBC,
185 NvRegTxRingPhysAddr = 0x100,
186 NvRegRxRingPhysAddr = 0x104,
187 NvRegRingSizes = 0x108,
188 #define NVREG_RINGSZ_TXSHIFT 0
189 #define NVREG_RINGSZ_RXSHIFT 16
190 NvRegUnknownTransmitterReg = 0x10c,
191 NvRegLinkSpeed = 0x110,
192 #define NVREG_LINKSPEED_FORCE 0x10000
193 #define NVREG_LINKSPEED_10 10
194 #define NVREG_LINKSPEED_100 100
195 #define NVREG_LINKSPEED_1000 1000
196 NvRegUnknownSetupReg5 = 0x130,
197 #define NVREG_UNKSETUP5_BIT31 (1<<31)
198 NvRegUnknownSetupReg3 = 0x134,
199 #define NVREG_UNKSETUP3_VAL1 0x200010
200 NvRegTxRxControl = 0x144,
201 #define NVREG_TXRXCTL_KICK 0x0001
202 #define NVREG_TXRXCTL_BIT1 0x0002
203 #define NVREG_TXRXCTL_BIT2 0x0004
204 #define NVREG_TXRXCTL_IDLE 0x0008
205 #define NVREG_TXRXCTL_RESET 0x0010
206 NvRegMIIStatus = 0x180,
207 #define NVREG_MIISTAT_ERROR 0x0001
208 #define NVREG_MIISTAT_LINKCHANGE 0x0008
209 #define NVREG_MIISTAT_MASK 0x000f
210 #define NVREG_MIISTAT_MASK2 0x000f
211 NvRegUnknownSetupReg4 = 0x184,
212 #define NVREG_UNKSETUP4_VAL 8
214 NvRegAdapterControl = 0x188,
215 #define NVREG_ADAPTCTL_START 0x02
216 #define NVREG_ADAPTCTL_LINKUP 0x04
217 #define NVREG_ADAPTCTL_PHYVALID 0x4000
218 #define NVREG_ADAPTCTL_RUNNING 0x100000
219 #define NVREG_ADAPTCTL_PHYSHIFT 24
220 NvRegMIISpeed = 0x18c,
221 #define NVREG_MIISPEED_BIT8 (1<<8)
222 #define NVREG_MIIDELAY 5
223 NvRegMIIControl = 0x190,
224 #define NVREG_MIICTL_INUSE 0x10000
225 #define NVREG_MIICTL_WRITE 0x08000
226 #define NVREG_MIICTL_ADDRSHIFT 5
227 NvRegMIIData = 0x194,
228 NvRegWakeUpFlags = 0x200,
229 #define NVREG_WAKEUPFLAGS_VAL 0x7770
230 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
231 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
232 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
233 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
234 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
235 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
236 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
237 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
238 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
239 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
241 NvRegPatternCRC = 0x204,
242 NvRegPatternMask = 0x208,
243 NvRegPowerCap = 0x268,
244 #define NVREG_POWERCAP_D3SUPP (1<<30)
245 #define NVREG_POWERCAP_D2SUPP (1<<26)
246 #define NVREG_POWERCAP_D1SUPP (1<<25)
247 NvRegPowerState = 0x26c,
248 #define NVREG_POWERSTATE_POWEREDUP 0x8000
249 #define NVREG_POWERSTATE_VALID 0x0100
250 #define NVREG_POWERSTATE_MASK 0x0003
251 #define NVREG_POWERSTATE_D0 0x0000
252 #define NVREG_POWERSTATE_D1 0x0001
253 #define NVREG_POWERSTATE_D2 0x0002
254 #define NVREG_POWERSTATE_D3 0x0003
263 #define NV_TX_LASTPACKET (1<<0)
264 #define NV_TX_RETRYERROR (1<<3)
265 #define NV_TX_LASTPACKET1 (1<<8)
266 #define NV_TX_DEFERRED (1<<10)
267 #define NV_TX_CARRIERLOST (1<<11)
268 #define NV_TX_LATECOLLISION (1<<12)
269 #define NV_TX_UNDERFLOW (1<<13)
270 #define NV_TX_ERROR (1<<14)
271 #define NV_TX_VALID (1<<15)
273 #define NV_RX_DESCRIPTORVALID (1<<0)
274 #define NV_RX_MISSEDFRAME (1<<1)
275 #define NV_RX_SUBSTRACT1 (1<<3)
276 #define NV_RX_ERROR1 (1<<7)
277 #define NV_RX_ERROR2 (1<<8)
278 #define NV_RX_ERROR3 (1<<9)
279 #define NV_RX_ERROR4 (1<<10)
280 #define NV_RX_CRCERR (1<<11)
281 #define NV_RX_OVERFLOW (1<<12)
282 #define NV_RX_FRAMINGERR (1<<13)
283 #define NV_RX_ERROR (1<<14)
284 #define NV_RX_AVAIL (1<<15)
286 /* Miscelaneous hardware related defines: */
287 #define NV_PCI_REGSZ 0x270
289 /* various timeout delays: all in usec */
290 #define NV_TXRX_RESET_DELAY 4
291 #define NV_TXSTOP_DELAY1 10
292 #define NV_TXSTOP_DELAY1MAX 500000
293 #define NV_TXSTOP_DELAY2 100
294 #define NV_RXSTOP_DELAY1 10
295 #define NV_RXSTOP_DELAY1MAX 500000
296 #define NV_RXSTOP_DELAY2 100
297 #define NV_SETUP5_DELAY 5
298 #define NV_SETUP5_DELAYMAX 50000
299 #define NV_POWERUP_DELAY 5
300 #define NV_POWERUP_DELAYMAX 5000
301 #define NV_MIIBUSY_DELAY 50
302 #define NV_MIIPHY_DELAY 10
303 #define NV_MIIPHY_DELAYMAX 10000
305 #define NV_WAKEUPPATTERNS 5
306 #define NV_WAKEUPMASKENTRIES 4
308 /* General driver defaults */
309 #define NV_WATCHDOG_TIMEO (5*HZ)
310 #define DEFAULT_MTU 1500 /* also maximum supported, at least for now */
314 /* limited to 1 packet until we understand NV_TX_LASTPACKET */
315 #define TX_LIMIT_STOP 10
316 #define TX_LIMIT_START 5
318 /* rx/tx mac addr + type + vlan + align + slack*/
319 #define RX_NIC_BUFSIZE (DEFAULT_MTU + 64)
320 /* even more slack */
321 #define RX_ALLOC_BUFSIZE (DEFAULT_MTU + 128)
323 #define OOM_REFILL (1+HZ/20)
324 #define POLL_WAIT (1+HZ/100)
328 * All hardware access under dev->priv->lock, except the performance
330 * - rx is (pseudo-) lockless: it relies on the single-threading provided
331 * by the arch code for interrupts.
332 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
333 * needs dev->priv->lock :-(
334 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
337 /* in dev: base, irq */
342 * Locking: spin_lock(&np->lock); */
343 struct net_device_stats stats;
350 /* General data: RO fields */
351 dma_addr_t ring_addr;
352 struct pci_dev *pci_dev;
356 /* rx specific fields.
357 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
359 struct ring_desc *rx_ring;
360 unsigned int cur_rx, refill_rx;
361 struct sk_buff *rx_skbuff[RX_RING];
362 dma_addr_t rx_dma[RX_RING];
363 unsigned int rx_buf_sz;
364 struct timer_list oom_kick;
365 struct timer_list nic_poll;
368 * tx specific fields.
370 struct ring_desc *tx_ring;
371 unsigned int next_tx, nic_tx;
372 struct sk_buff *tx_skbuff[TX_RING];
373 dma_addr_t tx_dma[TX_RING];
378 * Maximum number of loops until we assume that a bit in the irq mask
379 * is stuck. Overridable with module param.
381 static int max_interrupt_work = 5;
383 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
385 return (struct fe_priv *) dev->priv;
388 static inline u8 *get_hwbase(struct net_device *dev)
390 return (u8 *) dev->base_addr;
393 static inline void pci_push(u8 * base)
395 /* force out pending posted writes */
399 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
400 int delay, int delaymax, const char *msg)
402 u8 *base = get_hwbase(dev);
413 } while ((readl(base + offset) & mask) != target);
417 #define MII_READ (-1)
418 /* mii_rw: read/write a register on the PHY.
420 * Caller must guarantee serialization
422 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
424 u8 *base = get_hwbase(dev);
429 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
431 reg = readl(base + NvRegAdapterControl);
432 if (reg & NVREG_ADAPTCTL_RUNNING) {
434 writel(reg & ~NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
436 reg = readl(base + NvRegMIIControl);
437 if (reg & NVREG_MIICTL_INUSE) {
438 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
439 udelay(NV_MIIBUSY_DELAY);
442 reg = NVREG_MIICTL_INUSE | (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
443 if (value != MII_READ) {
444 writel(value, base + NvRegMIIData);
445 reg |= NVREG_MIICTL_WRITE;
447 writel(reg, base + NvRegMIIControl);
449 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
450 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
451 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
452 dev->name, miireg, addr);
454 } else if (value != MII_READ) {
455 /* it was a write operation - fewer failures are detectable */
456 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
457 dev->name, value, miireg, addr);
459 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
460 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
461 dev->name, miireg, addr);
464 /* FIXME: why is that required? */
466 retval = readl(base + NvRegMIIData);
467 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
468 dev->name, miireg, addr, retval);
471 reg = readl(base + NvRegAdapterControl);
472 writel(reg | NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
477 static void nv_start_rx(struct net_device *dev)
479 struct fe_priv *np = get_nvpriv(dev);
480 u8 *base = get_hwbase(dev);
482 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
483 /* Already running? Stop it. */
484 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
485 writel(0, base + NvRegReceiverControl);
488 writel(np->linkspeed, base + NvRegLinkSpeed);
490 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
494 static void nv_stop_rx(struct net_device *dev)
496 u8 *base = get_hwbase(dev);
498 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
499 writel(0, base + NvRegReceiverControl);
500 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
501 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
502 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
504 udelay(NV_RXSTOP_DELAY2);
505 writel(0, base + NvRegLinkSpeed);
508 static void nv_start_tx(struct net_device *dev)
510 u8 *base = get_hwbase(dev);
512 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
513 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
517 static void nv_stop_tx(struct net_device *dev)
519 u8 *base = get_hwbase(dev);
521 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
522 writel(0, base + NvRegTransmitterControl);
523 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
524 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
525 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
527 udelay(NV_TXSTOP_DELAY2);
528 writel(0, base + NvRegUnknownTransmitterReg);
531 static void nv_txrx_reset(struct net_device *dev)
533 u8 *base = get_hwbase(dev);
535 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
536 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET, base + NvRegTxRxControl);
538 udelay(NV_TXRX_RESET_DELAY);
539 writel(NVREG_TXRXCTL_BIT2, base + NvRegTxRxControl);
544 * nv_get_stats: dev->get_stats function
545 * Get latest stats value from the nic.
546 * Called with read_lock(&dev_base_lock) held for read -
547 * only synchronized against unregister_netdevice.
549 static struct net_device_stats *nv_get_stats(struct net_device *dev)
551 struct fe_priv *np = get_nvpriv(dev);
553 /* It seems that the nic always generates interrupts and doesn't
554 * accumulate errors internally. Thus the current values in np->stats
555 * are already up to date.
560 static int nv_ethtool_ioctl(struct net_device *dev, void __user *useraddr)
562 struct fe_priv *np = get_nvpriv(dev);
563 u8 *base = get_hwbase(dev);
566 if (copy_from_user(ðcmd, useraddr, sizeof (ethcmd)))
570 case ETHTOOL_GDRVINFO:
572 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
573 strcpy(info.driver, "forcedeth");
574 strcpy(info.version, FORCEDETH_VERSION);
575 strcpy(info.bus_info, pci_name(np->pci_dev));
576 if (copy_to_user(useraddr, &info, sizeof (info)))
582 struct ethtool_value edata = { ETHTOOL_GLINK };
584 edata.data = !!netif_carrier_ok(dev);
586 if (copy_to_user(useraddr, &edata, sizeof(edata)))
592 struct ethtool_wolinfo wolinfo;
593 memset(&wolinfo, 0, sizeof(wolinfo));
594 wolinfo.supported = WAKE_MAGIC;
596 spin_lock_irq(&np->lock);
598 wolinfo.wolopts = WAKE_MAGIC;
599 spin_unlock_irq(&np->lock);
601 if (copy_to_user(useraddr, &wolinfo, sizeof(wolinfo)))
607 struct ethtool_wolinfo wolinfo;
608 if (copy_from_user(&wolinfo, useraddr, sizeof(wolinfo)))
611 spin_lock_irq(&np->lock);
612 if (wolinfo.wolopts == 0) {
613 writel(0, base + NvRegWakeUpFlags);
616 if (wolinfo.wolopts & WAKE_MAGIC) {
617 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
620 spin_unlock_irq(&np->lock);
631 * nv_ioctl: dev->do_ioctl function
632 * Called with rtnl_lock held.
634 static int nv_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
638 return nv_ethtool_ioctl(dev, rq->ifr_data);
646 * nv_alloc_rx: fill rx ring entries.
647 * Return 1 if the allocations for the skbs failed and the
648 * rx engine is without Available descriptors
650 static int nv_alloc_rx(struct net_device *dev)
652 struct fe_priv *np = get_nvpriv(dev);
653 unsigned int refill_rx = np->refill_rx;
655 while (np->cur_rx != refill_rx) {
656 int nr = refill_rx % RX_RING;
659 if (np->rx_skbuff[nr] == NULL) {
661 skb = dev_alloc_skb(RX_ALLOC_BUFSIZE);
666 np->rx_skbuff[nr] = skb;
668 skb = np->rx_skbuff[nr];
670 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
672 np->rx_ring[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
673 np->rx_ring[nr].Length = cpu_to_le16(RX_NIC_BUFSIZE);
675 np->rx_ring[nr].Flags = cpu_to_le16(NV_RX_AVAIL);
676 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
677 dev->name, refill_rx);
680 np->refill_rx = refill_rx;
681 if (np->cur_rx - refill_rx == RX_RING)
686 static void nv_do_rx_refill(unsigned long data)
688 struct net_device *dev = (struct net_device *) data;
689 struct fe_priv *np = get_nvpriv(dev);
691 disable_irq(dev->irq);
692 if (nv_alloc_rx(dev)) {
693 spin_lock(&np->lock);
694 if (!np->in_shutdown)
695 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
696 spin_unlock(&np->lock);
698 enable_irq(dev->irq);
701 static int nv_init_ring(struct net_device *dev)
703 struct fe_priv *np = get_nvpriv(dev);
706 np->next_tx = np->nic_tx = 0;
707 for (i = 0; i < TX_RING; i++) {
708 np->tx_ring[i].Flags = 0;
711 np->cur_rx = RX_RING;
713 for (i = 0; i < RX_RING; i++) {
714 np->rx_ring[i].Flags = 0;
716 return nv_alloc_rx(dev);
719 static void nv_drain_tx(struct net_device *dev)
721 struct fe_priv *np = get_nvpriv(dev);
723 for (i = 0; i < TX_RING; i++) {
724 np->tx_ring[i].Flags = 0;
725 if (np->tx_skbuff[i]) {
726 pci_unmap_single(np->pci_dev, np->tx_dma[i],
727 np->tx_skbuff[i]->len,
729 dev_kfree_skb(np->tx_skbuff[i]);
730 np->tx_skbuff[i] = NULL;
731 np->stats.tx_dropped++;
736 static void nv_drain_rx(struct net_device *dev)
738 struct fe_priv *np = get_nvpriv(dev);
740 for (i = 0; i < RX_RING; i++) {
741 np->rx_ring[i].Flags = 0;
743 if (np->rx_skbuff[i]) {
744 pci_unmap_single(np->pci_dev, np->rx_dma[i],
745 np->rx_skbuff[i]->len,
747 dev_kfree_skb(np->rx_skbuff[i]);
748 np->rx_skbuff[i] = NULL;
753 static void drain_ring(struct net_device *dev)
760 * nv_start_xmit: dev->hard_start_xmit function
761 * Called with dev->xmit_lock held.
763 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
765 struct fe_priv *np = get_nvpriv(dev);
766 int nr = np->next_tx % TX_RING;
768 np->tx_skbuff[nr] = skb;
769 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data,skb->len,
772 np->tx_ring[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
773 np->tx_ring[nr].Length = cpu_to_le16(skb->len-1);
775 spin_lock_irq(&np->lock);
777 np->tx_ring[nr].Flags = np->tx_flags;
778 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission.\n",
779 dev->name, np->next_tx);
782 for (j=0; j<64; j++) {
784 dprintk("\n%03x:", j);
785 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
792 dev->trans_start = jiffies;
793 if (np->next_tx - np->nic_tx >= TX_LIMIT_STOP)
794 netif_stop_queue(dev);
795 spin_unlock_irq(&np->lock);
796 writel(NVREG_TXRXCTL_KICK, get_hwbase(dev) + NvRegTxRxControl);
797 pci_push(get_hwbase(dev));
802 * nv_tx_done: check for completed packets, release the skbs.
804 * Caller must own np->lock.
806 static void nv_tx_done(struct net_device *dev)
808 struct fe_priv *np = get_nvpriv(dev);
810 while (np->nic_tx < np->next_tx) {
811 struct ring_desc *prd;
812 int i = np->nic_tx % TX_RING;
814 prd = &np->tx_ring[i];
816 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
817 dev->name, np->nic_tx, prd->Flags);
818 if (prd->Flags & cpu_to_le16(NV_TX_VALID))
820 if (prd->Flags & cpu_to_le16(NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
821 NV_TX_UNDERFLOW|NV_TX_ERROR)) {
822 if (prd->Flags & cpu_to_le16(NV_TX_UNDERFLOW))
823 np->stats.tx_fifo_errors++;
824 if (prd->Flags & cpu_to_le16(NV_TX_CARRIERLOST))
825 np->stats.tx_carrier_errors++;
826 np->stats.tx_errors++;
828 np->stats.tx_packets++;
829 np->stats.tx_bytes += np->tx_skbuff[i]->len;
831 pci_unmap_single(np->pci_dev, np->tx_dma[i],
832 np->tx_skbuff[i]->len,
834 dev_kfree_skb_irq(np->tx_skbuff[i]);
835 np->tx_skbuff[i] = NULL;
838 if (np->next_tx - np->nic_tx < TX_LIMIT_START)
839 netif_wake_queue(dev);
843 * nv_tx_timeout: dev->tx_timeout function
844 * Called with dev->xmit_lock held.
846 static void nv_tx_timeout(struct net_device *dev)
848 struct fe_priv *np = get_nvpriv(dev);
849 u8 *base = get_hwbase(dev);
851 dprintk(KERN_DEBUG "%s: Got tx_timeout. irq: %08x\n", dev->name,
852 readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
854 spin_lock_irq(&np->lock);
856 /* 1) stop tx engine */
859 /* 2) check that the packets were not sent already: */
862 /* 3) if there are dead entries: clear everything */
863 if (np->next_tx != np->nic_tx) {
864 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
866 np->next_tx = np->nic_tx = 0;
867 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
868 netif_wake_queue(dev);
871 /* 4) restart tx engine */
873 spin_unlock_irq(&np->lock);
876 static void nv_rx_process(struct net_device *dev)
878 struct fe_priv *np = get_nvpriv(dev);
881 struct ring_desc *prd;
885 if (np->cur_rx - np->refill_rx >= RX_RING)
886 break; /* we scanned the whole ring - do not continue */
888 i = np->cur_rx % RX_RING;
889 prd = &np->rx_ring[i];
890 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
891 dev->name, np->cur_rx, prd->Flags);
893 if (prd->Flags & cpu_to_le16(NV_RX_AVAIL))
894 break; /* still owned by hardware, */
897 * the packet is for us - immediately tear down the pci mapping.
898 * TODO: check if a prefetch of the first cacheline improves
901 pci_unmap_single(np->pci_dev, np->rx_dma[i],
902 np->rx_skbuff[i]->len,
907 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",prd->Flags);
908 for (j=0; j<64; j++) {
910 dprintk("\n%03x:", j);
911 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
915 /* look at what we actually got: */
916 if (!(prd->Flags & cpu_to_le16(NV_RX_DESCRIPTORVALID)))
920 len = le16_to_cpu(prd->Length);
922 if (prd->Flags & cpu_to_le16(NV_RX_MISSEDFRAME)) {
923 np->stats.rx_missed_errors++;
924 np->stats.rx_errors++;
927 if (prd->Flags & cpu_to_le16(NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4)) {
928 np->stats.rx_errors++;
931 if (prd->Flags & cpu_to_le16(NV_RX_CRCERR)) {
932 np->stats.rx_crc_errors++;
933 np->stats.rx_errors++;
936 if (prd->Flags & cpu_to_le16(NV_RX_OVERFLOW)) {
937 np->stats.rx_over_errors++;
938 np->stats.rx_errors++;
941 if (prd->Flags & cpu_to_le16(NV_RX_ERROR)) {
942 /* framing errors are soft errors, the rest is fatal. */
943 if (prd->Flags & cpu_to_le16(NV_RX_FRAMINGERR)) {
944 if (prd->Flags & cpu_to_le16(NV_RX_SUBSTRACT1)) {
948 np->stats.rx_errors++;
952 /* got a valid packet - forward it to the network core */
953 skb = np->rx_skbuff[i];
954 np->rx_skbuff[i] = NULL;
957 skb->protocol = eth_type_trans(skb, dev);
958 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
959 dev->name, np->cur_rx, len, skb->protocol);
961 dev->last_rx = jiffies;
962 np->stats.rx_packets++;
963 np->stats.rx_bytes += len;
970 * nv_change_mtu: dev->change_mtu function
971 * Called with dev_base_lock held for read.
973 static int nv_change_mtu(struct net_device *dev, int new_mtu)
975 if (new_mtu > DEFAULT_MTU)
982 * nv_set_multicast: dev->set_multicast function
983 * Called with dev->xmit_lock held.
985 static void nv_set_multicast(struct net_device *dev)
987 struct fe_priv *np = get_nvpriv(dev);
988 u8 *base = get_hwbase(dev);
993 memset(addr, 0, sizeof(addr));
994 memset(mask, 0, sizeof(mask));
996 if (dev->flags & IFF_PROMISC) {
997 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
998 pff = NVREG_PFF_PROMISC;
1000 pff = NVREG_PFF_MYADDR;
1002 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1006 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1007 if (dev->flags & IFF_ALLMULTI) {
1008 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1010 struct dev_mc_list *walk;
1012 walk = dev->mc_list;
1013 while (walk != NULL) {
1015 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1016 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1024 addr[0] = alwaysOn[0];
1025 addr[1] = alwaysOn[1];
1026 mask[0] = alwaysOn[0] | alwaysOff[0];
1027 mask[1] = alwaysOn[1] | alwaysOff[1];
1030 addr[0] |= NVREG_MCASTADDRA_FORCE;
1031 pff |= NVREG_PFF_ALWAYS;
1032 spin_lock_irq(&np->lock);
1034 writel(addr[0], base + NvRegMulticastAddrA);
1035 writel(addr[1], base + NvRegMulticastAddrB);
1036 writel(mask[0], base + NvRegMulticastMaskA);
1037 writel(mask[1], base + NvRegMulticastMaskB);
1038 writel(pff, base + NvRegPacketFilterFlags);
1040 spin_unlock_irq(&np->lock);
1043 static int nv_update_linkspeed(struct net_device *dev)
1045 struct fe_priv *np = get_nvpriv(dev);
1046 int adv, lpa, newls, newdup;
1048 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1049 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1050 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1051 dev->name, adv, lpa);
1053 /* FIXME: handle parallel detection properly, handle gigabit ethernet */
1055 if (lpa & LPA_100FULL) {
1056 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1058 } else if (lpa & LPA_100HALF) {
1059 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1061 } else if (lpa & LPA_10FULL) {
1062 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1064 } else if (lpa & LPA_10HALF) {
1065 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1068 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1069 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1072 if (np->duplex != newdup || np->linkspeed != newls) {
1073 np->duplex = newdup;
1074 np->linkspeed = newls;
1080 static void nv_link_irq(struct net_device *dev)
1082 struct fe_priv *np = get_nvpriv(dev);
1083 u8 *base = get_hwbase(dev);
1087 miistat = readl(base + NvRegMIIStatus);
1088 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1089 printk(KERN_DEBUG "%s: link change notification, status 0x%x.\n", dev->name, miistat);
1091 miival = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1092 if (miival & BMSR_ANEGCOMPLETE) {
1093 nv_update_linkspeed(dev);
1095 if (netif_carrier_ok(dev)) {
1098 netif_carrier_on(dev);
1099 printk(KERN_INFO "%s: link up.\n", dev->name);
1101 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1105 if (netif_carrier_ok(dev)) {
1106 netif_carrier_off(dev);
1107 printk(KERN_INFO "%s: link down.\n", dev->name);
1110 writel(np->linkspeed, base + NvRegLinkSpeed);
1115 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1117 struct net_device *dev = (struct net_device *) data;
1118 struct fe_priv *np = get_nvpriv(dev);
1119 u8 *base = get_hwbase(dev);
1123 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1126 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1127 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1129 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1130 if (!(events & np->irqmask))
1133 if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX2|NVREG_IRQ_TX_ERR)) {
1134 spin_lock(&np->lock);
1136 spin_unlock(&np->lock);
1139 if (events & (NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF)) {
1141 if (nv_alloc_rx(dev)) {
1142 spin_lock(&np->lock);
1143 if (!np->in_shutdown)
1144 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1145 spin_unlock(&np->lock);
1149 if (events & NVREG_IRQ_LINK) {
1150 spin_lock(&np->lock);
1152 spin_unlock(&np->lock);
1154 if (events & (NVREG_IRQ_TX_ERR)) {
1155 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1158 if (events & (NVREG_IRQ_UNKNOWN)) {
1159 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1162 if (i > max_interrupt_work) {
1163 spin_lock(&np->lock);
1164 /* disable interrupts on the nic */
1165 writel(0, base + NvRegIrqMask);
1168 if (!np->in_shutdown)
1169 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1170 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1171 spin_unlock(&np->lock);
1176 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1178 return IRQ_RETVAL(i);
1181 static void nv_do_nic_poll(unsigned long data)
1183 struct net_device *dev = (struct net_device *) data;
1184 struct fe_priv *np = get_nvpriv(dev);
1185 u8 *base = get_hwbase(dev);
1187 disable_irq(dev->irq);
1188 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1190 * reenable interrupts on the nic, we have to do this before calling
1191 * nv_nic_irq because that may decide to do otherwise
1193 writel(np->irqmask, base + NvRegIrqMask);
1195 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1196 enable_irq(dev->irq);
1199 static int nv_open(struct net_device *dev)
1201 struct fe_priv *np = get_nvpriv(dev);
1202 u8 *base = get_hwbase(dev);
1205 dprintk(KERN_DEBUG "nv_open: begin\n");
1207 /* 1) erase previous misconfiguration */
1208 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
1209 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1210 writel(0, base + NvRegMulticastAddrB);
1211 writel(0, base + NvRegMulticastMaskA);
1212 writel(0, base + NvRegMulticastMaskB);
1213 writel(0, base + NvRegPacketFilterFlags);
1214 writel(0, base + NvRegAdapterControl);
1215 writel(0, base + NvRegLinkSpeed);
1216 writel(0, base + NvRegUnknownTransmitterReg);
1218 writel(0, base + NvRegUnknownSetupReg6);
1220 /* 2) initialize descriptor rings */
1221 np->in_shutdown = 0;
1222 oom = nv_init_ring(dev);
1224 /* 3) set mac address */
1228 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1229 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1230 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1232 writel(mac[0], base + NvRegMacAddrA);
1233 writel(mac[1], base + NvRegMacAddrB);
1236 /* 4) continue setup */
1237 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1239 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
1240 writel(0, base + NvRegTxRxControl);
1242 writel(NVREG_TXRXCTL_BIT1, base + NvRegTxRxControl);
1243 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
1244 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
1245 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
1246 writel(0, base + NvRegUnknownSetupReg4);
1248 /* 5) Find a suitable PHY */
1249 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
1250 for (i = 1; i < 32; i++) {
1253 spin_lock_irq(&np->lock);
1254 id1 = mii_rw(dev, i, MII_PHYSID1, MII_READ);
1255 spin_unlock_irq(&np->lock);
1256 if (id1 < 0 || id1 == 0xffff)
1258 spin_lock_irq(&np->lock);
1259 id2 = mii_rw(dev, i, MII_PHYSID2, MII_READ);
1260 spin_unlock_irq(&np->lock);
1261 if (id2 < 0 || id2 == 0xffff)
1263 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
1264 dev->name, id1, id2, i);
1267 spin_lock_irq(&np->lock);
1268 nv_update_linkspeed(dev);
1269 spin_unlock_irq(&np->lock);
1274 printk(KERN_INFO "%s: open: failing due to lack of suitable PHY.\n",
1280 /* 6) continue setup */
1281 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1283 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
1284 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
1285 writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig);
1287 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
1288 get_random_bytes(&i, sizeof(i));
1289 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
1290 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
1291 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
1292 writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
1293 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
1294 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID,
1295 base + NvRegAdapterControl);
1296 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
1297 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
1299 /* 7) start packet processing */
1300 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1301 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1302 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1303 base + NvRegRingSizes);
1305 i = readl(base + NvRegPowerState);
1306 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
1307 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
1311 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
1312 writel(NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
1315 writel(0, base + NvRegIrqMask);
1317 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1319 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1320 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1323 ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
1327 writel(np->irqmask, base + NvRegIrqMask);
1329 spin_lock_irq(&np->lock);
1330 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1331 writel(0, base + NvRegMulticastAddrB);
1332 writel(0, base + NvRegMulticastMaskA);
1333 writel(0, base + NvRegMulticastMaskB);
1334 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
1337 netif_start_queue(dev);
1339 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1340 if (mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ) & BMSR_ANEGCOMPLETE) {
1341 netif_carrier_on(dev);
1343 printk("%s: no link during initialization.\n", dev->name);
1344 netif_carrier_off(dev);
1347 spin_unlock_irq(&np->lock);
1355 static int nv_close(struct net_device *dev)
1357 struct fe_priv *np = get_nvpriv(dev);
1360 spin_lock_irq(&np->lock);
1361 np->in_shutdown = 1;
1362 spin_unlock_irq(&np->lock);
1363 synchronize_irq(dev->irq);
1365 del_timer_sync(&np->oom_kick);
1366 del_timer_sync(&np->nic_poll);
1368 netif_stop_queue(dev);
1369 spin_lock_irq(&np->lock);
1372 base = get_hwbase(dev);
1374 /* disable interrupts on the nic or we will lock up */
1375 writel(0, base + NvRegIrqMask);
1377 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
1379 spin_unlock_irq(&np->lock);
1381 free_irq(dev->irq, dev);
1388 /* FIXME: power down nic */
1393 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
1395 struct net_device *dev;
1401 dev = alloc_etherdev(sizeof(struct fe_priv));
1406 np = get_nvpriv(dev);
1407 np->pci_dev = pci_dev;
1408 spin_lock_init(&np->lock);
1409 SET_MODULE_OWNER(dev);
1410 SET_NETDEV_DEV(dev, &pci_dev->dev);
1412 init_timer(&np->oom_kick);
1413 np->oom_kick.data = (unsigned long) dev;
1414 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
1415 init_timer(&np->nic_poll);
1416 np->nic_poll.data = (unsigned long) dev;
1417 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
1419 err = pci_enable_device(pci_dev);
1421 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
1422 err, pci_name(pci_dev));
1426 pci_set_master(pci_dev);
1428 err = pci_request_regions(pci_dev, DRV_NAME);
1434 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1435 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
1436 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
1437 pci_resource_len(pci_dev, i),
1438 pci_resource_flags(pci_dev, i));
1439 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
1440 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
1441 addr = pci_resource_start(pci_dev, i);
1445 if (i == DEVICE_COUNT_RESOURCE) {
1446 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
1452 dev->base_addr = (unsigned long) ioremap(addr, NV_PCI_REGSZ);
1453 if (!dev->base_addr)
1455 dev->irq = pci_dev->irq;
1456 np->rx_ring = pci_alloc_consistent(pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
1460 np->tx_ring = &np->rx_ring[RX_RING];
1462 dev->open = nv_open;
1463 dev->stop = nv_close;
1464 dev->hard_start_xmit = nv_start_xmit;
1465 dev->get_stats = nv_get_stats;
1466 dev->change_mtu = nv_change_mtu;
1467 dev->set_multicast_list = nv_set_multicast;
1468 dev->do_ioctl = nv_ioctl;
1469 dev->tx_timeout = nv_tx_timeout;
1470 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
1472 pci_set_drvdata(pci_dev, dev);
1474 /* read the mac address */
1475 base = get_hwbase(dev);
1476 np->orig_mac[0] = readl(base + NvRegMacAddrA);
1477 np->orig_mac[1] = readl(base + NvRegMacAddrB);
1479 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
1480 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
1481 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
1482 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
1483 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
1484 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
1486 if (!is_valid_ether_addr(dev->dev_addr)) {
1488 * Bad mac address. At least one bios sets the mac address
1489 * to 01:23:45:67:89:ab
1491 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
1493 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1494 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1495 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
1496 dev->dev_addr[0] = 0x00;
1497 dev->dev_addr[1] = 0x00;
1498 dev->dev_addr[2] = 0x6c;
1499 get_random_bytes(&dev->dev_addr[3], 3);
1502 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
1503 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1504 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1507 writel(0, base + NvRegWakeUpFlags);
1510 np->tx_flags = cpu_to_le16(NV_TX_LASTPACKET|NV_TX_LASTPACKET1|NV_TX_VALID);
1511 if (id->driver_data & DEV_NEED_LASTPACKET1)
1512 np->tx_flags |= cpu_to_le16(NV_TX_LASTPACKET1);
1513 if (id->driver_data & DEV_IRQMASK_1)
1514 np->irqmask = NVREG_IRQMASK_WANTED_1;
1515 if (id->driver_data & DEV_IRQMASK_2)
1516 np->irqmask = NVREG_IRQMASK_WANTED_2;
1517 if (id->driver_data & DEV_NEED_TIMERIRQ)
1518 np->irqmask |= NVREG_IRQ_TIMER;
1520 err = register_netdev(dev);
1522 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
1525 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
1526 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
1532 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
1533 np->rx_ring, np->ring_addr);
1534 pci_set_drvdata(pci_dev, NULL);
1536 iounmap(get_hwbase(dev));
1538 pci_release_regions(pci_dev);
1540 pci_disable_device(pci_dev);
1547 static void __devexit nv_remove(struct pci_dev *pci_dev)
1549 struct net_device *dev = pci_get_drvdata(pci_dev);
1550 struct fe_priv *np = get_nvpriv(dev);
1551 u8 *base = get_hwbase(dev);
1553 unregister_netdev(dev);
1555 /* special op: write back the misordered MAC address - otherwise
1556 * the next nv_probe would see a wrong address.
1558 writel(np->orig_mac[0], base + NvRegMacAddrA);
1559 writel(np->orig_mac[1], base + NvRegMacAddrB);
1561 /* free all structures */
1562 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring, np->ring_addr);
1563 iounmap(get_hwbase(dev));
1564 pci_release_regions(pci_dev);
1565 pci_disable_device(pci_dev);
1567 pci_set_drvdata(pci_dev, NULL);
1570 static struct pci_device_id pci_tbl[] = {
1571 { /* nForce Ethernet Controller */
1572 .vendor = PCI_VENDOR_ID_NVIDIA,
1574 .subvendor = PCI_ANY_ID,
1575 .subdevice = PCI_ANY_ID,
1576 .driver_data = DEV_IRQMASK_1|DEV_NEED_TIMERIRQ,
1578 { /* nForce2 Ethernet Controller */
1579 .vendor = PCI_VENDOR_ID_NVIDIA,
1581 .subvendor = PCI_ANY_ID,
1582 .subdevice = PCI_ANY_ID,
1583 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1585 { /* nForce3 Ethernet Controller */
1586 .vendor = PCI_VENDOR_ID_NVIDIA,
1588 .subvendor = PCI_ANY_ID,
1589 .subdevice = PCI_ANY_ID,
1590 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1595 static struct pci_driver driver = {
1596 .name = "forcedeth",
1597 .id_table = pci_tbl,
1599 .remove = __devexit_p(nv_remove),
1603 static int __init init_nic(void)
1605 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
1606 return pci_module_init(&driver);
1609 static void __exit exit_nic(void)
1611 pci_unregister_driver(&driver);
1614 MODULE_PARM(max_interrupt_work, "i");
1615 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
1617 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
1618 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
1619 MODULE_LICENSE("GPL");
1621 MODULE_DEVICE_TABLE(pci, pci_tbl);
1623 module_init(init_nic);
1624 module_exit(exit_nic);