2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala (kumar.gala@freescale.com)
11 * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
18 * Gianfar: AKA Lambda Draconis, "Dragon"
25 * This driver is designed for the Triple-speed Ethernet
26 * controllers on the Freescale 8540/8560 integrated processors,
27 * as well as the Fast Ethernet Controller on the 8540.
29 * The driver is initialized through platform_device. Structures which
30 * define the configuration needed by the board are defined in a
31 * board structure in arch/ppc/platforms (though I do not
32 * discount the possibility that other architectures could one
33 * day be supported. One assumption the driver currently makes
34 * is that the PHY is configured in such a way to advertise all
35 * capabilities. This is a sensible default, and on certain
36 * PHYs, changing this default encounters substantial errata
37 * issues. Future versions may remove this requirement, but for
38 * now, it is best for the firmware to ensure this is the case.
40 * The Gianfar Ethernet Controller uses a ring of buffer
41 * descriptors. The beginning is indicated by a register
42 * pointing to the physical address of the start of the ring.
43 * The end is determined by a "wrap" bit being set in the
44 * last descriptor of the ring.
46 * When a packet is received, the RXF bit in the
47 * IEVENT register is set, triggering an interrupt when the
48 * corresponding bit in the IMASK register is also set (if
49 * interrupt coalescing is active, then the interrupt may not
50 * happen immediately, but will wait until either a set number
51 * of frames or amount of time have passed.). In NAPI, the
52 * interrupt handler will signal there is work to be done, and
53 * exit. Without NAPI, the packet(s) will be handled
54 * immediately. Both methods will start at the last known empty
55 * descriptor, and process every subsequent descriptor until there
56 * are none left with data (NAPI will stop after a set number of
57 * packets to give time to other tasks, but will eventually
58 * process all the packets). The data arrives inside a
59 * pre-allocated skb, and so after the skb is passed up to the
60 * stack, a new skb must be allocated, and the address field in
61 * the buffer descriptor must be updated to indicate this new
64 * When the kernel requests that a packet be transmitted, the
65 * driver starts where it left off last time, and points the
66 * descriptor at the buffer which was passed in. The driver
67 * then informs the DMA engine that there are packets ready to
68 * be transmitted. Once the controller is finished transmitting
69 * the packet, an interrupt may be triggered (under the same
70 * conditions as for reception, but depending on the TXF bit).
71 * The driver then cleans up the buffer.
74 #include <linux/config.h>
75 #include <linux/kernel.h>
76 #include <linux/sched.h>
77 #include <linux/string.h>
78 #include <linux/errno.h>
79 #include <linux/slab.h>
80 #include <linux/interrupt.h>
81 #include <linux/init.h>
82 #include <linux/delay.h>
83 #include <linux/netdevice.h>
84 #include <linux/etherdevice.h>
85 #include <linux/skbuff.h>
86 #include <linux/spinlock.h>
88 #include <linux/device.h>
92 #include <asm/uaccess.h>
93 #include <linux/module.h>
94 #include <linux/version.h>
95 #include <linux/dma-mapping.h>
96 #include <linux/crc32.h>
99 #include "gianfar_phy.h"
101 #define TX_TIMEOUT (1*HZ)
102 #define SKB_ALLOC_TIMEOUT 1000000
103 #undef BRIEF_GFAR_ERRORS
104 #undef VERBOSE_GFAR_ERRORS
106 #ifdef CONFIG_GFAR_NAPI
107 #define RECEIVE(x) netif_receive_skb(x)
109 #define RECEIVE(x) netif_rx(x)
112 const char gfar_driver_name[] = "Gianfar Ethernet";
113 const char gfar_driver_version[] = "1.1";
115 int startup_gfar(struct net_device *dev);
116 static int gfar_enet_open(struct net_device *dev);
117 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
118 static void gfar_timeout(struct net_device *dev);
119 static int gfar_close(struct net_device *dev);
120 struct sk_buff *gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp);
121 static struct net_device_stats *gfar_get_stats(struct net_device *dev);
122 static int gfar_set_mac_address(struct net_device *dev);
123 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
124 static irqreturn_t gfar_error(int irq, void *dev_id, struct pt_regs *regs);
125 static irqreturn_t gfar_transmit(int irq, void *dev_id, struct pt_regs *regs);
126 irqreturn_t gfar_receive(int irq, void *dev_id, struct pt_regs *regs);
127 static irqreturn_t gfar_interrupt(int irq, void *dev_id, struct pt_regs *regs);
128 static irqreturn_t phy_interrupt(int irq, void *dev_id, struct pt_regs *regs);
129 static void gfar_phy_change(void *data);
130 static void gfar_phy_timer(unsigned long data);
131 static void adjust_link(struct net_device *dev);
132 static void init_registers(struct net_device *dev);
133 static int init_phy(struct net_device *dev);
134 static int gfar_probe(struct device *device);
135 static int gfar_remove(struct device *device);
136 void free_skb_resources(struct gfar_private *priv);
137 static void gfar_set_multi(struct net_device *dev);
138 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
139 #ifdef CONFIG_GFAR_NAPI
140 static int gfar_poll(struct net_device *dev, int *budget);
142 static int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
143 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
144 static void gfar_phy_startup_timer(unsigned long data);
146 extern struct ethtool_ops gfar_ethtool_ops;
148 MODULE_AUTHOR("Freescale Semiconductor, Inc");
149 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
150 MODULE_LICENSE("GPL");
152 static int gfar_probe(struct device *device)
155 struct net_device *dev = NULL;
156 struct gfar_private *priv = NULL;
157 struct platform_device *pdev = to_platform_device(device);
158 struct gianfar_platform_data *einfo;
162 int dev_ethtool_ops = 0;
164 einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
167 printk(KERN_ERR "gfar %d: Missing additional data!\n",
173 /* Create an ethernet device instance */
174 dev = alloc_etherdev(sizeof (*priv));
179 priv = netdev_priv(dev);
181 /* Set the info in the priv to the current info */
184 /* fill out IRQ fields */
185 if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
186 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
187 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
188 priv->interruptError = platform_get_irq_byname(pdev, "error");
190 priv->interruptTransmit = platform_get_irq(pdev, 0);
193 /* get a pointer to the register memory */
194 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
195 priv->regs = (struct gfar *)
196 ioremap(r->start, sizeof (struct gfar));
198 if (priv->regs == NULL) {
203 /* Set the PHY base address */
204 priv->phyregs = (struct gfar *)
205 ioremap(einfo->phy_reg_addr, sizeof (struct gfar));
207 if (priv->phyregs == NULL) {
212 spin_lock_init(&priv->lock);
214 dev_set_drvdata(device, dev);
216 /* Stop the DMA engine now, in case it was running before */
217 /* (The firmware could have used it, and left it running). */
218 /* To do this, we write Graceful Receive Stop and Graceful */
219 /* Transmit Stop, and then wait until the corresponding bits */
220 /* in IEVENT indicate the stops have completed. */
221 tempval = gfar_read(&priv->regs->dmactrl);
222 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
223 gfar_write(&priv->regs->dmactrl, tempval);
225 tempval = gfar_read(&priv->regs->dmactrl);
226 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
227 gfar_write(&priv->regs->dmactrl, tempval);
229 while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
232 /* Reset MAC layer */
233 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
235 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
236 gfar_write(&priv->regs->maccfg1, tempval);
238 /* Initialize MACCFG2. */
239 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
241 /* Initialize ECNTRL */
242 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
244 /* Copy the station address into the dev structure, */
245 memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
247 /* Set the dev->base_addr to the gfar reg region */
248 dev->base_addr = (unsigned long) (priv->regs);
250 SET_MODULE_OWNER(dev);
251 SET_NETDEV_DEV(dev, device);
253 /* Fill in the dev structure */
254 dev->open = gfar_enet_open;
255 dev->hard_start_xmit = gfar_start_xmit;
256 dev->tx_timeout = gfar_timeout;
257 dev->watchdog_timeo = TX_TIMEOUT;
258 #ifdef CONFIG_GFAR_NAPI
259 dev->poll = gfar_poll;
260 dev->weight = GFAR_DEV_WEIGHT;
262 dev->stop = gfar_close;
263 dev->get_stats = gfar_get_stats;
264 dev->change_mtu = gfar_change_mtu;
266 dev->set_multicast_list = gfar_set_multi;
268 /* Index into the array of possible ethtool
269 * ops to catch all 4 possibilities */
270 if((priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) == 0)
271 dev_ethtool_ops += 1;
273 if((priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_COALESCE) == 0)
274 dev_ethtool_ops += 2;
276 dev->ethtool_ops = gfar_op_array[dev_ethtool_ops];
278 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
279 #ifdef CONFIG_GFAR_BUFSTASH
280 priv->rx_stash_size = STASH_LENGTH;
282 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
283 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
285 priv->txcoalescing = DEFAULT_TX_COALESCE;
286 priv->txcount = DEFAULT_TXCOUNT;
287 priv->txtime = DEFAULT_TXTIME;
288 priv->rxcoalescing = DEFAULT_RX_COALESCE;
289 priv->rxcount = DEFAULT_RXCOUNT;
290 priv->rxtime = DEFAULT_RXTIME;
292 err = register_netdev(dev);
295 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
300 /* Print out the device info */
301 printk(KERN_INFO DEVICE_NAME, dev->name);
302 for (idx = 0; idx < 6; idx++)
303 printk("%2.2x%c", dev->dev_addr[idx], idx == 5 ? ' ' : ':');
306 /* Even more device info helps when determining which kernel */
307 /* provided which set of benchmarks. Since this is global for all */
308 /* devices, we only print it once */
309 #ifdef CONFIG_GFAR_NAPI
310 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
312 printk(KERN_INFO "%s: Running with NAPI disabled\n", dev->name);
314 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
315 dev->name, priv->rx_ring_size, priv->tx_ring_size);
320 iounmap((void *) priv->phyregs);
322 iounmap((void *) priv->regs);
328 static int gfar_remove(struct device *device)
330 struct net_device *dev = dev_get_drvdata(device);
331 struct gfar_private *priv = netdev_priv(dev);
333 dev_set_drvdata(device, NULL);
335 iounmap((void *) priv->regs);
336 iounmap((void *) priv->phyregs);
343 /* Configure the PHY for dev.
344 * returns 0 if success. -1 if failure
346 static int init_phy(struct net_device *dev)
348 struct gfar_private *priv = netdev_priv(dev);
349 struct phy_info *curphy;
350 unsigned int timeout = PHY_INIT_TIMEOUT;
351 struct gfar *phyregs = priv->phyregs;
352 struct gfar_mii_info *mii_info;
357 priv->oldduplex = -1;
359 mii_info = kmalloc(sizeof(struct gfar_mii_info),
362 if(NULL == mii_info) {
363 printk(KERN_ERR "%s: Could not allocate mii_info\n",
368 mii_info->speed = SPEED_1000;
369 mii_info->duplex = DUPLEX_FULL;
373 mii_info->advertising = (ADVERTISED_10baseT_Half |
374 ADVERTISED_10baseT_Full |
375 ADVERTISED_100baseT_Half |
376 ADVERTISED_100baseT_Full |
377 ADVERTISED_1000baseT_Full);
378 mii_info->autoneg = 1;
380 mii_info->mii_id = priv->einfo->phyid;
384 mii_info->mdio_read = &read_phy_reg;
385 mii_info->mdio_write = &write_phy_reg;
387 priv->mii_info = mii_info;
389 /* Reset the management interface */
390 gfar_write(&phyregs->miimcfg, MIIMCFG_RESET);
392 /* Setup the MII Mgmt clock speed */
393 gfar_write(&phyregs->miimcfg, MIIMCFG_INIT_VALUE);
395 /* Wait until the bus is free */
396 while ((gfar_read(&phyregs->miimind) & MIIMIND_BUSY) &&
401 printk(KERN_ERR "%s: The MII Bus is stuck!\n",
407 /* get info for this PHY */
408 curphy = get_phy_info(priv->mii_info);
410 if (curphy == NULL) {
411 printk(KERN_ERR "%s: No PHY found\n", dev->name);
416 mii_info->phyinfo = curphy;
418 /* Run the commands which initialize the PHY */
420 err = curphy->init(priv->mii_info);
436 static void init_registers(struct net_device *dev)
438 struct gfar_private *priv = netdev_priv(dev);
441 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
443 /* Initialize IMASK */
444 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
446 /* Init hash registers to zero */
447 gfar_write(&priv->regs->iaddr0, 0);
448 gfar_write(&priv->regs->iaddr1, 0);
449 gfar_write(&priv->regs->iaddr2, 0);
450 gfar_write(&priv->regs->iaddr3, 0);
451 gfar_write(&priv->regs->iaddr4, 0);
452 gfar_write(&priv->regs->iaddr5, 0);
453 gfar_write(&priv->regs->iaddr6, 0);
454 gfar_write(&priv->regs->iaddr7, 0);
456 gfar_write(&priv->regs->gaddr0, 0);
457 gfar_write(&priv->regs->gaddr1, 0);
458 gfar_write(&priv->regs->gaddr2, 0);
459 gfar_write(&priv->regs->gaddr3, 0);
460 gfar_write(&priv->regs->gaddr4, 0);
461 gfar_write(&priv->regs->gaddr5, 0);
462 gfar_write(&priv->regs->gaddr6, 0);
463 gfar_write(&priv->regs->gaddr7, 0);
466 gfar_write(&priv->regs->rctrl, 0x00000000);
468 /* Zero out the rmon mib registers if it has them */
469 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
470 memset((void *) &(priv->regs->rmon), 0,
471 sizeof (struct rmon_mib));
473 /* Mask off the CAM interrupts */
474 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
475 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
478 /* Initialize the max receive buffer length */
479 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
481 #ifdef CONFIG_GFAR_BUFSTASH
482 /* If we are stashing buffers, we need to set the
483 * extraction length to the size of the buffer */
484 gfar_write(&priv->regs->attreli, priv->rx_stash_size << 16);
487 /* Initialize the Minimum Frame Length Register */
488 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
490 /* Setup Attributes so that snooping is on for rx */
491 gfar_write(&priv->regs->attr, ATTR_INIT_SETTINGS);
492 gfar_write(&priv->regs->attreli, ATTRELI_INIT_SETTINGS);
494 /* Assign the TBI an address which won't conflict with the PHYs */
495 gfar_write(&priv->regs->tbipa, TBIPA_VALUE);
498 void stop_gfar(struct net_device *dev)
500 struct gfar_private *priv = netdev_priv(dev);
501 struct gfar *regs = priv->regs;
506 spin_lock_irqsave(&priv->lock, flags);
508 /* Tell the kernel the link is down */
509 priv->mii_info->link = 0;
512 /* Mask all interrupts */
513 gfar_write(®s->imask, IMASK_INIT_CLEAR);
515 /* Clear all interrupts */
516 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
518 /* Stop the DMA, and wait for it to stop */
519 tempval = gfar_read(&priv->regs->dmactrl);
520 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
521 != (DMACTRL_GRS | DMACTRL_GTS)) {
522 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
523 gfar_write(&priv->regs->dmactrl, tempval);
525 while (!(gfar_read(&priv->regs->ievent) &
526 (IEVENT_GRSC | IEVENT_GTSC)))
530 /* Disable Rx and Tx */
531 tempval = gfar_read(®s->maccfg1);
532 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
533 gfar_write(®s->maccfg1, tempval);
535 if (priv->einfo->board_flags & FSL_GIANFAR_BRD_HAS_PHY_INTR) {
536 /* Clear any pending interrupts */
537 mii_clear_phy_interrupt(priv->mii_info);
539 /* Disable PHY Interrupts */
540 mii_configure_phy_interrupt(priv->mii_info,
541 MII_INTERRUPT_DISABLED);
544 spin_unlock_irqrestore(&priv->lock, flags);
547 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
548 free_irq(priv->interruptError, dev);
549 free_irq(priv->interruptTransmit, dev);
550 free_irq(priv->interruptReceive, dev);
552 free_irq(priv->interruptTransmit, dev);
555 if (priv->einfo->board_flags & FSL_GIANFAR_BRD_HAS_PHY_INTR) {
556 free_irq(priv->einfo->interruptPHY, dev);
558 del_timer_sync(&priv->phy_info_timer);
561 free_skb_resources(priv);
563 dma_free_coherent(NULL,
564 sizeof(struct txbd8)*priv->tx_ring_size
565 + sizeof(struct rxbd8)*priv->rx_ring_size,
567 gfar_read(®s->tbase));
570 /* If there are any tx skbs or rx skbs still around, free them.
571 * Then free tx_skbuff and rx_skbuff */
572 void free_skb_resources(struct gfar_private *priv)
578 /* Go through all the buffer descriptors and free their data buffers */
579 txbdp = priv->tx_bd_base;
581 for (i = 0; i < priv->tx_ring_size; i++) {
583 if (priv->tx_skbuff[i]) {
584 dma_unmap_single(NULL, txbdp->bufPtr,
587 dev_kfree_skb_any(priv->tx_skbuff[i]);
588 priv->tx_skbuff[i] = NULL;
592 kfree(priv->tx_skbuff);
594 rxbdp = priv->rx_bd_base;
596 /* rx_skbuff is not guaranteed to be allocated, so only
597 * free it and its contents if it is allocated */
598 if(priv->rx_skbuff != NULL) {
599 for (i = 0; i < priv->rx_ring_size; i++) {
600 if (priv->rx_skbuff[i]) {
601 dma_unmap_single(NULL, rxbdp->bufPtr,
606 dev_kfree_skb_any(priv->rx_skbuff[i]);
607 priv->rx_skbuff[i] = NULL;
617 kfree(priv->rx_skbuff);
621 /* Bring the controller up and running */
622 int startup_gfar(struct net_device *dev)
629 struct gfar_private *priv = netdev_priv(dev);
630 struct gfar *regs = priv->regs;
634 gfar_write(®s->imask, IMASK_INIT_CLEAR);
636 /* Allocate memory for the buffer descriptors */
637 vaddr = (unsigned long) dma_alloc_coherent(NULL,
638 sizeof (struct txbd8) * priv->tx_ring_size +
639 sizeof (struct rxbd8) * priv->rx_ring_size,
643 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
648 priv->tx_bd_base = (struct txbd8 *) vaddr;
650 /* enet DMA only understands physical addresses */
651 gfar_write(®s->tbase, addr);
653 /* Start the rx descriptor ring where the tx ring leaves off */
654 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
655 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
656 priv->rx_bd_base = (struct rxbd8 *) vaddr;
657 gfar_write(®s->rbase, addr);
659 /* Setup the skbuff rings */
661 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
662 priv->tx_ring_size, GFP_KERNEL);
664 if (priv->tx_skbuff == NULL) {
665 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
671 for (i = 0; i < priv->tx_ring_size; i++)
672 priv->tx_skbuff[i] = NULL;
675 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
676 priv->rx_ring_size, GFP_KERNEL);
678 if (priv->rx_skbuff == NULL) {
679 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
685 for (i = 0; i < priv->rx_ring_size; i++)
686 priv->rx_skbuff[i] = NULL;
688 /* Initialize some variables in our dev structure */
689 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
690 priv->cur_rx = priv->rx_bd_base;
691 priv->skb_curtx = priv->skb_dirtytx = 0;
694 /* Initialize Transmit Descriptor Ring */
695 txbdp = priv->tx_bd_base;
696 for (i = 0; i < priv->tx_ring_size; i++) {
703 /* Set the last descriptor in the ring to indicate wrap */
705 txbdp->status |= TXBD_WRAP;
707 rxbdp = priv->rx_bd_base;
708 for (i = 0; i < priv->rx_ring_size; i++) {
709 struct sk_buff *skb = NULL;
713 skb = gfar_new_skb(dev, rxbdp);
715 priv->rx_skbuff[i] = skb;
720 /* Set the last descriptor in the ring to wrap */
722 rxbdp->status |= RXBD_WRAP;
724 /* If the device has multiple interrupts, register for
725 * them. Otherwise, only register for the one */
726 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
727 /* Install our interrupt handlers for Error,
728 * Transmit, and Receive */
729 if (request_irq(priv->interruptError, gfar_error,
730 0, "enet_error", dev) < 0) {
731 printk(KERN_ERR "%s: Can't get IRQ %d\n",
732 dev->name, priv->interruptError);
738 if (request_irq(priv->interruptTransmit, gfar_transmit,
739 0, "enet_tx", dev) < 0) {
740 printk(KERN_ERR "%s: Can't get IRQ %d\n",
741 dev->name, priv->interruptTransmit);
748 if (request_irq(priv->interruptReceive, gfar_receive,
749 0, "enet_rx", dev) < 0) {
750 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
751 dev->name, priv->interruptReceive);
757 if (request_irq(priv->interruptTransmit, gfar_interrupt,
758 0, "gfar_interrupt", dev) < 0) {
759 printk(KERN_ERR "%s: Can't get IRQ %d\n",
760 dev->name, priv->interruptError);
767 /* Set up the PHY change work queue */
768 INIT_WORK(&priv->tq, gfar_phy_change, dev);
770 init_timer(&priv->phy_info_timer);
771 priv->phy_info_timer.function = &gfar_phy_startup_timer;
772 priv->phy_info_timer.data = (unsigned long) priv->mii_info;
773 mod_timer(&priv->phy_info_timer, jiffies + HZ);
775 /* Configure the coalescing support */
776 if (priv->txcoalescing)
777 gfar_write(®s->txic,
778 mk_ic_value(priv->txcount, priv->txtime));
780 gfar_write(®s->txic, 0);
782 if (priv->rxcoalescing)
783 gfar_write(®s->rxic,
784 mk_ic_value(priv->rxcount, priv->rxtime));
786 gfar_write(®s->rxic, 0);
788 init_waitqueue_head(&priv->rxcleanupq);
790 /* Enable Rx and Tx in MACCFG1 */
791 tempval = gfar_read(®s->maccfg1);
792 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
793 gfar_write(®s->maccfg1, tempval);
795 /* Initialize DMACTRL to have WWR and WOP */
796 tempval = gfar_read(&priv->regs->dmactrl);
797 tempval |= DMACTRL_INIT_SETTINGS;
798 gfar_write(&priv->regs->dmactrl, tempval);
800 /* Clear THLT, so that the DMA starts polling now */
801 gfar_write(®s->tstat, TSTAT_CLEAR_THALT);
803 /* Make sure we aren't stopped */
804 tempval = gfar_read(&priv->regs->dmactrl);
805 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
806 gfar_write(&priv->regs->dmactrl, tempval);
808 /* Unmask the interrupts we look for */
809 gfar_write(®s->imask, IMASK_DEFAULT);
814 free_irq(priv->interruptTransmit, dev);
816 free_irq(priv->interruptError, dev);
819 free_skb_resources(priv);
821 dma_free_coherent(NULL,
822 sizeof(struct txbd8)*priv->tx_ring_size
823 + sizeof(struct rxbd8)*priv->rx_ring_size,
825 gfar_read(®s->tbase));
827 if (priv->mii_info->phyinfo->close)
828 priv->mii_info->phyinfo->close(priv->mii_info);
830 kfree(priv->mii_info);
835 /* Called when something needs to use the ethernet device */
836 /* Returns 0 for success. */
837 static int gfar_enet_open(struct net_device *dev)
841 /* Initialize a bunch of registers */
844 gfar_set_mac_address(dev);
851 err = startup_gfar(dev);
853 netif_start_queue(dev);
858 /* This is called by the kernel when a frame is ready for transmission. */
859 /* It is pointed to by the dev->hard_start_xmit function pointer */
860 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
862 struct gfar_private *priv = netdev_priv(dev);
865 /* Update transmit stats */
866 priv->stats.tx_bytes += skb->len;
869 spin_lock_irq(&priv->lock);
871 /* Point at the first free tx descriptor */
872 txbdp = priv->cur_tx;
874 /* Clear all but the WRAP status flags */
875 txbdp->status &= TXBD_WRAP;
877 /* Set buffer length and pointer */
878 txbdp->length = skb->len;
879 txbdp->bufPtr = dma_map_single(NULL, skb->data,
880 skb->len, DMA_TO_DEVICE);
882 /* Save the skb pointer so we can free it later */
883 priv->tx_skbuff[priv->skb_curtx] = skb;
885 /* Update the current skb pointer (wrapping if this was the last) */
887 (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
889 /* Flag the BD as interrupt-causing */
890 txbdp->status |= TXBD_INTERRUPT;
892 /* Flag the BD as ready to go, last in frame, and */
894 txbdp->status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
896 dev->trans_start = jiffies;
898 /* If this was the last BD in the ring, the next one */
899 /* is at the beginning of the ring */
900 if (txbdp->status & TXBD_WRAP)
901 txbdp = priv->tx_bd_base;
905 /* If the next BD still needs to be cleaned up, then the bds
906 are full. We need to tell the kernel to stop sending us stuff. */
907 if (txbdp == priv->dirty_tx) {
908 netif_stop_queue(dev);
910 priv->stats.tx_fifo_errors++;
913 /* Update the current txbd to the next one */
914 priv->cur_tx = txbdp;
916 /* Tell the DMA to go go go */
917 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
920 spin_unlock_irq(&priv->lock);
925 /* Stops the kernel queue, and halts the controller */
926 static int gfar_close(struct net_device *dev)
928 struct gfar_private *priv = netdev_priv(dev);
931 /* Shutdown the PHY */
932 if (priv->mii_info->phyinfo->close)
933 priv->mii_info->phyinfo->close(priv->mii_info);
935 kfree(priv->mii_info);
937 netif_stop_queue(dev);
942 /* returns a net_device_stats structure pointer */
943 static struct net_device_stats * gfar_get_stats(struct net_device *dev)
945 struct gfar_private *priv = netdev_priv(dev);
947 return &(priv->stats);
950 /* Changes the mac address if the controller is not running. */
951 int gfar_set_mac_address(struct net_device *dev)
953 struct gfar_private *priv = netdev_priv(dev);
955 char tmpbuf[MAC_ADDR_LEN];
958 /* Now copy it into the mac registers backwards, cuz */
959 /* little endian is silly */
960 for (i = 0; i < MAC_ADDR_LEN; i++)
961 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->dev_addr[i];
963 gfar_write(&priv->regs->macstnaddr1, *((u32 *) (tmpbuf)));
965 tempval = *((u32 *) (tmpbuf + 4));
967 gfar_write(&priv->regs->macstnaddr2, tempval);
973 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
975 int tempsize, tempval;
976 struct gfar_private *priv = netdev_priv(dev);
977 int oldsize = priv->rx_buffer_size;
978 int frame_size = new_mtu + 18;
980 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
981 printk(KERN_ERR "%s: Invalid MTU setting\n", dev->name);
986 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
987 INCREMENTAL_BUFFER_SIZE;
989 /* Only stop and start the controller if it isn't already
991 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
994 priv->rx_buffer_size = tempsize;
998 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
999 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1001 /* If the mtu is larger than the max size for standard
1002 * ethernet frames (ie, a jumbo frame), then set maccfg2
1003 * to allow huge frames, and to check the length */
1004 tempval = gfar_read(&priv->regs->maccfg2);
1006 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1007 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1009 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1011 gfar_write(&priv->regs->maccfg2, tempval);
1013 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1019 /* gfar_timeout gets called when a packet has not been
1020 * transmitted after a set amount of time.
1021 * For now, assume that clearing out all the structures, and
1022 * starting over will fix the problem. */
1023 static void gfar_timeout(struct net_device *dev)
1025 struct gfar_private *priv = netdev_priv(dev);
1027 priv->stats.tx_errors++;
1029 if (dev->flags & IFF_UP) {
1034 netif_schedule(dev);
1037 /* Interrupt Handler for Transmit complete */
1038 static irqreturn_t gfar_transmit(int irq, void *dev_id, struct pt_regs *regs)
1040 struct net_device *dev = (struct net_device *) dev_id;
1041 struct gfar_private *priv = netdev_priv(dev);
1045 gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1048 spin_lock(&priv->lock);
1049 bdp = priv->dirty_tx;
1050 while ((bdp->status & TXBD_READY) == 0) {
1051 /* If dirty_tx and cur_tx are the same, then either the */
1052 /* ring is empty or full now (it could only be full in the beginning, */
1053 /* obviously). If it is empty, we are done. */
1054 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1057 priv->stats.tx_packets++;
1059 /* Deferred means some collisions occurred during transmit, */
1060 /* but we eventually sent the packet. */
1061 if (bdp->status & TXBD_DEF)
1062 priv->stats.collisions++;
1064 /* Free the sk buffer associated with this TxBD */
1065 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1066 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1068 (priv->skb_dirtytx +
1069 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1071 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1072 if (bdp->status & TXBD_WRAP)
1073 bdp = priv->tx_bd_base;
1077 /* Move dirty_tx to be the next bd */
1078 priv->dirty_tx = bdp;
1080 /* We freed a buffer, so now we can restart transmission */
1081 if (netif_queue_stopped(dev))
1082 netif_wake_queue(dev);
1083 } /* while ((bdp->status & TXBD_READY) == 0) */
1085 /* If we are coalescing the interrupts, reset the timer */
1086 /* Otherwise, clear it */
1087 if (priv->txcoalescing)
1088 gfar_write(&priv->regs->txic,
1089 mk_ic_value(priv->txcount, priv->txtime));
1091 gfar_write(&priv->regs->txic, 0);
1093 spin_unlock(&priv->lock);
1098 struct sk_buff * gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp)
1100 struct gfar_private *priv = netdev_priv(dev);
1101 struct sk_buff *skb = NULL;
1102 unsigned int timeout = SKB_ALLOC_TIMEOUT;
1104 /* We have to allocate the skb, so keep trying till we succeed */
1105 while ((!skb) && timeout--)
1106 skb = dev_alloc_skb(priv->rx_buffer_size + RXBUF_ALIGNMENT);
1111 /* We need the data buffer to be aligned properly. We will reserve
1112 * as many bytes as needed to align the data properly
1116 (((unsigned) skb->data) & (RXBUF_ALIGNMENT - 1)));
1120 bdp->bufPtr = dma_map_single(NULL, skb->data,
1121 priv->rx_buffer_size + RXBUF_ALIGNMENT,
1126 /* Mark the buffer empty */
1127 bdp->status |= (RXBD_EMPTY | RXBD_INTERRUPT);
1132 static inline void count_errors(unsigned short status, struct gfar_private *priv)
1134 struct net_device_stats *stats = &priv->stats;
1135 struct gfar_extra_stats *estats = &priv->extra_stats;
1137 /* If the packet was truncated, none of the other errors
1139 if (status & RXBD_TRUNCATED) {
1140 stats->rx_length_errors++;
1146 /* Count the errors, if there were any */
1147 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1148 stats->rx_length_errors++;
1150 if (status & RXBD_LARGE)
1155 if (status & RXBD_NONOCTET) {
1156 stats->rx_frame_errors++;
1157 estats->rx_nonoctet++;
1159 if (status & RXBD_CRCERR) {
1160 estats->rx_crcerr++;
1161 stats->rx_crc_errors++;
1163 if (status & RXBD_OVERRUN) {
1164 estats->rx_overrun++;
1165 stats->rx_crc_errors++;
1169 irqreturn_t gfar_receive(int irq, void *dev_id, struct pt_regs *regs)
1171 struct net_device *dev = (struct net_device *) dev_id;
1172 struct gfar_private *priv = netdev_priv(dev);
1174 #ifdef CONFIG_GFAR_NAPI
1178 /* Clear IEVENT, so rx interrupt isn't called again
1179 * because of this interrupt */
1180 gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1183 #ifdef CONFIG_GFAR_NAPI
1184 if (netif_rx_schedule_prep(dev)) {
1185 tempval = gfar_read(&priv->regs->imask);
1186 tempval &= IMASK_RX_DISABLED;
1187 gfar_write(&priv->regs->imask, tempval);
1189 __netif_rx_schedule(dev);
1191 #ifdef VERBOSE_GFAR_ERRORS
1192 printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1193 dev->name, gfar_read(&priv->regs->ievent),
1194 gfar_read(&priv->regs->imask));
1199 spin_lock(&priv->lock);
1200 gfar_clean_rx_ring(dev, priv->rx_ring_size);
1202 /* If we are coalescing interrupts, update the timer */
1203 /* Otherwise, clear it */
1204 if (priv->rxcoalescing)
1205 gfar_write(&priv->regs->rxic,
1206 mk_ic_value(priv->rxcount, priv->rxtime));
1208 gfar_write(&priv->regs->rxic, 0);
1210 /* Just in case we need to wake the ring param changer */
1213 spin_unlock(&priv->lock);
1220 /* gfar_process_frame() -- handle one incoming packet if skb
1222 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1225 struct gfar_private *priv = netdev_priv(dev);
1228 #ifdef BRIEF_GFAR_ERRORS
1229 printk(KERN_WARNING "%s: Missing skb!!.\n",
1232 priv->stats.rx_dropped++;
1233 priv->extra_stats.rx_skbmissing++;
1235 /* Prep the skb for the packet */
1236 skb_put(skb, length);
1238 /* Tell the skb what kind of packet this is */
1239 skb->protocol = eth_type_trans(skb, dev);
1241 /* Send the packet up the stack */
1242 if (RECEIVE(skb) == NET_RX_DROP) {
1243 priv->extra_stats.kernel_dropped++;
1250 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1251 * until the budget/quota has been reached. Returns the number
1254 static int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1257 struct sk_buff *skb;
1260 struct gfar_private *priv = netdev_priv(dev);
1262 /* Get the first full descriptor */
1265 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1266 skb = priv->rx_skbuff[priv->skb_currx];
1269 (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET
1270 | RXBD_CRCERR | RXBD_OVERRUN | RXBD_TRUNCATED))) {
1271 /* Increment the number of packets */
1272 priv->stats.rx_packets++;
1275 /* Remove the FCS from the packet length */
1276 pkt_len = bdp->length - 4;
1278 gfar_process_frame(dev, skb, pkt_len);
1280 priv->stats.rx_bytes += pkt_len;
1282 count_errors(bdp->status, priv);
1285 dev_kfree_skb_any(skb);
1287 priv->rx_skbuff[priv->skb_currx] = NULL;
1290 dev->last_rx = jiffies;
1292 /* Clear the status flags for this buffer */
1293 bdp->status &= ~RXBD_STATS;
1295 /* Add another skb for the future */
1296 skb = gfar_new_skb(dev, bdp);
1297 priv->rx_skbuff[priv->skb_currx] = skb;
1299 /* Update to the next pointer */
1300 if (bdp->status & RXBD_WRAP)
1301 bdp = priv->rx_bd_base;
1305 /* update to point at the next skb */
1308 1) & RX_RING_MOD_MASK(priv->rx_ring_size);
1312 /* Update the current rxbd pointer to be the next one */
1315 /* If no packets have arrived since the
1316 * last one we processed, clear the IEVENT RX and
1317 * BSY bits so that another interrupt won't be
1318 * generated when we set IMASK */
1319 if (bdp->status & RXBD_EMPTY)
1320 gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1325 #ifdef CONFIG_GFAR_NAPI
1326 static int gfar_poll(struct net_device *dev, int *budget)
1329 struct gfar_private *priv = netdev_priv(dev);
1330 int rx_work_limit = *budget;
1332 if (rx_work_limit > dev->quota)
1333 rx_work_limit = dev->quota;
1335 howmany = gfar_clean_rx_ring(dev, rx_work_limit);
1337 dev->quota -= howmany;
1338 rx_work_limit -= howmany;
1341 if (rx_work_limit >= 0) {
1342 netif_rx_complete(dev);
1344 /* Clear the halt bit in RSTAT */
1345 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1347 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1349 /* If we are coalescing interrupts, update the timer */
1350 /* Otherwise, clear it */
1351 if (priv->rxcoalescing)
1352 gfar_write(&priv->regs->rxic,
1353 mk_ic_value(priv->rxcount, priv->rxtime));
1355 gfar_write(&priv->regs->rxic, 0);
1357 /* Signal to the ring size changer that it's safe to go */
1361 return (rx_work_limit < 0) ? 1 : 0;
1365 /* The interrupt handler for devices with one interrupt */
1366 static irqreturn_t gfar_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1368 struct net_device *dev = dev_id;
1369 struct gfar_private *priv = netdev_priv(dev);
1371 /* Save ievent for future reference */
1372 u32 events = gfar_read(&priv->regs->ievent);
1375 gfar_write(&priv->regs->ievent, events);
1377 /* Check for reception */
1378 if ((events & IEVENT_RXF0) || (events & IEVENT_RXB0))
1379 gfar_receive(irq, dev_id, regs);
1381 /* Check for transmit completion */
1382 if ((events & IEVENT_TXF) || (events & IEVENT_TXB))
1383 gfar_transmit(irq, dev_id, regs);
1385 /* Update error statistics */
1386 if (events & IEVENT_TXE) {
1387 priv->stats.tx_errors++;
1389 if (events & IEVENT_LC)
1390 priv->stats.tx_window_errors++;
1391 if (events & IEVENT_CRL)
1392 priv->stats.tx_aborted_errors++;
1393 if (events & IEVENT_XFUN) {
1394 #ifdef VERBOSE_GFAR_ERRORS
1395 printk(KERN_WARNING "%s: tx underrun. dropped packet\n",
1398 priv->stats.tx_dropped++;
1399 priv->extra_stats.tx_underrun++;
1401 /* Reactivate the Tx Queues */
1402 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1405 if (events & IEVENT_BSY) {
1406 priv->stats.rx_errors++;
1407 priv->extra_stats.rx_bsy++;
1409 gfar_receive(irq, dev_id, regs);
1411 #ifndef CONFIG_GFAR_NAPI
1412 /* Clear the halt bit in RSTAT */
1413 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1416 #ifdef VERBOSE_GFAR_ERRORS
1417 printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n", dev->name,
1418 gfar_read(&priv->regs->rstat));
1421 if (events & IEVENT_BABR) {
1422 priv->stats.rx_errors++;
1423 priv->extra_stats.rx_babr++;
1425 #ifdef VERBOSE_GFAR_ERRORS
1426 printk(KERN_DEBUG "%s: babbling error\n", dev->name);
1429 if (events & IEVENT_EBERR) {
1430 priv->extra_stats.eberr++;
1431 #ifdef VERBOSE_GFAR_ERRORS
1432 printk(KERN_DEBUG "%s: EBERR\n", dev->name);
1435 if (events & IEVENT_RXC) {
1436 #ifdef VERBOSE_GFAR_ERRORS
1437 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1441 if (events & IEVENT_BABT) {
1442 priv->extra_stats.tx_babt++;
1443 #ifdef VERBOSE_GFAR_ERRORS
1444 printk(KERN_DEBUG "%s: babt error\n", dev->name);
1451 static irqreturn_t phy_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1453 struct net_device *dev = (struct net_device *) dev_id;
1454 struct gfar_private *priv = netdev_priv(dev);
1456 /* Clear the interrupt */
1457 mii_clear_phy_interrupt(priv->mii_info);
1459 /* Disable PHY interrupts */
1460 mii_configure_phy_interrupt(priv->mii_info,
1461 MII_INTERRUPT_DISABLED);
1463 /* Schedule the phy change */
1464 schedule_work(&priv->tq);
1469 /* Scheduled by the phy_interrupt/timer to handle PHY changes */
1470 static void gfar_phy_change(void *data)
1472 struct net_device *dev = (struct net_device *) data;
1473 struct gfar_private *priv = netdev_priv(dev);
1476 /* Delay to give the PHY a chance to change the
1480 /* Update the link, speed, duplex */
1481 result = priv->mii_info->phyinfo->read_status(priv->mii_info);
1483 /* Adjust the known status as long as the link
1484 * isn't still coming up */
1485 if((0 == result) || (priv->mii_info->link == 0))
1488 /* Reenable interrupts, if needed */
1489 if (priv->einfo->board_flags & FSL_GIANFAR_BRD_HAS_PHY_INTR)
1490 mii_configure_phy_interrupt(priv->mii_info,
1491 MII_INTERRUPT_ENABLED);
1494 /* Called every so often on systems that don't interrupt
1495 * the core for PHY changes */
1496 static void gfar_phy_timer(unsigned long data)
1498 struct net_device *dev = (struct net_device *) data;
1499 struct gfar_private *priv = netdev_priv(dev);
1501 schedule_work(&priv->tq);
1503 mod_timer(&priv->phy_info_timer, jiffies +
1504 GFAR_PHY_CHANGE_TIME * HZ);
1507 /* Keep trying aneg for some time
1508 * If, after GFAR_AN_TIMEOUT seconds, it has not
1509 * finished, we switch to forced.
1510 * Either way, once the process has completed, we either
1511 * request the interrupt, or switch the timer over to
1512 * using gfar_phy_timer to check status */
1513 static void gfar_phy_startup_timer(unsigned long data)
1516 static int secondary = GFAR_AN_TIMEOUT;
1517 struct gfar_mii_info *mii_info = (struct gfar_mii_info *)data;
1518 struct gfar_private *priv = netdev_priv(mii_info->dev);
1520 /* Configure the Auto-negotiation */
1521 result = mii_info->phyinfo->config_aneg(mii_info);
1523 /* If autonegotiation failed to start, and
1524 * we haven't timed out, reset the timer, and return */
1525 if (result && secondary--) {
1526 mod_timer(&priv->phy_info_timer, jiffies + HZ);
1528 } else if (result) {
1529 /* Couldn't start autonegotiation.
1530 * Try switching to forced */
1531 mii_info->autoneg = 0;
1532 result = mii_info->phyinfo->config_aneg(mii_info);
1534 /* Forcing failed! Give up */
1536 printk(KERN_ERR "%s: Forcing failed!\n",
1537 mii_info->dev->name);
1542 /* Kill the timer so it can be restarted */
1543 del_timer_sync(&priv->phy_info_timer);
1545 /* Grab the PHY interrupt, if necessary/possible */
1546 if (priv->einfo->board_flags & FSL_GIANFAR_BRD_HAS_PHY_INTR) {
1547 if (request_irq(priv->einfo->interruptPHY,
1551 mii_info->dev) < 0) {
1552 printk(KERN_ERR "%s: Can't get IRQ %d (PHY)\n",
1553 mii_info->dev->name,
1554 priv->einfo->interruptPHY);
1556 mii_configure_phy_interrupt(priv->mii_info,
1557 MII_INTERRUPT_ENABLED);
1562 /* Start the timer again, this time in order to
1563 * handle a change in status */
1564 init_timer(&priv->phy_info_timer);
1565 priv->phy_info_timer.function = &gfar_phy_timer;
1566 priv->phy_info_timer.data = (unsigned long) mii_info->dev;
1567 mod_timer(&priv->phy_info_timer, jiffies +
1568 GFAR_PHY_CHANGE_TIME * HZ);
1571 /* Called every time the controller might need to be made
1572 * aware of new link state. The PHY code conveys this
1573 * information through variables in the priv structure, and this
1574 * function converts those variables into the appropriate
1575 * register values, and can bring down the device if needed.
1577 static void adjust_link(struct net_device *dev)
1579 struct gfar_private *priv = netdev_priv(dev);
1580 struct gfar *regs = priv->regs;
1582 struct gfar_mii_info *mii_info = priv->mii_info;
1584 if (mii_info->link) {
1585 /* Now we make sure that we can be in full duplex mode.
1586 * If not, we operate in half-duplex mode. */
1587 if (mii_info->duplex != priv->oldduplex) {
1588 if (!(mii_info->duplex)) {
1589 tempval = gfar_read(®s->maccfg2);
1590 tempval &= ~(MACCFG2_FULL_DUPLEX);
1591 gfar_write(®s->maccfg2, tempval);
1593 printk(KERN_INFO "%s: Half Duplex\n",
1596 tempval = gfar_read(®s->maccfg2);
1597 tempval |= MACCFG2_FULL_DUPLEX;
1598 gfar_write(®s->maccfg2, tempval);
1600 printk(KERN_INFO "%s: Full Duplex\n",
1604 priv->oldduplex = mii_info->duplex;
1607 if (mii_info->speed != priv->oldspeed) {
1608 switch (mii_info->speed) {
1610 tempval = gfar_read(®s->maccfg2);
1612 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1613 gfar_write(®s->maccfg2, tempval);
1617 tempval = gfar_read(®s->maccfg2);
1619 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1620 gfar_write(®s->maccfg2, tempval);
1624 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1625 dev->name, mii_info->speed);
1629 printk(KERN_INFO "%s: Speed %dBT\n", dev->name,
1632 priv->oldspeed = mii_info->speed;
1635 if (!priv->oldlink) {
1636 printk(KERN_INFO "%s: Link is up\n", dev->name);
1638 netif_carrier_on(dev);
1639 netif_schedule(dev);
1642 if (priv->oldlink) {
1643 printk(KERN_INFO "%s: Link is down\n", dev->name);
1646 priv->oldduplex = -1;
1647 netif_carrier_off(dev);
1653 /* Update the hash table based on the current list of multicast
1654 * addresses we subscribe to. Also, change the promiscuity of
1655 * the device based on the flags (this function is called
1656 * whenever dev->flags is changed */
1657 static void gfar_set_multi(struct net_device *dev)
1659 struct dev_mc_list *mc_ptr;
1660 struct gfar_private *priv = netdev_priv(dev);
1661 struct gfar *regs = priv->regs;
1664 if(dev->flags & IFF_PROMISC) {
1665 printk(KERN_INFO "%s: Entering promiscuous mode.\n",
1667 /* Set RCTRL to PROM */
1668 tempval = gfar_read(®s->rctrl);
1669 tempval |= RCTRL_PROM;
1670 gfar_write(®s->rctrl, tempval);
1672 /* Set RCTRL to not PROM */
1673 tempval = gfar_read(®s->rctrl);
1674 tempval &= ~(RCTRL_PROM);
1675 gfar_write(®s->rctrl, tempval);
1678 if(dev->flags & IFF_ALLMULTI) {
1679 /* Set the hash to rx all multicast frames */
1680 gfar_write(®s->gaddr0, 0xffffffff);
1681 gfar_write(®s->gaddr1, 0xffffffff);
1682 gfar_write(®s->gaddr2, 0xffffffff);
1683 gfar_write(®s->gaddr3, 0xffffffff);
1684 gfar_write(®s->gaddr4, 0xffffffff);
1685 gfar_write(®s->gaddr5, 0xffffffff);
1686 gfar_write(®s->gaddr6, 0xffffffff);
1687 gfar_write(®s->gaddr7, 0xffffffff);
1689 /* zero out the hash */
1690 gfar_write(®s->gaddr0, 0x0);
1691 gfar_write(®s->gaddr1, 0x0);
1692 gfar_write(®s->gaddr2, 0x0);
1693 gfar_write(®s->gaddr3, 0x0);
1694 gfar_write(®s->gaddr4, 0x0);
1695 gfar_write(®s->gaddr5, 0x0);
1696 gfar_write(®s->gaddr6, 0x0);
1697 gfar_write(®s->gaddr7, 0x0);
1699 if(dev->mc_count == 0)
1702 /* Parse the list, and set the appropriate bits */
1703 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1704 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1711 /* Set the appropriate hash bit for the given addr */
1712 /* The algorithm works like so:
1713 * 1) Take the Destination Address (ie the multicast address), and
1714 * do a CRC on it (little endian), and reverse the bits of the
1716 * 2) Use the 8 most significant bits as a hash into a 256-entry
1717 * table. The table is controlled through 8 32-bit registers:
1718 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1719 * gaddr7. This means that the 3 most significant bits in the
1720 * hash index which gaddr register to use, and the 5 other bits
1721 * indicate which bit (assuming an IBM numbering scheme, which
1722 * for PowerPC (tm) is usually the case) in the register holds
1724 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1727 struct gfar_private *priv = netdev_priv(dev);
1728 struct gfar *regs = priv->regs;
1729 u32 *hash = ®s->gaddr0;
1730 u32 result = ether_crc(MAC_ADDR_LEN, addr);
1731 u8 whichreg = ((result >> 29) & 0x7);
1732 u8 whichbit = ((result >> 24) & 0x1f);
1733 u32 value = (1 << (31-whichbit));
1735 tempval = gfar_read(&hash[whichreg]);
1737 gfar_write(&hash[whichreg], tempval);
1742 /* GFAR error interrupt handler */
1743 static irqreturn_t gfar_error(int irq, void *dev_id, struct pt_regs *regs)
1745 struct net_device *dev = dev_id;
1746 struct gfar_private *priv = netdev_priv(dev);
1748 /* Save ievent for future reference */
1749 u32 events = gfar_read(&priv->regs->ievent);
1752 gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
1755 #if defined (BRIEF_GFAR_ERRORS) || defined (VERBOSE_GFAR_ERRORS)
1756 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1757 dev->name, events, gfar_read(&priv->regs->imask));
1760 /* Update the error counters */
1761 if (events & IEVENT_TXE) {
1762 priv->stats.tx_errors++;
1764 if (events & IEVENT_LC)
1765 priv->stats.tx_window_errors++;
1766 if (events & IEVENT_CRL)
1767 priv->stats.tx_aborted_errors++;
1768 if (events & IEVENT_XFUN) {
1769 #ifdef VERBOSE_GFAR_ERRORS
1770 printk(KERN_DEBUG "%s: underrun. packet dropped.\n",
1773 priv->stats.tx_dropped++;
1774 priv->extra_stats.tx_underrun++;
1776 /* Reactivate the Tx Queues */
1777 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1779 #ifdef VERBOSE_GFAR_ERRORS
1780 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1783 if (events & IEVENT_BSY) {
1784 priv->stats.rx_errors++;
1785 priv->extra_stats.rx_bsy++;
1787 gfar_receive(irq, dev_id, regs);
1789 #ifndef CONFIG_GFAR_NAPI
1790 /* Clear the halt bit in RSTAT */
1791 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1794 #ifdef VERBOSE_GFAR_ERRORS
1795 printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n", dev->name,
1796 gfar_read(&priv->regs->rstat));
1799 if (events & IEVENT_BABR) {
1800 priv->stats.rx_errors++;
1801 priv->extra_stats.rx_babr++;
1803 #ifdef VERBOSE_GFAR_ERRORS
1804 printk(KERN_DEBUG "%s: babbling error\n", dev->name);
1807 if (events & IEVENT_EBERR) {
1808 priv->extra_stats.eberr++;
1809 #ifdef VERBOSE_GFAR_ERRORS
1810 printk(KERN_DEBUG "%s: EBERR\n", dev->name);
1813 if (events & IEVENT_RXC)
1814 #ifdef VERBOSE_GFAR_ERRORS
1815 printk(KERN_DEBUG "%s: control frame\n", dev->name);
1818 if (events & IEVENT_BABT) {
1819 priv->extra_stats.tx_babt++;
1820 #ifdef VERBOSE_GFAR_ERRORS
1821 printk(KERN_DEBUG "%s: babt error\n", dev->name);
1827 /* Structure for a device driver */
1828 static struct device_driver gfar_driver = {
1829 .name = "fsl-gianfar",
1830 .bus = &platform_bus_type,
1831 .probe = gfar_probe,
1832 .remove = gfar_remove,
1835 static int __init gfar_init(void)
1837 return driver_register(&gfar_driver);
1840 static void __exit gfar_exit(void)
1842 driver_unregister(&gfar_driver);
1845 module_init(gfar_init);
1846 module_exit(gfar_exit);