2 * drivers/net/gianfar_phy.h
4 * Gianfar Ethernet Driver -- PHY handling
5 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala (kumar.gala@freescale.com)
11 * Copyright 2004 Freescale Semiconductor, Inc
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #ifndef __GIANFAR_PHY_H
20 #define __GIANFAR_PHY_H
22 /* simple datum processing commands */
23 #define miim_end (0xffff0000U)
24 #define miim_read (0x00010000U)
25 #define miim_clear_bits(reg,x) { reg, (0x00020000U | ~(u32)(x)), NULL }
26 #define miim_set_bits(reg,x) { reg, (0x00030000U | (u32)(x)), NULL }
27 #define miim_flip_bits(reg,x) { reg, (0x00040000U | (u32)(x)), NULL }
28 #define miim_write(reg, x) { reg, (0x0000ffffU & (u32)(x)), NULL }
30 #define MIIMIND_BUSY 0x00000001
31 #define MIIMIND_NOTVALID 0x00000004
33 #define MIIM_CONTROL 0x00
34 #define MIIM_CONTROL_RESET 0x00008000
35 #define MIIM_CONTROL_INIT 0x00001140
36 #define MIIM_ANEN 0x00001000
39 #define MIIM_CR_RST 0x00008000
40 #define MIIM_CR_INIT 0x00001000
42 #define MIIM_STATUS 0x1
43 #define MIIM_STATUS_AN_DONE 0x00000020
44 #define MIIM_STATUS_LINK 0x0004
46 #define MIIM_PHYIR1 0x2
47 #define MIIM_PHYIR2 0x3
49 #define GFAR_AN_TIMEOUT 0x000fffff
51 #define MIIM_ANLPBPA 0x5
52 #define MIIM_ANLPBPA_HALF 0x00000040
53 #define MIIM_ANLPBPA_FULL 0x00000020
56 #define MIIM_ANEX_NP 0x00000004
57 #define MIIM_ANEX_PRX 0x00000002
60 /* Cicada Extended Control Register 1 */
61 #define MIIM_CIS8201_EXT_CON1 0x17
62 #define MIIM_CIS8201_EXTCON1_INIT 0x0000
64 /* Cicada Interrupt Mask Register */
65 #define MIIM_CIS8204_IMASK 0x19
66 #define MIIM_CIS8204_IMASK_IEN 0x8000
67 #define MIIM_CIS8204_IMASK_SPEED 0x4000
68 #define MIIM_CIS8204_IMASK_LINK 0x2000
69 #define MIIM_CIS8204_IMASK_DUPLEX 0x1000
70 #define MIIM_CIS8204_IMASK_MASK 0xf000
72 /* Cicada Interrupt Status Register */
73 #define MIIM_CIS8204_ISTAT 0x1a
74 #define MIIM_CIS8204_ISTAT_STATUS 0x8000
75 #define MIIM_CIS8204_ISTAT_SPEED 0x4000
76 #define MIIM_CIS8204_ISTAT_LINK 0x2000
77 #define MIIM_CIS8204_ISTAT_DUPLEX 0x1000
79 /* Cicada Auxiliary Control/Status Register */
80 #define MIIM_CIS8201_AUX_CONSTAT 0x1c
81 #define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004
82 #define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020
83 #define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018
84 #define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010
85 #define MIIM_CIS8201_AUXCONSTAT_100 0x0008
87 /* 88E1011 PHY Status Register */
88 #define MIIM_88E1011_PHY_STATUS 0x11
89 #define MIIM_88E1011_PHYSTAT_SPEED 0xc000
90 #define MIIM_88E1011_PHYSTAT_GBIT 0x8000
91 #define MIIM_88E1011_PHYSTAT_100 0x4000
92 #define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000
93 #define MIIM_88E1011_PHYSTAT_LINK 0x0400
95 #define MIIM_88E1011_IEVENT 0x13
96 #define MIIM_88E1011_IEVENT_CLEAR 0x0000
98 #define MIIM_88E1011_IMASK 0x12
99 #define MIIM_88E1011_IMASK_INIT 0x6400
100 #define MIIM_88E1011_IMASK_CLEAR 0x0000
102 /* DM9161 Control register values */
103 #define MIIM_DM9161_CR_STOP 0x0400
104 #define MIIM_DM9161_CR_RSTAN 0x1200
106 #define MIIM_DM9161_SCR 0x10
107 #define MIIM_DM9161_SCR_INIT 0x0610
109 /* DM9161 Specified Configuration and Status Register */
110 #define MIIM_DM9161_SCSR 0x11
111 #define MIIM_DM9161_SCSR_100F 0x8000
112 #define MIIM_DM9161_SCSR_100H 0x4000
113 #define MIIM_DM9161_SCSR_10F 0x2000
114 #define MIIM_DM9161_SCSR_10H 0x1000
116 /* DM9161 Interrupt Register */
117 #define MIIM_DM9161_INTR 0x15
118 #define MIIM_DM9161_INTR_PEND 0x8000
119 #define MIIM_DM9161_INTR_DPLX_MASK 0x0800
120 #define MIIM_DM9161_INTR_SPD_MASK 0x0400
121 #define MIIM_DM9161_INTR_LINK_MASK 0x0200
122 #define MIIM_DM9161_INTR_MASK 0x0100
123 #define MIIM_DM9161_INTR_DPLX_CHANGE 0x0010
124 #define MIIM_DM9161_INTR_SPD_CHANGE 0x0008
125 #define MIIM_DM9161_INTR_LINK_CHANGE 0x0004
126 #define MIIM_DM9161_INTR_INIT 0x0000
127 #define MIIM_DM9161_INTR_STOP \
128 (MIIM_DM9161_INTR_DPLX_MASK | MIIM_DM9161_INTR_SPD_MASK \
129 | MIIM_DM9161_INTR_LINK_MASK | MIIM_DM9161_INTR_MASK)
131 /* DM9161 10BT Configuration/Status */
132 #define MIIM_DM9161_10BTCSR 0x12
133 #define MIIM_DM9161_10BTCSR_INIT 0x7800
136 #define MIIM_BCM54xx_AUXCONTROL 0x18
137 #define MIIM_BCM54xx_AUXSTATUS 0x19
138 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700
139 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8
141 #define MIIM_READ_COMMAND 0x00000001
144 * struct phy_cmd: A command for reading or writing a PHY register
146 * mii_reg: The register to read or write
148 * mii_data: For writes, the value to put in the register.
149 * A value of -1 indicates this is a read.
151 * funct: A function pointer which is invoked for each command.
152 * For reads, this function will be passed the value read
153 * from the PHY, and process it.
154 * For writes, the result of this function will be written
155 * to the PHY register
160 u16 (*funct) (u16 mii_reg, struct net_device * dev);
163 /* struct phy_info: a structure which defines attributes for a PHY
165 * id will contain a number which represents the PHY. During
166 * startup, the driver will poll the PHY to find out what its
167 * UID--as defined by registers 2 and 3--is. The 32-bit result
168 * gotten from the PHY will be shifted right by "shift" bits to
169 * discard any bits which may change based on revision numbers
170 * unimportant to functionality
172 * The struct phy_cmd entries represent pointers to an arrays of
173 * commands which tell the driver what to do to the PHY.
179 /* Called to configure the PHY, and modify the controller
180 * based on the results */
181 const struct phy_cmd *config;
183 /* Called when starting up the controller. Usually sets
184 * up the interrupt for state changes */
185 const struct phy_cmd *startup;
187 /* Called inside the interrupt handler to acknowledge
189 const struct phy_cmd *ack_int;
191 /* Called in the bottom half to handle the interrupt */
192 const struct phy_cmd *handle_int;
194 /* Called when bringing down the controller. Usually stops
195 * the interrupts from being generated */
196 const struct phy_cmd *shutdown;
199 struct phy_info *get_phy_info(struct net_device *dev);
200 void phy_run_commands(struct net_device *dev, const struct phy_cmd *cmd);
202 #endif /* GIANFAR_PHY_H */