2 * Copyright 2000, 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * stevel@mvista.com or source@mvista.com
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 * Ethernet driver for the MIPS GT96100 Advanced Communication Controller.
23 * 11.11.2001 Moved to 2.4.14, ppopov@mvista.com. Modified driver to add
24 * proper gt96100A support.
25 * 12.05.2001 Moved eth port 0 to irq 3 (mapped to GT_SERINT0 on EV96100A)
26 * in order for both ports to work. Also cleaned up boot
27 * option support (mac address string parsing), fleshed out
28 * gt96100_cleanup_module(), and other general code cleanups
29 * <stevel@mvista.com>.
31 #include <linux/config.h>
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/string.h>
35 #include <linux/timer.h>
36 #include <linux/errno.h>
38 #include <linux/ioport.h>
39 #include <linux/slab.h>
40 #include <linux/interrupt.h>
41 #include <linux/pci.h>
42 #include <linux/init.h>
43 #include <linux/netdevice.h>
44 #include <linux/etherdevice.h>
45 #include <linux/skbuff.h>
46 #include <linux/delay.h>
47 #include <linux/ctype.h>
50 #include <asm/bitops.h>
54 #define DESC_DATA_BE 1
56 #define GT96100_DEBUG 2
58 #include "gt96100eth.h"
61 static void* dmaalloc(size_t size, dma_addr_t *dma_handle);
62 static void dmafree(size_t size, void *vaddr);
63 static void gt96100_delay(int msec);
64 static int gt96100_add_hash_entry(struct net_device *dev,
66 static void read_mib_counters(struct gt96100_private *gp);
67 static int read_MII(int phy_addr, u32 reg);
68 static int write_MII(int phy_addr, u32 reg, u16 data);
70 static void dump_tx_ring(struct net_device *dev);
71 static void dump_rx_ring(struct net_device *dev);
73 static int gt96100_init_module(void);
74 static void gt96100_cleanup_module(void);
75 static void dump_MII(int dbg_lvl, struct net_device *dev);
76 static void dump_tx_desc(int dbg_lvl, struct net_device *dev, int i);
77 static void dump_rx_desc(int dbg_lvl, struct net_device *dev, int i);
78 static void dump_skb(int dbg_lvl, struct net_device *dev,
80 static void dump_hw_addr(int dbg_lvl, struct net_device *dev,
81 const char* pfx, unsigned char* addr_str);
82 static void update_stats(struct gt96100_private *gp);
83 static void abort(struct net_device *dev, u32 abort_bits);
84 static void hard_stop(struct net_device *dev);
85 static void enable_ether_irq(struct net_device *dev);
86 static void disable_ether_irq(struct net_device *dev);
87 static int gt96100_probe1(int port_num);
88 static void reset_tx(struct net_device *dev);
89 static void reset_rx(struct net_device *dev);
90 static int gt96100_check_tx_consistent(struct gt96100_private *gp);
91 static int gt96100_init(struct net_device *dev);
92 static int gt96100_open(struct net_device *dev);
93 static int gt96100_close(struct net_device *dev);
94 static int gt96100_tx(struct sk_buff *skb, struct net_device *dev);
95 static int gt96100_rx(struct net_device *dev, u32 status);
96 static irqreturn_t gt96100_interrupt(int irq, void *dev_id, struct pt_regs *regs);
97 static void gt96100_tx_timeout(struct net_device *dev);
98 static void gt96100_set_rx_mode(struct net_device *dev);
99 static struct net_device_stats* gt96100_get_stats(struct net_device *dev);
101 extern char * __init prom_getcmdline(void);
103 static int max_interrupt_work = 32;
105 #define nibswap(x) ((((x) >> 4) & 0x0f) | (((x) << 4) & 0xf0))
107 #define RUN_AT(x) (jiffies + (x))
109 // For reading/writing 32-bit words and half-words from/to DMA memory
111 #define cpu_to_dma32 cpu_to_be32
112 #define dma32_to_cpu be32_to_cpu
113 #define cpu_to_dma16 cpu_to_be16
114 #define dma16_to_cpu be16_to_cpu
116 #define cpu_to_dma32 cpu_to_le32
117 #define dma32_to_cpu le32_to_cpu
118 #define cpu_to_dma16 cpu_to_le16
119 #define dma16_to_cpu le16_to_cpu
122 static char mac0[18] = "00.02.03.04.05.06";
123 static char mac1[18] = "00.01.02.03.04.05";
124 MODULE_PARM(mac0, "c18");
125 MODULE_PARM(mac1, "c18");
126 MODULE_PARM_DESC(mac0, "MAC address for GT96100 ethernet port 0");
127 MODULE_PARM_DESC(mac1, "MAC address for GT96100 ethernet port 1");
130 * Info for the GT96100 ethernet controller's ports.
132 static struct gt96100_if_t {
133 struct net_device *dev;
134 unsigned int iobase; // IO Base address of this port
135 int irq; // IRQ number of this port
137 } gt96100_iflist[NUM_INTERFACES] = {
140 GT96100_ETH0_BASE, GT96100_ETHER0_IRQ,
145 GT96100_ETH1_BASE, GT96100_ETHER1_IRQ,
150 static inline const char*
151 chip_name(int chip_rev)
160 return "Unknown GT96100";
165 DMA memory allocation, derived from pci_alloc_consistent.
168 dmaalloc(size_t size, dma_addr_t *dma_handle)
172 ret = (void *)__get_free_pages(GFP_ATOMIC | GFP_DMA,
176 dma_cache_inv((unsigned long)ret, size);
177 if (dma_handle != NULL)
178 *dma_handle = virt_to_phys(ret);
180 /* bump virtual address up to non-cached area */
181 ret = (void*)KSEG1ADDR(ret);
188 dmafree(size_t size, void *vaddr)
190 vaddr = (void*)KSEG0ADDR(vaddr);
191 free_pages((unsigned long)vaddr, get_order(size));
197 gt96100_delay(int ms)
202 current->state = TASK_INTERRUPTIBLE;
203 schedule_timeout(ms*HZ/1000);
208 parse_mac_addr(struct net_device *dev, char* macstr)
211 unsigned char result, value;
213 for (i=0; i<6; i++) {
215 if (i != 5 && *(macstr+2) != '.') {
216 err(__FILE__ "invalid mac address format: %d %c\n",
221 for (j=0; j<2; j++) {
222 if (isxdigit(*macstr) &&
223 (value = isdigit(*macstr) ? *macstr-'0' :
224 toupper(*macstr)-'A'+10) < 16) {
225 result = result*16 + value;
228 err(__FILE__ "invalid mac address "
229 "character: %c\n", *macstr);
234 macstr++; // step over '.'
235 dev->dev_addr[i] = result;
243 read_MII(int phy_addr, u32 reg)
246 u32 smir = smirOpCode | (phy_addr << smirPhyAdBit) |
247 (reg << smirRegAdBit);
249 // wait for last operation to complete
250 while (GT96100_READ(GT96100_ETH_SMI_REG) & smirBusy) {
251 // snooze for 1 msec and check again
254 if (--timedout == 0) {
255 printk(KERN_ERR "%s: busy timeout!!\n", __FUNCTION__);
260 GT96100_WRITE(GT96100_ETH_SMI_REG, smir);
263 // wait for read to complete
264 while (!((smir = GT96100_READ(GT96100_ETH_SMI_REG)) & smirReadValid)) {
265 // snooze for 1 msec and check again
268 if (--timedout == 0) {
269 printk(KERN_ERR "%s: timeout!!\n", __FUNCTION__);
274 return (int)(smir & smirDataMask);
278 dump_tx_desc(int dbg_lvl, struct net_device *dev, int i)
280 struct gt96100_private *gp = netdev_priv(dev);
281 gt96100_td_t *td = &gp->tx_ring[i];
283 dbg(dbg_lvl, "Tx descriptor at 0x%08lx:\n", virt_to_phys(td));
285 " cmdstat=%04x, byte_cnt=%04x, buff_ptr=%04x, next=%04x\n",
286 dma32_to_cpu(td->cmdstat),
287 dma16_to_cpu(td->byte_cnt),
288 dma32_to_cpu(td->buff_ptr),
289 dma32_to_cpu(td->next));
293 dump_rx_desc(int dbg_lvl, struct net_device *dev, int i)
295 struct gt96100_private *gp = netdev_priv(dev);
296 gt96100_rd_t *rd = &gp->rx_ring[i];
298 dbg(dbg_lvl, "Rx descriptor at 0x%08lx:\n", virt_to_phys(rd));
299 dbg(dbg_lvl, " cmdstat=%04x, buff_sz=%04x, byte_cnt=%04x, "
300 "buff_ptr=%04x, next=%04x\n",
301 dma32_to_cpu(rd->cmdstat),
302 dma16_to_cpu(rd->buff_sz),
303 dma16_to_cpu(rd->byte_cnt),
304 dma32_to_cpu(rd->buff_ptr),
305 dma32_to_cpu(rd->next));
309 write_MII(int phy_addr, u32 reg, u16 data)
312 u32 smir = (phy_addr << smirPhyAdBit) |
313 (reg << smirRegAdBit) | data;
315 // wait for last operation to complete
316 while (GT96100_READ(GT96100_ETH_SMI_REG) & smirBusy) {
317 // snooze for 1 msec and check again
320 if (--timedout == 0) {
321 printk(KERN_ERR "%s: busy timeout!!\n", __FUNCTION__);
326 GT96100_WRITE(GT96100_ETH_SMI_REG, smir);
331 // These routines work, just disabled to avoid compile warnings
333 dump_tx_ring(struct net_device *dev)
335 struct gt96100_private *gp = netdev_priv(dev);
338 dbg(0, "%s: txno/txni/cnt=%d/%d/%d\n", __FUNCTION__,
339 gp->tx_next_out, gp->tx_next_in, gp->tx_count);
341 for (i=0; i<TX_RING_SIZE; i++)
342 dump_tx_desc(0, dev, i);
346 dump_rx_ring(struct net_device *dev)
348 struct gt96100_private *gp = netdev_priv(dev);
351 dbg(0, "%s: rxno=%d\n", __FUNCTION__, gp->rx_next_out);
353 for (i=0; i<RX_RING_SIZE; i++)
354 dump_rx_desc(0, dev, i);
359 dump_MII(int dbg_lvl, struct net_device *dev)
362 struct gt96100_private *gp = netdev_priv(dev);
364 if (dbg_lvl <= GT96100_DEBUG) {
365 for (i=0; i<7; i++) {
366 if ((val = read_MII(gp->phy_addr, i)) >= 0)
367 printk("MII Reg %d=%x\n", i, val);
369 for (i=16; i<21; i++) {
370 if ((val = read_MII(gp->phy_addr, i)) >= 0)
371 printk("MII Reg %d=%x\n", i, val);
377 dump_hw_addr(int dbg_lvl, struct net_device *dev, const char* pfx,
378 unsigned char* addr_str)
381 char buf[100], octet[5];
383 if (dbg_lvl <= GT96100_DEBUG) {
385 for (i = 0; i < 6; i++) {
386 sprintf(octet, "%2.2x%s",
387 addr_str[i], i<5 ? ":" : "\n");
396 dump_skb(int dbg_lvl, struct net_device *dev, struct sk_buff *skb)
399 unsigned char* skbdata;
401 if (dbg_lvl <= GT96100_DEBUG) {
402 dbg(dbg_lvl, "%s: skb=%p, skb->data=%p, skb->len=%d\n",
403 __FUNCTION__, skb, skb->data, skb->len);
405 skbdata = (unsigned char*)KSEG1ADDR(skb->data);
407 for (i=0; i<skb->len; i++) {
409 printk(KERN_DEBUG "\n %3.3x: %2.2x,",
412 printk(KERN_DEBUG "%2.2x,", skbdata[i]);
414 printk(KERN_DEBUG "\n");
420 gt96100_add_hash_entry(struct net_device *dev, unsigned char* addr)
422 struct gt96100_private *gp = netdev_priv(dev);
423 //u16 hashResult, stmp;
424 //unsigned char ctmp, hash_ea[6];
425 u32 tblEntry1, tblEntry0, *tblEntryAddr;
428 tblEntry1 = hteValid | hteRD;
429 tblEntry1 |= (u32)addr[5] << 3;
430 tblEntry1 |= (u32)addr[4] << 11;
431 tblEntry1 |= (u32)addr[3] << 19;
432 tblEntry1 |= ((u32)addr[2] & 0x1f) << 27;
433 dbg(3, "%s: tblEntry1=%x\n", __FUNCTION__, tblEntry1);
434 tblEntry0 = ((u32)addr[2] >> 5) & 0x07;
435 tblEntry0 |= (u32)addr[1] << 3;
436 tblEntry0 |= (u32)addr[0] << 11;
437 dbg(3, "%s: tblEntry0=%x\n", __FUNCTION__, tblEntry0);
441 for (i=0; i<6; i++) {
443 ctmp = nibswap(addr[i]);
444 // invert every nibble
445 hash_ea[i] = ((ctmp&1)<<3) | ((ctmp&8)>>3) |
446 ((ctmp&2)<<1) | ((ctmp&4)>>1);
447 hash_ea[i] |= ((ctmp&0x10)<<3) | ((ctmp&0x80)>>3) |
448 ((ctmp&0x20)<<1) | ((ctmp&0x40)>>1);
451 dump_hw_addr(3, dev, "%s: nib swap/invt addr=", __FUNCTION__, hash_ea);
453 if (gp->hash_mode == 0) {
454 hashResult = ((u16)hash_ea[0] & 0xfc) << 7;
455 stmp = ((u16)hash_ea[0] & 0x03) |
456 (((u16)hash_ea[1] & 0x7f) << 2);
457 stmp ^= (((u16)hash_ea[1] >> 7) & 0x01) |
458 ((u16)hash_ea[2] << 1);
459 stmp ^= (u16)hash_ea[3] | (((u16)hash_ea[4] & 1) << 8);
462 return -1; // don't support hash mode 1
465 dbg(3, "%s: hashResult=%x\n", __FUNCTION__, hashResult);
468 (u32 *)(&gp->hash_table[((u32)hashResult & 0x7ff) << 3]);
470 dbg(3, "%s: tblEntryAddr=%p\n", tblEntryAddr, __FUNCTION__);
472 for (i=0; i<HASH_HOP_NUMBER; i++) {
473 if ((*tblEntryAddr & hteValid) &&
474 !(*tblEntryAddr & hteSkip)) {
475 // This entry is already occupied, go to next entry
477 dbg(3, "%s: skipping to %p\n", __FUNCTION__,
480 memset(tblEntryAddr, 0, 8);
481 tblEntryAddr[1] = cpu_to_dma32(tblEntry1);
482 tblEntryAddr[0] = cpu_to_dma32(tblEntry0);
487 if (i >= HASH_HOP_NUMBER) {
488 err("%s: expired!\n", __FUNCTION__);
489 return -1; // Couldn't find an unused entry
494 tblEntryAddr = (u32 *)gp->hash_table;
495 for (i=0; i<RX_HASH_TABLE_SIZE/4; i+=2) {
496 tblEntryAddr[i+1] = cpu_to_dma32(tblEntry1);
497 tblEntryAddr[i] = cpu_to_dma32(tblEntry0);
507 read_mib_counters(struct gt96100_private *gp)
509 u32* mib_regs = (u32*)&gp->mib;
512 for (i=0; i<sizeof(mib_counters_t)/sizeof(u32); i++)
513 mib_regs[i] = GT96100ETH_READ(gp, GT96100_ETH_MIB_COUNT_BASE +
519 update_stats(struct gt96100_private *gp)
521 mib_counters_t *mib = &gp->mib;
522 struct net_device_stats *stats = &gp->stats;
524 read_mib_counters(gp);
526 stats->rx_packets = mib->totalFramesReceived;
527 stats->tx_packets = mib->framesSent;
528 stats->rx_bytes = mib->totalByteReceived;
529 stats->tx_bytes = mib->byteSent;
530 stats->rx_errors = mib->totalFramesReceived - mib->framesReceived;
531 //the tx error counters are incremented by the ISR
532 //rx_dropped incremented by gt96100_rx
533 //tx_dropped incremented by gt96100_tx
534 stats->multicast = mib->multicastFramesReceived;
535 // collisions incremented by gt96100_tx_complete
536 stats->rx_length_errors = mib->oversizeFrames + mib->fragments;
537 // The RxError condition means the Rx DMA encountered a
538 // CPU owned descriptor, which, if things are working as
539 // they should, means the Rx ring has overflowed.
540 stats->rx_over_errors = mib->macRxError;
541 stats->rx_crc_errors = mib->cRCError;
545 abort(struct net_device *dev, u32 abort_bits)
547 struct gt96100_private *gp = netdev_priv(dev);
548 int timedout = 100; // wait up to 100 msec for hard stop to complete
550 dbg(3, "%s\n", __FUNCTION__);
552 // Return if neither Rx or Tx abort bits are set
553 if (!(abort_bits & (sdcmrAR | sdcmrAT)))
556 // make sure only the Rx/Tx abort bits are set
557 abort_bits &= (sdcmrAR | sdcmrAT);
559 spin_lock(&gp->lock);
561 // abort any Rx/Tx DMA immediately
562 GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, abort_bits);
564 dbg(3, "%s: SDMA comm = %x\n", __FUNCTION__,
565 GT96100ETH_READ(gp, GT96100_ETH_SDMA_COMM));
567 // wait for abort to complete
568 while (GT96100ETH_READ(gp, GT96100_ETH_SDMA_COMM) & abort_bits) {
569 // snooze for 20 msec and check again
572 if (--timedout == 0) {
573 err("%s: timeout!!\n", __FUNCTION__);
578 spin_unlock(&gp->lock);
583 hard_stop(struct net_device *dev)
585 struct gt96100_private *gp = netdev_priv(dev);
587 dbg(3, "%s\n", __FUNCTION__);
589 disable_ether_irq(dev);
591 abort(dev, sdcmrAR | sdcmrAT);
594 GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG, 0);
599 enable_ether_irq(struct net_device *dev)
601 struct gt96100_private *gp = netdev_priv(dev);
604 * route ethernet interrupt to GT_SERINT0 for port 0,
605 * GT_INT0 for port 1.
607 int intr_mask_reg = (gp->port_num == 0) ?
608 GT96100_SERINT0_MASK : GT96100_INT0_HIGH_MASK;
610 if (gp->chip_rev >= REV_GT96100A_1) {
611 intMask = icrTxBufferLow | icrTxEndLow |
612 icrTxErrorLow | icrRxOVR | icrTxUdr |
613 icrRxBufferQ0 | icrRxErrorQ0 |
614 icrMIIPhySTC | icrEtherIntSum;
617 intMask = icrTxBufferLow | icrTxEndLow |
618 icrTxErrorLow | icrRxOVR | icrTxUdr |
619 icrRxBuffer | icrRxError |
620 icrMIIPhySTC | icrEtherIntSum;
624 GT96100ETH_WRITE(gp, GT96100_ETH_INT_MASK, intMask);
626 intMask = GT96100_READ(intr_mask_reg);
627 intMask |= 1<<gp->port_num;
628 GT96100_WRITE(intr_mask_reg, intMask);
632 disable_ether_irq(struct net_device *dev)
634 struct gt96100_private *gp = netdev_priv(dev);
636 int intr_mask_reg = (gp->port_num == 0) ?
637 GT96100_SERINT0_MASK : GT96100_INT0_HIGH_MASK;
639 intMask = GT96100_READ(intr_mask_reg);
640 intMask &= ~(1<<gp->port_num);
641 GT96100_WRITE(intr_mask_reg, intMask);
643 GT96100ETH_WRITE(gp, GT96100_ETH_INT_MASK, 0);
648 * Init GT96100 ethernet controller driver
650 int gt96100_init_module(void)
653 u16 vendor_id, device_id;
656 #ifndef CONFIG_MIPS_GT96100ETH
660 // probe for GT96100 by reading PCI0 vendor/device ID register
661 pcibios_read_config_word(0, 0, PCI_VENDOR_ID, &vendor_id);
662 pcibios_read_config_word(0, 0, PCI_DEVICE_ID, &device_id);
664 if (vendor_id != PCI_VENDOR_ID_MARVELL ||
665 (device_id != PCI_DEVICE_ID_MARVELL_GT96100 &&
666 device_id != PCI_DEVICE_ID_MARVELL_GT96100A)) {
667 printk(KERN_ERR __FILE__ ": GT96100 not found!\n");
671 cpuConfig = GT96100_READ(GT96100_CPU_INTERF_CONFIG);
672 if (cpuConfig & (1<<12)) {
673 printk(KERN_ERR __FILE__
674 ": must be in Big Endian mode!\n");
678 for (i=0; i < NUM_INTERFACES; i++) {
679 retval |= gt96100_probe1(i);
688 gt96100_probe1(int port_num)
690 struct gt96100_private *gp = NULL;
691 struct gt96100_if_t *gtif = >96100_iflist[port_num];
692 int phy_addr, phy_id1, phy_id2;
695 unsigned char chip_rev;
696 struct net_device *dev = NULL;
699 printk(KERN_ERR "%s: irq unknown - probing not supported\n", __FUNCTION_);
703 pcibios_read_config_byte(0, 0, PCI_REVISION_ID, &chip_rev);
705 if (chip_rev >= REV_GT96100A_1) {
706 phyAD = GT96100_READ(GT96100_ETH_PHY_ADDR_REG);
707 phy_addr = (phyAD >> (5*port_num)) & 0x1f;
710 * not sure what's this about -- probably
714 phyAD = GT96100_READ(GT96100_ETH_PHY_ADDR_REG);
715 phyAD &= ~(0x1f << (port_num*5));
716 phyAD |= phy_addr << (port_num*5);
717 GT96100_WRITE(GT96100_ETH_PHY_ADDR_REG, phyAD);
720 // probe for the external PHY
721 if ((phy_id1 = read_MII(phy_addr, 2)) <= 0 ||
722 (phy_id2 = read_MII(phy_addr, 3)) <= 0) {
723 printk(KERN_ERR "%s: no PHY found on MII%d\n", __FUNCTION__, port_num);
727 if (!request_region(gtif->iobase, GT96100_ETH_IO_SIZE, "GT96100ETH")) {
728 printk(KERN_ERR "%s: request_region failed\n", __FUNCTION__);
732 dev = alloc_etherdev(sizeof(struct gt96100_private));
737 /* private struct aligned and zeroed by alloc_etherdev */
738 /* Fill in the 'dev' fields. */
739 dev->base_addr = gtif->iobase;
740 dev->irq = gtif->irq;
742 if ((retval = parse_mac_addr(dev, gtif->mac_str))) {
743 err("%s: MAC address parse failed\n", __FUNCTION__);
748 gp = netdev_priv(dev);
750 memset(gp, 0, sizeof(*gp)); // clear it
752 gp->port_num = port_num;
753 gp->io_size = GT96100_ETH_IO_SIZE;
754 gp->port_offset = port_num * GT96100_ETH_IO_SIZE;
755 gp->phy_addr = phy_addr;
756 gp->chip_rev = chip_rev;
758 info("%s found at 0x%x, irq %d\n",
759 chip_name(gp->chip_rev), gtif->iobase, gtif->irq);
760 dump_hw_addr(0, dev, "HW Address ", dev->dev_addr);
761 info("%s chip revision=%d\n", chip_name(gp->chip_rev), gp->chip_rev);
762 info("%s ethernet port %d\n", chip_name(gp->chip_rev), gp->port_num);
763 info("external PHY ID1=0x%04x, ID2=0x%04x\n", phy_id1, phy_id2);
765 // Allocate Rx and Tx descriptor rings
766 if (gp->rx_ring == NULL) {
767 // All descriptors in ring must be 16-byte aligned
768 gp->rx_ring = dmaalloc(sizeof(gt96100_rd_t) * RX_RING_SIZE
769 + sizeof(gt96100_td_t) * TX_RING_SIZE,
771 if (gp->rx_ring == NULL) {
776 gp->tx_ring = (gt96100_td_t *)(gp->rx_ring + RX_RING_SIZE);
778 gp->rx_ring_dma + sizeof(gt96100_rd_t) * RX_RING_SIZE;
781 // Allocate the Rx Data Buffers
782 if (gp->rx_buff == NULL) {
783 gp->rx_buff = dmaalloc(PKT_BUF_SZ*RX_RING_SIZE,
785 if (gp->rx_buff == NULL) {
791 dbg(3, "%s: rx_ring=%p, tx_ring=%p\n", __FUNCTION__,
792 gp->rx_ring, gp->tx_ring);
794 // Allocate Rx Hash Table
795 if (gp->hash_table == NULL) {
796 gp->hash_table = (char*)dmaalloc(RX_HASH_TABLE_SIZE,
797 &gp->hash_table_dma);
798 if (gp->hash_table == NULL) {
804 dbg(3, "%s: hash=%p\n", __FUNCTION__, gp->hash_table);
806 spin_lock_init(&gp->lock);
808 dev->open = gt96100_open;
809 dev->hard_start_xmit = gt96100_tx;
810 dev->stop = gt96100_close;
811 dev->get_stats = gt96100_get_stats;
812 //dev->do_ioctl = gt96100_ioctl;
813 dev->set_multicast_list = gt96100_set_rx_mode;
814 dev->tx_timeout = gt96100_tx_timeout;
815 dev->watchdog_timeo = GT96100ETH_TX_TIMEOUT;
817 retval = register_netdev(dev);
823 dmafree(RX_HASH_TABLE_SIZE, gp->hash_table_dma);
825 dmafree(PKT_BUF_SZ*RX_RING_SIZE, gp->rx_buff);
827 dmafree(sizeof(gt96100_rd_t) * RX_RING_SIZE
828 + sizeof(gt96100_td_t) * TX_RING_SIZE,
833 release_region(gtif->iobase, GT96100_ETH_IO_SIZE);
834 err("%s failed. Returns %d\n", __FUNCTION__, retval);
840 reset_tx(struct net_device *dev)
842 struct gt96100_private *gp = netdev_priv(dev);
847 for (i=0; i<TX_RING_SIZE; i++) {
848 if (gp->tx_skbuff[i]) {
850 dev_kfree_skb_irq(gp->tx_skbuff[i]);
852 dev_kfree_skb(gp->tx_skbuff[i]);
853 gp->tx_skbuff[i] = NULL;
856 gp->tx_ring[i].cmdstat = 0; // CPU owns
857 gp->tx_ring[i].byte_cnt = 0;
858 gp->tx_ring[i].buff_ptr = 0;
859 gp->tx_ring[i].next =
860 cpu_to_dma32(gp->tx_ring_dma +
861 sizeof(gt96100_td_t) * (i+1));
862 dump_tx_desc(4, dev, i);
865 gp->tx_ring[i-1].next = cpu_to_dma32(gp->tx_ring_dma);
867 // setup only the lowest priority TxCDP reg
868 GT96100ETH_WRITE(gp, GT96100_ETH_CURR_TX_DESC_PTR0, gp->tx_ring_dma);
869 GT96100ETH_WRITE(gp, GT96100_ETH_CURR_TX_DESC_PTR1, 0);
871 // init Tx indeces and pkt counter
872 gp->tx_next_in = gp->tx_next_out = 0;
878 reset_rx(struct net_device *dev)
880 struct gt96100_private *gp = netdev_priv(dev);
885 for (i=0; i<RX_RING_SIZE; i++) {
886 gp->rx_ring[i].next =
887 cpu_to_dma32(gp->rx_ring_dma +
888 sizeof(gt96100_rd_t) * (i+1));
889 gp->rx_ring[i].buff_ptr =
890 cpu_to_dma32(gp->rx_buff_dma + i*PKT_BUF_SZ);
891 gp->rx_ring[i].buff_sz = cpu_to_dma16(PKT_BUF_SZ);
892 // Give ownership to device, set first and last, enable intr
893 gp->rx_ring[i].cmdstat =
894 cpu_to_dma32((u32)(rxFirst | rxLast | rxOwn | rxEI));
895 dump_rx_desc(4, dev, i);
898 gp->rx_ring[i-1].next = cpu_to_dma32(gp->rx_ring_dma);
900 // Setup only the lowest priority RxFDP and RxCDP regs
901 for (i=0; i<4; i++) {
903 GT96100ETH_WRITE(gp, GT96100_ETH_1ST_RX_DESC_PTR0,
905 GT96100ETH_WRITE(gp, GT96100_ETH_CURR_RX_DESC_PTR0,
909 GT96100_ETH_1ST_RX_DESC_PTR0 + i*4,
912 GT96100_ETH_CURR_RX_DESC_PTR0 + i*4,
917 // init Rx NextOut index
922 // Returns 1 if the Tx counter and indeces don't gel
924 gt96100_check_tx_consistent(struct gt96100_private *gp)
926 int diff = gp->tx_next_in - gp->tx_next_out;
928 diff = diff<0 ? TX_RING_SIZE + diff : diff;
929 diff = gp->tx_count == TX_RING_SIZE ? diff + TX_RING_SIZE : diff;
931 return (diff != gp->tx_count);
935 gt96100_init(struct net_device *dev)
937 struct gt96100_private *gp = netdev_priv(dev);
941 dbg(3, "%s: dev=%p\n", __FUNCTION__, dev);
942 dbg(3, "%s: scs10_lo=%4x, scs10_hi=%4x\n", __FUNCTION__,
943 GT96100_READ(0x8), GT96100_READ(0x10));
944 dbg(3, "%s: scs32_lo=%4x, scs32_hi=%4x\n", __FUNCTION__,
945 GT96100_READ(0x18), GT96100_READ(0x20));
947 // Stop and disable Port
951 tmp = GT96100_READ(GT96100_CIU_ARBITER_CONFIG);
952 tmp |= (0x0c << (gp->port_num*2)); // set Ether DMA req priority to hi
954 tmp &= ~(1<<31); // set desc endianess to little
958 GT96100_WRITE(GT96100_CIU_ARBITER_CONFIG, tmp);
959 dbg(3, "%s: CIU Config=%x/%x\n", __FUNCTION__,
960 tmp, GT96100_READ(GT96100_CIU_ARBITER_CONFIG));
963 tmp = GT96100_READ(GT96100_ROUTE_MAIN) & (0x3f << 18);
964 tmp |= (0x07 << (18 + gp->port_num*3));
965 GT96100_WRITE(GT96100_ROUTE_MAIN, tmp);
967 /* set MII as peripheral func */
968 tmp = GT96100_READ(GT96100_GPP_CONFIG2);
969 tmp |= 0x7fff << (gp->port_num*16);
970 GT96100_WRITE(GT96100_GPP_CONFIG2, tmp);
972 /* Set up MII port pin directions */
973 tmp = GT96100_READ(GT96100_GPP_IO2);
974 tmp |= 0x003d << (gp->port_num*16);
975 GT96100_WRITE(GT96100_GPP_IO2, tmp);
978 memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); // clear it
980 // Add a single entry to hash table - our ethernet address
981 gt96100_add_hash_entry(dev, dev->dev_addr);
982 // Set-up DMA ptr to hash table
983 GT96100ETH_WRITE(gp, GT96100_ETH_HASH_TBL_PTR, gp->hash_table_dma);
984 dbg(3, "%s: Hash Tbl Ptr=%x\n", __FUNCTION__,
985 GT96100ETH_READ(gp, GT96100_ETH_HASH_TBL_PTR));
990 dbg(3, "%s: Curr Tx Desc Ptr0=%x\n", __FUNCTION__,
991 GT96100ETH_READ(gp, GT96100_ETH_CURR_TX_DESC_PTR0));
996 dbg(3, "%s: 1st/Curr Rx Desc Ptr0=%x/%x\n", __FUNCTION__,
997 GT96100ETH_READ(gp, GT96100_ETH_1ST_RX_DESC_PTR0),
998 GT96100ETH_READ(gp, GT96100_ETH_CURR_RX_DESC_PTR0));
1000 // eth port config register
1001 GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG_EXT,
1002 pcxrFCTL | pcxrFCTLen | pcxrFLP | pcxrDPLXen);
1004 mii_reg = read_MII(gp->phy_addr, 0x11); /* int enable register */
1005 mii_reg |= 2; /* enable mii interrupt */
1006 write_MII(gp->phy_addr, 0x11, mii_reg);
1008 dbg(3, "%s: PhyAD=%x\n", __FUNCTION__,
1009 GT96100_READ(GT96100_ETH_PHY_ADDR_REG));
1013 // We want the Rx/Tx DMA to write/read data to/from memory in
1014 // Big Endian mode. Also set DMA Burst Size to 8 64Bit words.
1016 GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_CONFIG,
1017 (0xf<<sdcrRCBit) | sdcrRIFB | (3<<sdcrBSZBit));
1019 GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_CONFIG,
1020 sdcrBLMR | sdcrBLMT |
1021 (0xf<<sdcrRCBit) | sdcrRIFB | (3<<sdcrBSZBit));
1023 dbg(3, "%s: SDMA Config=%x\n", __FUNCTION__,
1024 GT96100ETH_READ(gp, GT96100_ETH_SDMA_CONFIG));
1027 GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, sdcmrERD);
1028 dbg(3, "%s: SDMA Comm=%x\n", __FUNCTION__,
1029 GT96100ETH_READ(gp, GT96100_ETH_SDMA_COMM));
1031 // enable this port (set hash size to 1/2K)
1032 GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG, pcrEN | pcrHS);
1033 dbg(3, "%s: Port Config=%x\n", __FUNCTION__,
1034 GT96100ETH_READ(gp, GT96100_ETH_PORT_CONFIG));
1037 * Disable all Type-of-Service queueing. All Rx packets will be
1038 * treated normally and will be sent to the lowest priority
1041 * Disable flow-control for now. FIXME: support flow control?
1044 // clear all the MIB ctr regs
1045 GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG_EXT,
1046 pcxrFCTL | pcxrFCTLen | pcxrFLP |
1047 pcxrPRIOrxOverride);
1048 read_mib_counters(gp);
1049 GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG_EXT,
1050 pcxrFCTL | pcxrFCTLen | pcxrFLP |
1051 pcxrPRIOrxOverride | pcxrMIBclrMode);
1053 dbg(3, "%s: Port Config Ext=%x\n", __FUNCTION__,
1054 GT96100ETH_READ(gp, GT96100_ETH_PORT_CONFIG_EXT));
1056 netif_start_queue(dev);
1060 // enable interrupts
1061 enable_ether_irq(dev);
1063 // we should now be receiving frames
1069 gt96100_open(struct net_device *dev)
1075 dbg(2, "%s: dev=%p\n", __FUNCTION__, dev);
1077 // Initialize and startup the GT-96100 ethernet port
1078 if ((retval = gt96100_init(dev))) {
1079 err("error in gt96100_init\n");
1080 free_irq(dev->irq, dev);
1085 if ((retval = request_irq(dev->irq, >96100_interrupt,
1086 SA_SHIRQ, dev->name, dev))) {
1087 err("unable to get IRQ %d\n", dev->irq);
1092 dbg(2, "%s: Initialization done.\n", __FUNCTION__);
1098 gt96100_close(struct net_device *dev)
1100 dbg(3, "%s: dev=%p\n", __FUNCTION__, dev);
1103 if (netif_device_present(dev)) {
1104 netif_stop_queue(dev);
1108 free_irq(dev->irq, dev);
1116 gt96100_tx(struct sk_buff *skb, struct net_device *dev)
1118 struct gt96100_private *gp = netdev_priv(dev);
1119 unsigned long flags;
1122 spin_lock_irqsave(&gp->lock, flags);
1124 nextIn = gp->tx_next_in;
1126 dbg(3, "%s: nextIn=%d\n", __FUNCTION__, nextIn);
1128 if (gp->tx_count >= TX_RING_SIZE) {
1129 warn("Tx Ring full, pkt dropped.\n");
1130 gp->stats.tx_dropped++;
1131 spin_unlock_irqrestore(&gp->lock, flags);
1135 if (!(gp->last_psr & psrLink)) {
1136 err("%s: Link down, pkt dropped.\n", __FUNCTION__);
1137 gp->stats.tx_dropped++;
1138 spin_unlock_irqrestore(&gp->lock, flags);
1142 if (dma32_to_cpu(gp->tx_ring[nextIn].cmdstat) & txOwn) {
1143 err("%s: device owns descriptor, pkt dropped.\n", __FUNCTION__);
1144 gp->stats.tx_dropped++;
1145 // stop the queue, so Tx timeout can fix it
1146 netif_stop_queue(dev);
1147 spin_unlock_irqrestore(&gp->lock, flags);
1151 // Prepare the Descriptor at tx_next_in
1152 gp->tx_skbuff[nextIn] = skb;
1153 gp->tx_ring[nextIn].byte_cnt = cpu_to_dma16(skb->len);
1154 gp->tx_ring[nextIn].buff_ptr = cpu_to_dma32(virt_to_phys(skb->data));
1155 // make sure packet gets written back to memory
1156 dma_cache_wback_inv((unsigned long)(skb->data), skb->len);
1157 // Give ownership to device, set first and last desc, enable interrupt
1158 // Setting of ownership bit must be *last*!
1159 gp->tx_ring[nextIn].cmdstat =
1160 cpu_to_dma32((u32)(txOwn | txGenCRC | txEI |
1161 txPad | txFirst | txLast));
1163 dump_tx_desc(4, dev, nextIn);
1164 dump_skb(4, dev, skb);
1166 // increment tx_next_in with wrap
1167 gp->tx_next_in = (nextIn + 1) % TX_RING_SIZE;
1168 // If DMA is stopped, restart
1169 if (!(GT96100ETH_READ(gp, GT96100_ETH_PORT_STATUS) & psrTxLow))
1170 GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM,
1171 sdcmrERD | sdcmrTXDL);
1173 // increment count and stop queue if full
1174 if (++gp->tx_count == TX_RING_SIZE) {
1176 netif_stop_queue(dev);
1177 dbg(2, "Tx Ring now full, queue stopped.\n");
1180 dev->trans_start = jiffies;
1181 spin_unlock_irqrestore(&gp->lock, flags);
1188 gt96100_rx(struct net_device *dev, u32 status)
1190 struct gt96100_private *gp = netdev_priv(dev);
1191 struct sk_buff *skb;
1192 int pkt_len, nextOut, cdp;
1196 dbg(3, "%s: dev=%p, status=%x\n", __FUNCTION__, dev, status);
1198 cdp = (GT96100ETH_READ(gp, GT96100_ETH_1ST_RX_DESC_PTR0)
1199 - gp->rx_ring_dma) / sizeof(gt96100_rd_t);
1201 // Continue until we reach 1st descriptor pointer
1202 for (nextOut = gp->rx_next_out; nextOut != cdp;
1203 nextOut = (nextOut + 1) % RX_RING_SIZE) {
1205 if (--gp->intr_work_done == 0)
1208 rd = &gp->rx_ring[nextOut];
1209 cmdstat = dma32_to_cpu(rd->cmdstat);
1211 dbg(4, "%s: Rx desc cmdstat=%x, nextOut=%d\n", __FUNCTION__,
1214 if (cmdstat & (u32)rxOwn) {
1215 //err("%s: device owns descriptor!\n", __FUNCTION__);
1216 // DMA is not finished updating descriptor???
1217 // Leave and come back later to pick-up where
1222 // Drop this received pkt if there were any errors
1223 if (((cmdstat & (u32)(rxErrorSummary)) &&
1224 (cmdstat & (u32)(rxFirst))) || (status & icrRxError)) {
1225 // update the detailed rx error counters that
1226 // are not covered by the MIB counters.
1227 if (cmdstat & (u32)rxOverrun)
1228 gp->stats.rx_fifo_errors++;
1229 cmdstat |= (u32)rxOwn;
1230 rd->cmdstat = cpu_to_dma32(cmdstat);
1235 * Must be first and last (ie only) descriptor of packet. We
1236 * ignore (drop) any packets that do not fit in one descriptor.
1237 * Every descriptor's receive buffer is large enough to hold
1238 * the maximum 802.3 frame size, so a multi-descriptor packet
1239 * indicates an error. Most if not all corrupted packets will
1240 * have already been dropped by the above check for the
1241 * rxErrorSummary status bit.
1243 if (!(cmdstat & (u32)rxFirst) || !(cmdstat & (u32)rxLast)) {
1244 if (cmdstat & (u32)rxFirst) {
1246 * This is the first descriptor of a
1247 * multi-descriptor packet. It isn't corrupted
1248 * because the above check for rxErrorSummary
1249 * would have dropped it already, so what's
1250 * the deal with this packet? Good question,
1251 * let's dump it out.
1253 err("%s: desc not first and last!\n", __FUNCTION__);
1254 dump_rx_desc(0, dev, nextOut);
1256 cmdstat |= (u32)rxOwn;
1257 rd->cmdstat = cpu_to_dma32(cmdstat);
1258 // continue to drop every descriptor of this packet
1262 pkt_len = dma16_to_cpu(rd->byte_cnt);
1264 /* Create new skb. */
1265 skb = dev_alloc_skb(pkt_len+2);
1267 err("%s: Memory squeeze, dropping packet.\n", __FUNCTION__);
1268 gp->stats.rx_dropped++;
1269 cmdstat |= (u32)rxOwn;
1270 rd->cmdstat = cpu_to_dma32(cmdstat);
1274 skb_reserve(skb, 2); /* 16 byte IP header align */
1275 memcpy(skb_put(skb, pkt_len),
1276 &gp->rx_buff[nextOut*PKT_BUF_SZ], pkt_len);
1277 skb->protocol = eth_type_trans(skb, dev);
1278 dump_skb(4, dev, skb);
1280 netif_rx(skb); /* pass the packet to upper layers */
1281 dev->last_rx = jiffies;
1283 // now we can release ownership of this desc back to device
1284 cmdstat |= (u32)rxOwn;
1285 rd->cmdstat = cpu_to_dma32(cmdstat);
1288 if (nextOut == gp->rx_next_out)
1289 dbg(3, "%s: RxCDP did not increment?\n", __FUNCTION__);
1291 gp->rx_next_out = nextOut;
1297 gt96100_tx_complete(struct net_device *dev, u32 status)
1299 struct gt96100_private *gp = netdev_priv(dev);
1304 cdp = (GT96100ETH_READ(gp, GT96100_ETH_CURR_TX_DESC_PTR0)
1305 - gp->tx_ring_dma) / sizeof(gt96100_td_t);
1307 // Continue until we reach the current descriptor pointer
1308 for (nextOut = gp->tx_next_out; nextOut != cdp;
1309 nextOut = (nextOut + 1) % TX_RING_SIZE) {
1311 if (--gp->intr_work_done == 0)
1314 td = &gp->tx_ring[nextOut];
1315 cmdstat = dma32_to_cpu(td->cmdstat);
1317 dbg(3, "%s: Tx desc cmdstat=%x, nextOut=%d\n", __FUNCTION__,
1320 if (cmdstat & (u32)txOwn) {
1321 //dump_tx_ring(dev);
1322 // DMA is not finished writing descriptor???
1323 // Leave and come back later to pick-up where
1328 // increment Tx error stats
1329 if (cmdstat & (u32)txErrorSummary) {
1330 dbg(2, "%s: Tx error, cmdstat = %x\n", __FUNCTION__,
1332 gp->stats.tx_errors++;
1333 if (cmdstat & (u32)txReTxLimit)
1334 gp->stats.tx_aborted_errors++;
1335 if (cmdstat & (u32)txUnderrun)
1336 gp->stats.tx_fifo_errors++;
1337 if (cmdstat & (u32)txLateCollision)
1338 gp->stats.tx_window_errors++;
1341 if (cmdstat & (u32)txCollision)
1342 gp->stats.collisions +=
1343 (u32)((cmdstat & txReTxCntMask) >>
1346 // Wake the queue if the ring was full
1349 if (gp->last_psr & psrLink) {
1350 netif_wake_queue(dev);
1351 dbg(2, "%s: Tx Ring was full, queue waked\n", __FUNCTION_);
1355 // decrement tx ring buffer count
1356 if (gp->tx_count) gp->tx_count--;
1359 if (gp->tx_skbuff[nextOut]) {
1360 dbg(3, "%s: good Tx, skb=%p\n", __FUNCTION__,
1361 gp->tx_skbuff[nextOut]);
1362 dev_kfree_skb_irq(gp->tx_skbuff[nextOut]);
1363 gp->tx_skbuff[nextOut] = NULL;
1365 err("%s: no skb!\n", __FUNCTION__);
1369 gp->tx_next_out = nextOut;
1371 if (gt96100_check_tx_consistent(gp)) {
1372 err("%s: Tx queue inconsistent!\n", __FUNCTION__);
1375 if ((status & icrTxEndLow) && gp->tx_count != 0) {
1376 // we must restart the DMA
1377 dbg(3, "%s: Restarting Tx DMA\n", __FUNCTION__);
1378 GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM,
1379 sdcmrERD | sdcmrTXDL);
1385 gt96100_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1387 struct net_device *dev = (struct net_device *)dev_id;
1388 struct gt96100_private *gp = netdev_priv(dev);
1393 err("%s: null dev ptr\n", __FUNCTION__);
1397 dbg(3, "%s: entry, icr=%x\n", __FUNCTION__,
1398 GT96100ETH_READ(gp, GT96100_ETH_INT_CAUSE));
1400 spin_lock(&gp->lock);
1402 gp->intr_work_done = max_interrupt_work;
1404 while (gp->intr_work_done > 0) {
1406 status = GT96100ETH_READ(gp, GT96100_ETH_INT_CAUSE);
1408 GT96100ETH_WRITE(gp, GT96100_ETH_INT_CAUSE, ~status);
1410 if ((status & icrEtherIntSum) == 0 &&
1411 !(status & (icrTxBufferLow|icrTxBufferHigh|icrRxBuffer)))
1416 if (status & icrMIIPhySTC) {
1417 u32 psr = GT96100ETH_READ(gp, GT96100_ETH_PORT_STATUS);
1418 if (gp->last_psr != psr) {
1419 dbg(0, "port status:\n");
1420 dbg(0, " %s MBit/s, %s-duplex, "
1421 "flow-control %s, link is %s,\n",
1422 psr & psrSpeed ? "100":"10",
1423 psr & psrDuplex ? "full":"half",
1424 psr & psrFctl ? "disabled":"enabled",
1425 psr & psrLink ? "up":"down");
1426 dbg(0, " TxLowQ is %s, TxHighQ is %s, "
1427 "Transmitter is %s\n",
1428 psr & psrTxLow ? "running":"stopped",
1429 psr & psrTxHigh ? "running":"stopped",
1430 psr & psrTxInProg ? "on":"off");
1432 if ((psr & psrLink) && !gp->tx_full &&
1433 netif_queue_stopped(dev)) {
1434 dbg(0, ": Link up, waking queue.\n",
1436 netif_wake_queue(dev);
1437 } else if (!(psr & psrLink) &&
1438 !netif_queue_stopped(dev)) {
1439 dbg(0, "Link down, stopping queue.\n",
1441 netif_stop_queue(dev);
1447 if (--gp->intr_work_done == 0)
1451 if (status & (icrTxBufferLow | icrTxEndLow))
1452 gt96100_tx_complete(dev, status);
1454 if (status & (icrRxBuffer | icrRxError)) {
1455 gt96100_rx(dev, status);
1458 // Now check TX errors (RX errors were handled in gt96100_rx)
1459 if (status & icrTxErrorLow) {
1460 err("%s: Tx resource error\n", __FUNCTION__);
1461 if (--gp->intr_work_done == 0)
1465 if (status & icrTxUdr) {
1466 err("%s: Tx underrun error\n", __FUNCTION__);
1467 if (--gp->intr_work_done == 0)
1472 if (gp->intr_work_done == 0) {
1473 // ACK any remaining pending interrupts
1474 GT96100ETH_WRITE(gp, GT96100_ETH_INT_CAUSE, 0);
1475 dbg(3, "%s: hit max work\n", __FUNCTION__);
1478 dbg(3, "%s: exit, icr=%x\n", __FUNCTION__,
1479 GT96100ETH_READ(gp, GT96100_ETH_INT_CAUSE));
1481 spin_unlock(&gp->lock);
1482 return IRQ_RETVAL(handled);
1487 gt96100_tx_timeout(struct net_device *dev)
1489 struct gt96100_private *gp = netdev_priv(dev);
1490 unsigned long flags;
1492 spin_lock_irqsave(&gp->lock, flags);
1494 if (!(gp->last_psr & psrLink)) {
1495 err("tx_timeout: link down.\n");
1496 spin_unlock_irqrestore(&gp->lock, flags);
1498 if (gt96100_check_tx_consistent(gp))
1499 err("tx_timeout: Tx ring error.\n");
1501 disable_ether_irq(dev);
1502 spin_unlock_irqrestore(&gp->lock, flags);
1504 enable_ether_irq(dev);
1506 netif_wake_queue(dev);
1512 gt96100_set_rx_mode(struct net_device *dev)
1514 struct gt96100_private *gp = netdev_priv(dev);
1515 unsigned long flags;
1516 //struct dev_mc_list *mcptr;
1518 dbg(3, "%s: dev=%p, flags=%x\n", __FUNCTION__, dev, dev->flags);
1520 // stop the Receiver DMA
1521 abort(dev, sdcmrAR);
1523 spin_lock_irqsave(&gp->lock, flags);
1525 if (dev->flags & IFF_PROMISC) {
1526 GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG,
1527 pcrEN | pcrHS | pcrPM);
1532 FIXME: currently multicast doesn't work - need to get hash table
1535 if (dev->mc_count) {
1537 memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE);
1538 // Add our ethernet address
1539 gt96100_add_hash_entry(dev, dev->dev_addr);
1541 for (mcptr = dev->mc_list; mcptr; mcptr = mcptr->next) {
1542 dump_hw_addr(2, dev, __FUNCTION__ ": addr=",
1544 gt96100_add_hash_entry(dev, mcptr->dmi_addr);
1550 GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, sdcmrERD);
1552 spin_unlock_irqrestore(&gp->lock, flags);
1555 static struct net_device_stats *
1556 gt96100_get_stats(struct net_device *dev)
1558 struct gt96100_private *gp = netdev_priv(dev);
1559 unsigned long flags;
1561 dbg(3, "%s: dev=%p\n", __FUNCTION__, dev);
1563 if (netif_device_present(dev)) {
1564 spin_lock_irqsave (&gp->lock, flags);
1566 spin_unlock_irqrestore (&gp->lock, flags);
1572 static void gt96100_cleanup_module(void)
1575 for (i=0; i<NUM_INTERFACES; i++) {
1576 struct gt96100_if_t *gtif = >96100_iflist[i];
1577 if (gtif->dev != NULL) {
1578 struct gt96100_private *gp =
1579 (struct gt96100_private *)gtif->dev->priv;
1580 unregister_netdev(gtif->dev);
1581 dmafree(RX_HASH_TABLE_SIZE, gp->hash_table_dma);
1582 dmafree(PKT_BUF_SZ*RX_RING_SIZE, gp->rx_buff);
1583 dmafree(sizeof(gt96100_rd_t) * RX_RING_SIZE
1584 + sizeof(gt96100_td_t) * TX_RING_SIZE,
1586 free_netdev(gtif->dev);
1587 release_region(gtif->iobase, gp->io_size);
1595 static int __init gt96100_setup(char *options)
1599 if (!options || !*options)
1602 while ((this_opt = strsep (&options, ",")) != NULL) {
1605 if (!strncmp(this_opt, "mac0:", 5)) {
1606 memcpy(mac0, this_opt+5, 17);
1608 } else if (!strncmp(this_opt, "mac1:", 5)) {
1609 memcpy(mac1, this_opt+5, 17);
1617 __setup("gt96100eth=", gt96100_setup);
1619 #endif /* !MODULE */
1622 module_init(gt96100_init_module);
1623 module_exit(gt96100_cleanup_module);
1625 MODULE_AUTHOR("Steve Longerbeam <stevel@mvista.com>");
1626 MODULE_DESCRIPTION("GT96100 Ethernet driver");