2 * $Id: dmascc.c,v 1.27 2000/06/01 14:46:23 oe1kib Exp $
4 * Driver for high-speed SCC boards (those with DMA support)
5 * Copyright (C) 1997-2000 Klaus Kudielka
7 * S5SCC/DMA support by Janko Koleznik S52HI
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/errno.h>
29 #include <linux/if_arp.h>
31 #include <linux/init.h>
32 #include <linux/interrupt.h>
33 #include <linux/ioport.h>
34 #include <linux/kernel.h>
36 #include <linux/netdevice.h>
37 #include <linux/rtnetlink.h>
38 #include <linux/sockios.h>
39 #include <linux/workqueue.h>
40 #include <asm/atomic.h>
41 #include <asm/bitops.h>
45 #include <asm/uaccess.h>
50 /* Number of buffers per channel */
52 #define NUM_TX_BUF 2 /* NUM_TX_BUF >= 1 (min. 2 recommended) */
53 #define NUM_RX_BUF 6 /* NUM_RX_BUF >= 1 (min. 2 recommended) */
54 #define BUF_SIZE 1576 /* BUF_SIZE >= mtu + hard_header_len */
59 #define HW_PI { "Ottawa PI", 0x300, 0x20, 0x10, 8, \
60 0, 8, 1843200, 3686400 }
61 #define HW_PI2 { "Ottawa PI2", 0x300, 0x20, 0x10, 8, \
62 0, 8, 3686400, 7372800 }
63 #define HW_TWIN { "Gracilis PackeTwin", 0x200, 0x10, 0x10, 32, \
64 0, 4, 6144000, 6144000 }
65 #define HW_S5 { "S5SCC/DMA", 0x200, 0x10, 0x10, 32, \
66 0, 8, 4915200, 9830400 }
68 #define HARDWARE { HW_PI, HW_PI2, HW_TWIN, HW_S5 }
70 #define TMR_0_HZ 25600 /* Frequency of timer 0 */
78 #define MAX_NUM_DEVS 32
81 /* SCC chips supported */
87 #define CHIPNAMES { "Z8530", "Z85C30", "Z85230" }
92 /* 8530 registers relative to card base */
94 #define SCCB_DATA 0x01
96 #define SCCA_DATA 0x03
98 /* 8253/8254 registers relative to card base */
100 #define TMR_CNT1 0x01
101 #define TMR_CNT2 0x02
102 #define TMR_CTRL 0x03
104 /* Additional PI/PI2 registers relative to card base */
105 #define PI_DREQ_MASK 0x04
107 /* Additional PackeTwin registers relative to card base */
108 #define TWIN_INT_REG 0x08
109 #define TWIN_CLR_TMR1 0x09
110 #define TWIN_CLR_TMR2 0x0a
111 #define TWIN_SPARE_1 0x0b
112 #define TWIN_DMA_CFG 0x08
113 #define TWIN_SERIAL_CFG 0x09
114 #define TWIN_DMA_CLR_FF 0x0a
115 #define TWIN_SPARE_2 0x0b
118 /* PackeTwin I/O register values */
121 #define TWIN_SCC_MSK 0x01
122 #define TWIN_TMR1_MSK 0x02
123 #define TWIN_TMR2_MSK 0x04
124 #define TWIN_INT_MSK 0x07
127 #define TWIN_DTRA_ON 0x01
128 #define TWIN_DTRB_ON 0x02
129 #define TWIN_EXTCLKA 0x04
130 #define TWIN_EXTCLKB 0x08
131 #define TWIN_LOOPA_ON 0x10
132 #define TWIN_LOOPB_ON 0x20
136 #define TWIN_DMA_HDX_T1 0x08
137 #define TWIN_DMA_HDX_R1 0x0a
138 #define TWIN_DMA_HDX_T3 0x14
139 #define TWIN_DMA_HDX_R3 0x16
140 #define TWIN_DMA_FDX_T3R1 0x1b
141 #define TWIN_DMA_FDX_T1R3 0x1d
160 #define SIOCGSCCPARAM SIOCDEVPRIVATE
161 #define SIOCSSCCPARAM (SIOCDEVPRIVATE+1)
167 int pclk_hz; /* frequency of BRG input (don't change) */
168 int brg_tc; /* BRG terminal count; BRG disabled if < 0 */
169 int nrzi; /* 0 (nrz), 1 (nrzi) */
170 int clocks; /* see dmascc_cfg documentation */
171 int txdelay; /* [1/TMR_0_HZ] */
172 int txtimeout; /* [1/HZ] */
173 int txtail; /* [1/TMR_0_HZ] */
174 int waittime; /* [1/TMR_0_HZ] */
175 int slottime; /* [1/TMR_0_HZ] */
176 int persist; /* 1 ... 256 */
177 int dma; /* -1 (disable), 0, 1, 3 */
178 int txpause; /* [1/TMR_0_HZ] */
179 int rtsoff; /* [1/TMR_0_HZ] */
180 int dcdon; /* [1/TMR_0_HZ] */
181 int dcdoff; /* [1/TMR_0_HZ] */
184 struct scc_hardware {
199 struct net_device *dev;
200 struct scc_info *info;
201 struct net_device_stats stats;
203 int card_base, scc_cmd, scc_data;
204 int tmr_cnt, tmr_ctrl, tmr_mode;
205 struct scc_param param;
206 char rx_buf[NUM_RX_BUF][BUF_SIZE];
207 int rx_len[NUM_RX_BUF];
209 struct work_struct rx_work;
210 int rx_head, rx_tail, rx_count;
212 char tx_buf[NUM_TX_BUF][BUF_SIZE];
213 int tx_len[NUM_TX_BUF];
215 int tx_head, tx_tail, tx_count;
217 unsigned long tx_start;
219 spinlock_t *register_lock; /* Per scc_info */
220 spinlock_t ring_lock;
226 struct net_device *dev[2];
227 struct scc_priv priv[2];
228 struct scc_info *next;
229 spinlock_t register_lock; /* Per device register lock */
233 /* Function declarations */
234 static int setup_adapter(int card_base, int type, int n) __init;
236 static void write_scc(struct scc_priv *priv, int reg, int val);
237 static void write_scc_data(struct scc_priv *priv, int val, int fast);
238 static int read_scc(struct scc_priv *priv, int reg);
239 static int read_scc_data(struct scc_priv *priv);
241 static int scc_open(struct net_device *dev);
242 static int scc_close(struct net_device *dev);
243 static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
244 static int scc_send_packet(struct sk_buff *skb, struct net_device *dev);
245 static struct net_device_stats *scc_get_stats(struct net_device *dev);
246 static int scc_set_mac_address(struct net_device *dev, void *sa);
248 static inline void tx_on(struct scc_priv *priv);
249 static inline void rx_on(struct scc_priv *priv);
250 static inline void rx_off(struct scc_priv *priv);
251 static void start_timer(struct scc_priv *priv, int t, int r15);
252 static inline unsigned char random(void);
254 static inline void z8530_isr(struct scc_info *info);
255 static irqreturn_t scc_isr(int irq, void *dev_id, struct pt_regs * regs);
256 static void rx_isr(struct scc_priv *priv);
257 static void special_condition(struct scc_priv *priv, int rc);
258 static void rx_bh(void *arg);
259 static void tx_isr(struct scc_priv *priv);
260 static void es_isr(struct scc_priv *priv);
261 static void tm_isr(struct scc_priv *priv);
264 /* Initialization variables */
266 static int io[MAX_NUM_DEVS] __initdata = { 0, };
267 /* Beware! hw[] is also used in cleanup_module(). */
268 static struct scc_hardware hw[NUM_TYPES] __initdata_or_module = HARDWARE;
269 static char ax25_broadcast[7] __initdata =
270 { 'Q'<<1, 'S'<<1, 'T'<<1, ' '<<1, ' '<<1, ' '<<1, '0'<<1 };
271 static char ax25_test[7] __initdata =
272 { 'L'<<1, 'I'<<1, 'N'<<1, 'U'<<1, 'X'<<1, ' '<<1, '1'<<1 };
275 /* Global variables */
277 static struct scc_info *first;
278 static unsigned long rand;
281 MODULE_AUTHOR("Klaus Kudielka");
282 MODULE_DESCRIPTION("Driver for high-speed SCC boards");
283 MODULE_PARM(io, "1-" __MODULE_STRING(MAX_NUM_DEVS) "i");
284 MODULE_LICENSE("GPL");
286 static void __exit dmascc_exit(void) {
288 struct scc_info *info;
293 /* Unregister devices */
294 for (i = 0; i < 2; i++)
295 unregister_netdev(info->dev[i]);
298 if (info->priv[0].type == TYPE_TWIN)
299 outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG);
300 write_scc(&info->priv[0], R9, FHWRES);
301 release_region(info->dev[0]->base_addr,
302 hw[info->priv[0].type].io_size);
304 for (i = 0; i < 2; i++)
305 free_netdev(info->dev[i]);
314 void __init dmascc_setup(char *str, int *ints) {
317 for (i = 0; i < MAX_NUM_DEVS && i < ints[0]; i++)
322 static int __init dmascc_init(void) {
324 int base[MAX_NUM_DEVS], tcmd[MAX_NUM_DEVS], t0[MAX_NUM_DEVS],
327 unsigned long time, start[MAX_NUM_DEVS], delay[MAX_NUM_DEVS],
328 counting[MAX_NUM_DEVS];
330 /* Initialize random number generator */
332 /* Cards found = 0 */
334 /* Warning message */
335 if (!io[0]) printk(KERN_INFO "dmascc: autoprobing (dangerous)\n");
337 /* Run autodetection for each card type */
338 for (h = 0; h < NUM_TYPES; h++) {
341 /* User-specified I/O address regions */
342 for (i = 0; i < hw[h].num_devs; i++) base[i] = 0;
343 for (i = 0; i < MAX_NUM_DEVS && io[i]; i++) {
344 j = (io[i] - hw[h].io_region) / hw[h].io_delta;
346 j < hw[h].num_devs &&
347 hw[h].io_region + j * hw[h].io_delta == io[i]) {
352 /* Default I/O address regions */
353 for (i = 0; i < hw[h].num_devs; i++) {
354 base[i] = hw[h].io_region + i * hw[h].io_delta;
358 /* Check valid I/O address regions */
359 for (i = 0; i < hw[h].num_devs; i++)
361 if (!request_region(base[i], hw[h].io_size, "dmascc"))
364 tcmd[i] = base[i] + hw[h].tmr_offset + TMR_CTRL;
365 t0[i] = base[i] + hw[h].tmr_offset + TMR_CNT0;
366 t1[i] = base[i] + hw[h].tmr_offset + TMR_CNT1;
371 for (i = 0; i < hw[h].num_devs; i++)
373 /* Timer 0: LSB+MSB, Mode 3, TMR_0_HZ */
375 outb((hw[h].tmr_hz/TMR_0_HZ) & 0xFF, t0[i]);
376 outb((hw[h].tmr_hz/TMR_0_HZ) >> 8, t0[i]);
377 /* Timer 1: LSB+MSB, Mode 0, HZ/10 */
379 outb((TMR_0_HZ/HZ*10) & 0xFF, t1[i]);
380 outb((TMR_0_HZ/HZ*10) >> 8, t1[i]);
384 /* Timer 2: LSB+MSB, Mode 0 */
388 /* Wait until counter registers are loaded */
389 udelay(2000000/TMR_0_HZ);
392 while (jiffies - time < 13) {
393 for (i = 0; i < hw[h].num_devs; i++)
394 if (base[i] && counting[i]) {
395 /* Read back Timer 1: latch; read LSB; read MSB */
397 t_val = inb(t1[i]) + (inb(t1[i]) << 8);
398 /* Also check whether counter did wrap */
399 if (t_val == 0 || t_val > TMR_0_HZ/HZ*10) counting[i] = 0;
400 delay[i] = jiffies - start[i];
404 /* Evaluate measurements */
405 for (i = 0; i < hw[h].num_devs; i++)
407 if ((delay[i] >= 9 && delay[i] <= 11)&&
408 /* Ok, we have found an adapter */
409 (setup_adapter(base[i], h, n) == 0))
412 release_region(base[i], hw[h].io_size);
417 /* If any adapter was successfully initialized, return ok */
420 /* If no adapter found, return error */
421 printk(KERN_INFO "dmascc: no adapters found\n");
425 module_init(dmascc_init);
426 module_exit(dmascc_exit);
428 static void dev_setup(struct net_device *dev)
430 dev->type = ARPHRD_AX25;
431 dev->hard_header_len = 73;
434 dev->tx_queue_len = 64;
435 memcpy(dev->broadcast, ax25_broadcast, 7);
436 memcpy(dev->dev_addr, ax25_test, 7);
439 static int __init setup_adapter(int card_base, int type, int n)
442 struct scc_info *info;
443 struct net_device *dev;
444 struct scc_priv *priv;
447 int tmr_base = card_base + hw[type].tmr_offset;
448 int scc_base = card_base + hw[type].scc_offset;
449 char *chipnames[] = CHIPNAMES;
451 /* Allocate memory */
452 info = kmalloc(sizeof(struct scc_info), GFP_KERNEL | GFP_DMA);
454 printk(KERN_ERR "dmascc: "
455 "could not allocate memory for %s at %#3x\n",
456 hw[type].name, card_base);
460 /* Initialize what is necessary for write_scc and write_scc_data */
461 memset(info, 0, sizeof(struct scc_info));
463 info->dev[0] = alloc_netdev(0, "", dev_setup);
465 printk(KERN_ERR "dmascc: "
466 "could not allocate memory for %s at %#3x\n",
467 hw[type].name, card_base);
471 info->dev[1] = alloc_netdev(0, "", dev_setup);
473 printk(KERN_ERR "dmascc: "
474 "could not allocate memory for %s at %#3x\n",
475 hw[type].name, card_base);
478 spin_lock_init(&info->register_lock);
480 priv = &info->priv[0];
482 priv->card_base = card_base;
483 priv->scc_cmd = scc_base + SCCA_CMD;
484 priv->scc_data = scc_base + SCCA_DATA;
485 priv->register_lock = &info->register_lock;
488 write_scc(priv, R9, FHWRES | MIE | NV);
490 /* Determine type of chip by enabling SDLC/HDLC enhancements */
491 write_scc(priv, R15, SHDLCE);
492 if (!read_scc(priv, R15)) {
493 /* WR7' not present. This is an ordinary Z8530 SCC. */
496 /* Put one character in TX FIFO */
497 write_scc_data(priv, 0, 0);
498 if (read_scc(priv, R0) & Tx_BUF_EMP) {
499 /* TX FIFO not full. This is a Z85230 ESCC with a 4-byte FIFO. */
502 /* TX FIFO full. This is a Z85C30 SCC with a 1-byte FIFO. */
506 write_scc(priv, R15, 0);
508 /* Start IRQ auto-detection */
509 irqs = probe_irq_on();
511 /* Enable interrupts */
512 if (type == TYPE_TWIN) {
513 outb(0, card_base + TWIN_DMA_CFG);
514 inb(card_base + TWIN_CLR_TMR1);
515 inb(card_base + TWIN_CLR_TMR2);
516 info->twin_serial_cfg = TWIN_EI;
517 outb(info->twin_serial_cfg, card_base + TWIN_SERIAL_CFG);
519 write_scc(priv, R15, CTSIE);
520 write_scc(priv, R0, RES_EXT_INT);
521 write_scc(priv, R1, EXT_INT_ENAB);
525 outb(1, tmr_base + TMR_CNT1);
526 outb(0, tmr_base + TMR_CNT1);
528 /* Wait and detect IRQ */
529 time = jiffies; while (jiffies - time < 2 + HZ / TMR_0_HZ);
530 irq = probe_irq_off(irqs);
532 /* Clear pending interrupt, disable interrupts */
533 if (type == TYPE_TWIN) {
534 inb(card_base + TWIN_CLR_TMR1);
536 write_scc(priv, R1, 0);
537 write_scc(priv, R15, 0);
538 write_scc(priv, R0, RES_EXT_INT);
542 printk(KERN_ERR "dmascc: could not find irq of %s at %#3x (irq=%d)\n",
543 hw[type].name, card_base, irq);
547 /* Set up data structures */
548 for (i = 0; i < 2; i++) {
550 priv = &info->priv[i];
556 spin_lock_init(&priv->ring_lock);
557 priv->register_lock = &info->register_lock;
558 priv->card_base = card_base;
559 priv->scc_cmd = scc_base + (i ? SCCB_CMD : SCCA_CMD);
560 priv->scc_data = scc_base + (i ? SCCB_DATA : SCCA_DATA);
561 priv->tmr_cnt = tmr_base + (i ? TMR_CNT2 : TMR_CNT1);
562 priv->tmr_ctrl = tmr_base + TMR_CTRL;
563 priv->tmr_mode = i ? 0xb0 : 0x70;
564 priv->param.pclk_hz = hw[type].pclk_hz;
565 priv->param.brg_tc = -1;
566 priv->param.clocks = TCTRxCP | RCRTxCP;
567 priv->param.persist = 256;
568 priv->param.dma = -1;
569 INIT_WORK(&priv->rx_work, rx_bh, priv);
571 sprintf(dev->name, "dmascc%i", 2*n+i);
572 SET_MODULE_OWNER(dev);
573 dev->base_addr = card_base;
575 dev->open = scc_open;
576 dev->stop = scc_close;
577 dev->do_ioctl = scc_ioctl;
578 dev->hard_start_xmit = scc_send_packet;
579 dev->get_stats = scc_get_stats;
580 dev->hard_header = ax25_encapsulate;
581 dev->rebuild_header = ax25_rebuild_header;
582 dev->set_mac_address = scc_set_mac_address;
584 if (register_netdev(info->dev[0])) {
585 printk(KERN_ERR "dmascc: could not register %s\n",
589 if (register_netdev(info->dev[1])) {
590 printk(KERN_ERR "dmascc: could not register %s\n",
598 printk(KERN_INFO "dmascc: found %s (%s) at %#3x, irq %d\n", hw[type].name,
599 chipnames[chip], card_base, irq);
603 unregister_netdev(info->dev[0]);
605 if (info->priv[0].type == TYPE_TWIN)
606 outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG);
607 write_scc(&info->priv[0], R9, FHWRES);
608 free_netdev(info->dev[1]);
610 free_netdev(info->dev[0]);
618 /* Driver functions */
620 static void write_scc(struct scc_priv *priv, int reg, int val) {
622 switch (priv->type) {
624 if (reg) outb(reg, priv->scc_cmd);
625 outb(val, priv->scc_cmd);
628 if (reg) outb_p(reg, priv->scc_cmd);
629 outb_p(val, priv->scc_cmd);
632 spin_lock_irqsave(priv->register_lock, flags);
633 outb_p(0, priv->card_base + PI_DREQ_MASK);
634 if (reg) outb_p(reg, priv->scc_cmd);
635 outb_p(val, priv->scc_cmd);
636 outb(1, priv->card_base + PI_DREQ_MASK);
637 spin_unlock_irqrestore(priv->register_lock, flags);
643 static void write_scc_data(struct scc_priv *priv, int val, int fast) {
645 switch (priv->type) {
647 outb(val, priv->scc_data);
650 outb_p(val, priv->scc_data);
653 if (fast) outb_p(val, priv->scc_data);
655 spin_lock_irqsave(priv->register_lock, flags);
656 outb_p(0, priv->card_base + PI_DREQ_MASK);
657 outb_p(val, priv->scc_data);
658 outb(1, priv->card_base + PI_DREQ_MASK);
659 spin_unlock_irqrestore(priv->register_lock, flags);
666 static int read_scc(struct scc_priv *priv, int reg) {
669 switch (priv->type) {
671 if (reg) outb(reg, priv->scc_cmd);
672 return inb(priv->scc_cmd);
674 if (reg) outb_p(reg, priv->scc_cmd);
675 return inb_p(priv->scc_cmd);
677 spin_lock_irqsave(priv->register_lock, flags);
678 outb_p(0, priv->card_base + PI_DREQ_MASK);
679 if (reg) outb_p(reg, priv->scc_cmd);
680 rc = inb_p(priv->scc_cmd);
681 outb(1, priv->card_base + PI_DREQ_MASK);
682 spin_unlock_irqrestore(priv->register_lock, flags);
688 static int read_scc_data(struct scc_priv *priv) {
691 switch (priv->type) {
693 return inb(priv->scc_data);
695 return inb_p(priv->scc_data);
697 spin_lock_irqsave(priv->register_lock, flags);
698 outb_p(0, priv->card_base + PI_DREQ_MASK);
699 rc = inb_p(priv->scc_data);
700 outb(1, priv->card_base + PI_DREQ_MASK);
701 spin_unlock_irqrestore(priv->register_lock, flags);
707 static int scc_open(struct net_device *dev) {
708 struct scc_priv *priv = dev->priv;
709 struct scc_info *info = priv->info;
710 int card_base = priv->card_base;
712 /* Request IRQ if not already used by other channel */
713 if (!info->irq_used) {
714 if (request_irq(dev->irq, scc_isr, 0, "dmascc", info)) {
720 /* Request DMA if required */
721 if (priv->param.dma >= 0) {
722 if (request_dma(priv->param.dma, "dmascc")) {
723 if (--info->irq_used == 0) free_irq(dev->irq, info);
726 unsigned long flags = claim_dma_lock();
727 clear_dma_ff(priv->param.dma);
728 release_dma_lock(flags);
732 /* Initialize local variables */
735 priv->rx_head = priv->rx_tail = priv->rx_count = 0;
737 priv->tx_head = priv->tx_tail = priv->tx_count = 0;
741 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
742 /* X1 clock, SDLC mode */
743 write_scc(priv, R4, SDLC | X1CLK);
745 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
746 /* 8 bit RX char, RX disable */
747 write_scc(priv, R3, Rx8);
748 /* 8 bit TX char, TX disable */
749 write_scc(priv, R5, Tx8);
750 /* SDLC address field */
751 write_scc(priv, R6, 0);
753 write_scc(priv, R7, FLAG);
754 switch (priv->chip) {
757 write_scc(priv, R15, SHDLCE);
759 write_scc(priv, R7, AUTOEOM);
760 write_scc(priv, R15, 0);
764 write_scc(priv, R15, SHDLCE);
765 /* The following bits are set (see 2.5.2.1):
766 - Automatic EOM reset
767 - Interrupt request if RX FIFO is half full
768 This bit should be ignored in DMA mode (according to the
769 documentation), but actually isn't. The receiver doesn't work if
770 it is set. Thus, we have to clear it in DMA mode.
771 - Interrupt/DMA request if TX FIFO is completely empty
772 a) If set, the ESCC behaves as if it had no TX FIFO (Z85C30
774 b) If cleared, DMA requests may follow each other very quickly,
775 filling up the TX FIFO.
776 Advantage: TX works even in case of high bus latency.
777 Disadvantage: Edge-triggered DMA request circuitry may miss
778 a request. No more data is delivered, resulting
779 in a TX FIFO underrun.
780 Both PI2 and S5SCC/DMA seem to work fine with TXFIFOE cleared.
781 The PackeTwin doesn't. I don't know about the PI, but let's
782 assume it behaves like the PI2.
784 if (priv->param.dma >= 0) {
785 if (priv->type == TYPE_TWIN) write_scc(priv, R7, AUTOEOM | TXFIFOE);
786 else write_scc(priv, R7, AUTOEOM);
788 write_scc(priv, R7, AUTOEOM | RXFIFOH);
790 write_scc(priv, R15, 0);
793 /* Preset CRC, NRZ(I) encoding */
794 write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ));
796 /* Configure baud rate generator */
797 if (priv->param.brg_tc >= 0) {
798 /* Program BR generator */
799 write_scc(priv, R12, priv->param.brg_tc & 0xFF);
800 write_scc(priv, R13, (priv->param.brg_tc>>8) & 0xFF);
801 /* BRG source = SYS CLK; enable BRG; DTR REQ function (required by
802 PackeTwin, not connected on the PI2); set DPLL source to BRG */
803 write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL);
805 write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL);
807 /* Disable BR generator */
808 write_scc(priv, R14, DTRREQ | BRSRC);
811 /* Configure clocks */
812 if (priv->type == TYPE_TWIN) {
813 /* Disable external TX clock receiver */
814 outb((info->twin_serial_cfg &=
815 ~(priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
816 card_base + TWIN_SERIAL_CFG);
818 write_scc(priv, R11, priv->param.clocks);
819 if ((priv->type == TYPE_TWIN) && !(priv->param.clocks & TRxCOI)) {
820 /* Enable external TX clock receiver */
821 outb((info->twin_serial_cfg |=
822 (priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
823 card_base + TWIN_SERIAL_CFG);
826 /* Configure PackeTwin */
827 if (priv->type == TYPE_TWIN) {
828 /* Assert DTR, enable interrupts */
829 outb((info->twin_serial_cfg |= TWIN_EI |
830 (priv->channel ? TWIN_DTRB_ON : TWIN_DTRA_ON)),
831 card_base + TWIN_SERIAL_CFG);
834 /* Read current status */
835 priv->rr0 = read_scc(priv, R0);
836 /* Enable DCD interrupt */
837 write_scc(priv, R15, DCDIE);
839 netif_start_queue(dev);
845 static int scc_close(struct net_device *dev) {
846 struct scc_priv *priv = dev->priv;
847 struct scc_info *info = priv->info;
848 int card_base = priv->card_base;
850 netif_stop_queue(dev);
852 if (priv->type == TYPE_TWIN) {
854 outb((info->twin_serial_cfg &=
855 (priv->channel ? ~TWIN_DTRB_ON : ~TWIN_DTRA_ON)),
856 card_base + TWIN_SERIAL_CFG);
859 /* Reset channel, free DMA and IRQ */
860 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
861 if (priv->param.dma >= 0) {
862 if (priv->type == TYPE_TWIN) outb(0, card_base + TWIN_DMA_CFG);
863 free_dma(priv->param.dma);
865 if (--info->irq_used == 0) free_irq(dev->irq, info);
871 static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) {
872 struct scc_priv *priv = dev->priv;
876 if (copy_to_user(ifr->ifr_data, &priv->param, sizeof(struct scc_param)))
880 if (!capable(CAP_NET_ADMIN)) return -EPERM;
881 if (netif_running(dev)) return -EAGAIN;
882 if (copy_from_user(&priv->param, ifr->ifr_data, sizeof(struct scc_param)))
891 static int scc_send_packet(struct sk_buff *skb, struct net_device *dev) {
892 struct scc_priv *priv = dev->priv;
896 /* Temporarily stop the scheduler feeding us packets */
897 netif_stop_queue(dev);
899 /* Transfer data to DMA buffer */
901 memcpy(priv->tx_buf[i], skb->data+1, skb->len-1);
902 priv->tx_len[i] = skb->len-1;
904 /* Clear interrupts while we touch our circular buffers */
906 spin_lock_irqsave(&priv->ring_lock, flags);
907 /* Move the ring buffer's head */
908 priv->tx_head = (i + 1) % NUM_TX_BUF;
911 /* If we just filled up the last buffer, leave queue stopped.
912 The higher layers must wait until we have a DMA buffer
913 to accept the data. */
914 if (priv->tx_count < NUM_TX_BUF) netif_wake_queue(dev);
916 /* Set new TX state */
917 if (priv->state == IDLE) {
918 /* Assert RTS, start timer */
919 priv->state = TX_HEAD;
920 priv->tx_start = jiffies;
921 write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);
922 write_scc(priv, R15, 0);
923 start_timer(priv, priv->param.txdelay, 0);
926 /* Turn interrupts back on and free buffer */
927 spin_unlock_irqrestore(&priv->ring_lock, flags);
934 static struct net_device_stats *scc_get_stats(struct net_device *dev) {
935 struct scc_priv *priv = dev->priv;
941 static int scc_set_mac_address(struct net_device *dev, void *sa) {
942 memcpy(dev->dev_addr, ((struct sockaddr *)sa)->sa_data, dev->addr_len);
947 static inline void tx_on(struct scc_priv *priv) {
951 if (priv->param.dma >= 0) {
952 n = (priv->chip == Z85230) ? 3 : 1;
953 /* Program DMA controller */
954 flags = claim_dma_lock();
955 set_dma_mode(priv->param.dma, DMA_MODE_WRITE);
956 set_dma_addr(priv->param.dma, (int) priv->tx_buf[priv->tx_tail]+n);
957 set_dma_count(priv->param.dma, priv->tx_len[priv->tx_tail]-n);
958 release_dma_lock(flags);
959 /* Enable TX underrun interrupt */
960 write_scc(priv, R15, TxUIE);
962 if (priv->type == TYPE_TWIN)
963 outb((priv->param.dma == 1) ? TWIN_DMA_HDX_T1 : TWIN_DMA_HDX_T3,
964 priv->card_base + TWIN_DMA_CFG);
966 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN | WT_RDY_ENAB);
967 /* Write first byte(s) */
968 spin_lock_irqsave(priv->register_lock, flags);
969 for (i = 0; i < n; i++)
970 write_scc_data(priv, priv->tx_buf[priv->tx_tail][i], 1);
971 enable_dma(priv->param.dma);
972 spin_unlock_irqrestore(priv->register_lock, flags);
974 write_scc(priv, R15, TxUIE);
975 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN | TxINT_ENAB);
978 /* Reset EOM latch if we do not have the AUTOEOM feature */
979 if (priv->chip == Z8530) write_scc(priv, R0, RES_EOM_L);
983 static inline void rx_on(struct scc_priv *priv) {
987 while (read_scc(priv, R0) & Rx_CH_AV) read_scc_data(priv);
989 if (priv->param.dma >= 0) {
990 /* Program DMA controller */
991 flags = claim_dma_lock();
992 set_dma_mode(priv->param.dma, DMA_MODE_READ);
993 set_dma_addr(priv->param.dma, (int) priv->rx_buf[priv->rx_head]);
994 set_dma_count(priv->param.dma, BUF_SIZE);
995 release_dma_lock(flags);
996 enable_dma(priv->param.dma);
997 /* Configure PackeTwin DMA */
998 if (priv->type == TYPE_TWIN) {
999 outb((priv->param.dma == 1) ? TWIN_DMA_HDX_R1 : TWIN_DMA_HDX_R3,
1000 priv->card_base + TWIN_DMA_CFG);
1002 /* Sp. cond. intr. only, ext int enable, RX DMA enable */
1003 write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx |
1004 WT_RDY_RT | WT_FN_RDYFN | WT_RDY_ENAB);
1006 /* Reset current frame */
1008 /* Intr. on all Rx characters and Sp. cond., ext int enable */
1009 write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT |
1012 write_scc(priv, R0, ERR_RES);
1013 write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB);
1017 static inline void rx_off(struct scc_priv *priv) {
1018 /* Disable receiver */
1019 write_scc(priv, R3, Rx8);
1020 /* Disable DREQ / RX interrupt */
1021 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN)
1022 outb(0, priv->card_base + TWIN_DMA_CFG);
1024 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1026 if (priv->param.dma >= 0) disable_dma(priv->param.dma);
1030 static void start_timer(struct scc_priv *priv, int t, int r15) {
1031 unsigned long flags;
1033 outb(priv->tmr_mode, priv->tmr_ctrl);
1039 outb(t & 0xFF, priv->tmr_cnt);
1040 outb((t >> 8) & 0xFF, priv->tmr_cnt);
1041 if (priv->type != TYPE_TWIN) {
1042 write_scc(priv, R15, r15 | CTSIE);
1045 restore_flags(flags);
1050 static inline unsigned char random(void) {
1051 /* See "Numerical Recipes in C", second edition, p. 284 */
1052 rand = rand * 1664525L + 1013904223L;
1053 return (unsigned char) (rand >> 24);
1056 static inline void z8530_isr(struct scc_info *info) {
1059 while ((is = read_scc(&info->priv[0], R3)) && i--) {
1061 rx_isr(&info->priv[0]);
1062 } else if (is & CHATxIP) {
1063 tx_isr(&info->priv[0]);
1064 } else if (is & CHAEXT) {
1065 es_isr(&info->priv[0]);
1066 } else if (is & CHBRxIP) {
1067 rx_isr(&info->priv[1]);
1068 } else if (is & CHBTxIP) {
1069 tx_isr(&info->priv[1]);
1071 es_isr(&info->priv[1]);
1073 write_scc(&info->priv[0], R0, RES_H_IUS);
1077 printk(KERN_ERR "dmascc: stuck in ISR with RR3=0x%02x.\n", is);
1079 /* Ok, no interrupts pending from this 8530. The INT line should
1084 static irqreturn_t scc_isr(int irq, void *dev_id, struct pt_regs * regs) {
1085 struct scc_info *info = dev_id;
1087 spin_lock(info->priv[0].register_lock);
1088 /* At this point interrupts are enabled, and the interrupt under service
1089 is already acknowledged, but masked off.
1091 Interrupt processing: We loop until we know that the IRQ line is
1092 low. If another positive edge occurs afterwards during the ISR,
1093 another interrupt will be triggered by the interrupt controller
1094 as soon as the IRQ level is enabled again (see asm/irq.h).
1096 Bottom-half handlers will be processed after scc_isr(). This is
1097 important, since we only have small ringbuffers and want new data
1098 to be fetched/delivered immediately. */
1100 if (info->priv[0].type == TYPE_TWIN) {
1101 int is, card_base = info->priv[0].card_base;
1102 while ((is = ~inb(card_base + TWIN_INT_REG)) &
1104 if (is & TWIN_SCC_MSK) {
1106 } else if (is & TWIN_TMR1_MSK) {
1107 inb(card_base + TWIN_CLR_TMR1);
1108 tm_isr(&info->priv[0]);
1110 inb(card_base + TWIN_CLR_TMR2);
1111 tm_isr(&info->priv[1]);
1114 } else z8530_isr(info);
1115 spin_unlock(info->priv[0].register_lock);
1120 static void rx_isr(struct scc_priv *priv) {
1121 if (priv->param.dma >= 0) {
1122 /* Check special condition and perform error reset. See 2.4.7.5. */
1123 special_condition(priv, read_scc(priv, R1));
1124 write_scc(priv, R0, ERR_RES);
1126 /* Check special condition for each character. Error reset not necessary.
1127 Same algorithm for SCC and ESCC. See 2.4.7.1 and 2.4.7.4. */
1129 while (read_scc(priv, R0) & Rx_CH_AV) {
1130 rc = read_scc(priv, R1);
1131 if (priv->rx_ptr < BUF_SIZE)
1132 priv->rx_buf[priv->rx_head][priv->rx_ptr++] =
1133 read_scc_data(priv);
1136 read_scc_data(priv);
1138 special_condition(priv, rc);
1144 static void special_condition(struct scc_priv *priv, int rc) {
1146 unsigned long flags;
1148 /* See Figure 2-15. Only overrun and EOF need to be checked. */
1151 /* Receiver overrun */
1153 if (priv->param.dma < 0) write_scc(priv, R0, ERR_RES);
1154 } else if (rc & END_FR) {
1155 /* End of frame. Get byte count */
1156 if (priv->param.dma >= 0) {
1157 flags = claim_dma_lock();
1158 cb = BUF_SIZE - get_dma_residue(priv->param.dma) - 2;
1159 release_dma_lock(flags);
1161 cb = priv->rx_ptr - 2;
1163 if (priv->rx_over) {
1164 /* We had an overrun */
1165 priv->stats.rx_errors++;
1166 if (priv->rx_over == 2) priv->stats.rx_length_errors++;
1167 else priv->stats.rx_fifo_errors++;
1169 } else if (rc & CRC_ERR) {
1170 /* Count invalid CRC only if packet length >= minimum */
1172 priv->stats.rx_errors++;
1173 priv->stats.rx_crc_errors++;
1177 if (priv->rx_count < NUM_RX_BUF - 1) {
1178 /* Put good frame in FIFO */
1179 priv->rx_len[priv->rx_head] = cb;
1180 priv->rx_head = (priv->rx_head + 1) % NUM_RX_BUF;
1182 schedule_work(&priv->rx_work);
1184 priv->stats.rx_errors++;
1185 priv->stats.rx_over_errors++;
1189 /* Get ready for new frame */
1190 if (priv->param.dma >= 0) {
1191 flags = claim_dma_lock();
1192 set_dma_addr(priv->param.dma, (int) priv->rx_buf[priv->rx_head]);
1193 set_dma_count(priv->param.dma, BUF_SIZE);
1194 release_dma_lock(flags);
1202 static void rx_bh(void *arg) {
1203 struct scc_priv *priv = arg;
1204 int i = priv->rx_tail;
1206 unsigned long flags;
1207 struct sk_buff *skb;
1208 unsigned char *data;
1210 spin_lock_irqsave(&priv->ring_lock, flags);
1211 while (priv->rx_count) {
1212 spin_unlock_irqrestore(&priv->ring_lock, flags);
1213 cb = priv->rx_len[i];
1214 /* Allocate buffer */
1215 skb = dev_alloc_skb(cb+1);
1218 priv->stats.rx_dropped++;
1221 data = skb_put(skb, cb+1);
1223 memcpy(&data[1], priv->rx_buf[i], cb);
1224 skb->dev = priv->dev;
1225 skb->protocol = ntohs(ETH_P_AX25);
1226 skb->mac.raw = skb->data;
1228 priv->dev->last_rx = jiffies;
1229 priv->stats.rx_packets++;
1230 priv->stats.rx_bytes += cb;
1232 spin_lock_irqsave(&priv->ring_lock, flags);
1234 priv->rx_tail = i = (i + 1) % NUM_RX_BUF;
1237 spin_unlock_irqrestore(&priv->ring_lock, flags);
1241 static void tx_isr(struct scc_priv *priv) {
1242 int i = priv->tx_tail, p = priv->tx_ptr;
1244 /* Suspend TX interrupts if we don't want to send anything.
1246 if (p == priv->tx_len[i]) {
1247 write_scc(priv, R0, RES_Tx_P);
1251 /* Write characters */
1252 while ((read_scc(priv, R0) & Tx_BUF_EMP) && p < priv->tx_len[i]) {
1253 write_scc_data(priv, priv->tx_buf[i][p++], 0);
1256 /* Reset EOM latch of Z8530 */
1257 if (!priv->tx_ptr && p && priv->chip == Z8530)
1258 write_scc(priv, R0, RES_EOM_L);
1264 static void es_isr(struct scc_priv *priv) {
1265 int i, rr0, drr0, res;
1266 unsigned long flags;
1268 /* Read status, reset interrupt bit (open latches) */
1269 rr0 = read_scc(priv, R0);
1270 write_scc(priv, R0, RES_EXT_INT);
1271 drr0 = priv->rr0 ^ rr0;
1274 /* Transmit underrun (2.4.9.6). We can't check the TxEOM flag, since
1275 it might have already been cleared again by AUTOEOM. */
1276 if (priv->state == TX_DATA) {
1277 /* Get remaining bytes */
1279 if (priv->param.dma >= 0) {
1280 disable_dma(priv->param.dma);
1281 flags = claim_dma_lock();
1282 res = get_dma_residue(priv->param.dma);
1283 release_dma_lock(flags);
1285 res = priv->tx_len[i] - priv->tx_ptr;
1288 /* Disable DREQ / TX interrupt */
1289 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN)
1290 outb(0, priv->card_base + TWIN_DMA_CFG);
1292 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1294 /* Update packet statistics */
1295 priv->stats.tx_errors++;
1296 priv->stats.tx_fifo_errors++;
1297 /* Other underrun interrupts may already be waiting */
1298 write_scc(priv, R0, RES_EXT_INT);
1299 write_scc(priv, R0, RES_EXT_INT);
1301 /* Update packet statistics */
1302 priv->stats.tx_packets++;
1303 priv->stats.tx_bytes += priv->tx_len[i];
1304 /* Remove frame from FIFO */
1305 priv->tx_tail = (i + 1) % NUM_TX_BUF;
1307 /* Inform upper layers */
1308 netif_wake_queue(priv->dev);
1311 write_scc(priv, R15, 0);
1312 if (priv->tx_count &&
1313 (jiffies - priv->tx_start) < priv->param.txtimeout) {
1314 priv->state = TX_PAUSE;
1315 start_timer(priv, priv->param.txpause, 0);
1317 priv->state = TX_TAIL;
1318 start_timer(priv, priv->param.txtail, 0);
1322 /* DCD transition */
1325 switch (priv->state) {
1328 priv->state = DCD_ON;
1329 write_scc(priv, R15, 0);
1330 start_timer(priv, priv->param.dcdon, 0);
1333 switch (priv->state) {
1336 priv->state = DCD_OFF;
1337 write_scc(priv, R15, 0);
1338 start_timer(priv, priv->param.dcdoff, 0);
1343 /* CTS transition */
1344 if ((drr0 & CTS) && (~rr0 & CTS) && priv->type != TYPE_TWIN)
1350 static void tm_isr(struct scc_priv *priv) {
1351 switch (priv->state) {
1355 priv->state = TX_DATA;
1358 write_scc(priv, R5, TxCRC_ENAB | Tx8);
1359 priv->state = RTS_OFF;
1360 if (priv->type != TYPE_TWIN) write_scc(priv, R15, 0);
1361 start_timer(priv, priv->param.rtsoff, 0);
1364 write_scc(priv, R15, DCDIE);
1365 priv->rr0 = read_scc(priv, R0);
1366 if (priv->rr0 & DCD) {
1367 priv->stats.collisions++;
1369 priv->state = RX_ON;
1372 start_timer(priv, priv->param.waittime, DCDIE);
1376 if (priv->tx_count) {
1377 priv->state = TX_HEAD;
1378 priv->tx_start = jiffies;
1379 write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);
1380 write_scc(priv, R15, 0);
1381 start_timer(priv, priv->param.txdelay, 0);
1384 if (priv->type != TYPE_TWIN) write_scc(priv, R15, DCDIE);
1389 write_scc(priv, R15, DCDIE);
1390 priv->rr0 = read_scc(priv, R0);
1391 if (priv->rr0 & DCD) {
1393 priv->state = RX_ON;
1397 random()/priv->param.persist*priv->param.slottime,