4 * Ethernet driver for the built in ethernet on the IBM 4xx PowerPC
7 * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
9 * Based on original work by
11 * Armin Kuster <akuster@mvista.com>
12 * Johnnie Peters <jpeters@mvista.com>
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
19 * - Check for races in the "remove" code path
20 * - Add some Power Management to the MAC and the PHY
21 * - Audit remaining of non-rewritten code (--BenH)
22 * - Cleanup message display using msglevel mecanism
23 * - Address all errata
24 * - Audit all register update paths to ensure they
25 * are being written post soft reset if required.
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/sched.h>
30 #include <linux/string.h>
31 #include <linux/timer.h>
32 #include <linux/ptrace.h>
33 #include <linux/errno.h>
34 #include <linux/ioport.h>
35 #include <linux/slab.h>
36 #include <linux/interrupt.h>
37 #include <linux/delay.h>
38 #include <linux/init.h>
39 #include <linux/types.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
44 #include <asm/processor.h>
45 #include <asm/bitops.h>
49 #include <asm/uaccess.h>
52 #include <linux/netdevice.h>
53 #include <linux/etherdevice.h>
54 #include <linux/skbuff.h>
55 #include <linux/crc32.h>
57 #include "ibm_emac_core.h"
59 //#define MDIO_DEBUG(fmt) printk fmt
60 #define MDIO_DEBUG(fmt)
62 //#define LINK_DEBUG(fmt) printk fmt
63 #define LINK_DEBUG(fmt)
65 //#define PKT_DEBUG(fmt) printk fmt
66 #define PKT_DEBUG(fmt)
68 #define DRV_NAME "emac"
69 #define DRV_VERSION "2.0"
70 #define DRV_AUTHOR "Benjamin Herrenschmidt <benh@kernel.crashing.org>"
71 #define DRV_DESC "IBM EMAC Ethernet driver"
74 * When mdio_idx >= 0, contains a list of emac ocp_devs
75 * that have had their initialization deferred until the
76 * common MDIO controller has been initialized.
78 LIST_HEAD(emac_init_list);
80 MODULE_AUTHOR(DRV_AUTHOR);
81 MODULE_DESCRIPTION(DRV_DESC);
82 MODULE_LICENSE("GPL");
84 static int skb_res = SKB_RES;
85 module_param(skb_res, int, 0444);
86 MODULE_PARM_DESC(skb_res, "Amount of data to reserve on skb buffs\n"
87 "The 405 handles a misaligned IP header fine but\n"
88 "this can help if you are routing to a tunnel or a\n"
89 "device that needs aligned data. 0..2");
91 #define RGMII_PRIV(ocpdev) ((struct ibm_ocp_rgmii*)ocp_get_drvdata(ocpdev))
93 static unsigned int rgmii_enable[] =
94 { RGMII_RTBI, RGMII_RGMII, RGMII_TBI, RGMII_GMII };
96 static unsigned int rgmii_speed_mask[] = { 0,
102 static unsigned int rgmii_speed100[] = { 0,
108 static unsigned int rgmii_speed1000[] = { 0,
114 #define ZMII_PRIV(ocpdev) ((struct ibm_ocp_zmii*)ocp_get_drvdata(ocpdev))
116 static unsigned int zmii_enable[][4] = {
117 {ZMII_SMII0, ZMII_RMII0, ZMII_MII0,
118 ~(ZMII_MDI1 | ZMII_MDI2 | ZMII_MDI3)},
119 {ZMII_SMII1, ZMII_RMII1, ZMII_MII1,
120 ~(ZMII_MDI0 | ZMII_MDI2 | ZMII_MDI3)},
121 {ZMII_SMII2, ZMII_RMII2, ZMII_MII2,
122 ~(ZMII_MDI0 | ZMII_MDI1 | ZMII_MDI3)},
123 {ZMII_SMII3, ZMII_RMII3, ZMII_MII3, ~(ZMII_MDI0 | ZMII_MDI1 | ZMII_MDI2)}
125 static unsigned int mdi_enable[] =
126 { ZMII_MDI0, ZMII_MDI1, ZMII_MDI2, ZMII_MDI3 };
128 static unsigned int zmii_speed = 0x0;
129 static unsigned int zmii_speed100[] = { ZMII_MII0_100MB, ZMII_MII1_100MB };
131 /* Since multiple EMACs share MDIO lines in various ways, we need
132 * to avoid re-using the same PHY ID in cases where the arch didn't
133 * setup precise phy_map entries
135 static u32 busy_phy_map = 0;
137 /* If EMACs share a common MDIO device, this points to it */
138 static struct net_device *mdio_ndev = NULL;
140 struct emac_def_dev {
141 struct list_head link;
142 struct ocp_device *ocpdev;
143 struct ibm_ocp_mal *mal;
146 static struct net_device_stats *emac_stats(struct net_device *dev)
148 struct ocp_enet_private *fep = dev->priv;
153 emac_init_rgmii(struct ocp_device *rgmii_dev, int input, int phy_mode)
155 struct ibm_ocp_rgmii *rgmii = RGMII_PRIV(rgmii_dev);
156 const char *mode_name[] = { "RTBI", "RGMII", "TBI", "GMII" };
160 rgmii = kmalloc(sizeof(struct ibm_ocp_rgmii), GFP_KERNEL);
164 "rgmii%d: Out of memory allocating RGMII structure!\n",
165 rgmii_dev->def->index);
169 memset(rgmii, 0, sizeof(*rgmii));
172 (struct rgmii_regs *)ioremap(rgmii_dev->def->paddr,
173 sizeof(*rgmii->base));
174 if (rgmii->base == NULL) {
176 "rgmii%d: Cannot ioremap bridge registers!\n",
177 rgmii_dev->def->index);
182 ocp_set_drvdata(rgmii_dev, rgmii);
200 rgmii->base->fer &= ~RGMII_FER_MASK(input);
201 rgmii->base->fer |= rgmii_enable[mode] << (4 * input);
203 switch ((rgmii->base->fer & RGMII_FER_MASK(input)) >> (4 *
219 /* Set mode to RGMII if nothing valid is detected */
223 printk(KERN_NOTICE "rgmii%d: input %d in %s mode\n",
224 rgmii_dev->def->index, input, mode_name[mode]);
226 rgmii->mode[input] = mode;
233 emac_rgmii_port_speed(struct ocp_device *ocpdev, int input, int speed)
235 struct ibm_ocp_rgmii *rgmii = RGMII_PRIV(ocpdev);
236 unsigned int rgmii_speed;
238 rgmii_speed = in_be32(&rgmii->base->ssr);
240 rgmii_speed &= ~rgmii_speed_mask[input];
243 rgmii_speed |= rgmii_speed1000[input];
244 else if (speed == 100)
245 rgmii_speed |= rgmii_speed100[input];
247 out_be32(&rgmii->base->ssr, rgmii_speed);
250 static void emac_close_rgmii(struct ocp_device *ocpdev)
252 struct ibm_ocp_rgmii *rgmii = RGMII_PRIV(ocpdev);
253 BUG_ON(!rgmii || rgmii->users == 0);
255 if (!--rgmii->users) {
256 ocp_set_drvdata(ocpdev, NULL);
257 iounmap((void *)rgmii->base);
262 static int emac_init_zmii(struct ocp_device *zmii_dev, int input, int phy_mode)
264 struct ibm_ocp_zmii *zmii = ZMII_PRIV(zmii_dev);
265 const char *mode_name[] = { "SMII", "RMII", "MII" };
269 zmii = kmalloc(sizeof(struct ibm_ocp_zmii), GFP_KERNEL);
272 "zmii%d: Out of memory allocating ZMII structure!\n",
273 zmii_dev->def->index);
276 memset(zmii, 0, sizeof(*zmii));
279 (struct zmii_regs *)ioremap(zmii_dev->def->paddr,
280 sizeof(*zmii->base));
281 if (zmii->base == NULL) {
283 "zmii%d: Cannot ioremap bridge registers!\n",
284 zmii_dev->def->index);
289 ocp_set_drvdata(zmii_dev, zmii);
304 zmii->base->fer &= ~ZMII_FER_MASK(input);
305 zmii->base->fer |= zmii_enable[input][mode];
307 switch ((zmii->base->fer & ZMII_FER_MASK(input)) << (4 * input)) {
319 /* Set mode to SMII if nothing valid is detected */
323 printk(KERN_NOTICE "zmii%d: input %d in %s mode\n",
324 zmii_dev->def->index, input, mode_name[mode]);
326 zmii->mode[input] = mode;
332 static void emac_enable_zmii_port(struct ocp_device *ocpdev, int input)
335 struct ibm_ocp_zmii *zmii = ZMII_PRIV(ocpdev);
337 mask = in_be32(&zmii->base->fer);
338 mask &= zmii_enable[input][MDI]; /* turn all non enabled MDI's off */
339 mask |= zmii_enable[input][zmii->mode[input]] | mdi_enable[input];
340 out_be32(&zmii->base->fer, mask);
344 emac_zmii_port_speed(struct ocp_device *ocpdev, int input, int speed)
346 struct ibm_ocp_zmii *zmii = ZMII_PRIV(ocpdev);
349 zmii_speed |= zmii_speed100[input];
351 zmii_speed &= ~zmii_speed100[input];
353 out_be32(&zmii->base->ssr, zmii_speed);
356 static void emac_close_zmii(struct ocp_device *ocpdev)
358 struct ibm_ocp_zmii *zmii = ZMII_PRIV(ocpdev);
359 BUG_ON(!zmii || zmii->users == 0);
361 if (!--zmii->users) {
362 ocp_set_drvdata(ocpdev, NULL);
363 iounmap((void *)zmii->base);
368 int emac_phy_read(struct net_device *dev, int mii_id, int reg)
371 struct ocp_enet_private *fep = dev->priv;
372 emac_t *emacp = fep->emacp;
374 MDIO_DEBUG(("%s: phy_read, id: 0x%x, reg: 0x%x\n", dev->name, mii_id,
377 /* Enable proper ZMII port */
379 emac_enable_zmii_port(fep->zmii_dev, fep->zmii_input);
381 /* Use the EMAC that has the MDIO port */
390 if ((in_be32(&emacp->em0stacr) & EMAC_STACR_OC) == 0) {
391 printk(KERN_WARNING "%s: PHY read timeout #1!\n", dev->name);
395 /* Clear the speed bits and make a read request to the PHY */
396 stacr = ((EMAC_STACR_READ | (reg & 0x1f)) & ~EMAC_STACR_CLK_100MHZ);
397 stacr |= ((mii_id & 0x1F) << 5);
399 out_be32(&emacp->em0stacr, stacr);
402 stacr = in_be32(&emacp->em0stacr);
404 if ((stacr & EMAC_STACR_OC) == 0) {
405 printk(KERN_WARNING "%s: PHY read timeout #2!\n", dev->name);
409 /* Check for a read error */
410 if (stacr & EMAC_STACR_PHYE) {
411 MDIO_DEBUG(("EMAC MDIO PHY error !\n"));
415 MDIO_DEBUG((" -> 0x%x\n", stacr >> 16));
417 return (stacr >> 16);
420 void emac_phy_write(struct net_device *dev, int mii_id, int reg, int data)
423 struct ocp_enet_private *fep = dev->priv;
424 emac_t *emacp = fep->emacp;
426 MDIO_DEBUG(("%s phy_write, id: 0x%x, reg: 0x%x, data: 0x%x\n",
427 dev->name, mii_id, reg, data));
429 /* Enable proper ZMII port */
431 emac_enable_zmii_port(fep->zmii_dev, fep->zmii_input);
433 /* Use the EMAC that has the MDIO port */
442 if ((in_be32(&emacp->em0stacr) & EMAC_STACR_OC) == 0) {
443 printk(KERN_WARNING "%s: PHY write timeout #2!\n", dev->name);
447 /* Clear the speed bits and make a read request to the PHY */
449 stacr = ((EMAC_STACR_WRITE | (reg & 0x1f)) & ~EMAC_STACR_CLK_100MHZ);
450 stacr |= ((mii_id & 0x1f) << 5) | ((data & 0xffff) << 16);
452 out_be32(&emacp->em0stacr, stacr);
456 if ((in_be32(&emacp->em0stacr) & EMAC_STACR_OC) == 0)
457 printk(KERN_WARNING "%s: PHY write timeout #2!\n", dev->name);
459 /* Check for a write error */
460 if ((stacr & EMAC_STACR_PHYE) != 0) {
461 MDIO_DEBUG(("EMAC MDIO PHY error !\n"));
465 static void emac_txeob_dev(void *param, u32 chanmask)
467 struct net_device *dev = param;
468 struct ocp_enet_private *fep = dev->priv;
471 spin_lock_irqsave(&fep->lock, flags);
473 PKT_DEBUG(("emac_txeob_dev() entry, tx_cnt: %d\n", fep->tx_cnt));
475 while (fep->tx_cnt &&
476 !(fep->tx_desc[fep->ack_slot].ctrl & MAL_TX_CTRL_READY)) {
478 if (fep->tx_desc[fep->ack_slot].ctrl & MAL_TX_CTRL_LAST) {
479 /* Tell the system the transmit completed. */
480 dma_unmap_single(&fep->ocpdev->dev,
481 fep->tx_desc[fep->ack_slot].data_ptr,
482 fep->tx_desc[fep->ack_slot].data_len,
484 dev_kfree_skb_irq(fep->tx_skb[fep->ack_slot]);
486 if (fep->tx_desc[fep->ack_slot].ctrl &
487 (EMAC_TX_ST_EC | EMAC_TX_ST_MC | EMAC_TX_ST_SC))
488 fep->stats.collisions++;
491 fep->tx_skb[fep->ack_slot] = (struct sk_buff *)NULL;
492 if (++fep->ack_slot == NUM_TX_BUFF)
497 if (fep->tx_cnt < NUM_TX_BUFF)
498 netif_wake_queue(dev);
500 PKT_DEBUG(("emac_txeob_dev() exit, tx_cnt: %d\n", fep->tx_cnt));
502 spin_unlock_irqrestore(&fep->lock, flags);
506 Fill/Re-fill the rx chain with valid ctrl/ptrs.
507 This function will fill from rx_slot up to the parm end.
508 So to completely fill the chain pre-set rx_slot to 0 and
511 static void emac_rx_fill(struct net_device *dev, int end)
514 struct ocp_enet_private *fep = dev->priv;
518 /* We don't want the 16 bytes skb_reserve done by dev_alloc_skb,
519 * it breaks our cache line alignement. However, we still allocate
520 * +16 so that we end up allocating the exact same size as
521 * dev_alloc_skb() would do.
522 * Also, because of the skb_res, the max DMA size we give to EMAC
523 * is slighly wrong, causing it to potentially DMA 2 more bytes
524 * from a broken/oversized packet. These 16 bytes will take care
525 * that we don't walk on somebody else toes with that.
528 alloc_skb(fep->rx_buffer_size + 16, GFP_ATOMIC);
530 if (fep->rx_skb[i] == NULL) {
531 /* Keep rx_slot here, the next time clean/fill is called
532 * we will try again before the MAL wraps back here
533 * If the MAL tries to use this descriptor with
534 * the EMPTY bit off it will cause the
535 * rxde interrupt. That is where we will
536 * try again to allocate an sk_buff.
543 skb_reserve(fep->rx_skb[i], skb_res);
545 /* We must NOT dma_map_single the cache line right after the
546 * buffer, so we must crop our sync size to account for the
549 fep->rx_desc[i].data_ptr =
550 (unsigned char *)dma_map_single(&fep->ocpdev->dev,
551 (void *)fep->rx_skb[i]->
553 fep->rx_buffer_size -
554 skb_res, DMA_FROM_DEVICE);
557 * Some 4xx implementations use the previously
558 * reserved bits in data_len to encode the MS
559 * 4-bits of a 36-bit physical address (ERPN)
560 * This must be initialized.
562 fep->rx_desc[i].data_len = 0;
563 fep->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR |
564 (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
566 } while ((i = (i + 1) % NUM_RX_BUFF) != end);
572 emac_rx_csum(struct net_device *dev, unsigned short ctrl, struct sk_buff *skb)
574 struct ocp_enet_private *fep = dev->priv;
576 /* Exit if interface has no TAH engine */
578 skb->ip_summed = CHECKSUM_NONE;
582 /* Check for TCP/UDP/IP csum error */
583 if (ctrl & EMAC_CSUM_VER_ERROR) {
584 /* Let the stack verify checksum errors */
585 skb->ip_summed = CHECKSUM_NONE;
586 /* adapter->hw_csum_err++; */
589 skb->ip_summed = CHECKSUM_UNNECESSARY;
590 /* adapter->hw_csum_good++; */
594 static int emac_rx_clean(struct net_device *dev)
596 int i, b, bnum, buf[6];
597 int error, frame_length;
598 struct ocp_enet_private *fep = dev->priv;
603 PKT_DEBUG(("emac_rx_clean() entry, rx_slot: %d\n", fep->rx_slot));
606 if (fep->rx_skb[i] == NULL)
607 continue; /*we have already handled the packet but haved failed to alloc */
609 since rx_desc is in uncached mem we don't keep reading it directly
610 we pull out a local copy of ctrl and do the checks on the copy.
612 ctrl = fep->rx_desc[i].ctrl;
613 if (ctrl & MAL_RX_CTRL_EMPTY)
614 break; /*we don't have any more ready packets */
616 if (EMAC_IS_BAD_RX_PACKET(ctrl)) {
617 fep->stats.rx_errors++;
618 fep->stats.rx_dropped++;
620 if (ctrl & EMAC_RX_ST_OE)
621 fep->stats.rx_fifo_errors++;
622 if (ctrl & EMAC_RX_ST_AE)
623 fep->stats.rx_frame_errors++;
624 if (ctrl & EMAC_RX_ST_BFCS)
625 fep->stats.rx_crc_errors++;
626 if (ctrl & (EMAC_RX_ST_RP | EMAC_RX_ST_PTL |
627 EMAC_RX_ST_ORE | EMAC_RX_ST_IRE))
628 fep->stats.rx_length_errors++;
630 if ((ctrl & (MAL_RX_CTRL_FIRST | MAL_RX_CTRL_LAST)) ==
631 (MAL_RX_CTRL_FIRST | MAL_RX_CTRL_LAST)) {
632 /* Single descriptor packet */
633 emac_rx_csum(dev, ctrl, fep->rx_skb[i]);
634 /* Send the skb up the chain. */
635 frame_length = fep->rx_desc[i].data_len - 4;
636 skb_put(fep->rx_skb[i], frame_length);
637 fep->rx_skb[i]->dev = dev;
638 fep->rx_skb[i]->protocol =
639 eth_type_trans(fep->rx_skb[i], dev);
640 error = netif_rx(fep->rx_skb[i]);
642 if ((error == NET_RX_DROP) ||
643 (error == NET_RX_BAD)) {
644 fep->stats.rx_dropped++;
646 fep->stats.rx_packets++;
647 fep->stats.rx_bytes += frame_length;
649 fep->rx_skb[i] = NULL;
651 /* Multiple descriptor packet */
652 if (ctrl & MAL_RX_CTRL_FIRST) {
653 if (fep->rx_desc[(i + 1) % NUM_RX_BUFF].
654 ctrl & MAL_RX_CTRL_EMPTY)
661 if (((ctrl & MAL_RX_CTRL_FIRST) !=
662 MAL_RX_CTRL_FIRST) &&
663 ((ctrl & MAL_RX_CTRL_LAST) !=
665 if (fep->rx_desc[(i + 1) %
675 if (ctrl & MAL_RX_CTRL_LAST) {
678 skb_put(fep->rx_skb[buf[0]],
679 fep->rx_desc[buf[0]].data_len);
680 for (b = 1; b < bnum; b++) {
682 * MAL is braindead, we need
683 * to copy the remainder
684 * of the packet from the
685 * latter descriptor buffers
686 * to the first skb. Then
687 * dispose of the source
690 * Once the stack is fixed
691 * to handle frags on most
692 * protocols we can generate
693 * a fragmented skb with
696 memcpy(fep->rx_skb[buf[0]]->
698 fep->rx_skb[buf[0]]->len,
699 fep->rx_skb[buf[b]]->
701 fep->rx_desc[buf[b]].
703 skb_put(fep->rx_skb[buf[0]],
704 fep->rx_desc[buf[b]].
706 dma_unmap_single(&fep->ocpdev->
720 emac_rx_csum(dev, ctrl,
721 fep->rx_skb[buf[0]]);
723 fep->rx_skb[buf[0]]->dev = dev;
724 fep->rx_skb[buf[0]]->protocol =
725 eth_type_trans(fep->rx_skb[buf[0]],
727 error = netif_rx(fep->rx_skb[buf[0]]);
729 if ((error == NET_RX_DROP)
730 || (error == NET_RX_BAD)) {
731 fep->stats.rx_dropped++;
733 fep->stats.rx_packets++;
734 fep->stats.rx_bytes +=
735 fep->rx_skb[buf[0]]->len;
737 for (b = 0; b < bnum; b++)
738 fep->rx_skb[buf[b]] = NULL;
742 } while ((i = (i + 1) % NUM_RX_BUFF) != fep->rx_slot);
744 PKT_DEBUG(("emac_rx_clean() exit, rx_slot: %d\n", fep->rx_slot));
749 static void emac_rxeob_dev(void *param, u32 chanmask)
751 struct net_device *dev = param;
752 struct ocp_enet_private *fep = dev->priv;
756 spin_lock_irqsave(&fep->lock, flags);
757 if ((n = emac_rx_clean(dev)) != fep->rx_slot)
758 emac_rx_fill(dev, n);
759 spin_unlock_irqrestore(&fep->lock, flags);
763 * This interrupt should never occurr, we don't program
764 * the MAL for contiunous mode.
766 static void emac_txde_dev(void *param, u32 chanmask)
768 struct net_device *dev = param;
769 struct ocp_enet_private *fep = dev->priv;
771 printk(KERN_WARNING "%s: transmit descriptor error\n", dev->name);
776 /* Reenable the transmit channel */
777 mal_enable_tx_channels(fep->mal, fep->commac.tx_chan_mask);
781 * This interrupt should be very rare at best. This occurs when
782 * the hardware has a problem with the receive descriptors. The manual
783 * states that it occurs when the hardware cannot the receive descriptor
784 * empty bit is not set. The recovery mechanism will be to
785 * traverse through the descriptors, handle any that are marked to be
786 * handled and reinitialize each along the way. At that point the driver
789 static void emac_rxde_dev(void *param, u32 chanmask)
791 struct net_device *dev = param;
792 struct ocp_enet_private *fep = dev->priv;
795 if (net_ratelimit()) {
796 printk(KERN_WARNING "%s: receive descriptor error\n",
804 /* Disable RX channel */
805 spin_lock_irqsave(&fep->lock, flags);
806 mal_disable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
808 /* For now, charge the error against all emacs */
809 fep->stats.rx_errors++;
811 /* so do we have any good packets still? */
814 /* When the interface is restarted it resets processing to the
815 * first descriptor in the table.
819 emac_rx_fill(dev, 0);
821 set_mal_dcrn(fep->mal, DCRN_MALRXEOBISR, fep->commac.rx_chan_mask);
822 set_mal_dcrn(fep->mal, DCRN_MALRXDEIR, fep->commac.rx_chan_mask);
824 /* Reenable the receive channels */
825 mal_enable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
826 spin_unlock_irqrestore(&fep->lock, flags);
830 emac_mac_irq(int irq, void *dev_instance, struct pt_regs *regs)
832 struct net_device *dev = dev_instance;
833 struct ocp_enet_private *fep = dev->priv;
834 emac_t *emacp = fep->emacp;
835 unsigned long tmp_em0isr;
838 tmp_em0isr = in_be32(&emacp->em0isr);
839 if (tmp_em0isr & (EMAC_ISR_TE0 | EMAC_ISR_TE1)) {
840 /* This error is a hard transmit error - could retransmit */
841 fep->stats.tx_errors++;
843 /* Reenable the transmit channel */
844 mal_enable_tx_channels(fep->mal, fep->commac.tx_chan_mask);
847 fep->stats.rx_errors++;
850 if (tmp_em0isr & EMAC_ISR_RP)
851 fep->stats.rx_length_errors++;
852 if (tmp_em0isr & EMAC_ISR_ALE)
853 fep->stats.rx_frame_errors++;
854 if (tmp_em0isr & EMAC_ISR_BFCS)
855 fep->stats.rx_crc_errors++;
856 if (tmp_em0isr & EMAC_ISR_PTLE)
857 fep->stats.rx_length_errors++;
858 if (tmp_em0isr & EMAC_ISR_ORE)
859 fep->stats.rx_length_errors++;
860 if (tmp_em0isr & EMAC_ISR_TE0)
861 fep->stats.tx_aborted_errors++;
863 emac_err_dump(dev, tmp_em0isr);
865 out_be32(&emacp->em0isr, tmp_em0isr);
870 static int emac_start_xmit(struct sk_buff *skb, struct net_device *dev)
874 struct ocp_enet_private *fep = dev->priv;
875 emac_t *emacp = fep->emacp;
877 unsigned int offset = 0, size, f, tx_slot_first;
878 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
880 spin_lock_irqsave(&fep->lock, flags);
882 len -= skb->data_len;
884 if ((fep->tx_cnt + nr_frags + len / DESC_BUF_SIZE + 1) > NUM_TX_BUFF) {
885 PKT_DEBUG(("emac_start_xmit() stopping queue\n"));
886 netif_stop_queue(dev);
887 spin_unlock_irqrestore(&fep->lock, flags);
888 restore_flags(flags);
892 tx_slot_first = fep->tx_slot;
895 size = min(len, DESC_BUF_SIZE);
897 fep->tx_desc[fep->tx_slot].data_len = (short)size;
898 fep->tx_desc[fep->tx_slot].data_ptr =
899 (unsigned char *)dma_map_single(&fep->ocpdev->dev,
900 (void *)((unsigned int)skb->
902 size, DMA_TO_DEVICE);
904 ctrl = EMAC_TX_CTRL_DFLT;
905 if (fep->tx_slot != tx_slot_first)
906 ctrl |= MAL_TX_CTRL_READY;
907 if ((NUM_TX_BUFF - 1) == fep->tx_slot)
908 ctrl |= MAL_TX_CTRL_WRAP;
909 if (!nr_frags && (len == size)) {
910 ctrl |= MAL_TX_CTRL_LAST;
911 fep->tx_skb[fep->tx_slot] = skb;
913 if (skb->ip_summed == CHECKSUM_HW)
914 ctrl |= EMAC_TX_CTRL_TAH_CSUM;
916 fep->tx_desc[fep->tx_slot].ctrl = ctrl;
922 if (++fep->tx_cnt == NUM_TX_BUFF)
923 netif_stop_queue(dev);
925 /* Next descriptor */
926 if (++fep->tx_slot == NUM_TX_BUFF)
930 for (f = 0; f < nr_frags; f++) {
931 struct skb_frag_struct *frag;
933 frag = &skb_shinfo(skb)->frags[f];
938 size = min(len, DESC_BUF_SIZE);
940 dma_map_page(&fep->ocpdev->dev,
942 frag->page_offset + offset,
943 size, DMA_TO_DEVICE);
945 ctrl = EMAC_TX_CTRL_DFLT | MAL_TX_CTRL_READY;
946 if ((NUM_TX_BUFF - 1) == fep->tx_slot)
947 ctrl |= MAL_TX_CTRL_WRAP;
948 if ((f == (nr_frags - 1)) && (len == size)) {
949 ctrl |= MAL_TX_CTRL_LAST;
950 fep->tx_skb[fep->tx_slot] = skb;
953 if (skb->ip_summed == CHECKSUM_HW)
954 ctrl |= EMAC_TX_CTRL_TAH_CSUM;
956 fep->tx_desc[fep->tx_slot].data_len = (short)size;
957 fep->tx_desc[fep->tx_slot].data_ptr =
958 (char *)((page_to_pfn(frag->page) << PAGE_SHIFT) +
959 frag->page_offset + offset);
960 fep->tx_desc[fep->tx_slot].ctrl = ctrl;
966 if (++fep->tx_cnt == NUM_TX_BUFF)
967 netif_stop_queue(dev);
969 /* Next descriptor */
970 if (++fep->tx_slot == NUM_TX_BUFF)
976 * Deferred set READY on first descriptor of packet to
979 fep->tx_desc[tx_slot_first].ctrl |= MAL_TX_CTRL_READY;
981 /* Send the packet out. */
982 out_be32(&emacp->em0tmr0, EMAC_TMR0_XMIT);
984 fep->stats.tx_packets++;
985 fep->stats.tx_bytes += skb->len;
987 PKT_DEBUG(("emac_start_xmit() exitn"));
989 spin_unlock_irqrestore(&fep->lock, flags);
994 static int emac_adjust_to_link(struct ocp_enet_private *fep)
996 emac_t *emacp = fep->emacp;
997 struct ibm_ocp_rgmii *rgmii;
998 unsigned long mode_reg;
999 int full_duplex, speed;
1004 /* set mode register 1 defaults */
1005 mode_reg = EMAC_M1_DEFAULT;
1007 /* Read link mode on PHY */
1008 if (fep->phy_mii.def->ops->read_link(&fep->phy_mii) == 0) {
1009 /* If an error occurred, we don't deal with it yet */
1010 full_duplex = (fep->phy_mii.duplex == DUPLEX_FULL);
1011 speed = fep->phy_mii.speed;
1015 rgmii = RGMII_PRIV(fep->rgmii_dev);
1017 /* set speed (default is 10Mb) */
1020 mode_reg |= EMAC_M1_JUMBO_ENABLE | EMAC_M1_RFS_16K;
1021 if ((rgmii->mode[fep->rgmii_input] == RTBI)
1022 || (rgmii->mode[fep->rgmii_input] == TBI))
1023 mode_reg |= EMAC_M1_MF_1000GPCS;
1025 mode_reg |= EMAC_M1_MF_1000MBPS;
1027 emac_rgmii_port_speed(fep->rgmii_dev, fep->rgmii_input,
1031 mode_reg |= EMAC_M1_MF_100MBPS | EMAC_M1_RFS_4K;
1033 emac_rgmii_port_speed(fep->rgmii_dev, fep->rgmii_input,
1036 emac_zmii_port_speed(fep->zmii_dev, fep->zmii_input,
1041 mode_reg = (mode_reg & ~EMAC_M1_MF_100MBPS) | EMAC_M1_RFS_4K;
1043 emac_rgmii_port_speed(fep->rgmii_dev, fep->rgmii_input,
1046 emac_zmii_port_speed(fep->zmii_dev, fep->zmii_input,
1051 mode_reg |= EMAC_M1_FDE | EMAC_M1_EIFC | EMAC_M1_IST;
1053 mode_reg &= ~(EMAC_M1_FDE | EMAC_M1_EIFC | EMAC_M1_ILE);
1055 LINK_DEBUG(("%s: adjust to link, speed: %d, duplex: %d, opened: %d\n",
1056 fep->ndev->name, speed, full_duplex, fep->opened));
1058 printk(KERN_INFO "%s: Speed: %d, %s duplex.\n",
1059 fep->ndev->name, speed, full_duplex ? "Full" : "Half");
1061 out_be32(&emacp->em0mr1, mode_reg);
1066 static int emac_set_mac_address(struct net_device *ndev, void *p)
1068 struct ocp_enet_private *fep = ndev->priv;
1069 emac_t *emacp = fep->emacp;
1070 struct sockaddr *addr = p;
1072 if (!is_valid_ether_addr(addr->sa_data))
1073 return -EADDRNOTAVAIL;
1075 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1077 /* set the high address */
1078 out_be32(&emacp->em0iahr,
1079 (fep->ndev->dev_addr[0] << 8) | fep->ndev->dev_addr[1]);
1081 /* set the low address */
1082 out_be32(&emacp->em0ialr,
1083 (fep->ndev->dev_addr[2] << 24) | (fep->ndev->dev_addr[3] << 16)
1084 | (fep->ndev->dev_addr[4] << 8) | fep->ndev->dev_addr[5]);
1089 static int emac_change_mtu(struct net_device *dev, int new_mtu)
1091 struct ocp_enet_private *fep = dev->priv;
1092 int old_mtu = dev->mtu;
1093 emac_t *emacp = fep->emacp;
1096 unsigned long flags;
1098 if ((new_mtu < EMAC_MIN_MTU) || (new_mtu > EMAC_MAX_MTU)) {
1100 "emac: Invalid MTU setting, MTU must be between %d and %d\n",
1101 EMAC_MIN_MTU, EMAC_MAX_MTU);
1105 if (old_mtu != new_mtu && netif_running(dev)) {
1106 /* Stop rx engine */
1107 em0mr0 = in_be32(&emacp->em0mr0);
1108 out_be32(&emacp->em0mr0, em0mr0 & ~EMAC_M0_RXE);
1110 /* Wait for descriptors to be empty */
1113 for (i = 0; i < NUM_RX_BUFF; i++)
1114 if (!(fep->rx_desc[i].ctrl & MAL_RX_CTRL_EMPTY)) {
1116 "emac: RX ring is still full\n");
1121 spin_lock_irqsave(&fep->lock, flags);
1123 mal_disable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
1125 /* Destroy all old rx skbs */
1126 for (i = 0; i < NUM_RX_BUFF; i++) {
1127 dma_unmap_single(&fep->ocpdev->dev,
1128 fep->rx_desc[i].data_ptr,
1129 fep->rx_desc[i].data_len,
1131 dev_kfree_skb(fep->rx_skb[i]);
1132 fep->rx_skb[i] = NULL;
1135 /* Set new rx_buffer_size and advertise new mtu */
1136 fep->rx_buffer_size =
1137 new_mtu + ENET_HEADER_SIZE + ENET_FCS_SIZE;
1140 /* Re-init rx skbs */
1142 emac_rx_fill(dev, 0);
1144 /* Restart the rx engine */
1145 mal_enable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
1146 out_be32(&emacp->em0mr0, em0mr0 | EMAC_M0_RXE);
1148 spin_unlock_irqrestore(&fep->lock, flags);
1154 static void __emac_set_multicast_list(struct net_device *dev)
1156 struct ocp_enet_private *fep = dev->priv;
1157 emac_t *emacp = fep->emacp;
1158 u32 rmr = in_be32(&emacp->em0rmr);
1160 /* First clear all special bits, they can be set later */
1161 rmr &= ~(EMAC_RMR_PME | EMAC_RMR_PMME | EMAC_RMR_MAE);
1163 if (dev->flags & IFF_PROMISC) {
1164 rmr |= EMAC_RMR_PME;
1165 } else if (dev->flags & IFF_ALLMULTI || 32 < dev->mc_count) {
1167 * Must be setting up to use multicast
1168 * Now check for promiscuous multicast
1170 rmr |= EMAC_RMR_PMME;
1171 } else if (dev->flags & IFF_MULTICAST && 0 < dev->mc_count) {
1172 unsigned short em0gaht[4] = { 0, 0, 0, 0 };
1173 struct dev_mc_list *dmi;
1175 /* Need to hash on the multicast address. */
1176 for (dmi = dev->mc_list; dmi; dmi = dmi->next) {
1177 unsigned long mc_crc;
1178 unsigned int bit_number;
1180 mc_crc = ether_crc(6, (char *)dmi->dmi_addr);
1181 bit_number = 63 - (mc_crc >> 26); /* MSB: 0 LSB: 63 */
1182 em0gaht[bit_number >> 4] |=
1183 0x8000 >> (bit_number & 0x0f);
1185 emacp->em0gaht1 = em0gaht[0];
1186 emacp->em0gaht2 = em0gaht[1];
1187 emacp->em0gaht3 = em0gaht[2];
1188 emacp->em0gaht4 = em0gaht[3];
1190 /* Turn on multicast addressing */
1191 rmr |= EMAC_RMR_MAE;
1193 out_be32(&emacp->em0rmr, rmr);
1196 static int emac_init_tah(struct ocp_enet_private *fep)
1200 /* Initialize TAH and enable checksum verification */
1201 tahp = (tah_t *) ioremap(fep->tah_dev->def->paddr, sizeof(*tahp));
1204 printk(KERN_ERR "tah%d: Cannot ioremap TAH registers!\n",
1205 fep->tah_dev->def->index);
1210 out_be32(&tahp->tah_mr, TAH_MR_SR);
1212 /* wait for reset to complete */
1213 while (in_be32(&tahp->tah_mr) & TAH_MR_SR) ;
1215 /* 10KB TAH TX FIFO accomodates the max MTU of 9000 */
1216 out_be32(&tahp->tah_mr,
1217 TAH_MR_CVR | TAH_MR_ST_768 | TAH_MR_TFS_10KB | TAH_MR_DTFP |
1225 static void emac_init_rings(struct net_device *dev)
1227 struct ocp_enet_private *ep = dev->priv;
1230 ep->tx_desc = (struct mal_descriptor *)((char *)ep->mal->tx_virt_addr +
1234 (struct mal_descriptor *)((char *)ep->mal->rx_virt_addr +
1235 (ep->mal_rx_chan * MAL_DT_ALIGN));
1237 /* Fill in the transmit descriptor ring. */
1238 for (loop = 0; loop < NUM_TX_BUFF; loop++) {
1239 if (ep->tx_skb[loop]) {
1240 dma_unmap_single(&ep->ocpdev->dev,
1241 ep->tx_desc[loop].data_ptr,
1242 ep->tx_desc[loop].data_len,
1244 dev_kfree_skb_irq(ep->tx_skb[loop]);
1246 ep->tx_skb[loop] = NULL;
1247 ep->tx_desc[loop].ctrl = 0;
1248 ep->tx_desc[loop].data_len = 0;
1249 ep->tx_desc[loop].data_ptr = NULL;
1251 ep->tx_desc[loop - 1].ctrl |= MAL_TX_CTRL_WRAP;
1253 /* Format the receive descriptor ring. */
1255 /* Default is MTU=1500 + Ethernet overhead */
1256 ep->rx_buffer_size = ENET_DEF_BUF_SIZE;
1257 emac_rx_fill(dev, 0);
1258 if (ep->rx_slot != 0) {
1260 "%s: Not enough mem for RxChain durning Open?\n",
1262 /*We couldn't fill the ring at startup?
1263 *We could clean up and fail to open but right now we will try to
1264 *carry on. It may be a sign of a bad NUM_RX_BUFF value
1273 static void emac_reset_configure(struct ocp_enet_private *fep)
1275 emac_t *emacp = fep->emacp;
1278 mal_disable_tx_channels(fep->mal, fep->commac.tx_chan_mask);
1279 mal_disable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
1282 * Check for a link, some PHYs don't provide a clock if
1283 * no link is present. Some EMACs will not come out of
1284 * soft reset without a PHY clock present.
1286 if (fep->phy_mii.def->ops->poll_link(&fep->phy_mii)) {
1287 /* Reset the EMAC */
1288 out_be32(&emacp->em0mr0, EMAC_M0_SRST);
1290 for (i = 0; i < 100; i++) {
1291 if ((in_be32(&emacp->em0mr0) & EMAC_M0_SRST) == 0)
1297 printk(KERN_ERR "%s: Cannot reset EMAC\n",
1303 /* Switch IRQs off for now */
1304 out_be32(&emacp->em0iser, 0);
1306 /* Configure MAL rx channel */
1307 mal_set_rcbs(fep->mal, fep->mal_rx_chan, DESC_BUF_SIZE_REG);
1309 /* set the high address */
1310 out_be32(&emacp->em0iahr,
1311 (fep->ndev->dev_addr[0] << 8) | fep->ndev->dev_addr[1]);
1313 /* set the low address */
1314 out_be32(&emacp->em0ialr,
1315 (fep->ndev->dev_addr[2] << 24) | (fep->ndev->dev_addr[3] << 16)
1316 | (fep->ndev->dev_addr[4] << 8) | fep->ndev->dev_addr[5]);
1318 /* Adjust to link */
1319 if (netif_carrier_ok(fep->ndev))
1320 emac_adjust_to_link(fep);
1322 /* enable broadcast/individual address and RX FIFO defaults */
1323 out_be32(&emacp->em0rmr, EMAC_RMR_DEFAULT);
1325 /* set transmit request threshold register */
1326 out_be32(&emacp->em0trtr, EMAC_TRTR_DEFAULT);
1328 /* Reconfigure multicast */
1329 __emac_set_multicast_list(fep->ndev);
1331 /* Set receiver/transmitter defaults */
1332 out_be32(&emacp->em0rwmr, EMAC_RWMR_DEFAULT);
1333 out_be32(&emacp->em0tmr0, EMAC_TMR0_DEFAULT);
1334 out_be32(&emacp->em0tmr1, EMAC_TMR1_DEFAULT);
1337 out_be32(&emacp->em0ipgvr, CONFIG_IBM_EMAC_FGAP);
1339 /* Init ring buffers */
1340 emac_init_rings(fep->ndev);
1343 static void emac_kick(struct ocp_enet_private *fep)
1345 emac_t *emacp = fep->emacp;
1346 unsigned long emac_ier;
1348 emac_ier = EMAC_ISR_PP | EMAC_ISR_BP | EMAC_ISR_RP |
1349 EMAC_ISR_SE | EMAC_ISR_PTLE | EMAC_ISR_ALE |
1350 EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
1352 out_be32(&emacp->em0iser, emac_ier);
1354 /* enable all MAL transmit and receive channels */
1355 mal_enable_tx_channels(fep->mal, fep->commac.tx_chan_mask);
1356 mal_enable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
1358 /* set transmit and receive enable */
1359 out_be32(&emacp->em0mr0, EMAC_M0_TXE | EMAC_M0_RXE);
1363 emac_start_link(struct ocp_enet_private *fep, struct ethtool_cmd *ep)
1370 /* Default advertise */
1371 advertise = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1372 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1373 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full;
1374 autoneg = fep->want_autoneg;
1375 forced_speed = fep->phy_mii.speed;
1376 forced_duplex = fep->phy_mii.duplex;
1378 /* Setup link parameters */
1380 if (ep->autoneg == AUTONEG_ENABLE) {
1381 advertise = ep->advertising;
1385 forced_speed = ep->speed;
1386 forced_duplex = ep->duplex;
1390 /* Configure PHY & start aneg */
1391 fep->want_autoneg = autoneg;
1393 LINK_DEBUG(("%s: start link aneg, advertise: 0x%x\n",
1394 fep->ndev->name, advertise));
1395 fep->phy_mii.def->ops->setup_aneg(&fep->phy_mii, advertise);
1397 LINK_DEBUG(("%s: start link forced, speed: %d, duplex: %d\n",
1398 fep->ndev->name, forced_speed, forced_duplex));
1399 fep->phy_mii.def->ops->setup_forced(&fep->phy_mii, forced_speed,
1402 fep->timer_ticks = 0;
1403 mod_timer(&fep->link_timer, jiffies + HZ);
1406 static void emac_link_timer(unsigned long data)
1408 struct ocp_enet_private *fep = (struct ocp_enet_private *)data;
1411 if (fep->going_away)
1414 spin_lock_irq(&fep->lock);
1416 link = fep->phy_mii.def->ops->poll_link(&fep->phy_mii);
1417 LINK_DEBUG(("%s: poll_link: %d\n", fep->ndev->name, link));
1419 if (link == netif_carrier_ok(fep->ndev)) {
1420 if (!link && fep->want_autoneg && (++fep->timer_ticks) > 10)
1421 emac_start_link(fep, NULL);
1424 printk(KERN_INFO "%s: Link is %s\n", fep->ndev->name,
1425 link ? "Up" : "Down");
1427 netif_carrier_on(fep->ndev);
1428 /* Chip needs a full reset on config change. That sucks, so I
1429 * should ultimately move that to some tasklet to limit
1430 * latency peaks caused by this code
1432 emac_reset_configure(fep);
1436 fep->timer_ticks = 0;
1437 netif_carrier_off(fep->ndev);
1440 mod_timer(&fep->link_timer, jiffies + HZ);
1441 spin_unlock_irq(&fep->lock);
1444 static void emac_set_multicast_list(struct net_device *dev)
1446 struct ocp_enet_private *fep = dev->priv;
1448 spin_lock_irq(&fep->lock);
1449 __emac_set_multicast_list(dev);
1450 spin_unlock_irq(&fep->lock);
1453 static int emac_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
1455 struct ocp_enet_private *fep = ndev->priv;
1457 cmd->supported = fep->phy_mii.def->features;
1458 cmd->port = PORT_MII;
1459 cmd->transceiver = XCVR_EXTERNAL;
1460 cmd->phy_address = fep->mii_phy_addr;
1461 spin_lock_irq(&fep->lock);
1462 cmd->autoneg = fep->want_autoneg;
1463 cmd->speed = fep->phy_mii.speed;
1464 cmd->duplex = fep->phy_mii.duplex;
1465 spin_unlock_irq(&fep->lock);
1469 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
1471 struct ocp_enet_private *fep = ndev->priv;
1472 unsigned long features = fep->phy_mii.def->features;
1474 if (!capable(CAP_NET_ADMIN))
1477 if (cmd->autoneg != AUTONEG_ENABLE && cmd->autoneg != AUTONEG_DISABLE)
1479 if (cmd->autoneg == AUTONEG_ENABLE && cmd->advertising == 0)
1481 if (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL)
1483 if (cmd->autoneg == AUTONEG_DISABLE)
1484 switch (cmd->speed) {
1486 if (cmd->duplex == DUPLEX_HALF &&
1487 (features & SUPPORTED_10baseT_Half) == 0)
1489 if (cmd->duplex == DUPLEX_FULL &&
1490 (features & SUPPORTED_10baseT_Full) == 0)
1494 if (cmd->duplex == DUPLEX_HALF &&
1495 (features & SUPPORTED_100baseT_Half) == 0)
1497 if (cmd->duplex == DUPLEX_FULL &&
1498 (features & SUPPORTED_100baseT_Full) == 0)
1502 if (cmd->duplex == DUPLEX_HALF &&
1503 (features & SUPPORTED_1000baseT_Half) == 0)
1505 if (cmd->duplex == DUPLEX_FULL &&
1506 (features & SUPPORTED_1000baseT_Full) == 0)
1511 } else if ((features & SUPPORTED_Autoneg) == 0)
1513 spin_lock_irq(&fep->lock);
1514 emac_start_link(fep, cmd);
1515 spin_unlock_irq(&fep->lock);
1520 emac_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1522 struct ocp_enet_private *fep = ndev->priv;
1524 strcpy(info->driver, DRV_NAME);
1525 strcpy(info->version, DRV_VERSION);
1526 info->fw_version[0] = '\0';
1527 sprintf(info->bus_info, "IBM EMAC %d", fep->ocpdev->def->index);
1528 info->regdump_len = 0;
1531 static int emac_nway_reset(struct net_device *ndev)
1533 struct ocp_enet_private *fep = ndev->priv;
1535 if (!fep->want_autoneg)
1537 spin_lock_irq(&fep->lock);
1538 emac_start_link(fep, NULL);
1539 spin_unlock_irq(&fep->lock);
1543 static u32 emac_get_link(struct net_device *ndev)
1545 return netif_carrier_ok(ndev);
1548 static struct ethtool_ops emac_ethtool_ops = {
1549 .get_settings = emac_get_settings,
1550 .set_settings = emac_set_settings,
1551 .get_drvinfo = emac_get_drvinfo,
1552 .nway_reset = emac_nway_reset,
1553 .get_link = emac_get_link
1556 static int emac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1558 struct ocp_enet_private *fep = dev->priv;
1559 uint *data = (uint *) & rq->ifr_data;
1563 data[0] = fep->mii_phy_addr;
1566 data[3] = emac_phy_read(dev, fep->mii_phy_addr, data[1]);
1569 if (!capable(CAP_NET_ADMIN))
1572 emac_phy_write(dev, fep->mii_phy_addr, data[1], data[2]);
1579 static int emac_open(struct net_device *dev)
1581 struct ocp_enet_private *fep = dev->priv;
1584 spin_lock_irq(&fep->lock);
1587 netif_carrier_off(dev);
1589 /* Reset & configure the chip */
1590 emac_reset_configure(fep);
1592 spin_unlock_irq(&fep->lock);
1594 /* Request our interrupt lines */
1595 rc = request_irq(dev->irq, emac_mac_irq, 0, "IBM EMAC MAC", dev);
1597 printk("dev->irq %d failed\n", dev->irq);
1600 /* Kick the chip rx & tx channels into life */
1601 spin_lock_irq(&fep->lock);
1603 spin_unlock_irq(&fep->lock);
1605 netif_start_queue(dev);
1610 static int emac_close(struct net_device *dev)
1612 struct ocp_enet_private *fep = dev->priv;
1613 emac_t *emacp = fep->emacp;
1615 /* XXX Stop IRQ emitting here */
1616 spin_lock_irq(&fep->lock);
1618 mal_disable_tx_channels(fep->mal, fep->commac.tx_chan_mask);
1619 mal_disable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
1620 netif_carrier_off(dev);
1621 netif_stop_queue(dev);
1624 * Check for a link, some PHYs don't provide a clock if
1625 * no link is present. Some EMACs will not come out of
1626 * soft reset without a PHY clock present.
1628 if (fep->phy_mii.def->ops->poll_link(&fep->phy_mii)) {
1629 out_be32(&emacp->em0mr0, EMAC_M0_SRST);
1632 if (emacp->em0mr0 & EMAC_M0_SRST) {
1633 /*not sure what to do here hopefully it clears before another open */
1635 "%s: Phy SoftReset didn't clear, no link?\n",
1640 /* Free the irq's */
1641 free_irq(dev->irq, dev);
1643 spin_unlock_irq(&fep->lock);
1648 static void emac_remove(struct ocp_device *ocpdev)
1650 struct net_device *dev = ocp_get_drvdata(ocpdev);
1651 struct ocp_enet_private *ep = dev->priv;
1653 /* FIXME: locking, races, ... */
1655 ocp_set_drvdata(ocpdev, NULL);
1657 emac_close_rgmii(ep->rgmii_dev);
1659 emac_close_zmii(ep->zmii_dev);
1661 unregister_netdev(dev);
1662 del_timer_sync(&ep->link_timer);
1663 mal_unregister_commac(ep->mal, &ep->commac);
1664 iounmap((void *)ep->emacp);
1668 struct mal_commac_ops emac_commac_ops = {
1669 .txeob = &emac_txeob_dev,
1670 .txde = &emac_txde_dev,
1671 .rxeob = &emac_rxeob_dev,
1672 .rxde = &emac_rxde_dev,
1675 static int emac_init_device(struct ocp_device *ocpdev, struct ibm_ocp_mal *mal)
1677 int deferred_init = 0;
1679 struct net_device *ndev;
1680 struct ocp_enet_private *ep;
1681 struct ocp_func_emac_data *emacdata;
1685 emacdata = (struct ocp_func_emac_data *)ocpdev->def->additions;
1687 printk(KERN_ERR "emac%d: Missing additional data!\n",
1688 ocpdev->def->index);
1692 /* Allocate our net_device structure */
1693 ndev = alloc_etherdev(sizeof(struct ocp_enet_private));
1696 "emac%d: Could not allocate ethernet device.\n",
1697 ocpdev->def->index);
1702 ep->ocpdev = ocpdev;
1703 ndev->irq = ocpdev->def->irq;
1704 ep->wol_irq = emacdata->wol_irq;
1705 if (emacdata->mdio_idx >= 0) {
1706 if (emacdata->mdio_idx == ocpdev->def->index) {
1707 /* Set the common MDIO net_device */
1711 ep->mdio_dev = mdio_ndev;
1713 ep->mdio_dev = ndev;
1716 ocp_set_drvdata(ocpdev, ndev);
1718 spin_lock_init(&ep->lock);
1720 /* Fill out MAL informations and register commac */
1722 ep->mal_tx_chan = emacdata->mal_tx_chan;
1723 ep->mal_rx_chan = emacdata->mal_rx_chan;
1724 ep->commac.ops = &emac_commac_ops;
1725 ep->commac.dev = ndev;
1726 ep->commac.tx_chan_mask = MAL_CHAN_MASK(ep->mal_tx_chan);
1727 ep->commac.rx_chan_mask = MAL_CHAN_MASK(ep->mal_rx_chan);
1728 rc = mal_register_commac(ep->mal, &ep->commac);
1734 ep->emacp = (emac_t *) ioremap(ocpdev->def->paddr, sizeof(emac_t));
1736 /* Check if we need to attach to a ZMII */
1737 if (emacdata->zmii_idx >= 0) {
1738 ep->zmii_input = emacdata->zmii_mux;
1740 ocp_find_device(OCP_ANY_ID, OCP_FUNC_ZMII,
1741 emacdata->zmii_idx);
1742 if (ep->zmii_dev == NULL)
1744 "emac%d: ZMII %d requested but not found !\n",
1745 ocpdev->def->index, emacdata->zmii_idx);
1747 emac_init_zmii(ep->zmii_dev, ep->zmii_input,
1748 emacdata->phy_mode)) != 0)
1752 /* Check if we need to attach to a RGMII */
1753 if (emacdata->rgmii_idx >= 0) {
1754 ep->rgmii_input = emacdata->rgmii_mux;
1756 ocp_find_device(OCP_ANY_ID, OCP_FUNC_RGMII,
1757 emacdata->rgmii_idx);
1758 if (ep->rgmii_dev == NULL)
1760 "emac%d: RGMII %d requested but not found !\n",
1761 ocpdev->def->index, emacdata->rgmii_idx);
1763 emac_init_rgmii(ep->rgmii_dev, ep->rgmii_input,
1764 emacdata->phy_mode)) != 0)
1768 /* Check if we need to attach to a TAH */
1769 if (emacdata->tah_idx >= 0) {
1771 ocp_find_device(OCP_ANY_ID, OCP_FUNC_TAH,
1773 if (ep->tah_dev == NULL)
1775 "emac%d: TAH %d requested but not found !\n",
1776 ocpdev->def->index, emacdata->tah_idx);
1777 else if ((rc = emac_init_tah(ep)) != 0)
1781 if (deferred_init) {
1782 if (!list_empty(&emac_init_list)) {
1783 struct list_head *entry;
1784 struct emac_def_dev *ddev;
1786 list_for_each(entry, &emac_init_list) {
1788 list_entry(entry, struct emac_def_dev,
1790 emac_init_device(ddev->ocpdev, ddev->mal);
1795 /* Init link monitoring timer */
1796 init_timer(&ep->link_timer);
1797 ep->link_timer.function = emac_link_timer;
1798 ep->link_timer.data = (unsigned long)ep;
1799 ep->timer_ticks = 0;
1801 /* Fill up the mii_phy structure */
1802 ep->phy_mii.dev = ndev;
1803 ep->phy_mii.mdio_read = emac_phy_read;
1804 ep->phy_mii.mdio_write = emac_phy_write;
1805 ep->phy_mii.mode = emacdata->phy_mode;
1808 phy_map = emacdata->phy_map | busy_phy_map;
1809 for (i = 0; i <= 0x1f; i++, phy_map >>= 1) {
1810 if ((phy_map & 0x1) == 0) {
1811 int val = emac_phy_read(ndev, i, MII_BMCR);
1812 if (val != 0xffff && val != -1)
1817 printk(KERN_WARNING "emac%d: Can't find PHY.\n",
1818 ocpdev->def->index);
1822 busy_phy_map |= 1 << i;
1823 ep->mii_phy_addr = i;
1824 rc = mii_phy_probe(&ep->phy_mii, i);
1826 printk(KERN_WARNING "emac%d: Failed to probe PHY type.\n",
1827 ocpdev->def->index);
1832 /* Setup initial PHY config & startup aneg */
1833 if (ep->phy_mii.def->ops->init)
1834 ep->phy_mii.def->ops->init(&ep->phy_mii);
1835 netif_carrier_off(ndev);
1836 if (ep->phy_mii.def->features & SUPPORTED_Autoneg)
1837 ep->want_autoneg = 1;
1838 emac_start_link(ep, NULL);
1840 /* read the MAC Address */
1841 for (i = 0; i < 6; i++)
1842 ndev->dev_addr[i] = emacdata->mac_addr[i];
1844 /* Fill in the driver function table */
1845 ndev->open = &emac_open;
1846 ndev->hard_start_xmit = &emac_start_xmit;
1847 ndev->stop = &emac_close;
1848 ndev->get_stats = &emac_stats;
1849 if (emacdata->jumbo)
1850 ndev->change_mtu = &emac_change_mtu;
1851 ndev->set_mac_address = &emac_set_mac_address;
1852 ndev->set_multicast_list = &emac_set_multicast_list;
1853 ndev->do_ioctl = &emac_ioctl;
1854 SET_ETHTOOL_OPS(ndev, &emac_ethtool_ops);
1855 if (emacdata->tah_idx >= 0)
1856 ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG;
1858 SET_MODULE_OWNER(ndev);
1860 rc = register_netdev(ndev);
1864 printk("%s: IBM emac, MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1866 ndev->dev_addr[0], ndev->dev_addr[1], ndev->dev_addr[2],
1867 ndev->dev_addr[3], ndev->dev_addr[4], ndev->dev_addr[5]);
1868 printk(KERN_INFO "%s: Found %s PHY (0x%02x)\n",
1869 ndev->name, ep->phy_mii.def->name, ep->mii_phy_addr);
1872 if (rc && commac_reg)
1873 mal_unregister_commac(ep->mal, &ep->commac);
1880 static int emac_probe(struct ocp_device *ocpdev)
1882 struct ocp_device *maldev;
1883 struct ibm_ocp_mal *mal;
1884 struct ocp_func_emac_data *emacdata;
1886 emacdata = (struct ocp_func_emac_data *)ocpdev->def->additions;
1887 if (emacdata == NULL) {
1888 printk(KERN_ERR "emac%d: Missing additional datas !\n",
1889 ocpdev->def->index);
1893 /* Get the MAL device */
1894 maldev = ocp_find_device(OCP_ANY_ID, OCP_FUNC_MAL, emacdata->mal_idx);
1895 if (maldev == NULL) {
1896 printk("No maldev\n");
1900 * Get MAL driver data, it must be here due to link order.
1901 * When the driver is modularized, symbol dependencies will
1902 * ensure the MAL driver is already present if built as a
1905 mal = (struct ibm_ocp_mal *)ocp_get_drvdata(maldev);
1907 printk("No maldrv\n");
1911 /* If we depend on another EMAC for MDIO, wait for it to show up */
1912 if (emacdata->mdio_idx >= 0 &&
1913 (emacdata->mdio_idx != ocpdev->def->index) && !mdio_ndev) {
1914 struct emac_def_dev *ddev;
1915 /* Add this index to the deferred init table */
1916 ddev = kmalloc(sizeof(struct emac_def_dev), GFP_KERNEL);
1917 ddev->ocpdev = ocpdev;
1919 list_add_tail(&ddev->link, &emac_init_list);
1921 emac_init_device(ocpdev, mal);
1927 /* Structure for a device driver */
1928 static struct ocp_device_id emac_ids[] = {
1929 {.vendor = OCP_ANY_ID,.function = OCP_FUNC_EMAC},
1930 {.vendor = OCP_VENDOR_INVALID}
1933 static struct ocp_driver emac_driver = {
1935 .id_table = emac_ids,
1937 .probe = emac_probe,
1938 .remove = emac_remove,
1941 static int __init emac_init(void)
1945 printk(KERN_INFO DRV_NAME ": " DRV_DESC ", version " DRV_VERSION "\n");
1946 printk(KERN_INFO "Maintained by " DRV_AUTHOR "\n");
1949 printk(KERN_WARNING "Invalid skb_res: %d, cropping to 2\n",
1953 rc = ocp_register_driver(&emac_driver);
1955 ocp_unregister_driver(&emac_driver);
1962 static void __exit emac_exit(void)
1964 ocp_unregister_driver(&emac_driver);
1967 module_init(emac_init);
1968 module_exit(emac_exit);