4 * Ethernet driver for the built in ethernet on the IBM 4xx PowerPC
7 * (c) 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
9 * Based on original work by
11 * Armin Kuster <akuster@mvista.com>
12 * Johnnie Peters <jpeters@mvista.com>
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
19 * - Check for races in the "remove" code path
20 * - Add some Power Management to the MAC and the PHY
21 * - Audit remaining of non-rewritten code (--BenH)
22 * - Cleanup message display using msglevel mecanism
23 * - Address all errata
24 * - Audit all register update paths to ensure they
25 * are being written post soft reset if required.
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/sched.h>
30 #include <linux/string.h>
31 #include <linux/timer.h>
32 #include <linux/ptrace.h>
33 #include <linux/errno.h>
34 #include <linux/ioport.h>
35 #include <linux/slab.h>
36 #include <linux/interrupt.h>
37 #include <linux/delay.h>
38 #include <linux/init.h>
39 #include <linux/types.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
44 #include <asm/processor.h>
45 #include <asm/bitops.h>
49 #include <asm/uaccess.h>
52 #include <linux/netdevice.h>
53 #include <linux/etherdevice.h>
54 #include <linux/skbuff.h>
55 #include <linux/crc32.h>
57 #include "ibm_emac_core.h"
59 //#define MDIO_DEBUG(fmt) printk fmt
60 #define MDIO_DEBUG(fmt)
62 //#define LINK_DEBUG(fmt) printk fmt
63 #define LINK_DEBUG(fmt)
65 //#define PKT_DEBUG(fmt) printk fmt
66 #define PKT_DEBUG(fmt)
68 #define DRV_NAME "emac"
69 #define DRV_VERSION "2.0"
70 #define DRV_AUTHOR "Benjamin Herrenschmidt <benh@kernel.crashing.org>"
71 #define DRV_DESC "IBM EMAC Ethernet driver"
74 * When mdio_idx >= 0, contains a list of emac ocp_devs
75 * that have had their initialization deferred until the
76 * common MDIO controller has been initialized.
78 LIST_HEAD(emac_init_list);
80 MODULE_AUTHOR(DRV_AUTHOR);
81 MODULE_DESCRIPTION(DRV_DESC);
82 MODULE_LICENSE("GPL");
84 static int skb_res = SKB_RES;
85 module_param(skb_res, int, 0444);
86 MODULE_PARM_DESC(skb_res, "Amount of data to reserve on skb buffs\n"
87 "The 405 handles a misaligned IP header fine but\n"
88 "this can help if you are routing to a tunnel or a\n"
89 "device that needs aligned data. 0..2");
91 #define RGMII_PRIV(ocpdev) ((struct ibm_ocp_rgmii*)ocp_get_drvdata(ocpdev))
93 static unsigned int rgmii_enable[] = {
100 static unsigned int rgmii_speed_mask[] = {
105 static unsigned int rgmii_speed100[] = {
110 static unsigned int rgmii_speed1000[] = {
115 #define ZMII_PRIV(ocpdev) ((struct ibm_ocp_zmii*)ocp_get_drvdata(ocpdev))
117 static unsigned int zmii_enable[][4] = {
118 {ZMII_SMII0, ZMII_RMII0, ZMII_MII0,
119 ~(ZMII_MDI1 | ZMII_MDI2 | ZMII_MDI3)},
120 {ZMII_SMII1, ZMII_RMII1, ZMII_MII1,
121 ~(ZMII_MDI0 | ZMII_MDI2 | ZMII_MDI3)},
122 {ZMII_SMII2, ZMII_RMII2, ZMII_MII2,
123 ~(ZMII_MDI0 | ZMII_MDI1 | ZMII_MDI3)},
124 {ZMII_SMII3, ZMII_RMII3, ZMII_MII3, ~(ZMII_MDI0 | ZMII_MDI1 | ZMII_MDI2)}
127 static unsigned int mdi_enable[] = {
134 static unsigned int zmii_speed = 0x0;
135 static unsigned int zmii_speed100[] = {
142 /* Since multiple EMACs share MDIO lines in various ways, we need
143 * to avoid re-using the same PHY ID in cases where the arch didn't
144 * setup precise phy_map entries
146 static u32 busy_phy_map = 0;
148 /* If EMACs share a common MDIO device, this points to it */
149 static struct net_device *mdio_ndev = NULL;
151 struct emac_def_dev {
152 struct list_head link;
153 struct ocp_device *ocpdev;
154 struct ibm_ocp_mal *mal;
157 static struct net_device_stats *emac_stats(struct net_device *dev)
159 struct ocp_enet_private *fep = dev->priv;
164 emac_init_rgmii(struct ocp_device *rgmii_dev, int input, int phy_mode)
166 struct ibm_ocp_rgmii *rgmii = RGMII_PRIV(rgmii_dev);
167 const char *mode_name[] = { "RTBI", "RGMII", "TBI", "GMII" };
171 rgmii = kmalloc(sizeof(struct ibm_ocp_rgmii), GFP_KERNEL);
175 "rgmii%d: Out of memory allocating RGMII structure!\n",
176 rgmii_dev->def->index);
180 memset(rgmii, 0, sizeof(*rgmii));
183 (struct rgmii_regs *)ioremap(rgmii_dev->def->paddr,
184 sizeof(*rgmii->base));
185 if (rgmii->base == NULL) {
187 "rgmii%d: Cannot ioremap bridge registers!\n",
188 rgmii_dev->def->index);
193 ocp_set_drvdata(rgmii_dev, rgmii);
211 rgmii->base->fer &= ~RGMII_FER_MASK(input);
212 rgmii->base->fer |= rgmii_enable[mode] << (4 * input);
214 switch ((rgmii->base->fer & RGMII_FER_MASK(input)) >> (4 *
230 /* Set mode to RGMII if nothing valid is detected */
234 printk(KERN_NOTICE "rgmii%d: input %d in %s mode\n",
235 rgmii_dev->def->index, input, mode_name[mode]);
237 rgmii->mode[input] = mode;
244 emac_rgmii_port_speed(struct ocp_device *ocpdev, int input, int speed)
246 struct ibm_ocp_rgmii *rgmii = RGMII_PRIV(ocpdev);
247 unsigned int rgmii_speed;
249 rgmii_speed = in_be32(&rgmii->base->ssr);
251 rgmii_speed &= ~rgmii_speed_mask[input];
254 rgmii_speed |= rgmii_speed1000[input];
255 else if (speed == 100)
256 rgmii_speed |= rgmii_speed100[input];
258 out_be32(&rgmii->base->ssr, rgmii_speed);
261 static void emac_close_rgmii(struct ocp_device *ocpdev)
263 struct ibm_ocp_rgmii *rgmii = RGMII_PRIV(ocpdev);
264 BUG_ON(!rgmii || rgmii->users == 0);
266 if (!--rgmii->users) {
267 ocp_set_drvdata(ocpdev, NULL);
268 iounmap((void *)rgmii->base);
273 static int emac_init_zmii(struct ocp_device *zmii_dev, int input, int phy_mode)
275 struct ibm_ocp_zmii *zmii = ZMII_PRIV(zmii_dev);
276 const char *mode_name[] = { "SMII", "RMII", "MII" };
280 zmii = kmalloc(sizeof(struct ibm_ocp_zmii), GFP_KERNEL);
283 "zmii%d: Out of memory allocating ZMII structure!\n",
284 zmii_dev->def->index);
287 memset(zmii, 0, sizeof(*zmii));
290 (struct zmii_regs *)ioremap(zmii_dev->def->paddr,
291 sizeof(*zmii->base));
292 if (zmii->base == NULL) {
294 "zmii%d: Cannot ioremap bridge registers!\n",
295 zmii_dev->def->index);
300 ocp_set_drvdata(zmii_dev, zmii);
315 zmii->base->fer &= ~ZMII_FER_MASK(input);
316 zmii->base->fer |= zmii_enable[input][mode];
318 switch ((zmii->base->fer & ZMII_FER_MASK(input)) << (4 * input)) {
330 /* Set mode to SMII if nothing valid is detected */
334 printk(KERN_NOTICE "zmii%d: input %d in %s mode\n",
335 zmii_dev->def->index, input, mode_name[mode]);
337 zmii->mode[input] = mode;
343 static void emac_enable_zmii_port(struct ocp_device *ocpdev, int input)
346 struct ibm_ocp_zmii *zmii = ZMII_PRIV(ocpdev);
348 mask = in_be32(&zmii->base->fer);
349 mask &= zmii_enable[input][MDI]; /* turn all non enabled MDI's off */
350 mask |= zmii_enable[input][zmii->mode[input]] | mdi_enable[input];
351 out_be32(&zmii->base->fer, mask);
355 emac_zmii_port_speed(struct ocp_device *ocpdev, int input, int speed)
357 struct ibm_ocp_zmii *zmii = ZMII_PRIV(ocpdev);
360 zmii_speed |= zmii_speed100[input];
362 zmii_speed &= ~zmii_speed100[input];
364 out_be32(&zmii->base->ssr, zmii_speed);
367 static void emac_close_zmii(struct ocp_device *ocpdev)
369 struct ibm_ocp_zmii *zmii = ZMII_PRIV(ocpdev);
370 BUG_ON(!zmii || zmii->users == 0);
372 if (!--zmii->users) {
373 ocp_set_drvdata(ocpdev, NULL);
374 iounmap((void *)zmii->base);
379 int emac_phy_read(struct net_device *dev, int mii_id, int reg)
383 struct ocp_enet_private *fep = dev->priv;
384 emac_t *emacp = fep->emacp;
386 MDIO_DEBUG(("%s: phy_read, id: 0x%x, reg: 0x%x\n", dev->name, mii_id,
389 /* Enable proper ZMII port */
391 emac_enable_zmii_port(fep->zmii_dev, fep->zmii_input);
393 /* Use the EMAC that has the MDIO port */
401 while ((((stacr = in_be32(&emacp->em0stacr)) & EMAC_STACR_OC) == 0)
402 && (count++ < MDIO_DELAY))
404 MDIO_DEBUG((" (count was %d)\n", count));
406 if ((stacr & EMAC_STACR_OC) == 0) {
407 printk(KERN_WARNING "%s: PHY read timeout #1!\n", dev->name);
411 /* Clear the speed bits and make a read request to the PHY */
412 stacr = ((EMAC_STACR_READ | (reg & 0x1f)) & ~EMAC_STACR_CLK_100MHZ);
413 stacr |= ((mii_id & 0x1F) << 5);
415 out_be32(&emacp->em0stacr, stacr);
418 while ((((stacr = in_be32(&emacp->em0stacr)) & EMAC_STACR_OC) == 0)
419 && (count++ < MDIO_DELAY))
421 MDIO_DEBUG((" (count was %d)\n", count));
423 if ((stacr & EMAC_STACR_OC) == 0) {
424 printk(KERN_WARNING "%s: PHY read timeout #2!\n", dev->name);
428 /* Check for a read error */
429 if (stacr & EMAC_STACR_PHYE) {
430 MDIO_DEBUG(("EMAC MDIO PHY error !\n"));
434 MDIO_DEBUG((" -> 0x%x\n", stacr >> 16));
436 return (stacr >> 16);
439 void emac_phy_write(struct net_device *dev, int mii_id, int reg, int data)
443 struct ocp_enet_private *fep = dev->priv;
444 emac_t *emacp = fep->emacp;
446 MDIO_DEBUG(("%s phy_write, id: 0x%x, reg: 0x%x, data: 0x%x\n",
447 dev->name, mii_id, reg, data));
449 /* Enable proper ZMII port */
451 emac_enable_zmii_port(fep->zmii_dev, fep->zmii_input);
453 /* Use the EMAC that has the MDIO port */
461 while ((((stacr = in_be32(&emacp->em0stacr)) & EMAC_STACR_OC) == 0)
462 && (count++ < MDIO_DELAY))
464 MDIO_DEBUG((" (count was %d)\n", count));
466 if ((stacr & EMAC_STACR_OC) == 0) {
467 printk(KERN_WARNING "%s: PHY write timeout #2!\n", dev->name);
471 /* Clear the speed bits and make a read request to the PHY */
473 stacr = ((EMAC_STACR_WRITE | (reg & 0x1f)) & ~EMAC_STACR_CLK_100MHZ);
474 stacr |= ((mii_id & 0x1f) << 5) | ((data & 0xffff) << 16);
476 out_be32(&emacp->em0stacr, stacr);
478 while (((stacr = in_be32(&emacp->em0stacr) & EMAC_STACR_OC) == 0)
481 MDIO_DEBUG((" (count was %d)\n", count));
483 if ((stacr & EMAC_STACR_OC) == 0)
484 printk(KERN_WARNING "%s: PHY write timeout #2!\n", dev->name);
486 /* Check for a write error */
487 if ((stacr & EMAC_STACR_PHYE) != 0) {
488 MDIO_DEBUG(("EMAC MDIO PHY error !\n"));
492 static void emac_txeob_dev(void *param, u32 chanmask)
494 struct net_device *dev = param;
495 struct ocp_enet_private *fep = dev->priv;
498 spin_lock_irqsave(&fep->lock, flags);
500 PKT_DEBUG(("emac_txeob_dev() entry, tx_cnt: %d\n", fep->tx_cnt));
502 while (fep->tx_cnt &&
503 !(fep->tx_desc[fep->ack_slot].ctrl & MAL_TX_CTRL_READY)) {
505 if (fep->tx_desc[fep->ack_slot].ctrl & MAL_TX_CTRL_LAST) {
506 /* Tell the system the transmit completed. */
507 dma_unmap_single(&fep->ocpdev->dev,
508 fep->tx_desc[fep->ack_slot].data_ptr,
509 fep->tx_desc[fep->ack_slot].data_len,
511 dev_kfree_skb_irq(fep->tx_skb[fep->ack_slot]);
513 if (fep->tx_desc[fep->ack_slot].ctrl &
514 (EMAC_TX_ST_EC | EMAC_TX_ST_MC | EMAC_TX_ST_SC))
515 fep->stats.collisions++;
518 fep->tx_skb[fep->ack_slot] = (struct sk_buff *)NULL;
519 if (++fep->ack_slot == NUM_TX_BUFF)
524 if (fep->tx_cnt < NUM_TX_BUFF)
525 netif_wake_queue(dev);
527 PKT_DEBUG(("emac_txeob_dev() exit, tx_cnt: %d\n", fep->tx_cnt));
529 spin_unlock_irqrestore(&fep->lock, flags);
533 Fill/Re-fill the rx chain with valid ctrl/ptrs.
534 This function will fill from rx_slot up to the parm end.
535 So to completely fill the chain pre-set rx_slot to 0 and
538 static void emac_rx_fill(struct net_device *dev, int end)
541 struct ocp_enet_private *fep = dev->priv;
545 /* We don't want the 16 bytes skb_reserve done by dev_alloc_skb,
546 * it breaks our cache line alignement. However, we still allocate
547 * +16 so that we end up allocating the exact same size as
548 * dev_alloc_skb() would do.
549 * Also, because of the skb_res, the max DMA size we give to EMAC
550 * is slighly wrong, causing it to potentially DMA 2 more bytes
551 * from a broken/oversized packet. These 16 bytes will take care
552 * that we don't walk on somebody else toes with that.
555 alloc_skb(fep->rx_buffer_size + 16, GFP_ATOMIC);
557 if (fep->rx_skb[i] == NULL) {
558 /* Keep rx_slot here, the next time clean/fill is called
559 * we will try again before the MAL wraps back here
560 * If the MAL tries to use this descriptor with
561 * the EMPTY bit off it will cause the
562 * rxde interrupt. That is where we will
563 * try again to allocate an sk_buff.
570 skb_reserve(fep->rx_skb[i], skb_res);
572 /* We must NOT dma_map_single the cache line right after the
573 * buffer, so we must crop our sync size to account for the
576 fep->rx_desc[i].data_ptr =
577 (unsigned char *)dma_map_single(&fep->ocpdev->dev,
578 (void *)fep->rx_skb[i]->
580 fep->rx_buffer_size -
581 skb_res, DMA_FROM_DEVICE);
584 * Some 4xx implementations use the previously
585 * reserved bits in data_len to encode the MS
586 * 4-bits of a 36-bit physical address (ERPN)
587 * This must be initialized.
589 fep->rx_desc[i].data_len = 0;
590 fep->rx_desc[i].ctrl = MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR |
591 (i == (NUM_RX_BUFF - 1) ? MAL_RX_CTRL_WRAP : 0);
593 } while ((i = (i + 1) % NUM_RX_BUFF) != end);
599 emac_rx_csum(struct net_device *dev, unsigned short ctrl, struct sk_buff *skb)
601 struct ocp_enet_private *fep = dev->priv;
603 /* Exit if interface has no TAH engine */
605 skb->ip_summed = CHECKSUM_NONE;
609 /* Check for TCP/UDP/IP csum error */
610 if (ctrl & EMAC_CSUM_VER_ERROR) {
611 /* Let the stack verify checksum errors */
612 skb->ip_summed = CHECKSUM_NONE;
613 /* adapter->hw_csum_err++; */
616 skb->ip_summed = CHECKSUM_UNNECESSARY;
617 /* adapter->hw_csum_good++; */
621 static int emac_rx_clean(struct net_device *dev)
623 int i, b, bnum, buf[6];
624 int error, frame_length;
625 struct ocp_enet_private *fep = dev->priv;
630 PKT_DEBUG(("emac_rx_clean() entry, rx_slot: %d\n", fep->rx_slot));
633 if (fep->rx_skb[i] == NULL)
634 continue; /*we have already handled the packet but haved failed to alloc */
636 since rx_desc is in uncached mem we don't keep reading it directly
637 we pull out a local copy of ctrl and do the checks on the copy.
639 ctrl = fep->rx_desc[i].ctrl;
640 if (ctrl & MAL_RX_CTRL_EMPTY)
641 break; /*we don't have any more ready packets */
643 if (EMAC_IS_BAD_RX_PACKET(ctrl)) {
644 fep->stats.rx_errors++;
645 fep->stats.rx_dropped++;
647 if (ctrl & EMAC_RX_ST_OE)
648 fep->stats.rx_fifo_errors++;
649 if (ctrl & EMAC_RX_ST_AE)
650 fep->stats.rx_frame_errors++;
651 if (ctrl & EMAC_RX_ST_BFCS)
652 fep->stats.rx_crc_errors++;
653 if (ctrl & (EMAC_RX_ST_RP | EMAC_RX_ST_PTL |
654 EMAC_RX_ST_ORE | EMAC_RX_ST_IRE))
655 fep->stats.rx_length_errors++;
657 if ((ctrl & (MAL_RX_CTRL_FIRST | MAL_RX_CTRL_LAST)) ==
658 (MAL_RX_CTRL_FIRST | MAL_RX_CTRL_LAST)) {
659 /* Single descriptor packet */
660 emac_rx_csum(dev, ctrl, fep->rx_skb[i]);
661 /* Send the skb up the chain. */
662 frame_length = fep->rx_desc[i].data_len - 4;
663 skb_put(fep->rx_skb[i], frame_length);
664 fep->rx_skb[i]->dev = dev;
665 fep->rx_skb[i]->protocol =
666 eth_type_trans(fep->rx_skb[i], dev);
667 error = netif_rx(fep->rx_skb[i]);
669 if ((error == NET_RX_DROP) ||
670 (error == NET_RX_BAD)) {
671 fep->stats.rx_dropped++;
673 fep->stats.rx_packets++;
674 fep->stats.rx_bytes += frame_length;
676 fep->rx_skb[i] = NULL;
678 /* Multiple descriptor packet */
679 if (ctrl & MAL_RX_CTRL_FIRST) {
680 if (fep->rx_desc[(i + 1) % NUM_RX_BUFF].
681 ctrl & MAL_RX_CTRL_EMPTY)
688 if (((ctrl & MAL_RX_CTRL_FIRST) !=
689 MAL_RX_CTRL_FIRST) &&
690 ((ctrl & MAL_RX_CTRL_LAST) !=
692 if (fep->rx_desc[(i + 1) %
702 if (ctrl & MAL_RX_CTRL_LAST) {
705 skb_put(fep->rx_skb[buf[0]],
706 fep->rx_desc[buf[0]].data_len);
707 for (b = 1; b < bnum; b++) {
709 * MAL is braindead, we need
710 * to copy the remainder
711 * of the packet from the
712 * latter descriptor buffers
713 * to the first skb. Then
714 * dispose of the source
717 * Once the stack is fixed
718 * to handle frags on most
719 * protocols we can generate
720 * a fragmented skb with
723 memcpy(fep->rx_skb[buf[0]]->
725 fep->rx_skb[buf[0]]->len,
726 fep->rx_skb[buf[b]]->
728 fep->rx_desc[buf[b]].
730 skb_put(fep->rx_skb[buf[0]],
731 fep->rx_desc[buf[b]].
733 dma_unmap_single(&fep->ocpdev->
747 emac_rx_csum(dev, ctrl,
748 fep->rx_skb[buf[0]]);
750 fep->rx_skb[buf[0]]->dev = dev;
751 fep->rx_skb[buf[0]]->protocol =
752 eth_type_trans(fep->rx_skb[buf[0]],
754 error = netif_rx(fep->rx_skb[buf[0]]);
756 if ((error == NET_RX_DROP)
757 || (error == NET_RX_BAD)) {
758 fep->stats.rx_dropped++;
760 fep->stats.rx_packets++;
761 fep->stats.rx_bytes +=
762 fep->rx_skb[buf[0]]->len;
764 for (b = 0; b < bnum; b++)
765 fep->rx_skb[buf[b]] = NULL;
769 } while ((i = (i + 1) % NUM_RX_BUFF) != fep->rx_slot);
771 PKT_DEBUG(("emac_rx_clean() exit, rx_slot: %d\n", fep->rx_slot));
776 static void emac_rxeob_dev(void *param, u32 chanmask)
778 struct net_device *dev = param;
779 struct ocp_enet_private *fep = dev->priv;
783 spin_lock_irqsave(&fep->lock, flags);
784 if ((n = emac_rx_clean(dev)) != fep->rx_slot)
785 emac_rx_fill(dev, n);
786 spin_unlock_irqrestore(&fep->lock, flags);
790 * This interrupt should never occurr, we don't program
791 * the MAL for contiunous mode.
793 static void emac_txde_dev(void *param, u32 chanmask)
795 struct net_device *dev = param;
796 struct ocp_enet_private *fep = dev->priv;
798 printk(KERN_WARNING "%s: transmit descriptor error\n", dev->name);
803 /* Reenable the transmit channel */
804 mal_enable_tx_channels(fep->mal, fep->commac.tx_chan_mask);
808 * This interrupt should be very rare at best. This occurs when
809 * the hardware has a problem with the receive descriptors. The manual
810 * states that it occurs when the hardware cannot the receive descriptor
811 * empty bit is not set. The recovery mechanism will be to
812 * traverse through the descriptors, handle any that are marked to be
813 * handled and reinitialize each along the way. At that point the driver
816 static void emac_rxde_dev(void *param, u32 chanmask)
818 struct net_device *dev = param;
819 struct ocp_enet_private *fep = dev->priv;
822 if (net_ratelimit()) {
823 printk(KERN_WARNING "%s: receive descriptor error\n",
831 /* Disable RX channel */
832 spin_lock_irqsave(&fep->lock, flags);
833 mal_disable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
835 /* For now, charge the error against all emacs */
836 fep->stats.rx_errors++;
838 /* so do we have any good packets still? */
841 /* When the interface is restarted it resets processing to the
842 * first descriptor in the table.
846 emac_rx_fill(dev, 0);
848 set_mal_dcrn(fep->mal, DCRN_MALRXEOBISR, fep->commac.rx_chan_mask);
849 set_mal_dcrn(fep->mal, DCRN_MALRXDEIR, fep->commac.rx_chan_mask);
851 /* Reenable the receive channels */
852 mal_enable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
853 spin_unlock_irqrestore(&fep->lock, flags);
857 emac_mac_irq(int irq, void *dev_instance, struct pt_regs *regs)
859 struct net_device *dev = dev_instance;
860 struct ocp_enet_private *fep = dev->priv;
861 emac_t *emacp = fep->emacp;
862 unsigned long tmp_em0isr;
865 tmp_em0isr = in_be32(&emacp->em0isr);
866 if (tmp_em0isr & (EMAC_ISR_TE0 | EMAC_ISR_TE1)) {
867 /* This error is a hard transmit error - could retransmit */
868 fep->stats.tx_errors++;
870 /* Reenable the transmit channel */
871 mal_enable_tx_channels(fep->mal, fep->commac.tx_chan_mask);
874 fep->stats.rx_errors++;
877 if (tmp_em0isr & EMAC_ISR_RP)
878 fep->stats.rx_length_errors++;
879 if (tmp_em0isr & EMAC_ISR_ALE)
880 fep->stats.rx_frame_errors++;
881 if (tmp_em0isr & EMAC_ISR_BFCS)
882 fep->stats.rx_crc_errors++;
883 if (tmp_em0isr & EMAC_ISR_PTLE)
884 fep->stats.rx_length_errors++;
885 if (tmp_em0isr & EMAC_ISR_ORE)
886 fep->stats.rx_length_errors++;
887 if (tmp_em0isr & EMAC_ISR_TE0)
888 fep->stats.tx_aborted_errors++;
890 emac_err_dump(dev, tmp_em0isr);
892 out_be32(&emacp->em0isr, tmp_em0isr);
897 static int emac_start_xmit(struct sk_buff *skb, struct net_device *dev)
901 struct ocp_enet_private *fep = dev->priv;
902 emac_t *emacp = fep->emacp;
904 unsigned int offset = 0, size, f, tx_slot_first;
905 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
907 spin_lock_irqsave(&fep->lock, flags);
909 len -= skb->data_len;
911 if ((fep->tx_cnt + nr_frags + len / DESC_BUF_SIZE + 1) > NUM_TX_BUFF) {
912 PKT_DEBUG(("emac_start_xmit() stopping queue\n"));
913 netif_stop_queue(dev);
914 spin_unlock_irqrestore(&fep->lock, flags);
915 restore_flags(flags);
919 tx_slot_first = fep->tx_slot;
922 size = min(len, DESC_BUF_SIZE);
924 fep->tx_desc[fep->tx_slot].data_len = (short)size;
925 fep->tx_desc[fep->tx_slot].data_ptr =
926 (unsigned char *)dma_map_single(&fep->ocpdev->dev,
927 (void *)((unsigned int)skb->
929 size, DMA_TO_DEVICE);
931 ctrl = EMAC_TX_CTRL_DFLT;
932 if (fep->tx_slot != tx_slot_first)
933 ctrl |= MAL_TX_CTRL_READY;
934 if ((NUM_TX_BUFF - 1) == fep->tx_slot)
935 ctrl |= MAL_TX_CTRL_WRAP;
936 if (!nr_frags && (len == size)) {
937 ctrl |= MAL_TX_CTRL_LAST;
938 fep->tx_skb[fep->tx_slot] = skb;
940 if (skb->ip_summed == CHECKSUM_HW)
941 ctrl |= EMAC_TX_CTRL_TAH_CSUM;
943 fep->tx_desc[fep->tx_slot].ctrl = ctrl;
949 if (++fep->tx_cnt == NUM_TX_BUFF)
950 netif_stop_queue(dev);
952 /* Next descriptor */
953 if (++fep->tx_slot == NUM_TX_BUFF)
957 for (f = 0; f < nr_frags; f++) {
958 struct skb_frag_struct *frag;
960 frag = &skb_shinfo(skb)->frags[f];
965 size = min(len, DESC_BUF_SIZE);
967 dma_map_page(&fep->ocpdev->dev,
969 frag->page_offset + offset,
970 size, DMA_TO_DEVICE);
972 ctrl = EMAC_TX_CTRL_DFLT | MAL_TX_CTRL_READY;
973 if ((NUM_TX_BUFF - 1) == fep->tx_slot)
974 ctrl |= MAL_TX_CTRL_WRAP;
975 if ((f == (nr_frags - 1)) && (len == size)) {
976 ctrl |= MAL_TX_CTRL_LAST;
977 fep->tx_skb[fep->tx_slot] = skb;
980 if (skb->ip_summed == CHECKSUM_HW)
981 ctrl |= EMAC_TX_CTRL_TAH_CSUM;
983 fep->tx_desc[fep->tx_slot].data_len = (short)size;
984 fep->tx_desc[fep->tx_slot].data_ptr =
985 (char *)((page_to_pfn(frag->page) << PAGE_SHIFT) +
986 frag->page_offset + offset);
987 fep->tx_desc[fep->tx_slot].ctrl = ctrl;
993 if (++fep->tx_cnt == NUM_TX_BUFF)
994 netif_stop_queue(dev);
996 /* Next descriptor */
997 if (++fep->tx_slot == NUM_TX_BUFF)
1003 * Deferred set READY on first descriptor of packet to
1004 * avoid TX MAL race.
1006 fep->tx_desc[tx_slot_first].ctrl |= MAL_TX_CTRL_READY;
1008 /* Send the packet out. */
1009 out_be32(&emacp->em0tmr0, EMAC_TMR0_XMIT);
1011 fep->stats.tx_packets++;
1012 fep->stats.tx_bytes += skb->len;
1014 PKT_DEBUG(("emac_start_xmit() exitn"));
1016 spin_unlock_irqrestore(&fep->lock, flags);
1021 static int emac_adjust_to_link(struct ocp_enet_private *fep)
1023 emac_t *emacp = fep->emacp;
1024 struct ibm_ocp_rgmii *rgmii;
1025 unsigned long mode_reg;
1026 int full_duplex, speed;
1031 /* set mode register 1 defaults */
1032 mode_reg = EMAC_M1_DEFAULT;
1034 /* Read link mode on PHY */
1035 if (fep->phy_mii.def->ops->read_link(&fep->phy_mii) == 0) {
1036 /* If an error occurred, we don't deal with it yet */
1037 full_duplex = (fep->phy_mii.duplex == DUPLEX_FULL);
1038 speed = fep->phy_mii.speed;
1042 rgmii = RGMII_PRIV(fep->rgmii_dev);
1044 /* set speed (default is 10Mb) */
1047 mode_reg |= EMAC_M1_JUMBO_ENABLE | EMAC_M1_RFS_16K;
1048 if ((rgmii->mode[fep->rgmii_input] == RTBI)
1049 || (rgmii->mode[fep->rgmii_input] == TBI))
1050 mode_reg |= EMAC_M1_MF_1000GPCS;
1052 mode_reg |= EMAC_M1_MF_1000MBPS;
1054 emac_rgmii_port_speed(fep->rgmii_dev, fep->rgmii_input,
1058 mode_reg |= EMAC_M1_MF_100MBPS | EMAC_M1_RFS_4K;
1060 emac_rgmii_port_speed(fep->rgmii_dev, fep->rgmii_input,
1063 emac_zmii_port_speed(fep->zmii_dev, fep->zmii_input,
1068 mode_reg = (mode_reg & ~EMAC_M1_MF_100MBPS) | EMAC_M1_RFS_4K;
1070 emac_rgmii_port_speed(fep->rgmii_dev, fep->rgmii_input,
1073 emac_zmii_port_speed(fep->zmii_dev, fep->zmii_input,
1078 mode_reg |= EMAC_M1_FDE | EMAC_M1_EIFC | EMAC_M1_IST;
1080 mode_reg &= ~(EMAC_M1_FDE | EMAC_M1_EIFC | EMAC_M1_ILE);
1082 LINK_DEBUG(("%s: adjust to link, speed: %d, duplex: %d, opened: %d\n",
1083 fep->ndev->name, speed, full_duplex, fep->opened));
1085 printk(KERN_INFO "%s: Speed: %d, %s duplex.\n",
1086 fep->ndev->name, speed, full_duplex ? "Full" : "Half");
1088 out_be32(&emacp->em0mr1, mode_reg);
1093 static int emac_set_mac_address(struct net_device *ndev, void *p)
1095 struct ocp_enet_private *fep = ndev->priv;
1096 emac_t *emacp = fep->emacp;
1097 struct sockaddr *addr = p;
1099 if (!is_valid_ether_addr(addr->sa_data))
1100 return -EADDRNOTAVAIL;
1102 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1104 /* set the high address */
1105 out_be32(&emacp->em0iahr,
1106 (fep->ndev->dev_addr[0] << 8) | fep->ndev->dev_addr[1]);
1108 /* set the low address */
1109 out_be32(&emacp->em0ialr,
1110 (fep->ndev->dev_addr[2] << 24) | (fep->ndev->dev_addr[3] << 16)
1111 | (fep->ndev->dev_addr[4] << 8) | fep->ndev->dev_addr[5]);
1116 static int emac_change_mtu(struct net_device *dev, int new_mtu)
1118 struct ocp_enet_private *fep = dev->priv;
1119 int old_mtu = dev->mtu;
1120 emac_t *emacp = fep->emacp;
1123 unsigned long flags;
1125 if ((new_mtu < EMAC_MIN_MTU) || (new_mtu > EMAC_MAX_MTU)) {
1127 "emac: Invalid MTU setting, MTU must be between %d and %d\n",
1128 EMAC_MIN_MTU, EMAC_MAX_MTU);
1132 if (old_mtu != new_mtu && netif_running(dev)) {
1133 /* Stop rx engine */
1134 em0mr0 = in_be32(&emacp->em0mr0);
1135 out_be32(&emacp->em0mr0, em0mr0 & ~EMAC_M0_RXE);
1137 /* Wait for descriptors to be empty */
1140 for (i = 0; i < NUM_RX_BUFF; i++)
1141 if (!(fep->rx_desc[i].ctrl & MAL_RX_CTRL_EMPTY)) {
1143 "emac: RX ring is still full\n");
1148 spin_lock_irqsave(&fep->lock, flags);
1150 mal_disable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
1152 /* Destroy all old rx skbs */
1153 for (i = 0; i < NUM_RX_BUFF; i++) {
1154 dma_unmap_single(&fep->ocpdev->dev,
1155 fep->rx_desc[i].data_ptr,
1156 fep->rx_desc[i].data_len,
1158 dev_kfree_skb(fep->rx_skb[i]);
1159 fep->rx_skb[i] = NULL;
1162 /* Set new rx_buffer_size and advertise new mtu */
1163 fep->rx_buffer_size =
1164 new_mtu + ENET_HEADER_SIZE + ENET_FCS_SIZE;
1167 /* Re-init rx skbs */
1169 emac_rx_fill(dev, 0);
1171 /* Restart the rx engine */
1172 mal_enable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
1173 out_be32(&emacp->em0mr0, em0mr0 | EMAC_M0_RXE);
1175 spin_unlock_irqrestore(&fep->lock, flags);
1181 static void __emac_set_multicast_list(struct net_device *dev)
1183 struct ocp_enet_private *fep = dev->priv;
1184 emac_t *emacp = fep->emacp;
1185 u32 rmr = in_be32(&emacp->em0rmr);
1187 /* First clear all special bits, they can be set later */
1188 rmr &= ~(EMAC_RMR_PME | EMAC_RMR_PMME | EMAC_RMR_MAE);
1190 if (dev->flags & IFF_PROMISC) {
1191 rmr |= EMAC_RMR_PME;
1192 } else if (dev->flags & IFF_ALLMULTI || 32 < dev->mc_count) {
1194 * Must be setting up to use multicast
1195 * Now check for promiscuous multicast
1197 rmr |= EMAC_RMR_PMME;
1198 } else if (dev->flags & IFF_MULTICAST && 0 < dev->mc_count) {
1199 unsigned short em0gaht[4] = { 0, 0, 0, 0 };
1200 struct dev_mc_list *dmi;
1202 /* Need to hash on the multicast address. */
1203 for (dmi = dev->mc_list; dmi; dmi = dmi->next) {
1204 unsigned long mc_crc;
1205 unsigned int bit_number;
1207 mc_crc = ether_crc(6, (char *)dmi->dmi_addr);
1208 bit_number = 63 - (mc_crc >> 26); /* MSB: 0 LSB: 63 */
1209 em0gaht[bit_number >> 4] |=
1210 0x8000 >> (bit_number & 0x0f);
1212 emacp->em0gaht1 = em0gaht[0];
1213 emacp->em0gaht2 = em0gaht[1];
1214 emacp->em0gaht3 = em0gaht[2];
1215 emacp->em0gaht4 = em0gaht[3];
1217 /* Turn on multicast addressing */
1218 rmr |= EMAC_RMR_MAE;
1220 out_be32(&emacp->em0rmr, rmr);
1223 static int emac_init_tah(struct ocp_enet_private *fep)
1227 /* Initialize TAH and enable checksum verification */
1228 tahp = (tah_t *) ioremap(fep->tah_dev->def->paddr, sizeof(*tahp));
1231 printk(KERN_ERR "tah%d: Cannot ioremap TAH registers!\n",
1232 fep->tah_dev->def->index);
1237 out_be32(&tahp->tah_mr, TAH_MR_SR);
1239 /* wait for reset to complete */
1240 while (in_be32(&tahp->tah_mr) & TAH_MR_SR) ;
1242 /* 10KB TAH TX FIFO accomodates the max MTU of 9000 */
1243 out_be32(&tahp->tah_mr,
1244 TAH_MR_CVR | TAH_MR_ST_768 | TAH_MR_TFS_10KB | TAH_MR_DTFP |
1252 static void emac_init_rings(struct net_device *dev)
1254 struct ocp_enet_private *ep = dev->priv;
1257 ep->tx_desc = (struct mal_descriptor *)((char *)ep->mal->tx_virt_addr +
1261 (struct mal_descriptor *)((char *)ep->mal->rx_virt_addr +
1262 (ep->mal_rx_chan * MAL_DT_ALIGN));
1264 /* Fill in the transmit descriptor ring. */
1265 for (loop = 0; loop < NUM_TX_BUFF; loop++) {
1266 if (ep->tx_skb[loop]) {
1267 dma_unmap_single(&ep->ocpdev->dev,
1268 ep->tx_desc[loop].data_ptr,
1269 ep->tx_desc[loop].data_len,
1271 dev_kfree_skb_irq(ep->tx_skb[loop]);
1273 ep->tx_skb[loop] = NULL;
1274 ep->tx_desc[loop].ctrl = 0;
1275 ep->tx_desc[loop].data_len = 0;
1276 ep->tx_desc[loop].data_ptr = NULL;
1278 ep->tx_desc[loop - 1].ctrl |= MAL_TX_CTRL_WRAP;
1280 /* Format the receive descriptor ring. */
1282 /* Default is MTU=1500 + Ethernet overhead */
1283 ep->rx_buffer_size = ENET_DEF_BUF_SIZE;
1284 emac_rx_fill(dev, 0);
1285 if (ep->rx_slot != 0) {
1287 "%s: Not enough mem for RxChain durning Open?\n",
1289 /*We couldn't fill the ring at startup?
1290 *We could clean up and fail to open but right now we will try to
1291 *carry on. It may be a sign of a bad NUM_RX_BUFF value
1300 static void emac_reset_configure(struct ocp_enet_private *fep)
1302 emac_t *emacp = fep->emacp;
1305 mal_disable_tx_channels(fep->mal, fep->commac.tx_chan_mask);
1306 mal_disable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
1309 * Check for a link, some PHYs don't provide a clock if
1310 * no link is present. Some EMACs will not come out of
1311 * soft reset without a PHY clock present.
1313 if (fep->phy_mii.def->ops->poll_link(&fep->phy_mii)) {
1314 /* Reset the EMAC */
1315 out_be32(&emacp->em0mr0, EMAC_M0_SRST);
1317 for (i = 0; i < 100; i++) {
1318 if ((in_be32(&emacp->em0mr0) & EMAC_M0_SRST) == 0)
1324 printk(KERN_ERR "%s: Cannot reset EMAC\n",
1330 /* Switch IRQs off for now */
1331 out_be32(&emacp->em0iser, 0);
1333 /* Configure MAL rx channel */
1334 mal_set_rcbs(fep->mal, fep->mal_rx_chan, DESC_BUF_SIZE_REG);
1336 /* set the high address */
1337 out_be32(&emacp->em0iahr,
1338 (fep->ndev->dev_addr[0] << 8) | fep->ndev->dev_addr[1]);
1340 /* set the low address */
1341 out_be32(&emacp->em0ialr,
1342 (fep->ndev->dev_addr[2] << 24) | (fep->ndev->dev_addr[3] << 16)
1343 | (fep->ndev->dev_addr[4] << 8) | fep->ndev->dev_addr[5]);
1345 /* Adjust to link */
1346 if (netif_carrier_ok(fep->ndev))
1347 emac_adjust_to_link(fep);
1349 /* enable broadcast/individual address and RX FIFO defaults */
1350 out_be32(&emacp->em0rmr, EMAC_RMR_DEFAULT);
1352 /* set transmit request threshold register */
1353 out_be32(&emacp->em0trtr, EMAC_TRTR_DEFAULT);
1355 /* Reconfigure multicast */
1356 __emac_set_multicast_list(fep->ndev);
1358 /* Set receiver/transmitter defaults */
1359 out_be32(&emacp->em0rwmr, EMAC_RWMR_DEFAULT);
1360 out_be32(&emacp->em0tmr0, EMAC_TMR0_DEFAULT);
1361 out_be32(&emacp->em0tmr1, EMAC_TMR1_DEFAULT);
1364 out_be32(&emacp->em0ipgvr, CONFIG_IBM_EMAC_FGAP);
1366 /* Init ring buffers */
1367 emac_init_rings(fep->ndev);
1370 static void emac_kick(struct ocp_enet_private *fep)
1372 emac_t *emacp = fep->emacp;
1373 unsigned long emac_ier;
1375 emac_ier = EMAC_ISR_PP | EMAC_ISR_BP | EMAC_ISR_RP |
1376 EMAC_ISR_SE | EMAC_ISR_PTLE | EMAC_ISR_ALE |
1377 EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
1379 out_be32(&emacp->em0iser, emac_ier);
1381 /* enable all MAL transmit and receive channels */
1382 mal_enable_tx_channels(fep->mal, fep->commac.tx_chan_mask);
1383 mal_enable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
1385 /* set transmit and receive enable */
1386 out_be32(&emacp->em0mr0, EMAC_M0_TXE | EMAC_M0_RXE);
1390 emac_start_link(struct ocp_enet_private *fep, struct ethtool_cmd *ep)
1397 /* Default advertise */
1398 advertise = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1399 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1400 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full;
1401 autoneg = fep->want_autoneg;
1402 forced_speed = fep->phy_mii.speed;
1403 forced_duplex = fep->phy_mii.duplex;
1405 /* Setup link parameters */
1407 if (ep->autoneg == AUTONEG_ENABLE) {
1408 advertise = ep->advertising;
1412 forced_speed = ep->speed;
1413 forced_duplex = ep->duplex;
1417 /* Configure PHY & start aneg */
1418 fep->want_autoneg = autoneg;
1420 LINK_DEBUG(("%s: start link aneg, advertise: 0x%x\n",
1421 fep->ndev->name, advertise));
1422 fep->phy_mii.def->ops->setup_aneg(&fep->phy_mii, advertise);
1424 LINK_DEBUG(("%s: start link forced, speed: %d, duplex: %d\n",
1425 fep->ndev->name, forced_speed, forced_duplex));
1426 fep->phy_mii.def->ops->setup_forced(&fep->phy_mii, forced_speed,
1429 fep->timer_ticks = 0;
1430 mod_timer(&fep->link_timer, jiffies + HZ);
1433 static void emac_link_timer(unsigned long data)
1435 struct ocp_enet_private *fep = (struct ocp_enet_private *)data;
1438 if (fep->going_away)
1441 spin_lock_irq(&fep->lock);
1443 link = fep->phy_mii.def->ops->poll_link(&fep->phy_mii);
1444 LINK_DEBUG(("%s: poll_link: %d\n", fep->ndev->name, link));
1446 if (link == netif_carrier_ok(fep->ndev)) {
1447 if (!link && fep->want_autoneg && (++fep->timer_ticks) > 10)
1448 emac_start_link(fep, NULL);
1451 printk(KERN_INFO "%s: Link is %s\n", fep->ndev->name,
1452 link ? "Up" : "Down");
1454 netif_carrier_on(fep->ndev);
1455 /* Chip needs a full reset on config change. That sucks, so I
1456 * should ultimately move that to some tasklet to limit
1457 * latency peaks caused by this code
1459 emac_reset_configure(fep);
1463 fep->timer_ticks = 0;
1464 netif_carrier_off(fep->ndev);
1467 mod_timer(&fep->link_timer, jiffies + HZ);
1468 spin_unlock_irq(&fep->lock);
1471 static void emac_set_multicast_list(struct net_device *dev)
1473 struct ocp_enet_private *fep = dev->priv;
1475 spin_lock_irq(&fep->lock);
1476 __emac_set_multicast_list(dev);
1477 spin_unlock_irq(&fep->lock);
1480 static int emac_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
1482 struct ocp_enet_private *fep = ndev->priv;
1484 cmd->supported = fep->phy_mii.def->features;
1485 cmd->port = PORT_MII;
1486 cmd->transceiver = XCVR_EXTERNAL;
1487 cmd->phy_address = fep->mii_phy_addr;
1488 spin_lock_irq(&fep->lock);
1489 cmd->autoneg = fep->want_autoneg;
1490 cmd->speed = fep->phy_mii.speed;
1491 cmd->duplex = fep->phy_mii.duplex;
1492 spin_unlock_irq(&fep->lock);
1496 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
1498 struct ocp_enet_private *fep = ndev->priv;
1499 unsigned long features = fep->phy_mii.def->features;
1501 if (!capable(CAP_NET_ADMIN))
1504 if (cmd->autoneg != AUTONEG_ENABLE && cmd->autoneg != AUTONEG_DISABLE)
1506 if (cmd->autoneg == AUTONEG_ENABLE && cmd->advertising == 0)
1508 if (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL)
1510 if (cmd->autoneg == AUTONEG_DISABLE)
1511 switch (cmd->speed) {
1513 if (cmd->duplex == DUPLEX_HALF &&
1514 (features & SUPPORTED_10baseT_Half) == 0)
1516 if (cmd->duplex == DUPLEX_FULL &&
1517 (features & SUPPORTED_10baseT_Full) == 0)
1521 if (cmd->duplex == DUPLEX_HALF &&
1522 (features & SUPPORTED_100baseT_Half) == 0)
1524 if (cmd->duplex == DUPLEX_FULL &&
1525 (features & SUPPORTED_100baseT_Full) == 0)
1529 if (cmd->duplex == DUPLEX_HALF &&
1530 (features & SUPPORTED_1000baseT_Half) == 0)
1532 if (cmd->duplex == DUPLEX_FULL &&
1533 (features & SUPPORTED_1000baseT_Full) == 0)
1538 } else if ((features & SUPPORTED_Autoneg) == 0)
1540 spin_lock_irq(&fep->lock);
1541 emac_start_link(fep, cmd);
1542 spin_unlock_irq(&fep->lock);
1547 emac_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1549 struct ocp_enet_private *fep = ndev->priv;
1551 strcpy(info->driver, DRV_NAME);
1552 strcpy(info->version, DRV_VERSION);
1553 info->fw_version[0] = '\0';
1554 sprintf(info->bus_info, "IBM EMAC %d", fep->ocpdev->def->index);
1555 info->regdump_len = 0;
1558 static int emac_nway_reset(struct net_device *ndev)
1560 struct ocp_enet_private *fep = ndev->priv;
1562 if (!fep->want_autoneg)
1564 spin_lock_irq(&fep->lock);
1565 emac_start_link(fep, NULL);
1566 spin_unlock_irq(&fep->lock);
1570 static u32 emac_get_link(struct net_device *ndev)
1572 return netif_carrier_ok(ndev);
1575 static struct ethtool_ops emac_ethtool_ops = {
1576 .get_settings = emac_get_settings,
1577 .set_settings = emac_set_settings,
1578 .get_drvinfo = emac_get_drvinfo,
1579 .nway_reset = emac_nway_reset,
1580 .get_link = emac_get_link
1583 static int emac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1585 struct ocp_enet_private *fep = dev->priv;
1586 uint *data = (uint *) & rq->ifr_ifru;
1590 data[0] = fep->mii_phy_addr;
1593 data[3] = emac_phy_read(dev, fep->mii_phy_addr, data[1]);
1596 if (!capable(CAP_NET_ADMIN))
1599 emac_phy_write(dev, fep->mii_phy_addr, data[1], data[2]);
1606 static int emac_open(struct net_device *dev)
1608 struct ocp_enet_private *fep = dev->priv;
1611 spin_lock_irq(&fep->lock);
1614 netif_carrier_off(dev);
1616 /* Reset & configure the chip */
1617 emac_reset_configure(fep);
1619 spin_unlock_irq(&fep->lock);
1621 /* Request our interrupt lines */
1622 rc = request_irq(dev->irq, emac_mac_irq, 0, "IBM EMAC MAC", dev);
1624 printk("dev->irq %d failed\n", dev->irq);
1627 /* Kick the chip rx & tx channels into life */
1628 spin_lock_irq(&fep->lock);
1630 spin_unlock_irq(&fep->lock);
1632 netif_start_queue(dev);
1637 static int emac_close(struct net_device *dev)
1639 struct ocp_enet_private *fep = dev->priv;
1640 emac_t *emacp = fep->emacp;
1642 /* XXX Stop IRQ emitting here */
1643 spin_lock_irq(&fep->lock);
1645 mal_disable_tx_channels(fep->mal, fep->commac.tx_chan_mask);
1646 mal_disable_rx_channels(fep->mal, fep->commac.rx_chan_mask);
1647 netif_carrier_off(dev);
1648 netif_stop_queue(dev);
1651 * Check for a link, some PHYs don't provide a clock if
1652 * no link is present. Some EMACs will not come out of
1653 * soft reset without a PHY clock present.
1655 if (fep->phy_mii.def->ops->poll_link(&fep->phy_mii)) {
1656 out_be32(&emacp->em0mr0, EMAC_M0_SRST);
1659 if (emacp->em0mr0 & EMAC_M0_SRST) {
1660 /*not sure what to do here hopefully it clears before another open */
1662 "%s: Phy SoftReset didn't clear, no link?\n",
1667 /* Free the irq's */
1668 free_irq(dev->irq, dev);
1670 spin_unlock_irq(&fep->lock);
1675 static void emac_remove(struct ocp_device *ocpdev)
1677 struct net_device *dev = ocp_get_drvdata(ocpdev);
1678 struct ocp_enet_private *ep = dev->priv;
1680 /* FIXME: locking, races, ... */
1682 ocp_set_drvdata(ocpdev, NULL);
1684 emac_close_rgmii(ep->rgmii_dev);
1686 emac_close_zmii(ep->zmii_dev);
1688 unregister_netdev(dev);
1689 del_timer_sync(&ep->link_timer);
1690 mal_unregister_commac(ep->mal, &ep->commac);
1691 iounmap((void *)ep->emacp);
1695 struct mal_commac_ops emac_commac_ops = {
1696 .txeob = &emac_txeob_dev,
1697 .txde = &emac_txde_dev,
1698 .rxeob = &emac_rxeob_dev,
1699 .rxde = &emac_rxde_dev,
1702 static int emac_init_device(struct ocp_device *ocpdev, struct ibm_ocp_mal *mal)
1704 int deferred_init = 0;
1706 struct net_device *ndev;
1707 struct ocp_enet_private *ep;
1708 struct ocp_func_emac_data *emacdata;
1712 emacdata = (struct ocp_func_emac_data *)ocpdev->def->additions;
1714 printk(KERN_ERR "emac%d: Missing additional data!\n",
1715 ocpdev->def->index);
1719 /* Allocate our net_device structure */
1720 ndev = alloc_etherdev(sizeof(struct ocp_enet_private));
1723 "emac%d: Could not allocate ethernet device.\n",
1724 ocpdev->def->index);
1729 ep->ocpdev = ocpdev;
1730 ndev->irq = ocpdev->def->irq;
1731 ep->wol_irq = emacdata->wol_irq;
1732 if (emacdata->mdio_idx >= 0) {
1733 if (emacdata->mdio_idx == ocpdev->def->index) {
1734 /* Set the common MDIO net_device */
1738 ep->mdio_dev = mdio_ndev;
1740 ep->mdio_dev = ndev;
1743 ocp_set_drvdata(ocpdev, ndev);
1745 spin_lock_init(&ep->lock);
1747 /* Fill out MAL informations and register commac */
1749 ep->mal_tx_chan = emacdata->mal_tx_chan;
1750 ep->mal_rx_chan = emacdata->mal_rx_chan;
1751 ep->commac.ops = &emac_commac_ops;
1752 ep->commac.dev = ndev;
1753 ep->commac.tx_chan_mask = MAL_CHAN_MASK(ep->mal_tx_chan);
1754 ep->commac.rx_chan_mask = MAL_CHAN_MASK(ep->mal_rx_chan);
1755 rc = mal_register_commac(ep->mal, &ep->commac);
1761 ep->emacp = (emac_t *) ioremap(ocpdev->def->paddr, sizeof(emac_t));
1763 /* Check if we need to attach to a ZMII */
1764 if (emacdata->zmii_idx >= 0) {
1765 ep->zmii_input = emacdata->zmii_mux;
1767 ocp_find_device(OCP_ANY_ID, OCP_FUNC_ZMII,
1768 emacdata->zmii_idx);
1769 if (ep->zmii_dev == NULL)
1771 "emac%d: ZMII %d requested but not found !\n",
1772 ocpdev->def->index, emacdata->zmii_idx);
1774 emac_init_zmii(ep->zmii_dev, ep->zmii_input,
1775 emacdata->phy_mode)) != 0)
1779 /* Check if we need to attach to a RGMII */
1780 if (emacdata->rgmii_idx >= 0) {
1781 ep->rgmii_input = emacdata->rgmii_mux;
1783 ocp_find_device(OCP_ANY_ID, OCP_FUNC_RGMII,
1784 emacdata->rgmii_idx);
1785 if (ep->rgmii_dev == NULL)
1787 "emac%d: RGMII %d requested but not found !\n",
1788 ocpdev->def->index, emacdata->rgmii_idx);
1790 emac_init_rgmii(ep->rgmii_dev, ep->rgmii_input,
1791 emacdata->phy_mode)) != 0)
1795 /* Check if we need to attach to a TAH */
1796 if (emacdata->tah_idx >= 0) {
1798 ocp_find_device(OCP_ANY_ID, OCP_FUNC_TAH,
1800 if (ep->tah_dev == NULL)
1802 "emac%d: TAH %d requested but not found !\n",
1803 ocpdev->def->index, emacdata->tah_idx);
1804 else if ((rc = emac_init_tah(ep)) != 0)
1808 if (deferred_init) {
1809 if (!list_empty(&emac_init_list)) {
1810 struct list_head *entry;
1811 struct emac_def_dev *ddev;
1813 list_for_each(entry, &emac_init_list) {
1815 list_entry(entry, struct emac_def_dev,
1817 emac_init_device(ddev->ocpdev, ddev->mal);
1822 /* Init link monitoring timer */
1823 init_timer(&ep->link_timer);
1824 ep->link_timer.function = emac_link_timer;
1825 ep->link_timer.data = (unsigned long)ep;
1826 ep->timer_ticks = 0;
1828 /* Fill up the mii_phy structure */
1829 ep->phy_mii.dev = ndev;
1830 ep->phy_mii.mdio_read = emac_phy_read;
1831 ep->phy_mii.mdio_write = emac_phy_write;
1832 ep->phy_mii.mode = emacdata->phy_mode;
1835 phy_map = emacdata->phy_map | busy_phy_map;
1836 for (i = 0; i <= 0x1f; i++, phy_map >>= 1) {
1837 if ((phy_map & 0x1) == 0) {
1838 int val = emac_phy_read(ndev, i, MII_BMCR);
1839 if (val != 0xffff && val != -1)
1844 printk(KERN_WARNING "emac%d: Can't find PHY.\n",
1845 ocpdev->def->index);
1849 busy_phy_map |= 1 << i;
1850 ep->mii_phy_addr = i;
1851 rc = mii_phy_probe(&ep->phy_mii, i);
1853 printk(KERN_WARNING "emac%d: Failed to probe PHY type.\n",
1854 ocpdev->def->index);
1859 /* Setup initial PHY config & startup aneg */
1860 if (ep->phy_mii.def->ops->init)
1861 ep->phy_mii.def->ops->init(&ep->phy_mii);
1862 netif_carrier_off(ndev);
1863 if (ep->phy_mii.def->features & SUPPORTED_Autoneg)
1864 ep->want_autoneg = 1;
1865 emac_start_link(ep, NULL);
1867 /* read the MAC Address */
1868 for (i = 0; i < 6; i++)
1869 ndev->dev_addr[i] = emacdata->mac_addr[i];
1871 /* Fill in the driver function table */
1872 ndev->open = &emac_open;
1873 ndev->hard_start_xmit = &emac_start_xmit;
1874 ndev->stop = &emac_close;
1875 ndev->get_stats = &emac_stats;
1876 if (emacdata->jumbo)
1877 ndev->change_mtu = &emac_change_mtu;
1878 ndev->set_mac_address = &emac_set_mac_address;
1879 ndev->set_multicast_list = &emac_set_multicast_list;
1880 ndev->do_ioctl = &emac_ioctl;
1881 SET_ETHTOOL_OPS(ndev, &emac_ethtool_ops);
1882 if (emacdata->tah_idx >= 0)
1883 ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG;
1885 SET_MODULE_OWNER(ndev);
1887 rc = register_netdev(ndev);
1891 printk("%s: IBM emac, MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1893 ndev->dev_addr[0], ndev->dev_addr[1], ndev->dev_addr[2],
1894 ndev->dev_addr[3], ndev->dev_addr[4], ndev->dev_addr[5]);
1895 printk(KERN_INFO "%s: Found %s PHY (0x%02x)\n",
1896 ndev->name, ep->phy_mii.def->name, ep->mii_phy_addr);
1899 if (rc && commac_reg)
1900 mal_unregister_commac(ep->mal, &ep->commac);
1907 static int emac_probe(struct ocp_device *ocpdev)
1909 struct ocp_device *maldev;
1910 struct ibm_ocp_mal *mal;
1911 struct ocp_func_emac_data *emacdata;
1913 emacdata = (struct ocp_func_emac_data *)ocpdev->def->additions;
1914 if (emacdata == NULL) {
1915 printk(KERN_ERR "emac%d: Missing additional datas !\n",
1916 ocpdev->def->index);
1920 /* Get the MAL device */
1921 maldev = ocp_find_device(OCP_ANY_ID, OCP_FUNC_MAL, emacdata->mal_idx);
1922 if (maldev == NULL) {
1923 printk("No maldev\n");
1927 * Get MAL driver data, it must be here due to link order.
1928 * When the driver is modularized, symbol dependencies will
1929 * ensure the MAL driver is already present if built as a
1932 mal = (struct ibm_ocp_mal *)ocp_get_drvdata(maldev);
1934 printk("No maldrv\n");
1938 /* If we depend on another EMAC for MDIO, wait for it to show up */
1939 if (emacdata->mdio_idx >= 0 &&
1940 (emacdata->mdio_idx != ocpdev->def->index) && !mdio_ndev) {
1941 struct emac_def_dev *ddev;
1942 /* Add this index to the deferred init table */
1943 ddev = kmalloc(sizeof(struct emac_def_dev), GFP_KERNEL);
1944 ddev->ocpdev = ocpdev;
1946 list_add_tail(&ddev->link, &emac_init_list);
1948 emac_init_device(ocpdev, mal);
1954 /* Structure for a device driver */
1955 static struct ocp_device_id emac_ids[] = {
1956 {.vendor = OCP_ANY_ID,.function = OCP_FUNC_EMAC},
1957 {.vendor = OCP_VENDOR_INVALID}
1960 static struct ocp_driver emac_driver = {
1962 .id_table = emac_ids,
1964 .probe = emac_probe,
1965 .remove = emac_remove,
1968 static int __init emac_init(void)
1970 printk(KERN_INFO DRV_NAME ": " DRV_DESC ", version " DRV_VERSION "\n");
1971 printk(KERN_INFO "Maintained by " DRV_AUTHOR "\n");
1974 printk(KERN_WARNING "Invalid skb_res: %d, cropping to 2\n",
1979 return ocp_register_driver(&emac_driver);
1982 static void __exit emac_exit(void)
1984 ocp_unregister_driver(&emac_driver);
1987 module_init(emac_init);
1988 module_exit(emac_exit);