1 /*******************************************************************************
4 Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 The full GNU General Public License is included in this distribution in the
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
29 * Shared functions for accessing and configuring the adapter
35 /* Local function prototypes */
37 static u32 ixgb_hash_mc_addr(struct ixgb_hw *hw, u8 * mc_addr);
39 static void ixgb_mta_set(struct ixgb_hw *hw, u32 hash_value);
41 static void ixgb_get_bus_info(struct ixgb_hw *hw);
43 boolean_t mac_addr_valid(u8 * mac_addr);
45 static boolean_t ixgb_link_reset(struct ixgb_hw *hw);
47 static void ixgb_optics_reset(struct ixgb_hw *hw);
49 u32 ixgb_mac_reset(struct ixgb_hw *hw);
52 ixgb_mac_reset(struct ixgb_hw *hw)
56 /* Setup up hardware to known state with RESET. */
57 ctrl_reg = IXGB_CTRL0_RST | IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */
58 IXGB_CTRL0_SDP2_DIR | IXGB_CTRL0_SDP1_DIR | IXGB_CTRL0_SDP0_DIR | IXGB_CTRL0_SDP3 | /* Initial value 1101 */
59 IXGB_CTRL0_SDP2 | IXGB_CTRL0_SDP0;
61 outl(IXGB_CTRL0, hw->io_base);
62 outl(ctrl_reg, hw->io_base + 4);
64 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
67 /* Delay a few ms just to allow the reset to complete */
68 msec_delay(IXGB_DELAY_AFTER_RESET);
69 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
71 /* Make sure the self-clearing global reset bit did self clear */
72 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
75 ixgb_optics_reset(hw);
79 /******************************************************************************
80 * Reset the transmit and receive units; mask and clear all interrupts.
82 * hw - Struct containing variables accessed by shared code
83 *****************************************************************************/
85 ixgb_adapter_stop(struct ixgb_hw * hw)
90 DEBUGFUNC("ixgb_adapter_stop");
92 /* If we are stopped or resetting exit gracefully and wait to be
93 * started again before accessing the hardware.
95 if (hw->adapter_stopped) {
96 DEBUGOUT("Exiting because the adapter is already stopped!!!\n");
100 /* Set the Adapter Stopped flag so other driver functions stop
101 * touching the Hardware.
103 hw->adapter_stopped = TRUE;
105 /* Clear interrupt mask to stop board from generating interrupts */
106 DEBUGOUT("Masking off all interrupts\n");
107 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
109 /* Disable the Transmit and Receive units. Then delay to allow
110 * any pending transactions to complete before we hit the MAC with
113 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
114 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
115 msec_delay(IXGB_DELAY_BEFORE_RESET);
117 /* Issue a global reset to the MAC. This will reset the chip's
118 * transmit, receive, DMA, and link units. It will not effect
119 * the current PCI configuration. The global reset bit is self-
120 * clearing, and should clear within a microsecond.
122 DEBUGOUT("Issuing a global reset to MAC\n");
124 ctrl_reg = ixgb_mac_reset(hw);
126 /* Clear interrupt mask to stop board from generating interrupts */
127 DEBUGOUT("Masking off all interrupts\n");
128 IXGB_WRITE_REG(hw, IMC, 0xffffffff);
130 /* Clear any pending interrupt events. */
131 icr_reg = IXGB_READ_REG(hw, ICR);
133 return (ctrl_reg & IXGB_CTRL0_RST);
136 /******************************************************************************
137 * Performs basic configuration of the adapter.
139 * hw - Struct containing variables accessed by shared code
141 * Resets the controller.
142 * Reads and validates the EEPROM.
143 * Initializes the receive address registers.
144 * Initializes the multicast table.
145 * Clears all on-chip counters.
146 * Calls routine to setup flow control settings.
147 * Leaves the transmit and receive units disabled and uninitialized.
150 * TRUE if successful,
151 * FALSE if unrecoverable problems were encountered.
152 *****************************************************************************/
154 ixgb_init_hw(struct ixgb_hw * hw)
160 DEBUGFUNC("ixgb_init_hw");
162 /* Issue a global reset to the MAC. This will reset the chip's
163 * transmit, receive, DMA, and link units. It will not effect
164 * the current PCI configuration. The global reset bit is self-
165 * clearing, and should clear within a microsecond.
167 DEBUGOUT("Issuing a global reset to MAC\n");
169 ctrl_reg = ixgb_mac_reset(hw);
171 DEBUGOUT("Issuing an EE reset to MAC\n");
173 outl(IXGB_CTRL1, hw->io_base);
174 outl(IXGB_CTRL1_EE_RST, hw->io_base + 4);
176 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
179 /* Delay a few ms just to allow the reset to complete */
180 msec_delay(IXGB_DELAY_AFTER_EE_RESET);
182 if (ixgb_get_eeprom_data(hw) == FALSE) {
186 /* Setup the receive addresses.
187 * Receive Address Registers (RARs 0 - 15).
189 ixgb_init_rx_addrs(hw);
192 * Check that a valid MAC address has been set.
193 * If it is not valid, we fail hardware init.
195 if (!mac_addr_valid(hw->curr_mac_addr)) {
196 DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n");
200 /* tell the routines in this file they can access hardware again */
201 hw->adapter_stopped = FALSE;
203 /* Fill in the bus_info structure */
204 ixgb_get_bus_info(hw);
206 /* Zero out the Multicast HASH table */
207 DEBUGOUT("Zeroing the MTA\n");
208 for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
209 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
211 /* Zero out the VLAN Filter Table Array */
214 /* Zero all of the hardware counters */
215 ixgb_clear_hw_cntrs(hw);
217 /* Call a subroutine to setup flow control. */
218 status = ixgb_setup_fc(hw);
220 /* check-for-link in case lane deskew is locked */
221 ixgb_check_for_link(hw);
226 /******************************************************************************
227 * Initializes receive address filters.
229 * hw - Struct containing variables accessed by shared code
231 * Places the MAC address in receive address register 0 and clears the rest
232 * of the receive addresss registers. Clears the multicast table. Assumes
233 * the receiver is in reset when the routine is called.
234 *****************************************************************************/
236 ixgb_init_rx_addrs(struct ixgb_hw *hw)
240 DEBUGFUNC("ixgb_init_rx_addrs");
243 * If the current mac address is valid, assume it is a software override
244 * to the permanent address.
245 * Otherwise, use the permanent address from the eeprom.
247 if (!mac_addr_valid(hw->curr_mac_addr)) {
249 /* Get the MAC address from the eeprom for later reference */
250 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
252 DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ",
253 hw->curr_mac_addr[0],
254 hw->curr_mac_addr[1], hw->curr_mac_addr[2]);
255 DEBUGOUT3("%.2X %.2X %.2X\n",
256 hw->curr_mac_addr[3],
257 hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
260 /* Setup the receive address. */
261 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
262 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
263 hw->curr_mac_addr[0],
264 hw->curr_mac_addr[1], hw->curr_mac_addr[2]);
265 DEBUGOUT3("%.2X %.2X %.2X\n",
266 hw->curr_mac_addr[3],
267 hw->curr_mac_addr[4], hw->curr_mac_addr[5]);
269 ixgb_rar_set(hw, hw->curr_mac_addr, 0);
272 /* Zero out the other 15 receive addresses. */
273 DEBUGOUT("Clearing RAR[1-15]\n");
274 for (i = 1; i < IXGB_RAR_ENTRIES; i++) {
275 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
276 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
282 /******************************************************************************
283 * Updates the MAC's list of multicast addresses.
285 * hw - Struct containing variables accessed by shared code
286 * mc_addr_list - the list of new multicast addresses
287 * mc_addr_count - number of addresses
288 * pad - number of bytes between addresses in the list
290 * The given list replaces any existing list. Clears the last 15 receive
291 * address registers and the multicast table. Uses receive address registers
292 * for the first 15 multicast addresses, and hashes the rest into the
294 *****************************************************************************/
296 ixgb_mc_addr_list_update(struct ixgb_hw *hw,
298 u32 mc_addr_count, u32 pad)
302 u32 rar_used_count = 1; /* RAR[0] is used for our MAC address */
304 DEBUGFUNC("ixgb_mc_addr_list_update");
306 /* Set the new number of MC addresses that we are being requested to use. */
307 hw->num_mc_addrs = mc_addr_count;
309 /* Clear RAR[1-15] */
310 DEBUGOUT(" Clearing RAR[1-15]\n");
311 for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
312 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
313 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
317 DEBUGOUT(" Clearing MTA\n");
318 for (i = 0; i < IXGB_MC_TBL_SIZE; i++) {
319 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
322 /* Add the new addresses */
323 for (i = 0; i < mc_addr_count; i++) {
324 DEBUGOUT(" Adding the multicast addresses:\n");
325 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
326 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)],
327 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
329 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
331 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
333 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
335 mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) +
338 /* Place this multicast address in the RAR if there is room, *
339 * else put it in the MTA
341 if (rar_used_count < IXGB_RAR_ENTRIES) {
344 (i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)),
346 DEBUGOUT1("Added a multicast address to RAR[%d]\n", i);
349 hash_value = ixgb_hash_mc_addr(hw,
352 (IXGB_ETH_LENGTH_OF_ADDRESS
355 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
357 ixgb_mta_set(hw, hash_value);
361 DEBUGOUT("MC Update Complete\n");
365 /******************************************************************************
366 * Hashes an address to determine its location in the multicast table
368 * hw - Struct containing variables accessed by shared code
369 * mc_addr - the multicast address to hash
373 *****************************************************************************/
375 ixgb_hash_mc_addr(struct ixgb_hw *hw, u8 * mc_addr)
379 DEBUGFUNC("ixgb_hash_mc_addr");
381 /* The portion of the address that is used for the hash table is
382 * determined by the mc_filter_type setting.
384 switch (hw->mc_filter_type) {
385 /* [0] [1] [2] [3] [4] [5]
387 * LSB MSB - According to H/W docs */
389 /* [47:36] i.e. 0x563 for above example address */
391 ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
393 case 1: /* [46:35] i.e. 0xAC6 for above example address */
395 ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
397 case 2: /* [45:34] i.e. 0x5D8 for above example address */
399 ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
401 case 3: /* [43:32] i.e. 0x634 for above example address */
402 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
405 /* Invalid mc_filter_type, what should we do? */
406 DEBUGOUT("MC filter type param set incorrectly\n");
415 /******************************************************************************
416 * Sets the bit in the multicast table corresponding to the hash value.
418 * hw - Struct containing variables accessed by shared code
419 * hash_value - Multicast address hash value
420 *****************************************************************************/
422 ixgb_mta_set(struct ixgb_hw *hw, u32 hash_value)
424 u32 hash_bit, hash_reg;
427 /* The MTA is a register array of 128 32-bit registers.
428 * It is treated like an array of 4096 bits. We want to set
429 * bit BitArray[hash_value]. So we figure out what register
430 * the bit is in, read it, OR in the new bit, then write
431 * back the new value. The register is determined by the
432 * upper 7 bits of the hash value and the bit within that
433 * register are determined by the lower 5 bits of the value.
435 hash_reg = (hash_value >> 5) & 0x7F;
436 hash_bit = hash_value & 0x1F;
438 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg);
440 mta_reg |= (1 << hash_bit);
442 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
447 /******************************************************************************
448 * Puts an ethernet address into a receive address register.
450 * hw - Struct containing variables accessed by shared code
451 * addr - Address to put into receive address register
452 * index - Receive address register to write
453 *****************************************************************************/
455 ixgb_rar_set(struct ixgb_hw *hw, u8 * addr, u32 index)
457 u32 rar_low, rar_high;
459 DEBUGFUNC("ixgb_rar_set");
461 /* HW expects these in little endian so we reverse the byte order
462 * from network order (big endian) to little endian
464 rar_low = ((u32) addr[0] |
465 ((u32) addr[1] << 8) |
466 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
468 rar_high = ((u32) addr[4] |
469 ((u32) addr[5] << 8) | IXGB_RAH_AV);
471 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
472 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
476 /******************************************************************************
477 * Writes a value to the specified offset in the VLAN filter table.
479 * hw - Struct containing variables accessed by shared code
480 * offset - Offset in VLAN filer table to write
481 * value - Value to write into VLAN filter table
482 *****************************************************************************/
484 ixgb_write_vfta(struct ixgb_hw *hw, u32 offset, u32 value)
486 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
490 /******************************************************************************
491 * Clears the VLAN filer table
493 * hw - Struct containing variables accessed by shared code
494 *****************************************************************************/
496 ixgb_clear_vfta(struct ixgb_hw *hw)
500 for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
501 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
505 /******************************************************************************
506 * Configures the flow control settings based on SW configuration.
508 * hw - Struct containing variables accessed by shared code
509 *****************************************************************************/
512 ixgb_setup_fc(struct ixgb_hw * hw)
515 u32 pap_reg = 0; /* by default, assume no pause time */
516 boolean_t status = TRUE;
518 DEBUGFUNC("ixgb_setup_fc");
520 /* Get the current control reg 0 settings */
521 ctrl_reg = IXGB_READ_REG(hw, CTRL0);
523 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
524 ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
526 /* The possible values of the "flow_control" parameter are:
527 * 0: Flow control is completely disabled
528 * 1: Rx flow control is enabled (we can receive pause frames
529 * but not send pause frames).
530 * 2: Tx flow control is enabled (we can send pause frames
531 * but we do not support receiving pause frames).
532 * 3: Both Rx and TX flow control (symmetric) are enabled.
535 switch (hw->fc.type) {
536 case ixgb_fc_none: /* 0 */
538 case ixgb_fc_rx_pause: /* 1 */
539 /* RX Flow control is enabled, and TX Flow control is
542 ctrl_reg |= (IXGB_CTRL0_RPE);
544 case ixgb_fc_tx_pause: /* 2 */
545 /* TX Flow control is enabled, and RX Flow control is
546 * disabled, by a software over-ride.
548 ctrl_reg |= (IXGB_CTRL0_TPE);
549 pap_reg = hw->fc.pause_time;
551 case ixgb_fc_full: /* 3 */
552 /* Flow control (both RX and TX) is enabled by a software
555 ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
556 pap_reg = hw->fc.pause_time;
559 /* We should never get here. The value should be 0-3. */
560 DEBUGOUT("Flow control param set incorrectly\n");
565 /* Write the new settings */
566 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
569 IXGB_WRITE_REG(hw, PAP, pap_reg);
572 /* Set the flow control receive threshold registers. Normally,
573 * these registers will be set to a default threshold that may be
574 * adjusted later by the driver's runtime code. However, if the
575 * ability to transmit pause frames in not enabled, then these
576 * registers will be set to 0.
578 if (!(hw->fc.type & ixgb_fc_tx_pause)) {
579 IXGB_WRITE_REG(hw, FCRTL, 0);
580 IXGB_WRITE_REG(hw, FCRTH, 0);
582 /* We need to set up the Receive Threshold high and low water
583 * marks as well as (optionally) enabling the transmission of XON frames.
585 if (hw->fc.send_xon) {
586 IXGB_WRITE_REG(hw, FCRTL,
587 (hw->fc.low_water | IXGB_FCRTL_XONE));
589 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
591 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
596 /******************************************************************************
597 * Reads a word from a device over the Management Data Interface (MDI) bus.
598 * This interface is used to manage Physical layer devices.
600 * hw - Struct containing variables accessed by hw code
601 * reg_address - Offset of device register being read.
602 * phy_address - Address of device on MDI.
604 * Returns: Data word (16 bits) from MDI device.
606 * This routine uses the new protocol MDI Single Command and Address Operation.
607 * This requires that first an address cycle command is sent, followed by a
609 *****************************************************************************/
611 ixgb_read_phy_reg(struct ixgb_hw * hw,
613 u32 phy_address, u32 device_type)
619 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
620 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
621 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
623 /* Setup and write the address cycle command */
624 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
625 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
626 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
627 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
629 IXGB_WRITE_REG(hw, MSCA, command);
631 /**************************************************************
632 ** Check every 10 usec to see if the address cycle completed
633 ** The COMMAND bit will clear when the operation is complete.
634 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
635 ** from the CPU Write to the Ready bit assertion.
636 **************************************************************/
638 for (i = 0; i < 10; i++) {
641 command = IXGB_READ_REG(hw, MSCA);
643 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
647 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
649 /* Address cycle complete, setup and write the read command */
650 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
651 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
652 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
653 (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND));
655 IXGB_WRITE_REG(hw, MSCA, command);
657 /**************************************************************
658 ** Check every 10 usec to see if the read command completed
659 ** The COMMAND bit will clear when the operation is complete.
660 ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
661 ** from the CPU Write to the Ready bit assertion.
662 **************************************************************/
664 for (i = 0; i < 10; i++) {
667 command = IXGB_READ_REG(hw, MSCA);
669 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
673 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
675 /* Operation is complete, get the data from the MDIO Read/Write Data
676 * register and return.
678 data = IXGB_READ_REG(hw, MSRWD);
679 data >>= IXGB_MSRWD_READ_DATA_SHIFT;
683 /******************************************************************************
684 * Writes a word to a device over the Management Data Interface (MDI) bus.
685 * This interface is used to manage Physical layer devices.
687 * hw - Struct containing variables accessed by hw code
688 * reg_address - Offset of device register being read.
689 * phy_address - Address of device on MDI.
690 * device_type - Also known as the Device ID or DID.
691 * data - 16-bit value to be written
695 * This routine uses the new protocol MDI Single Command and Address Operation.
696 * This requires that first an address cycle command is sent, followed by a
698 *****************************************************************************/
700 ixgb_write_phy_reg(struct ixgb_hw *hw,
702 u32 phy_address, u32 device_type, u16 data)
707 ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
708 ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
709 ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
711 /* Put the data in the MDIO Read/Write Data register */
712 IXGB_WRITE_REG(hw, MSRWD, (u32) data);
714 /* Setup and write the address cycle command */
715 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
716 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
717 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
718 (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
720 IXGB_WRITE_REG(hw, MSCA, command);
722 /**************************************************************
723 ** Check every 10 usec to see if the address cycle completed
724 ** The COMMAND bit will clear when the operation is complete.
725 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
726 ** from the CPU Write to the Ready bit assertion.
727 **************************************************************/
729 for (i = 0; i < 10; i++) {
732 command = IXGB_READ_REG(hw, MSCA);
734 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
738 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
740 /* Address cycle complete, setup and write the write command */
741 command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
742 (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
743 (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
744 (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND));
746 IXGB_WRITE_REG(hw, MSCA, command);
748 /**************************************************************
749 ** Check every 10 usec to see if the read command completed
750 ** The COMMAND bit will clear when the operation is complete.
751 ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
752 ** from the CPU Write to the Ready bit assertion.
753 **************************************************************/
755 for (i = 0; i < 10; i++) {
758 command = IXGB_READ_REG(hw, MSCA);
760 if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
764 ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
766 /* Operation is complete, return. */
769 /******************************************************************************
770 * Checks to see if the link status of the hardware has changed.
772 * hw - Struct containing variables accessed by hw code
774 * Called by any function that needs to check the link status of the adapter.
775 *****************************************************************************/
777 ixgb_check_for_link(struct ixgb_hw *hw)
782 DEBUGFUNC("ixgb_check_for_link");
784 xpcss_reg = IXGB_READ_REG(hw, XPCSS);
785 status_reg = IXGB_READ_REG(hw, STATUS);
787 if ((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
788 (status_reg & IXGB_STATUS_LU)) {
790 } else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
791 (status_reg & IXGB_STATUS_LU)) {
792 DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n");
793 hw->link_up = ixgb_link_reset(hw);
795 hw->link_up = ixgb_link_reset(hw);
798 /* Anything else for 10 Gig?? */
802 ixgb_check_for_bad_link(struct ixgb_hw *hw)
805 boolean_t bad_link_returncode = FALSE;
807 /* check for a bad reset that may have occured
808 * the indication is that the RFC / LFC registers may be incrementing
809 * continually. Do a full adapter reset to recover
811 newLFC = IXGB_READ_REG(hw, LFC);
812 newRFC = IXGB_READ_REG(hw, RFC);
813 if ((hw->lastLFC + 250 < newLFC) || (hw->lastRFC + 250 < newRFC)) {
814 DEBUGOUT("BAD LINK! too many LFC/RFC since last check\n");
815 bad_link_returncode = TRUE;
817 hw->lastLFC = newLFC;
818 hw->lastRFC = newRFC;
819 return bad_link_returncode;
822 /******************************************************************************
823 * Clears all hardware statistics counters.
825 * hw - Struct containing variables accessed by shared code
826 *****************************************************************************/
828 ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
830 volatile u32 temp_reg;
832 DEBUGFUNC("ixgb_clear_hw_cntrs");
834 /* if we are stopped or resetting exit gracefully */
835 if (hw->adapter_stopped) {
836 DEBUGOUT("Exiting because the adapter is stopped!!!\n");
840 temp_reg = IXGB_READ_REG(hw, TPRL);
841 temp_reg = IXGB_READ_REG(hw, TPRH);
842 temp_reg = IXGB_READ_REG(hw, GPRCL);
843 temp_reg = IXGB_READ_REG(hw, GPRCH);
844 temp_reg = IXGB_READ_REG(hw, BPRCL);
845 temp_reg = IXGB_READ_REG(hw, BPRCH);
846 temp_reg = IXGB_READ_REG(hw, MPRCL);
847 temp_reg = IXGB_READ_REG(hw, MPRCH);
848 temp_reg = IXGB_READ_REG(hw, UPRCL);
849 temp_reg = IXGB_READ_REG(hw, UPRCH);
850 temp_reg = IXGB_READ_REG(hw, VPRCL);
851 temp_reg = IXGB_READ_REG(hw, VPRCH);
852 temp_reg = IXGB_READ_REG(hw, JPRCL);
853 temp_reg = IXGB_READ_REG(hw, JPRCH);
854 temp_reg = IXGB_READ_REG(hw, GORCL);
855 temp_reg = IXGB_READ_REG(hw, GORCH);
856 temp_reg = IXGB_READ_REG(hw, TORL);
857 temp_reg = IXGB_READ_REG(hw, TORH);
858 temp_reg = IXGB_READ_REG(hw, RNBC);
859 temp_reg = IXGB_READ_REG(hw, RUC);
860 temp_reg = IXGB_READ_REG(hw, ROC);
861 temp_reg = IXGB_READ_REG(hw, RLEC);
862 temp_reg = IXGB_READ_REG(hw, CRCERRS);
863 temp_reg = IXGB_READ_REG(hw, ICBC);
864 temp_reg = IXGB_READ_REG(hw, ECBC);
865 temp_reg = IXGB_READ_REG(hw, MPC);
866 temp_reg = IXGB_READ_REG(hw, TPTL);
867 temp_reg = IXGB_READ_REG(hw, TPTH);
868 temp_reg = IXGB_READ_REG(hw, GPTCL);
869 temp_reg = IXGB_READ_REG(hw, GPTCH);
870 temp_reg = IXGB_READ_REG(hw, BPTCL);
871 temp_reg = IXGB_READ_REG(hw, BPTCH);
872 temp_reg = IXGB_READ_REG(hw, MPTCL);
873 temp_reg = IXGB_READ_REG(hw, MPTCH);
874 temp_reg = IXGB_READ_REG(hw, UPTCL);
875 temp_reg = IXGB_READ_REG(hw, UPTCH);
876 temp_reg = IXGB_READ_REG(hw, VPTCL);
877 temp_reg = IXGB_READ_REG(hw, VPTCH);
878 temp_reg = IXGB_READ_REG(hw, JPTCL);
879 temp_reg = IXGB_READ_REG(hw, JPTCH);
880 temp_reg = IXGB_READ_REG(hw, GOTCL);
881 temp_reg = IXGB_READ_REG(hw, GOTCH);
882 temp_reg = IXGB_READ_REG(hw, TOTL);
883 temp_reg = IXGB_READ_REG(hw, TOTH);
884 temp_reg = IXGB_READ_REG(hw, DC);
885 temp_reg = IXGB_READ_REG(hw, PLT64C);
886 temp_reg = IXGB_READ_REG(hw, TSCTC);
887 temp_reg = IXGB_READ_REG(hw, TSCTFC);
888 temp_reg = IXGB_READ_REG(hw, IBIC);
889 temp_reg = IXGB_READ_REG(hw, RFC);
890 temp_reg = IXGB_READ_REG(hw, LFC);
891 temp_reg = IXGB_READ_REG(hw, PFRC);
892 temp_reg = IXGB_READ_REG(hw, PFTC);
893 temp_reg = IXGB_READ_REG(hw, MCFRC);
894 temp_reg = IXGB_READ_REG(hw, MCFTC);
895 temp_reg = IXGB_READ_REG(hw, XONRXC);
896 temp_reg = IXGB_READ_REG(hw, XONTXC);
897 temp_reg = IXGB_READ_REG(hw, XOFFRXC);
898 temp_reg = IXGB_READ_REG(hw, XOFFTXC);
899 temp_reg = IXGB_READ_REG(hw, RJC);
903 /******************************************************************************
904 * Turns on the software controllable LED
906 * hw - Struct containing variables accessed by shared code
907 *****************************************************************************/
909 ixgb_led_on(struct ixgb_hw *hw)
911 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
913 /* To turn on the LED, clear software-definable pin 0 (SDP0). */
914 ctrl0_reg &= ~IXGB_CTRL0_SDP0;
915 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
919 /******************************************************************************
920 * Turns off the software controllable LED
922 * hw - Struct containing variables accessed by shared code
923 *****************************************************************************/
925 ixgb_led_off(struct ixgb_hw *hw)
927 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
929 /* To turn off the LED, set software-definable pin 0 (SDP0). */
930 ctrl0_reg |= IXGB_CTRL0_SDP0;
931 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
935 /******************************************************************************
936 * Gets the current PCI bus type, speed, and width of the hardware
938 * hw - Struct containing variables accessed by shared code
939 *****************************************************************************/
941 ixgb_get_bus_info(struct ixgb_hw *hw)
945 status_reg = IXGB_READ_REG(hw, STATUS);
947 hw->bus.type = (status_reg & IXGB_STATUS_PCIX_MODE) ?
948 ixgb_bus_type_pcix : ixgb_bus_type_pci;
950 if (hw->bus.type == ixgb_bus_type_pci) {
951 hw->bus.speed = (status_reg & IXGB_STATUS_PCI_SPD) ?
952 ixgb_bus_speed_66 : ixgb_bus_speed_33;
954 switch (status_reg & IXGB_STATUS_PCIX_SPD_MASK) {
955 case IXGB_STATUS_PCIX_SPD_66:
956 hw->bus.speed = ixgb_bus_speed_66;
958 case IXGB_STATUS_PCIX_SPD_100:
959 hw->bus.speed = ixgb_bus_speed_100;
961 case IXGB_STATUS_PCIX_SPD_133:
962 hw->bus.speed = ixgb_bus_speed_133;
965 hw->bus.speed = ixgb_bus_speed_reserved;
970 hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ?
971 ixgb_bus_width_64 : ixgb_bus_width_32;
976 /******************************************************************************
977 * Tests a MAC address to ensure it is a valid Individual Address
979 * mac_addr - pointer to MAC address.
981 *****************************************************************************/
983 mac_addr_valid(u8 * mac_addr)
985 boolean_t is_valid = TRUE;
986 DEBUGFUNC("mac_addr_valid");
988 /* Make sure it is not a multicast address */
989 if (IS_MULTICAST(mac_addr)) {
990 DEBUGOUT("MAC address is multicast\n");
993 /* Not a broadcast address */
994 else if (IS_BROADCAST(mac_addr)) {
995 DEBUGOUT("MAC address is broadcast\n");
998 /* Reject the zero address */
999 else if (mac_addr[0] == 0 &&
1002 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
1003 DEBUGOUT("MAC address is all zeros\n");
1009 /******************************************************************************
1010 * Resets the 10GbE link. Waits the settle time and returns the state of
1013 * hw - Struct containing variables accessed by shared code
1014 *****************************************************************************/
1016 ixgb_link_reset(struct ixgb_hw * hw)
1018 boolean_t link_status = FALSE;
1019 u8 wait_retries = MAX_RESET_ITERATIONS;
1020 u8 lrst_retries = MAX_RESET_ITERATIONS;
1023 IXGB_WRITE_REG(hw, CTRL0,
1024 IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
1027 udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
1029 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU)
1030 && (IXGB_READ_REG(hw, XPCSS) &
1031 IXGB_XPCSS_ALIGN_STATUS)) ? TRUE : FALSE;
1032 } while (!link_status && --wait_retries);
1033 } while (!link_status && --lrst_retries);
1038 /******************************************************************************
1039 * Resets the 10GbE optics module.
1041 * hw - Struct containing variables accessed by shared code
1042 *****************************************************************************/
1044 ixgb_optics_reset(struct ixgb_hw *hw)
1048 ixgb_write_phy_reg(hw,
1049 TXN17401_PMA_PMD_CR1,
1051 TXN17401_PMA_PMD_DID, TXN17401_PMA_PMD_CR1_RESET);
1052 mdio_reg = ixgb_read_phy_reg(hw,
1053 TXN17401_PMA_PMD_CR1,
1054 IXGB_PHY_ADDRESS, TXN17401_PMA_PMD_DID);