2 * Network device driver for the MACE ethernet controller on
3 * Apple Powermacs. Assumes it's under a DBDMA controller.
5 * Copyright (C) 1996 Paul Mackerras.
8 #include <linux/config.h>
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/netdevice.h>
12 #include <linux/etherdevice.h>
13 #include <linux/delay.h>
14 #include <linux/string.h>
15 #include <linux/timer.h>
16 #include <linux/init.h>
17 #include <linux/crc32.h>
18 #include <linux/spinlock.h>
20 #include <asm/dbdma.h>
22 #include <asm/pgtable.h>
23 #include <asm/macio.h>
27 static int port_aaui = -1;
31 #define MAX_TX_ACTIVE 1
32 #define NCMDS_TX 1 /* dma commands per element in tx ring */
33 #define RX_BUFLEN (ETH_FRAME_LEN + 8)
34 #define TX_TIMEOUT HZ /* 1 second */
36 /* Chip rev needs workaround on HW & multicast addr change */
37 #define BROKEN_ADDRCHG_REV 0x0941
39 /* Bits in transmit DMA status */
40 #define TX_DMA_ERR 0x80
43 volatile struct mace *mace;
44 volatile struct dbdma_regs *tx_dma;
46 volatile struct dbdma_regs *rx_dma;
48 volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */
49 volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */
50 struct sk_buff *rx_bufs[N_RX_RING];
53 struct sk_buff *tx_bufs[N_TX_RING];
57 unsigned char tx_fullup;
58 unsigned char tx_active;
59 unsigned char tx_bad_runt;
60 struct net_device_stats stats;
61 struct timer_list tx_timeout;
65 struct macio_dev *mdev;
70 * Number of bytes of private data per MACE: allow enough for
71 * the rx and tx dma commands plus a branch dma command each,
72 * and another 16 bytes to allow us to align the dma command
73 * buffers on a 16 byte boundary.
75 #define PRIV_BYTES (sizeof(struct mace_data) \
76 + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd))
78 static int bitrev(int);
79 static int mace_open(struct net_device *dev);
80 static int mace_close(struct net_device *dev);
81 static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
82 static struct net_device_stats *mace_stats(struct net_device *dev);
83 static void mace_set_multicast(struct net_device *dev);
84 static void mace_reset(struct net_device *dev);
85 static int mace_set_address(struct net_device *dev, void *addr);
86 static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs);
87 static irqreturn_t mace_txdma_intr(int irq, void *dev_id, struct pt_regs *regs);
88 static irqreturn_t mace_rxdma_intr(int irq, void *dev_id, struct pt_regs *regs);
89 static void mace_set_timeout(struct net_device *dev);
90 static void mace_tx_timeout(unsigned long data);
91 static inline void dbdma_reset(volatile struct dbdma_regs *dma);
92 static inline void mace_clean_rings(struct mace_data *mp);
93 static void __mace_set_address(struct net_device *dev, void *addr);
96 * If we can't get a skbuff when we need it, we use this area for DMA.
98 static unsigned char *dummy_buf;
100 /* Bit-reverse one byte of an ethernet hardware address. */
106 for (i = 0; i < 8; ++i, b >>= 1)
107 d = (d << 1) | (b & 1);
112 static int __devinit mace_probe(struct macio_dev *mdev, const struct of_match *match)
114 struct device_node *mace = macio_get_of_node(mdev);
115 struct net_device *dev;
116 struct mace_data *mp;
118 int j, rev, rc = -EBUSY;
120 if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) {
121 printk(KERN_ERR "can't use MACE %s: need 3 addrs and 3 irqs\n",
126 addr = get_property(mace, "mac-address", NULL);
128 addr = get_property(mace, "local-mac-address", NULL);
130 printk(KERN_ERR "Can't get mac-address for MACE %s\n",
137 * lazy allocate the driver-wide dummy buffer. (Note that we
138 * never have more than one MACE in the system anyway)
140 if (dummy_buf == NULL) {
141 dummy_buf = kmalloc(RX_BUFLEN+2, GFP_KERNEL);
142 if (dummy_buf == NULL) {
143 printk(KERN_ERR "MACE: couldn't allocate dummy buffer\n");
148 if (macio_request_resources(mdev, "mace")) {
149 printk(KERN_ERR "MACE: can't request IO resources !\n");
153 dev = alloc_etherdev(PRIV_BYTES);
155 printk(KERN_ERR "MACE: can't allocate ethernet device !\n");
159 SET_MODULE_OWNER(dev);
160 SET_NETDEV_DEV(dev, &mdev->ofdev.dev);
164 macio_set_drvdata(mdev, dev);
166 dev->base_addr = macio_resource_start(mdev, 0);
167 mp->mace = (volatile struct mace *)ioremap(dev->base_addr, 0x1000);
168 if (mp->mace == NULL) {
169 printk(KERN_ERR "MACE: can't map IO resources !\n");
173 dev->irq = macio_irq(mdev, 0);
175 rev = addr[0] == 0 && addr[1] == 0xA0;
176 for (j = 0; j < 6; ++j) {
177 dev->dev_addr[j] = rev? bitrev(addr[j]): addr[j];
179 mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) |
180 in_8(&mp->mace->chipid_lo);
183 mp = (struct mace_data *) dev->priv;
184 mp->maccc = ENXMT | ENRCV;
186 mp->tx_dma = (volatile struct dbdma_regs *)
187 ioremap(macio_resource_start(mdev, 1), 0x1000);
188 if (mp->tx_dma == NULL) {
189 printk(KERN_ERR "MACE: can't map TX DMA resources !\n");
193 mp->tx_dma_intr = macio_irq(mdev, 1);
195 mp->rx_dma = (volatile struct dbdma_regs *)
196 ioremap(macio_resource_start(mdev, 2), 0x1000);
197 if (mp->rx_dma == NULL) {
198 printk(KERN_ERR "MACE: can't map RX DMA resources !\n");
200 goto err_unmap_tx_dma;
202 mp->rx_dma_intr = macio_irq(mdev, 2);
204 mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1);
205 mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1;
207 memset(&mp->stats, 0, sizeof(mp->stats));
208 memset((char *) mp->tx_cmds, 0,
209 (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd));
210 init_timer(&mp->tx_timeout);
211 spin_lock_init(&mp->lock);
212 mp->timeout_active = 0;
215 mp->port_aaui = port_aaui;
217 /* Apple Network Server uses the AAUI port */
218 if (machine_is_compatible("AAPL,ShinerESB"))
221 #ifdef CONFIG_MACE_AAUI_PORT
229 dev->open = mace_open;
230 dev->stop = mace_close;
231 dev->hard_start_xmit = mace_xmit_start;
232 dev->get_stats = mace_stats;
233 dev->set_multicast_list = mace_set_multicast;
234 dev->set_mac_address = mace_set_address;
237 * Most of what is below could be moved to mace_open()
241 rc = request_irq(dev->irq, mace_interrupt, 0, "MACE", dev);
243 printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq);
244 goto err_unmap_rx_dma;
246 rc = request_irq(mp->tx_dma_intr, mace_txdma_intr, 0, "MACE-txdma", dev);
248 printk(KERN_ERR "MACE: can't get irq %d\n", mace->intrs[1].line);
251 rc = request_irq(mp->rx_dma_intr, mace_rxdma_intr, 0, "MACE-rxdma", dev);
253 printk(KERN_ERR "MACE: can't get irq %d\n", mace->intrs[2].line);
254 goto err_free_tx_irq;
257 rc = register_netdev(dev);
259 printk(KERN_ERR "MACE: Cannot register net device, aborting.\n");
260 goto err_free_rx_irq;
263 printk(KERN_INFO "%s: MACE at", dev->name);
264 for (j = 0; j < 6; ++j) {
265 printk("%c%.2x", (j? ':': ' '), dev->dev_addr[j]);
267 printk(", chip revision %d.%d\n", mp->chipid >> 8, mp->chipid & 0xff);
272 free_irq(macio_irq(mdev, 2), dev);
274 free_irq(macio_irq(mdev, 1), dev);
276 free_irq(macio_irq(mdev, 0), dev);
278 iounmap((void*)mp->rx_dma);
280 iounmap((void*)mp->tx_dma);
282 iounmap((void*)mp->mace);
286 macio_release_resources(mdev);
291 static int __devexit mace_remove(struct macio_dev *mdev)
293 struct net_device *dev = macio_get_drvdata(mdev);
294 struct mace_data *mp;
298 macio_set_drvdata(mdev, NULL);
302 unregister_netdev(dev);
304 free_irq(dev->irq, dev);
305 free_irq(mp->tx_dma_intr, dev);
306 free_irq(mp->rx_dma_intr, dev);
308 iounmap((void*)mp->rx_dma);
309 iounmap((void*)mp->tx_dma);
310 iounmap((void*)mp->mace);
314 macio_release_resources(mdev);
319 static void dbdma_reset(volatile struct dbdma_regs *dma)
323 out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16);
326 * Yes this looks peculiar, but apparently it needs to be this
327 * way on some machines.
329 for (i = 200; i > 0; --i)
330 if (ld_le32(&dma->control) & RUN)
334 static void mace_reset(struct net_device *dev)
336 struct mace_data *mp = (struct mace_data *) dev->priv;
337 volatile struct mace *mb = mp->mace;
340 /* soft-reset the chip */
343 out_8(&mb->biucc, SWRST);
344 if (in_8(&mb->biucc) & SWRST) {
351 printk(KERN_ERR "mace: cannot reset chip!\n");
355 out_8(&mb->imr, 0xff); /* disable all intrs for now */
357 out_8(&mb->maccc, 0); /* turn off tx, rx */
359 out_8(&mb->biucc, XMTSP_64);
360 out_8(&mb->utr, RTRD);
361 out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST);
362 out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */
363 out_8(&mb->rcvfc, 0);
365 /* load up the hardware address */
366 __mace_set_address(dev, dev->dev_addr);
368 /* clear the multicast filter */
369 if (mp->chipid == BROKEN_ADDRCHG_REV)
370 out_8(&mb->iac, LOGADDR);
372 out_8(&mb->iac, ADDRCHG | LOGADDR);
373 while ((in_8(&mb->iac) & ADDRCHG) != 0)
376 for (i = 0; i < 8; ++i)
377 out_8(&mb->ladrf, 0);
379 /* done changing address */
380 if (mp->chipid != BROKEN_ADDRCHG_REV)
384 out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO);
386 out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO);
389 static void __mace_set_address(struct net_device *dev, void *addr)
391 struct mace_data *mp = (struct mace_data *) dev->priv;
392 volatile struct mace *mb = mp->mace;
393 unsigned char *p = addr;
396 /* load up the hardware address */
397 if (mp->chipid == BROKEN_ADDRCHG_REV)
398 out_8(&mb->iac, PHYADDR);
400 out_8(&mb->iac, ADDRCHG | PHYADDR);
401 while ((in_8(&mb->iac) & ADDRCHG) != 0)
404 for (i = 0; i < 6; ++i)
405 out_8(&mb->padr, dev->dev_addr[i] = p[i]);
406 if (mp->chipid != BROKEN_ADDRCHG_REV)
410 static int mace_set_address(struct net_device *dev, void *addr)
412 struct mace_data *mp = (struct mace_data *) dev->priv;
413 volatile struct mace *mb = mp->mace;
416 spin_lock_irqsave(&mp->lock, flags);
418 __mace_set_address(dev, addr);
420 /* note: setting ADDRCHG clears ENRCV */
421 out_8(&mb->maccc, mp->maccc);
423 spin_unlock_irqrestore(&mp->lock, flags);
427 static inline void mace_clean_rings(struct mace_data *mp)
431 /* free some skb's */
432 for (i = 0; i < N_RX_RING; ++i) {
433 if (mp->rx_bufs[i] != 0) {
434 dev_kfree_skb(mp->rx_bufs[i]);
438 for (i = mp->tx_empty; i != mp->tx_fill; ) {
439 dev_kfree_skb(mp->tx_bufs[i]);
440 if (++i >= N_TX_RING)
445 static int mace_open(struct net_device *dev)
447 struct mace_data *mp = (struct mace_data *) dev->priv;
448 volatile struct mace *mb = mp->mace;
449 volatile struct dbdma_regs *rd = mp->rx_dma;
450 volatile struct dbdma_regs *td = mp->tx_dma;
451 volatile struct dbdma_cmd *cp;
459 /* initialize list of sk_buffs for receiving and set up recv dma */
460 mace_clean_rings(mp);
461 memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd));
463 for (i = 0; i < N_RX_RING - 1; ++i) {
464 skb = dev_alloc_skb(RX_BUFLEN + 2);
468 skb_reserve(skb, 2); /* so IP header lands on 4-byte bdry */
471 mp->rx_bufs[i] = skb;
472 st_le16(&cp->req_count, RX_BUFLEN);
473 st_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
474 st_le32(&cp->phy_addr, virt_to_bus(data));
479 st_le16(&cp->command, DBDMA_STOP);
483 /* Put a branch back to the beginning of the receive command list */
485 st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS);
486 st_le32(&cp->cmd_dep, virt_to_bus(mp->rx_cmds));
489 out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
490 out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds));
491 out_le32(&rd->control, (RUN << 16) | RUN);
493 /* put a branch at the end of the tx command list */
494 cp = mp->tx_cmds + NCMDS_TX * N_TX_RING;
495 st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS);
496 st_le32(&cp->cmd_dep, virt_to_bus(mp->tx_cmds));
499 out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16);
500 out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds));
508 out_8(&mb->maccc, mp->maccc);
509 /* enable all interrupts except receive interrupts */
510 out_8(&mb->imr, RCVINT);
515 static int mace_close(struct net_device *dev)
517 struct mace_data *mp = (struct mace_data *) dev->priv;
518 volatile struct mace *mb = mp->mace;
519 volatile struct dbdma_regs *rd = mp->rx_dma;
520 volatile struct dbdma_regs *td = mp->tx_dma;
522 /* disable rx and tx */
523 out_8(&mb->maccc, 0);
524 out_8(&mb->imr, 0xff); /* disable all intrs */
526 /* disable rx and tx dma */
527 st_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
528 st_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */
530 mace_clean_rings(mp);
535 static inline void mace_set_timeout(struct net_device *dev)
537 struct mace_data *mp = (struct mace_data *) dev->priv;
539 if (mp->timeout_active)
540 del_timer(&mp->tx_timeout);
541 mp->tx_timeout.expires = jiffies + TX_TIMEOUT;
542 mp->tx_timeout.function = mace_tx_timeout;
543 mp->tx_timeout.data = (unsigned long) dev;
544 add_timer(&mp->tx_timeout);
545 mp->timeout_active = 1;
548 static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
550 struct mace_data *mp = (struct mace_data *) dev->priv;
551 volatile struct dbdma_regs *td = mp->tx_dma;
552 volatile struct dbdma_cmd *cp, *np;
556 /* see if there's a free slot in the tx ring */
557 spin_lock_irqsave(&mp->lock, flags);
560 if (next >= N_TX_RING)
562 if (next == mp->tx_empty) {
563 netif_stop_queue(dev);
565 spin_unlock_irqrestore(&mp->lock, flags);
566 return 1; /* can't take it at the moment */
568 spin_unlock_irqrestore(&mp->lock, flags);
570 /* partially fill in the dma command block */
572 if (len > ETH_FRAME_LEN) {
573 printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len);
576 mp->tx_bufs[fill] = skb;
577 cp = mp->tx_cmds + NCMDS_TX * fill;
578 st_le16(&cp->req_count, len);
579 st_le32(&cp->phy_addr, virt_to_bus(skb->data));
581 np = mp->tx_cmds + NCMDS_TX * next;
582 out_le16(&np->command, DBDMA_STOP);
584 /* poke the tx dma channel */
585 spin_lock_irqsave(&mp->lock, flags);
587 if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) {
588 out_le16(&cp->xfer_status, 0);
589 out_le16(&cp->command, OUTPUT_LAST);
590 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
592 mace_set_timeout(dev);
594 if (++next >= N_TX_RING)
596 if (next == mp->tx_empty)
597 netif_stop_queue(dev);
598 spin_unlock_irqrestore(&mp->lock, flags);
603 static struct net_device_stats *mace_stats(struct net_device *dev)
605 struct mace_data *p = (struct mace_data *) dev->priv;
610 static void mace_set_multicast(struct net_device *dev)
612 struct mace_data *mp = (struct mace_data *) dev->priv;
613 volatile struct mace *mb = mp->mace;
618 spin_lock_irqsave(&mp->lock, flags);
620 if (dev->flags & IFF_PROMISC) {
623 unsigned char multicast_filter[8];
624 struct dev_mc_list *dmi = dev->mc_list;
626 if (dev->flags & IFF_ALLMULTI) {
627 for (i = 0; i < 8; i++)
628 multicast_filter[i] = 0xff;
630 for (i = 0; i < 8; i++)
631 multicast_filter[i] = 0;
632 for (i = 0; i < dev->mc_count; i++) {
633 crc = ether_crc_le(6, dmi->dmi_addr);
634 j = crc >> 26; /* bit number in multicast_filter */
635 multicast_filter[j >> 3] |= 1 << (j & 7);
640 printk("Multicast filter :");
641 for (i = 0; i < 8; i++)
642 printk("%02x ", multicast_filter[i]);
646 if (mp->chipid == BROKEN_ADDRCHG_REV)
647 out_8(&mb->iac, LOGADDR);
649 out_8(&mb->iac, ADDRCHG | LOGADDR);
650 while ((in_8(&mb->iac) & ADDRCHG) != 0)
653 for (i = 0; i < 8; ++i)
654 out_8(&mb->ladrf, multicast_filter[i]);
655 if (mp->chipid != BROKEN_ADDRCHG_REV)
659 out_8(&mb->maccc, mp->maccc);
660 spin_unlock_irqrestore(&mp->lock, flags);
663 static void mace_handle_misc_intrs(struct mace_data *mp, int intr)
665 volatile struct mace *mb = mp->mace;
666 static int mace_babbles, mace_jabbers;
669 mp->stats.rx_missed_errors += 256;
670 mp->stats.rx_missed_errors += in_8(&mb->mpc); /* reading clears it */
672 mp->stats.rx_length_errors += 256;
673 mp->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */
675 ++mp->stats.tx_heartbeat_errors;
677 if (mace_babbles++ < 4)
678 printk(KERN_DEBUG "mace: babbling transmitter\n");
680 if (mace_jabbers++ < 4)
681 printk(KERN_DEBUG "mace: jabbering transceiver\n");
684 static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs)
686 struct net_device *dev = (struct net_device *) dev_id;
687 struct mace_data *mp = (struct mace_data *) dev->priv;
688 volatile struct mace *mb = mp->mace;
689 volatile struct dbdma_regs *td = mp->tx_dma;
690 volatile struct dbdma_cmd *cp;
691 int intr, fs, i, stat, x;
694 /* static int mace_last_fs, mace_last_xcount; */
696 spin_lock_irqsave(&mp->lock, flags);
697 intr = in_8(&mb->ir); /* read interrupt register */
698 in_8(&mb->xmtrc); /* get retries */
699 mace_handle_misc_intrs(mp, intr);
702 while (in_8(&mb->pr) & XMTSV) {
703 del_timer(&mp->tx_timeout);
704 mp->timeout_active = 0;
706 * Clear any interrupt indication associated with this status
707 * word. This appears to unlatch any error indication from
708 * the DMA controller.
710 intr = in_8(&mb->ir);
712 mace_handle_misc_intrs(mp, intr);
713 if (mp->tx_bad_runt) {
714 fs = in_8(&mb->xmtfs);
716 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
719 dstat = ld_le32(&td->status);
720 /* stop DMA controller */
721 out_le32(&td->control, RUN << 16);
723 * xcount is the number of complete frames which have been
724 * written to the fifo but for which status has not been read.
726 xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
727 if (xcount == 0 || (dstat & DEAD)) {
729 * If a packet was aborted before the DMA controller has
730 * finished transferring it, it seems that there are 2 bytes
731 * which are stuck in some buffer somewhere. These will get
732 * transmitted as soon as we read the frame status (which
733 * reenables the transmit data transfer request). Turning
734 * off the DMA controller and/or resetting the MACE doesn't
735 * help. So we disable auto-padding and FCS transmission
736 * so the two bytes will only be a runt packet which should
737 * be ignored by other stations.
739 out_8(&mb->xmtfc, DXMTFCS);
741 fs = in_8(&mb->xmtfs);
742 if ((fs & XMTSV) == 0) {
743 printk(KERN_ERR "mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n",
747 * XXX mace likes to hang the machine after a xmtfs error.
748 * This is hard to reproduce, reseting *may* help
751 cp = mp->tx_cmds + NCMDS_TX * i;
752 stat = ld_le16(&cp->xfer_status);
753 if ((fs & (UFLO|LCOL|LCAR|RTRY)) || (dstat & DEAD) || xcount == 0) {
755 * Check whether there were in fact 2 bytes written to
759 x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK;
761 /* there were two bytes with an end-of-packet indication */
763 mace_set_timeout(dev);
766 * Either there weren't the two bytes buffered up, or they
767 * didn't have an end-of-packet indication.
768 * We flush the transmit FIFO just in case (by setting the
769 * XMTFWU bit with the transmitter disabled).
771 out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT);
772 out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU);
774 out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT);
775 out_8(&mb->xmtfc, AUTO_PAD_XMIT);
778 /* dma should have finished */
779 if (i == mp->tx_fill) {
780 printk(KERN_DEBUG "mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n",
785 if (fs & (UFLO|LCOL|LCAR|RTRY)) {
786 ++mp->stats.tx_errors;
788 ++mp->stats.tx_carrier_errors;
789 if (fs & (UFLO|LCOL|RTRY))
790 ++mp->stats.tx_aborted_errors;
792 mp->stats.tx_bytes += mp->tx_bufs[i]->len;
793 ++mp->stats.tx_packets;
795 dev_kfree_skb_irq(mp->tx_bufs[i]);
797 if (++i >= N_TX_RING)
801 mace_last_xcount = xcount;
805 if (i != mp->tx_empty) {
807 netif_wake_queue(dev);
813 if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) {
815 /* set up the next one */
816 cp = mp->tx_cmds + NCMDS_TX * i;
817 out_le16(&cp->xfer_status, 0);
818 out_le16(&cp->command, OUTPUT_LAST);
820 if (++i >= N_TX_RING)
822 } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE);
823 out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE));
824 mace_set_timeout(dev);
826 spin_unlock_irqrestore(&mp->lock, flags);
830 static void mace_tx_timeout(unsigned long data)
832 struct net_device *dev = (struct net_device *) data;
833 struct mace_data *mp = (struct mace_data *) dev->priv;
834 volatile struct mace *mb = mp->mace;
835 volatile struct dbdma_regs *td = mp->tx_dma;
836 volatile struct dbdma_regs *rd = mp->rx_dma;
837 volatile struct dbdma_cmd *cp;
841 spin_lock_irqsave(&mp->lock, flags);
842 mp->timeout_active = 0;
843 if (mp->tx_active == 0 && !mp->tx_bad_runt)
846 /* update various counters */
847 mace_handle_misc_intrs(mp, in_8(&mb->ir));
849 cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty;
851 /* turn off both tx and rx and reset the chip */
852 out_8(&mb->maccc, 0);
853 printk(KERN_ERR "mace: transmit timeout - resetting\n");
858 cp = bus_to_virt(ld_le32(&rd->cmdptr));
860 out_le16(&cp->xfer_status, 0);
861 out_le32(&rd->cmdptr, virt_to_bus(cp));
862 out_le32(&rd->control, (RUN << 16) | RUN);
864 /* fix up the transmit side */
867 ++mp->stats.tx_errors;
868 if (mp->tx_bad_runt) {
870 } else if (i != mp->tx_fill) {
871 dev_kfree_skb(mp->tx_bufs[i]);
872 if (++i >= N_TX_RING)
877 netif_wake_queue(dev);
878 if (i != mp->tx_fill) {
879 cp = mp->tx_cmds + NCMDS_TX * i;
880 out_le16(&cp->xfer_status, 0);
881 out_le16(&cp->command, OUTPUT_LAST);
882 out_le32(&td->cmdptr, virt_to_bus(cp));
883 out_le32(&td->control, (RUN << 16) | RUN);
885 mace_set_timeout(dev);
888 /* turn it back on */
889 out_8(&mb->imr, RCVINT);
890 out_8(&mb->maccc, mp->maccc);
893 spin_unlock_irqrestore(&mp->lock, flags);
896 static irqreturn_t mace_txdma_intr(int irq, void *dev_id, struct pt_regs *regs)
901 static irqreturn_t mace_rxdma_intr(int irq, void *dev_id, struct pt_regs *regs)
903 struct net_device *dev = (struct net_device *) dev_id;
904 struct mace_data *mp = (struct mace_data *) dev->priv;
905 volatile struct dbdma_regs *rd = mp->rx_dma;
906 volatile struct dbdma_cmd *cp, *np;
907 int i, nb, stat, next;
909 unsigned frame_status;
910 static int mace_lost_status;
914 spin_lock_irqsave(&mp->lock, flags);
915 for (i = mp->rx_empty; i != mp->rx_fill; ) {
916 cp = mp->rx_cmds + i;
917 stat = ld_le16(&cp->xfer_status);
918 if ((stat & ACTIVE) == 0) {
920 if (next >= N_RX_RING)
922 np = mp->rx_cmds + next;
923 if (next != mp->rx_fill
924 && (ld_le16(&np->xfer_status) & ACTIVE) != 0) {
925 printk(KERN_DEBUG "mace: lost a status word\n");
930 nb = ld_le16(&cp->req_count) - ld_le16(&cp->res_count);
931 out_le16(&cp->command, DBDMA_STOP);
932 /* got a packet, have a look at it */
933 skb = mp->rx_bufs[i];
935 ++mp->stats.rx_dropped;
938 frame_status = (data[nb-3] << 8) + data[nb-4];
939 if (frame_status & (RS_OFLO|RS_CLSN|RS_FRAMERR|RS_FCSERR)) {
940 ++mp->stats.rx_errors;
941 if (frame_status & RS_OFLO)
942 ++mp->stats.rx_over_errors;
943 if (frame_status & RS_FRAMERR)
944 ++mp->stats.rx_frame_errors;
945 if (frame_status & RS_FCSERR)
946 ++mp->stats.rx_crc_errors;
948 /* Mace feature AUTO_STRIP_RCV is on by default, dropping the
949 * FCS on frames with 802.3 headers. This means that Ethernet
950 * frames have 8 extra octets at the end, while 802.3 frames
951 * have only 4. We need to correctly account for this. */
952 if (*(unsigned short *)(data+12) < 1536) /* 802.3 header */
954 else /* Ethernet header; mace includes FCS */
958 skb->protocol = eth_type_trans(skb, dev);
959 mp->stats.rx_bytes += skb->len;
961 dev->last_rx = jiffies;
963 ++mp->stats.rx_packets;
966 ++mp->stats.rx_errors;
967 ++mp->stats.rx_length_errors;
970 /* advance to next */
971 if (++i >= N_RX_RING)
979 if (next >= N_RX_RING)
981 if (next == mp->rx_empty)
983 cp = mp->rx_cmds + i;
984 skb = mp->rx_bufs[i];
986 skb = dev_alloc_skb(RX_BUFLEN + 2);
989 mp->rx_bufs[i] = skb;
992 st_le16(&cp->req_count, RX_BUFLEN);
993 data = skb? skb->data: dummy_buf;
994 st_le32(&cp->phy_addr, virt_to_bus(data));
995 out_le16(&cp->xfer_status, 0);
996 out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS);
998 if ((ld_le32(&rd->status) & ACTIVE) != 0) {
999 out_le32(&rd->control, (PAUSE << 16) | PAUSE);
1000 while ((in_le32(&rd->status) & ACTIVE) != 0)
1006 if (i != mp->rx_fill) {
1007 out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE));
1010 spin_unlock_irqrestore(&mp->lock, flags);
1014 static struct of_match mace_match[] =
1018 .type = OF_ANY_MATCH,
1019 .compatible = OF_ANY_MATCH
1024 static struct macio_driver mace_driver =
1027 .match_table = mace_match,
1028 .probe = mace_probe,
1029 .remove = mace_remove,
1033 static int __init mace_init(void)
1035 return macio_register_driver(&mace_driver);
1038 static void __exit mace_cleanup(void)
1040 macio_unregister_driver(&mace_driver);
1048 MODULE_AUTHOR("Paul Mackerras");
1049 MODULE_DESCRIPTION("PowerMac MACE driver.");
1050 MODULE_PARM(port_aaui, "i");
1051 MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)");
1052 MODULE_LICENSE("GPL");
1054 module_init(mace_init);
1055 module_exit(mace_cleanup);