2 * meth.c -- O2 Builtin 10/100 Ethernet driver
4 * Copyright (C) 2001-2003 Ilya Volynets
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/module.h>
12 #include <linux/init.h>
14 #include <linux/sched.h>
15 #include <linux/kernel.h> /* printk() */
16 #include <linux/delay.h>
17 #include <linux/slab.h>
18 #include <linux/errno.h> /* error codes */
19 #include <linux/types.h> /* size_t */
20 #include <linux/interrupt.h> /* mark_bh */
23 #include <linux/in6.h>
24 #include <linux/device.h> /* struct device, et al */
25 #include <linux/netdevice.h> /* struct device, and other headers */
26 #include <linux/etherdevice.h> /* eth_type_trans */
27 #include <linux/ip.h> /* struct iphdr */
28 #include <linux/tcp.h> /* struct tcphdr */
29 #include <linux/skbuff.h>
30 #include <linux/mii.h> /*MII definitions */
32 #include <asm/ip32/mace.h>
33 #include <asm/ip32/ip32_ints.h>
36 #include <asm/checksum.h>
37 #include <asm/scatterlist.h>
38 #include <linux/dma-mapping.h>
47 #define DPRINTK(str,args...) printk(KERN_DEBUG "meth: %s: " str, __FUNCTION__ , ## args)
48 #define MFE_RX_DEBUG 2
50 #define DPRINTK(str,args...)
51 #define MFE_RX_DEBUG 0
55 static const char *meth_str="SGI O2 Fast Ethernet";
56 MODULE_AUTHOR("Ilya Volynets <ilya@theIlya.com>");
57 MODULE_DESCRIPTION("SGI O2 Builtin Fast Ethernet driver");
59 #define HAVE_TX_TIMEOUT
60 /* The maximum time waited (in jiffies) before assuming a Tx failed. (400ms) */
61 #define TX_TIMEOUT (400*HZ/1000)
63 #ifdef HAVE_TX_TIMEOUT
64 static int timeout = TX_TIMEOUT;
65 MODULE_PARM(timeout, "i");
69 * This structure is private to each device. It is used to pass
70 * packets in and out, so there is place for a packet
73 struct net_device_stats stats;
74 /* in-memory copy of MAC Control register */
75 unsigned long mac_ctrl;
76 /* in-memory copy of DMA Control register */
77 unsigned long dma_ctrl;
78 /* address of PHY, used by mdio_* functions, initialized in mdio_probe */
79 unsigned long phy_addr;
81 dma_addr_t tx_ring_dma;
82 struct sk_buff *tx_skbs[TX_RING_ENTRIES];
83 dma_addr_t tx_skb_dmas[TX_RING_ENTRIES];
84 unsigned long tx_read, tx_write, tx_count;
86 rx_packet *rx_ring[RX_RING_ENTRIES];
87 dma_addr_t rx_ring_dmas[RX_RING_ENTRIES];
88 struct sk_buff *rx_skbs[RX_RING_ENTRIES];
89 unsigned long rx_write;
94 static void meth_tx_timeout(struct net_device *dev);
95 static irqreturn_t meth_interrupt(int irq, void *dev_id, struct pt_regs *pregs);
97 /* global, initialized in ip32-setup.c */
98 char o2meth_eaddr[8]={0,0,0,0,0,0,0,0};
100 static inline void load_eaddr(struct net_device *dev)
103 DPRINTK("Loading MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n",
104 (int)o2meth_eaddr[0]&0xFF,(int)o2meth_eaddr[1]&0xFF,(int)o2meth_eaddr[2]&0xFF,
105 (int)o2meth_eaddr[3]&0xFF,(int)o2meth_eaddr[4]&0xFF,(int)o2meth_eaddr[5]&0xFF);
106 for (i = 0; i < 6; i++)
107 dev->dev_addr[i] = o2meth_eaddr[i];
108 mace_eth_write((*(u64*)o2meth_eaddr)>>16, mac_addr);
112 * Waits for BUSY status of mdio bus to clear
114 #define WAIT_FOR_PHY(___rval) \
115 while ((___rval = mace_eth_read(phy_data)) & MDIO_BUSY) { \
118 /*read phy register, return value read */
119 static unsigned long mdio_read(struct meth_private *priv, unsigned long phyreg)
123 mace_eth_write((priv->phy_addr << 5) | (phyreg & 0x1f), phy_regs);
125 mace_eth_write(1, phy_trans_go);
128 return rval&MDIO_DATA_MASK;
131 static int mdio_probe(struct meth_private *priv)
134 unsigned long p2, p3;
135 /* check if phy is detected already */
136 if(priv->phy_addr>=0&&priv->phy_addr<32)
138 spin_lock(&priv->meth_lock);
141 p2=mdio_read(priv,2);
142 p3=mdio_read(priv,3);
144 switch ((p2<<12)|(p3>>4)){
146 DPRINTK("PHY is QS6612X\n");
149 DPRINTK("PHY is ICS1889\n");
152 DPRINTK("PHY is ICS1890\n");
155 DPRINTK("PHY is DP83840\n");
159 if(p2!=0xffff&&p2!=0x0000){
160 DPRINTK("PHY code: %x\n",(p2<<12)|(p3>>4));
164 spin_unlock(&priv->meth_lock);
165 if(priv->phy_addr<32) {
168 DPRINTK("Oopsie! PHY is not known!\n");
173 static void meth_check_link(struct net_device *dev)
175 struct meth_private *priv = (struct meth_private *) dev->priv;
176 unsigned long mii_advertising = mdio_read(priv, 4);
177 unsigned long mii_partner = mdio_read(priv, 5);
178 unsigned long negotiated = mii_advertising & mii_partner;
179 unsigned long duplex, speed;
181 if (mii_partner == 0xffff)
184 speed = (negotiated & 0x0380) ? METH_100MBIT : 0;
185 duplex = ((negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040) ?
188 if ((priv->mac_ctrl & METH_PHY_FDX) ^ duplex) {
189 DPRINTK("Setting %s-duplex\n", duplex ? "full" : "half");
191 priv->mac_ctrl |= METH_PHY_FDX;
193 priv->mac_ctrl &= ~METH_PHY_FDX;
194 mace_eth_write(priv->mac_ctrl, mac_ctrl);
197 if ((priv->mac_ctrl & METH_100MBIT) ^ speed) {
198 DPRINTK("Setting %dMbs mode\n", speed ? 100 : 10);
200 priv->mac_ctrl |= METH_100MBIT;
202 priv->mac_ctrl &= ~METH_100MBIT;
203 mace_eth_write(priv->mac_ctrl, mac_ctrl);
208 static int meth_init_tx_ring(struct meth_private *priv)
211 priv->tx_ring = dma_alloc_coherent(NULL, TX_RING_BUFFER_SIZE,
212 &priv->tx_ring_dma, GFP_ATOMIC);
215 memset(priv->tx_ring, 0, TX_RING_BUFFER_SIZE);
216 priv->tx_count = priv->tx_read = priv->tx_write = 0;
217 mace_eth_write(priv->tx_ring_dma, tx_ring_base);
218 /* Now init skb save area */
219 memset(priv->tx_skbs,0,sizeof(priv->tx_skbs));
220 memset(priv->tx_skb_dmas,0,sizeof(priv->tx_skb_dmas));
224 static int meth_init_rx_ring(struct meth_private *priv)
227 for(i=0;i<RX_RING_ENTRIES;i++){
228 priv->rx_skbs[i]=alloc_skb(METH_RX_BUFF_SIZE,0);
229 /* 8byte status vector+3quad padding + 2byte padding,
230 to put data on 64bit aligned boundary */
231 skb_reserve(priv->rx_skbs[i],METH_RX_HEAD);
232 priv->rx_ring[i]=(rx_packet*)(priv->rx_skbs[i]->head);
233 /* I'll need to re-sync it after each RX */
234 priv->rx_ring_dmas[i]=dma_map_single(NULL,priv->rx_ring[i],
235 METH_RX_BUFF_SIZE,DMA_FROM_DEVICE);
236 mace_eth_write(priv->rx_ring_dmas[i], rx_fifo);
241 static void meth_free_tx_ring(struct meth_private *priv)
245 /* Remove any pending skb */
246 for (i = 0; i < TX_RING_ENTRIES; i++) {
247 if (priv->tx_skbs[i])
248 dev_kfree_skb(priv->tx_skbs[i]);
249 priv->tx_skbs[i] = NULL;
251 dma_free_coherent(NULL, TX_RING_BUFFER_SIZE, priv->tx_ring,
255 /* Presumes RX DMA engine is stopped, and RX fifo ring is reset */
256 static void meth_free_rx_ring(struct meth_private *priv)
260 for(i=0;i<RX_RING_ENTRIES;i++) {
261 dma_unmap_single(NULL,priv->rx_ring_dmas[i],METH_RX_BUFF_SIZE,DMA_FROM_DEVICE);
263 priv->rx_ring_dmas[i]=0;
264 kfree_skb(priv->rx_skbs[i]);
268 int meth_reset(struct net_device *dev)
270 struct meth_private *priv = (struct meth_private *) dev->priv;
273 mace_eth_write(SGI_MAC_RESET, mac_ctrl);
274 mace_eth_write(0, mac_ctrl);
277 /* Load ethernet address */
279 /* Should load some "errata", but later */
281 /* Check for device */
282 if(mdio_probe(priv) < 0) {
283 DPRINTK("Unable to find PHY\n");
287 /* Initial mode: 10 | Half-duplex | Accept normal packets */
288 priv->mac_ctrl = METH_ACCEPT_MCAST | METH_DEFAULT_IPG;
289 if(dev->flags | IFF_PROMISC)
290 priv->mac_ctrl |= METH_PROMISC;
291 mace_eth_write(priv->mac_ctrl, mac_ctrl);
293 /* Autonegotiate speed and duplex mode */
294 meth_check_link(dev);
296 /* Now set dma control, but don't enable DMA, yet */
297 priv->dma_ctrl= (4 << METH_RX_OFFSET_SHIFT) |
298 (RX_RING_ENTRIES << METH_RX_DEPTH_SHIFT);
299 mace_eth_write(priv->dma_ctrl, dma_ctrl);
304 /*============End Helper Routines=====================*/
309 static int meth_open(struct net_device *dev)
311 struct meth_private *priv = dev->priv;
314 priv->phy_addr = -1; /* No PHY is known yet... */
316 /* Initialize the hardware */
317 ret = meth_reset(dev);
321 /* Allocate the ring buffers */
322 ret = meth_init_tx_ring(priv);
325 ret = meth_init_rx_ring(priv);
327 goto out_free_tx_ring;
329 ret = request_irq(dev->irq, meth_interrupt, 0, meth_str, dev);
331 printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
332 goto out_free_rx_ring;
336 priv->dma_ctrl |= METH_DMA_TX_EN | /*METH_DMA_TX_INT_EN |*/
337 METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
338 mace_eth_write(priv->dma_ctrl, dma_ctrl);
340 DPRINTK("About to start queue\n");
341 netif_start_queue(dev);
346 meth_free_rx_ring(priv);
348 meth_free_tx_ring(priv);
353 static int meth_release(struct net_device *dev)
355 struct meth_private *priv = dev->priv;
357 DPRINTK("Stopping queue\n");
358 netif_stop_queue(dev); /* can't transmit any more */
360 priv->dma_ctrl &= ~(METH_DMA_TX_EN | METH_DMA_TX_INT_EN |
361 METH_DMA_RX_EN | METH_DMA_RX_INT_EN);
362 mace_eth_write(priv->dma_ctrl, dma_ctrl);
363 free_irq(dev->irq, dev);
364 meth_free_tx_ring(priv);
365 meth_free_rx_ring(priv);
371 * Receive a packet: retrieve, encapsulate and pass over to upper levels
373 static void meth_rx(struct net_device* dev, unsigned long int_status)
376 struct meth_private *priv = (struct meth_private *) dev->priv;
377 unsigned long fifo_rptr=(int_status&METH_INT_RX_RPTR_MASK)>>8;
378 spin_lock(&priv->meth_lock);
379 priv->dma_ctrl&=~METH_DMA_RX_INT_EN;
380 mace_eth_write(priv->dma_ctrl, dma_ctrl);
381 spin_unlock(&priv->meth_lock);
383 if (int_status & METH_INT_RX_UNDERFLOW){
384 fifo_rptr=(fifo_rptr-1)&(0xF);
386 while(priv->rx_write != fifo_rptr) {
388 dma_unmap_single(NULL,priv->rx_ring_dmas[priv->rx_write],
389 METH_RX_BUFF_SIZE,DMA_FROM_DEVICE);
390 status=priv->rx_ring[priv->rx_write]->status.raw;
392 if(!(status&METH_RX_ST_VALID)) {
393 DPRINTK("Not received? status=%016lx\n",status);
396 if((!(status&METH_RX_STATUS_ERRORS))&&(status&METH_RX_ST_VALID)){
397 int len=(status&0xFFFF) - 4; /* omit CRC */
398 /* length sanity check */
399 if(len < 60 || len > 1518) {
400 printk(KERN_DEBUG "%s: bogus packet size: %d, status=%#2lx.\n",
401 dev->name, priv->rx_write,
402 priv->rx_ring[priv->rx_write]->status.raw);
403 priv->stats.rx_errors++;
404 priv->stats.rx_length_errors++;
405 skb=priv->rx_skbs[priv->rx_write];
407 skb=alloc_skb(METH_RX_BUFF_SIZE,GFP_ATOMIC|GFP_DMA);
409 /* Ouch! No memory! Drop packet on the floor */
410 DPRINTK("No mem: dropping packet\n");
411 priv->stats.rx_dropped++;
412 skb=priv->rx_skbs[priv->rx_write];
414 struct sk_buff *skb_c=priv->rx_skbs[priv->rx_write];
415 /* 8byte status vector+3quad padding + 2byte padding,
416 to put data on 64bit aligned boundary */
417 skb_reserve(skb,METH_RX_HEAD);
418 /* Write metadata, and then pass to the receive level */
420 priv->rx_skbs[priv->rx_write]=skb;
422 skb_c->protocol = eth_type_trans(skb_c, dev);
423 dev->last_rx = jiffies;
424 priv->stats.rx_packets++;
425 priv->stats.rx_bytes+=len;
430 priv->stats.rx_errors++;
431 skb=priv->rx_skbs[priv->rx_write];
433 printk(KERN_WARNING "meth: RX error: status=0x%016lx\n",status);
434 if(status&METH_RX_ST_RCV_CODE_VIOLATION)
435 printk(KERN_WARNING "Receive Code Violation\n");
436 if(status&METH_RX_ST_CRC_ERR)
437 printk(KERN_WARNING "CRC error\n");
438 if(status&METH_RX_ST_INV_PREAMBLE_CTX)
439 printk(KERN_WARNING "Invalid Preamble Context\n");
440 if(status&METH_RX_ST_LONG_EVT_SEEN)
441 printk(KERN_WARNING "Long Event Seen...\n");
442 if(status&METH_RX_ST_BAD_PACKET)
443 printk(KERN_WARNING "Bad Packet\n");
444 if(status&METH_RX_ST_CARRIER_EVT_SEEN)
445 printk(KERN_WARNING "Carrier Event Seen\n");
448 priv->rx_ring[priv->rx_write]=(rx_packet*)skb->head;
449 priv->rx_ring[priv->rx_write]->status.raw=0;
450 priv->rx_ring_dmas[priv->rx_write]=dma_map_single(NULL,priv->rx_ring[priv->rx_write],
451 METH_RX_BUFF_SIZE,DMA_FROM_DEVICE);
452 mace_eth_write(priv->rx_ring_dmas[priv->rx_write], rx_fifo);
453 ADVANCE_RX_PTR(priv->rx_write);
455 spin_lock(&priv->meth_lock);
456 /* In case there was underflow, and Rx DMA was disabled */
457 priv->dma_ctrl|=METH_DMA_RX_INT_EN|METH_DMA_RX_EN;
458 mace_eth_write(priv->dma_ctrl, dma_ctrl);
459 mace_eth_write(METH_INT_RX_THRESHOLD, int_stat);
460 spin_unlock(&priv->meth_lock);
463 static int meth_tx_full(struct net_device *dev)
465 struct meth_private *priv = (struct meth_private *) dev->priv;
467 return(priv->tx_count >= TX_RING_ENTRIES-1);
470 static void meth_tx_cleanup(struct net_device* dev, unsigned long int_status)
472 struct meth_private *priv = dev->priv;
475 unsigned long rptr=(int_status&TX_INFO_RPTR)>>16;
477 spin_lock(&priv->meth_lock);
479 /* Stop DMA notification */
480 priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
481 mace_eth_write(priv->dma_ctrl, dma_ctrl);
483 while(priv->tx_read != rptr){
484 skb = priv->tx_skbs[priv->tx_read];
485 status = priv->tx_ring[priv->tx_read].header.raw;
487 if(priv->tx_read==priv->tx_write)
488 DPRINTK("Auchi! tx_read=%d,tx_write=%d,rptr=%d?\n",priv->tx_read,priv->tx_write,rptr);
490 if(status & METH_TX_ST_DONE) {
491 if(status & METH_TX_ST_SUCCESS){
492 priv->stats.tx_packets++;
493 priv->stats.tx_bytes += skb->len;
495 priv->stats.tx_errors++;
497 DPRINTK("TX error: status=%016lx <",status);
498 if(status & METH_TX_ST_SUCCESS)
500 if(status & METH_TX_ST_TOOLONG)
502 if(status & METH_TX_ST_UNDERRUN)
504 if(status & METH_TX_ST_EXCCOLL)
506 if(status & METH_TX_ST_DEFER)
508 if(status & METH_TX_ST_LATECOLL)
514 DPRINTK("RPTR points us here, but packet not done?\n");
517 dev_kfree_skb_irq(skb);
518 priv->tx_skbs[priv->tx_read] = NULL;
519 priv->tx_ring[priv->tx_read].header.raw = 0;
520 priv->tx_read = (priv->tx_read+1)&(TX_RING_ENTRIES-1);
524 /* wake up queue if it was stopped */
525 if (netif_queue_stopped(dev) && ! meth_tx_full(dev)) {
526 netif_wake_queue(dev);
529 mace_eth_write(METH_INT_TX_EMPTY | METH_INT_TX_PKT, int_stat);
530 spin_unlock(&priv->meth_lock);
533 static void meth_error(struct net_device* dev, u32 status)
535 struct meth_private *priv = (struct meth_private *) dev->priv;
537 printk(KERN_WARNING "meth: error status: 0x%08x\n",status);
538 /* check for errors too... */
539 if (status & (METH_INT_TX_LINK_FAIL))
540 printk(KERN_WARNING "meth: link failure\n");
541 /* Should I do full reset in this case? */
542 if (status & (METH_INT_MEM_ERROR))
543 printk(KERN_WARNING "meth: memory error\n");
544 if (status & (METH_INT_TX_ABORT))
545 printk(KERN_WARNING "meth: aborted\n");
546 if (status & (METH_INT_RX_OVERFLOW))
547 printk(KERN_WARNING "meth: Rx overflow\n");
548 if (status & (METH_INT_RX_UNDERFLOW)) {
549 printk(KERN_WARNING "meth: Rx underflow\n");
550 spin_lock(&priv->meth_lock);
551 mace_eth_write(METH_INT_RX_UNDERFLOW, int_stat);
552 /* more underflow interrupts will be delivered,
553 effectively throwing us into an infinite loop.
554 Thus I stop processing Rx in this case.
556 priv->dma_ctrl&=~METH_DMA_RX_EN;
557 mace_eth_write(priv->dma_ctrl, dma_ctrl);
558 DPRINTK("Disabled meth Rx DMA temporarily\n");
559 spin_unlock(&priv->meth_lock);
561 mace_eth_write(METH_INT_ERROR, int_stat);
565 * The typical interrupt entry point
567 static irqreturn_t meth_interrupt(int irq, void *dev_id, struct pt_regs *pregs)
569 struct net_device *dev = (struct net_device *)dev_id;
570 struct meth_private *priv = (struct meth_private *) dev->priv;
571 unsigned long status;
573 status = mace_eth_read(int_stat);
574 while (status & 0xFF) {
575 /* First handle errors - if we get Rx underflow,
576 Rx DMA will be disabled, and Rx handler will reenable
577 it. I don't think it's possible to get Rx underflow,
578 without getting Rx interrupt */
579 if (status & METH_INT_ERROR) {
580 meth_error(dev, status);
582 if (status & (METH_INT_TX_EMPTY | METH_INT_TX_PKT)) {
583 /* a transmission is over: free the skb */
584 meth_tx_cleanup(dev, status);
586 if (status & METH_INT_RX_THRESHOLD) {
587 if (!(priv->dma_ctrl & METH_DMA_RX_INT_EN))
589 /* send it to meth_rx for handling */
590 meth_rx(dev, status);
592 status = mace_eth_read(int_stat);
599 * Transmits packets that fit into TX descriptor (are <=120B)
601 static void meth_tx_short_prepare(struct meth_private *priv,
604 tx_packet *desc=&priv->tx_ring[priv->tx_write];
605 int len = (skb->len<ETH_ZLEN)?ETH_ZLEN:skb->len;
607 desc->header.raw=METH_TX_CMD_INT_EN|(len-1)|((128-len)<<16);
608 /* maybe I should set whole thing to 0 first... */
609 memcpy(desc->data.dt+(120-len),skb->data,skb->len);
611 memset(desc->data.dt+120-len+skb->len,0,len-skb->len);
613 #define TX_CATBUF1 BIT(25)
614 static void meth_tx_1page_prepare(struct meth_private *priv,
617 tx_packet *desc=&priv->tx_ring[priv->tx_write];
618 void *buffer_data = (void *)(((unsigned long)skb->data + 7) & ~7);
619 int unaligned_len = (int)((unsigned long)buffer_data - (unsigned long)skb->data);
620 int buffer_len = skb->len - unaligned_len;
623 desc->header.raw=METH_TX_CMD_INT_EN|TX_CATBUF1|(skb->len-1);
627 memcpy(desc->data.dt+(120-unaligned_len),
628 skb->data, unaligned_len);
629 desc->header.raw |= (128-unaligned_len) << 16;
633 catbuf = dma_map_single(NULL, buffer_data, buffer_len,
635 desc->data.cat_buf[0].form.start_addr = catbuf >> 3;
636 desc->data.cat_buf[0].form.len = buffer_len-1;
638 #define TX_CATBUF2 BIT(26)
639 static void meth_tx_2page_prepare(struct meth_private *priv,
642 tx_packet *desc=&priv->tx_ring[priv->tx_write];
643 void *buffer1_data = (void *)(((unsigned long)skb->data + 7) & ~7);
644 void *buffer2_data = (void *)PAGE_ALIGN((unsigned long)skb->data);
645 int unaligned_len = (int)((unsigned long)buffer1_data - (unsigned long)skb->data);
646 int buffer1_len = (int)((unsigned long)buffer2_data - (unsigned long)buffer1_data);
647 int buffer2_len = skb->len - buffer1_len - unaligned_len;
648 dma_addr_t catbuf1, catbuf2;
650 desc->header.raw=METH_TX_CMD_INT_EN|TX_CATBUF1|TX_CATBUF2|(skb->len-1);
653 memcpy(desc->data.dt+(120-unaligned_len),
654 skb->data, unaligned_len);
655 desc->header.raw |= (128-unaligned_len) << 16;
659 catbuf1 = dma_map_single(NULL, buffer1_data, buffer1_len,
661 desc->data.cat_buf[0].form.start_addr = catbuf1 >> 3;
662 desc->data.cat_buf[0].form.len = buffer1_len-1;
664 catbuf2 = dma_map_single(NULL, buffer2_data, buffer2_len,
666 desc->data.cat_buf[1].form.start_addr = catbuf2 >> 3;
667 desc->data.cat_buf[1].form.len = buffer2_len-1;
670 static void meth_add_to_tx_ring(struct meth_private *priv, struct sk_buff *skb)
672 /* Remember the skb, so we can free it at interrupt time */
673 priv->tx_skbs[priv->tx_write] = skb;
674 if(skb->len <= 120) {
675 /* Whole packet fits into descriptor */
676 meth_tx_short_prepare(priv,skb);
677 } else if(PAGE_ALIGN((unsigned long)skb->data) !=
678 PAGE_ALIGN((unsigned long)skb->data+skb->len-1)) {
679 /* Packet crosses page boundary */
680 meth_tx_2page_prepare(priv,skb);
682 /* Packet is in one page */
683 meth_tx_1page_prepare(priv,skb);
685 priv->tx_write = (priv->tx_write+1) & (TX_RING_ENTRIES-1);
686 mace_eth_write(priv->tx_write, tx_info);
691 * Transmit a packet (called by the kernel)
693 static int meth_tx(struct sk_buff *skb, struct net_device *dev)
695 struct meth_private *priv = (struct meth_private *) dev->priv;
698 spin_lock_irqsave(&priv->meth_lock,flags);
699 /* Stop DMA notification */
700 priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
701 mace_eth_write(priv->dma_ctrl, dma_ctrl);
703 meth_add_to_tx_ring(priv, skb);
704 dev->trans_start = jiffies; /* save the timestamp */
706 /* If TX ring is full, tell the upper layer to stop sending packets */
707 if (meth_tx_full(dev)) {
708 printk(KERN_DEBUG "TX full: stopping\n");
709 netif_stop_queue(dev);
712 /* Restart DMA notification */
713 priv->dma_ctrl |= METH_DMA_TX_INT_EN;
714 mace_eth_write(priv->dma_ctrl, dma_ctrl);
716 spin_unlock_irqrestore(&priv->meth_lock,flags);
722 * Deal with a transmit timeout.
724 static void meth_tx_timeout(struct net_device *dev)
726 struct meth_private *priv = (struct meth_private *) dev->priv;
729 printk(KERN_WARNING "%s: transmit timed out\n", dev->name);
731 /* Protect against concurrent rx interrupts */
732 spin_lock_irqsave(&priv->meth_lock,flags);
734 /* Try to reset the interface. */
737 priv->stats.tx_errors++;
739 /* Clear all rings */
740 meth_free_tx_ring(priv);
741 meth_free_rx_ring(priv);
742 meth_init_tx_ring(priv);
743 meth_init_rx_ring(priv);
746 priv->dma_ctrl|=METH_DMA_TX_EN|METH_DMA_RX_EN|METH_DMA_RX_INT_EN;
747 mace_eth_write(priv->dma_ctrl, dma_ctrl);
749 /* Enable interrupt */
750 spin_unlock_irqrestore(&priv->meth_lock,flags);
752 dev->trans_start = jiffies;
753 netif_wake_queue(dev);
761 static int meth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
768 * Return statistics to the caller
770 static struct net_device_stats *meth_stats(struct net_device *dev)
772 struct meth_private *priv = (struct meth_private *) dev->priv;
779 static struct net_device *meth_init(void)
781 struct net_device *dev;
782 struct meth_private *priv;
785 dev = alloc_etherdev(sizeof(struct meth_private));
787 return ERR_PTR(-ENOMEM);
789 dev->open = meth_open;
790 dev->stop = meth_release;
791 dev->hard_start_xmit = meth_tx;
792 dev->do_ioctl = meth_ioctl;
793 dev->get_stats = meth_stats;
794 #ifdef HAVE_TX_TIMEOUT
795 dev->tx_timeout = meth_tx_timeout;
796 dev->watchdog_timeo = timeout;
798 dev->irq = MACE_ETHERNET_IRQ;
799 dev->base_addr = (unsigned long)&mace->eth;
801 priv = (struct meth_private *) dev->priv;
802 spin_lock_init(&priv->meth_lock);
804 ret = register_netdev(dev);
810 printk(KERN_INFO "%s: SGI MACE Ethernet rev. %d\n",
811 dev->name, (unsigned int)mace_eth_read(mac_ctrl) >> 29);
815 static struct net_device *meth_dev;
817 static int __init meth_init_module(void)
819 meth_dev = meth_init();
820 if (IS_ERR(meth_dev))
821 return PTR_ERR(meth_dev);
825 static void __exit meth_exit_module(void)
827 unregister_netdev(meth_dev);
828 free_netdev(meth_dev);
831 module_init(meth_init_module);
832 module_exit(meth_exit_module);