1 /* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */
3 Written/copyright 1999-2001 by Donald Becker.
4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com)
5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com)
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL. License for under other terms may be
13 available. Contact the original author for details.
15 The original author may be reached as becker@scyld.com, or at
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
20 Support information and updates available at
21 http://www.scyld.com/network/netsemi.html
24 Linux kernel modifications:
28 - Bug fixes and better intr performance (Tjeerd)
30 - Now reads correct MAC address from eeprom
32 - Eliminate redundant priv->tx_full flag
33 - Call netif_start_queue from dev->tx_timeout
34 - wmb() in start_tx() to flush data
36 - Clean up PCI enable (davej)
38 - Merge Donald Becker's natsemi.c version 1.07
42 * ethtool support (jgarzik)
43 * Proper initialization of the card (which sometimes
44 fails to occur and leaves the card in a non-functional
47 * Some documented register settings to optimize some
48 of the 100Mbit autodetection circuitry in rev C cards. (uzi)
50 * Polling of the PHY intr for stuff like link state
51 change and auto- negotiation to finally work properly. (uzi)
53 * One-liner removal of a duplicate declaration of
56 Version 1.0.7: (Manfred Spraul)
59 * full reset added into tx_timeout
60 * correct multicast hash generation (both big and little endian)
61 [copied from a natsemi driver version
62 from Myrio Corporation, Greg Smith]
65 version 1.0.8 (Tim Hockin <thockin@sun.com>)
67 * Wake on lan support (Erik Gilling)
68 * MXDMA fixes for serverworks
71 version 1.0.9 (Manfred Spraul)
72 * Main change: fix lack of synchronize
73 netif_close/netif_suspend against a last interrupt
75 * do not enable superflous interrupts (e.g. the
76 drivers relies on TxDone - TxIntr not needed)
77 * wait that the hardware has really stopped in close
79 * workaround for the (at least) gcc-2.95.1 compiler
80 problem. Also simplifies the code a bit.
81 * disable_irq() in tx_timeout - needed to protect
82 against rx interrupts.
83 * stop the nic before switching into silent rx mode
84 for wol (required according to docu).
87 * use long for ee_addr (various)
88 * print pointers properly (DaveM)
89 * include asm/irq.h (?)
92 * check and reset if PHY errors appear (Adrian Sun)
93 * WoL cleanup (Tim Hockin)
94 * Magic number cleanup (Tim Hockin)
95 * Don't reload EEPROM on every reset (Tim Hockin)
96 * Save and restore EEPROM state across reset (Tim Hockin)
97 * MDIO Cleanup (Tim Hockin)
98 * Reformat register offsets/bits (jgarzik)
101 * ETHTOOL_* further support (Tim Hockin)
104 * ETHTOOL_[G]EEPROM support (Tim Hockin)
107 * crc cleanup (Matt Domsch <Matt_Domsch@dell.com>)
110 * Cleanup some messages and autoneg in ethtool (Tim Hockin)
113 * Get rid of cable_magic flag
114 * use new (National provided) solution for cable magic issue
117 * call netdev_rx() for RxErrors (Manfred Spraul)
118 * formatting and cleanups
119 * change options and full_duplex arrays to be zero
121 * enable only the WoL and PHY interrupts in wol mode
124 * only do cable_magic on 83815 and early 83816 (Tim Hockin)
125 * create a function for rx refill (Manfred Spraul)
126 * combine drain_ring and init_ring (Manfred Spraul)
127 * oom handling (Manfred Spraul)
128 * hands_off instead of playing with netif_device_{de,a}ttach
130 * be sure to write the MAC back to the chip (Manfred Spraul)
131 * lengthen EEPROM timeout, and always warn about timeouts
133 * comments update (Manfred)
134 * do the right thing on a phy-reset (Manfred and Tim)
137 * big endian support with CFG:BEM instead of cpu_to_le32
138 * support for an external PHY
142 #include <linux/config.h>
143 #include <linux/module.h>
144 #include <linux/kernel.h>
145 #include <linux/string.h>
146 #include <linux/timer.h>
147 #include <linux/errno.h>
148 #include <linux/ioport.h>
149 #include <linux/slab.h>
150 #include <linux/interrupt.h>
151 #include <linux/pci.h>
152 #include <linux/netdevice.h>
153 #include <linux/etherdevice.h>
154 #include <linux/skbuff.h>
155 #include <linux/init.h>
156 #include <linux/spinlock.h>
157 #include <linux/ethtool.h>
158 #include <linux/delay.h>
159 #include <linux/rtnetlink.h>
160 #include <linux/mii.h>
161 #include <linux/crc32.h>
162 #include <asm/processor.h> /* Processor type for cache alignment. */
163 #include <asm/bitops.h>
166 #include <asm/uaccess.h>
168 #define DRV_NAME "natsemi"
169 #define DRV_VERSION "1.07+LK1.0.17"
170 #define DRV_RELDATE "Sep 27, 2002"
174 /* Updated to recommendations in pci-skeleton v2.03. */
176 /* The user-configurable values.
177 These may be modified when a driver module is loaded.*/
179 #define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \
184 static int debug = -1;
186 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
187 static int max_interrupt_work = 20;
190 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
191 This chip uses a 512 element hash table based on the Ethernet CRC. */
192 static int multicast_filter_limit = 100;
194 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
195 Setting to > 1518 effectively disables this feature. */
196 static int rx_copybreak;
198 /* Used to pass the media type, etc.
199 Both 'options[]' and 'full_duplex[]' should exist for driver
201 The media type is usually passed in 'options[]'.
203 #define MAX_UNITS 8 /* More are supported, limit only on options */
204 static int options[MAX_UNITS];
205 static int full_duplex[MAX_UNITS];
207 /* Operational parameters that are set at compile time. */
209 /* Keep the ring sizes a power of two for compile efficiency.
210 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
211 Making the Tx ring too large decreases the effectiveness of channel
212 bonding and packet priority.
213 There are no ill effects from too-large receive rings. */
214 #define TX_RING_SIZE 16
215 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */
216 #define RX_RING_SIZE 32
218 /* Operational parameters that usually are not changed. */
219 /* Time in jiffies before concluding the transmitter is hung. */
220 #define TX_TIMEOUT (2*HZ)
222 #define NATSEMI_HW_TIMEOUT 400
223 #define NATSEMI_TIMER_FREQ 3*HZ
224 #define NATSEMI_PG0_NREGS 64
225 #define NATSEMI_RFDR_NREGS 8
226 #define NATSEMI_PG1_NREGS 4
227 #define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \
229 #define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */
230 #define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32))
231 #define NATSEMI_EEPROM_SIZE 24 /* 12 16-bit values */
234 * The nic writes 32-bit values, even if the upper bytes of
235 * a 32-bit value are beyond the end of the buffer.
237 #define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */
238 #define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */
239 #define NATSEMI_LONGPKT 1518 /* limit for normal packets */
240 #define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */
242 /* These identify the driver base version and may not be removed. */
243 static char version[] __devinitdata =
244 KERN_INFO DRV_NAME " dp8381x driver, version "
245 DRV_VERSION ", " DRV_RELDATE "\n"
246 KERN_INFO " originally by Donald Becker <becker@scyld.com>\n"
247 KERN_INFO " http://www.scyld.com/network/natsemi.html\n"
248 KERN_INFO " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n";
250 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
251 MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver");
252 MODULE_LICENSE("GPL");
254 MODULE_PARM(max_interrupt_work, "i");
255 MODULE_PARM(mtu, "i");
256 MODULE_PARM(debug, "i");
257 MODULE_PARM(rx_copybreak, "i");
258 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
259 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
260 MODULE_PARM_DESC(max_interrupt_work,
261 "DP8381x maximum events handled per interrupt");
262 MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)");
263 MODULE_PARM_DESC(debug, "DP8381x default debug level");
264 MODULE_PARM_DESC(rx_copybreak,
265 "DP8381x copy breakpoint for copy-only-tiny-frames");
266 MODULE_PARM_DESC(options,
267 "DP8381x: Bits 0-3: media type, bit 17: full duplex");
268 MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)");
273 I. Board Compatibility
275 This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC.
276 It also works with other chips in in the DP83810 series.
278 II. Board-specific settings
280 This driver requires the PCI interrupt line to be valid.
281 It honors the EEPROM-set values.
283 III. Driver operation
287 This driver uses two statically allocated fixed-size descriptor lists
288 formed into rings by a branch from the final descriptor to the beginning of
289 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
290 The NatSemi design uses a 'next descriptor' pointer that the driver forms
293 IIIb/c. Transmit/Receive Structure
295 This driver uses a zero-copy receive and transmit scheme.
296 The driver allocates full frame size skbuffs for the Rx ring buffers at
297 open() time and passes the skb->data field to the chip as receive data
298 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
299 a fresh skbuff is allocated and the frame is copied to the new skbuff.
300 When the incoming frame is larger, the skbuff is passed directly up the
301 protocol stack. Buffers consumed this way are replaced by newly allocated
302 skbuffs in a later phase of receives.
304 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
305 using a full-sized skbuff for small frames vs. the copying costs of larger
306 frames. New boards are typically used in generously configured machines
307 and the underfilled buffers have negligible impact compared to the benefit of
308 a single allocation size, so the default value of zero results in never
309 copying packets. When copying is done, the cost is usually mitigated by using
310 a combined copy/checksum routine. Copying also preloads the cache, which is
311 most useful with small frames.
313 A subtle aspect of the operation is that unaligned buffers are not permitted
314 by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't
315 longword aligned for further processing. On copies frames are put into the
316 skbuff at an offset of "+2", 16-byte aligning the IP header.
318 IIId. Synchronization
320 Most operations are synchronized on the np->lock irq spinlock, except the
321 performance critical codepaths:
323 The rx process only runs in the interrupt handler. Access from outside
324 the interrupt handler is only permitted after disable_irq().
326 The rx process usually runs under the dev->xmit_lock. If np->intr_tx_reap
327 is set, then access is permitted under spin_lock_irq(&np->lock).
329 Thus configuration functions that want to access everything must call
330 disable_irq(dev->irq);
331 spin_lock_bh(dev->xmit_lock);
332 spin_lock_irq(&np->lock);
336 NatSemi PCI network controllers are very uncommon.
340 http://www.scyld.com/expert/100mbps.html
341 http://www.scyld.com/expert/NWay.html
342 Datasheet is available from:
343 http://www.national.com/pf/DP/DP83815.html
355 PCI_USES_MASTER = 0x04,
360 /* MMIO operations required */
361 #define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_MEM | PCI_ADDR1)
365 * Support for fibre connections on Am79C874:
366 * This phy needs a special setup when connected to a fibre cable.
367 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf
369 #define PHYID_AM79C874 0x0022561b
371 #define MII_MCTRL 0x15 /* mode control register */
372 #define MII_FX_SEL 0x0001 /* 100BASE-FX (fiber) */
373 #define MII_EN_SCRM 0x0004 /* enable scrambler (tp) */
376 /* array of board data directly indexed by pci_tbl[x].driver_data */
380 } natsemi_pci_info[] __devinitdata = {
381 { "NatSemi DP8381[56]", PCI_IOTYPE },
384 static struct pci_device_id natsemi_pci_tbl[] = {
385 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID, PCI_ANY_ID, },
388 MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl);
390 /* Offsets to the device registers.
391 Unlike software-only systems, device drivers interact with complex hardware.
392 It's not useful to define symbolic names for every register bit in the
395 enum register_offsets {
403 IntrHoldoff = 0x1C, /* DP83816 only */
430 /* These are from the spec, around page 78... on a separate table.
431 * The meaning of these registers depend on the value of PGSEL. */
438 /* the values for the 'magic' registers above (PGSEL=1) */
439 #define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */
440 #define TSTDAT_VAL 0x0
441 #define DSPCFG_VAL 0x5040
442 #define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */
443 #define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */
444 #define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */
446 /* misc PCI space registers */
447 enum pci_register_offsets {
461 enum ChipConfig_bits {
465 CfgAnegEnable = 0x2000,
467 CfgAnegFull = 0x8000,
468 CfgAnegDone = 0x8000000,
469 CfgFullDuplex = 0x20000000,
470 CfgSpeed100 = 0x40000000,
471 CfgLink = 0x80000000,
477 EE_ChipSelect = 0x08,
484 enum PCIBusCfg_bits {
488 /* Bits in the interrupt status/mask registers. */
489 enum IntrStatus_bits {
493 IntrRxEarly = 0x0008,
495 IntrRxOverrun = 0x0020,
500 IntrTxUnderrun = 0x0400,
505 IntrHighBits = 0x8000,
506 RxStatusFIFOOver = 0x10000,
507 IntrPCIErr = 0xf00000,
508 RxResetDone = 0x1000000,
509 TxResetDone = 0x2000000,
510 IntrAbnormalSummary = 0xCD20,
514 * Default Interrupts:
515 * Rx OK, Rx Packet Error, Rx Overrun,
516 * Tx OK, Tx Packet Error, Tx Underrun,
517 * MIB Service, Phy Interrupt, High Bits,
518 * Rx Status FIFO overrun,
519 * Received Target Abort, Received Master Abort,
520 * Signalled System Error, Received Parity Error
522 #define DEFAULT_INTR 0x00f1cd65
527 TxMxdmaMask = 0x700000,
529 TxMxdma_4 = 0x100000,
530 TxMxdma_8 = 0x200000,
531 TxMxdma_16 = 0x300000,
532 TxMxdma_32 = 0x400000,
533 TxMxdma_64 = 0x500000,
534 TxMxdma_128 = 0x600000,
535 TxMxdma_256 = 0x700000,
536 TxCollRetry = 0x800000,
537 TxAutoPad = 0x10000000,
538 TxMacLoop = 0x20000000,
539 TxHeartIgn = 0x40000000,
540 TxCarrierIgn = 0x80000000
545 * - 256 byte DMA burst length
546 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free)
547 * - 64 bytes initial drain threshold (i.e. begin actual transmission
548 * when 64 byte are in the fifo)
549 * - on tx underruns, increase drain threshold by 64.
550 * - at most use a drain threshold of 1472 bytes: The sum of the fill
551 * threshold and the drain threshold must be less than 2016 bytes.
554 #define TX_FLTH_VAL ((512/32) << 8)
555 #define TX_DRTH_VAL_START (64/32)
556 #define TX_DRTH_VAL_INC 2
557 #define TX_DRTH_VAL_LIMIT (1472/32)
561 RxMxdmaMask = 0x700000,
563 RxMxdma_4 = 0x100000,
564 RxMxdma_8 = 0x200000,
565 RxMxdma_16 = 0x300000,
566 RxMxdma_32 = 0x400000,
567 RxMxdma_64 = 0x500000,
568 RxMxdma_128 = 0x600000,
569 RxMxdma_256 = 0x700000,
570 RxAcceptLong = 0x8000000,
571 RxAcceptTx = 0x10000000,
572 RxAcceptRunt = 0x40000000,
573 RxAcceptErr = 0x80000000
575 #define RX_DRTH_VAL (128/8)
593 WakeMagicSecure = 0x400,
594 SecureHack = 0x100000,
596 WokeUnicast = 0x800000,
597 WokeMulticast = 0x1000000,
598 WokeBroadcast = 0x2000000,
600 WokePMatch0 = 0x8000000,
601 WokePMatch1 = 0x10000000,
602 WokePMatch2 = 0x20000000,
603 WokePMatch3 = 0x40000000,
604 WokeMagic = 0x80000000,
605 WakeOptsSummary = 0x7ff
608 enum RxFilterAddr_bits {
609 RFCRAddressMask = 0x3ff,
610 AcceptMulticast = 0x00200000,
611 AcceptMyPhys = 0x08000000,
612 AcceptAllPhys = 0x10000000,
613 AcceptAllMulticast = 0x20000000,
614 AcceptBroadcast = 0x40000000,
615 RxFilterEnable = 0x80000000
618 enum StatsCtrl_bits {
625 enum MIntrCtrl_bits {
633 #define PHY_ADDR_NONE 32
634 #define PHY_ADDR_INTERNAL 1
636 /* values we might find in the silicon revision register */
637 #define SRR_DP83815_C 0x0302
638 #define SRR_DP83815_D 0x0403
639 #define SRR_DP83816_A4 0x0504
640 #define SRR_DP83816_A5 0x0505
642 /* The Rx and Tx buffer descriptors. */
643 /* Note that using only 32 bit fields simplifies conversion to big-endian
652 /* Bits in network_desc.status */
653 enum desc_status_bits {
654 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000,
655 DescNoCRC=0x10000000, DescPktOK=0x08000000,
658 DescTxAbort=0x04000000, DescTxFIFO=0x02000000,
659 DescTxCarrier=0x01000000, DescTxDefer=0x00800000,
660 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000,
661 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000,
663 DescRxAbort=0x04000000, DescRxOver=0x02000000,
664 DescRxDest=0x01800000, DescRxLong=0x00400000,
665 DescRxRunt=0x00200000, DescRxInvalid=0x00100000,
666 DescRxCRC=0x00080000, DescRxAlign=0x00040000,
667 DescRxLoop=0x00020000, DesRxColl=0x00010000,
670 struct netdev_private {
671 /* Descriptor rings first for alignment */
673 struct netdev_desc *rx_ring;
674 struct netdev_desc *tx_ring;
675 /* The addresses of receive-in-place skbuffs */
676 struct sk_buff *rx_skbuff[RX_RING_SIZE];
677 dma_addr_t rx_dma[RX_RING_SIZE];
678 /* address of a sent-in-place packet/buffer, for later free() */
679 struct sk_buff *tx_skbuff[TX_RING_SIZE];
680 dma_addr_t tx_dma[TX_RING_SIZE];
681 struct net_device_stats stats;
682 /* Media monitoring timer */
683 struct timer_list timer;
684 /* Frequently used values: keep some adjacent for cache effect */
685 struct pci_dev *pci_dev;
686 struct netdev_desc *rx_head_desc;
687 /* Producer/consumer ring indices */
688 unsigned int cur_rx, dirty_rx;
689 unsigned int cur_tx, dirty_tx;
690 /* Based on MTU+slack. */
691 unsigned int rx_buf_sz;
693 /* Do not touch the nic registers */
695 /* external phy that is used: only valid if dev->if_port != PORT_TP */
697 int phy_addr_external;
698 unsigned int full_duplex;
702 /* FIFO and PCI burst thresholds */
703 u32 tx_config, rx_config;
704 /* original contents of ClkRun register */
706 /* silicon revision */
708 /* expected DSPCFG value */
710 /* parms saved in ethtool format */
711 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
712 u8 duplex; /* Duplex, half or full */
713 u8 autoneg; /* Autonegotiation enabled */
714 /* MII transceiver section */
721 static void move_int_phy(struct net_device *dev, int addr);
722 static int eeprom_read(long ioaddr, int location);
723 static int mdio_read(struct net_device *dev, int reg);
724 static void mdio_write(struct net_device *dev, int reg, u16 data);
725 static void init_phy_fixup(struct net_device *dev);
726 static int miiport_read(struct net_device *dev, int phy_id, int reg);
727 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data);
728 static int find_mii(struct net_device *dev);
729 static void natsemi_reset(struct net_device *dev);
730 static void natsemi_reload_eeprom(struct net_device *dev);
731 static void natsemi_stop_rxtx(struct net_device *dev);
732 static int netdev_open(struct net_device *dev);
733 static void do_cable_magic(struct net_device *dev);
734 static void undo_cable_magic(struct net_device *dev);
735 static void check_link(struct net_device *dev);
736 static void netdev_timer(unsigned long data);
737 static void dump_ring(struct net_device *dev);
738 static void tx_timeout(struct net_device *dev);
739 static int alloc_ring(struct net_device *dev);
740 static void refill_rx(struct net_device *dev);
741 static void init_ring(struct net_device *dev);
742 static void drain_tx(struct net_device *dev);
743 static void drain_ring(struct net_device *dev);
744 static void free_ring(struct net_device *dev);
745 static void reinit_ring(struct net_device *dev);
746 static void init_registers(struct net_device *dev);
747 static int start_tx(struct sk_buff *skb, struct net_device *dev);
748 static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *regs);
749 static void netdev_error(struct net_device *dev, int intr_status);
750 static void netdev_rx(struct net_device *dev);
751 static void netdev_tx_done(struct net_device *dev);
752 static int natsemi_change_mtu(struct net_device *dev, int new_mtu);
753 static void __set_rx_mode(struct net_device *dev);
754 static void set_rx_mode(struct net_device *dev);
755 static void __get_stats(struct net_device *dev);
756 static struct net_device_stats *get_stats(struct net_device *dev);
757 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
758 static int netdev_set_wol(struct net_device *dev, u32 newval);
759 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur);
760 static int netdev_set_sopass(struct net_device *dev, u8 *newval);
761 static int netdev_get_sopass(struct net_device *dev, u8 *data);
762 static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
763 static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd);
764 static void enable_wol_mode(struct net_device *dev, int enable_intr);
765 static int netdev_close(struct net_device *dev);
766 static int netdev_get_regs(struct net_device *dev, u8 *buf);
767 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
769 static void move_int_phy(struct net_device *dev, int addr)
771 struct netdev_private *np = netdev_priv(dev);
775 * The internal phy is visible on the external mii bus. Therefore we must
776 * move it away before we can send commands to an external phy.
777 * There are two addresses we must avoid:
778 * - the address on the external phy that is used for transmission.
779 * - the address that we want to access. User space can access phys
780 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independant from the
781 * phy that is used for transmission.
786 if (target == np->phy_addr_external)
788 writew(target, dev->base_addr + PhyCtrl);
789 readw(dev->base_addr + PhyCtrl);
793 static int __devinit natsemi_probe1 (struct pci_dev *pdev,
794 const struct pci_device_id *ent)
796 struct net_device *dev;
797 struct netdev_private *np;
798 int i, option, irq, chip_idx = ent->driver_data;
799 static int find_cnt = -1;
800 unsigned long ioaddr, iosize;
801 const int pcibar = 1; /* PCI base address register */
805 /* when built into the kernel, we only print version if device is found */
807 static int printed_version;
808 if (!printed_version++)
812 i = pci_enable_device(pdev);
815 /* natsemi has a non-standard PM control register
816 * in PCI config space. Some boards apparently need
817 * to be brought to D0 in this manner.
819 pci_read_config_dword(pdev, PCIPM, &tmp);
820 if (tmp & PCI_PM_CTRL_STATE_MASK) {
821 /* D0 state, disable PME assertion */
822 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK;
823 pci_write_config_dword(pdev, PCIPM, newtmp);
827 ioaddr = pci_resource_start(pdev, pcibar);
828 iosize = pci_resource_len(pdev, pcibar);
831 if (natsemi_pci_info[chip_idx].flags & PCI_USES_MASTER)
832 pci_set_master(pdev);
834 dev = alloc_etherdev(sizeof (struct netdev_private));
837 SET_MODULE_OWNER(dev);
838 SET_NETDEV_DEV(dev, &pdev->dev);
840 i = pci_request_regions(pdev, DRV_NAME);
842 goto err_pci_request_regions;
844 ioaddr = (unsigned long) ioremap (ioaddr, iosize);
850 /* Work around the dropped serial bit. */
851 prev_eedata = eeprom_read(ioaddr, 6);
852 for (i = 0; i < 3; i++) {
853 int eedata = eeprom_read(ioaddr, i + 7);
854 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15);
855 dev->dev_addr[i*2+1] = eedata >> 7;
856 prev_eedata = eedata;
859 dev->base_addr = ioaddr;
862 np = netdev_priv(dev);
865 pci_set_drvdata(pdev, dev);
867 spin_lock_init(&np->lock);
868 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG;
872 * - If the nic was configured to use an external phy and if find_mii
873 * finds a phy: use external port, first phy that replies.
874 * - Otherwise: internal port.
875 * Note that the phy address for the internal phy doesn't matter:
876 * The address would be used to access a phy over the mii bus, but
877 * the internal phy is accessed through mapped registers.
879 if (readl(dev->base_addr + ChipConfig) & CfgExtPhy)
880 dev->if_port = PORT_MII;
882 dev->if_port = PORT_TP;
883 /* Reset the chip to erase previous misconfiguration. */
884 natsemi_reload_eeprom(dev);
887 if (dev->if_port != PORT_TP) {
888 np->phy_addr_external = find_mii(dev);
889 if (np->phy_addr_external == PHY_ADDR_NONE) {
890 dev->if_port = PORT_TP;
891 np->phy_addr_external = PHY_ADDR_INTERNAL;
894 np->phy_addr_external = PHY_ADDR_INTERNAL;
897 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
899 option = dev->mem_start;
901 /* The lower four bits are the media type. */
907 "natsemi %s: ignoring user supplied media type %d",
908 pci_name(np->pci_dev), option & 15);
910 if (find_cnt < MAX_UNITS && full_duplex[find_cnt])
913 /* The chip-specific entries in the device structure. */
914 dev->open = &netdev_open;
915 dev->hard_start_xmit = &start_tx;
916 dev->stop = &netdev_close;
917 dev->get_stats = &get_stats;
918 dev->set_multicast_list = &set_rx_mode;
919 dev->change_mtu = &natsemi_change_mtu;
920 dev->do_ioctl = &netdev_ioctl;
921 dev->tx_timeout = &tx_timeout;
922 dev->watchdog_timeo = TX_TIMEOUT;
927 netif_carrier_off(dev);
929 /* get the initial settings from hardware */
930 tmp = mdio_read(dev, MII_BMCR);
931 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10;
932 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF;
933 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE;
934 np->advertising= mdio_read(dev, MII_ADVERTISE);
936 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL
937 && netif_msg_probe(np)) {
938 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s "
940 pci_name(np->pci_dev),
941 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)?
942 "enabled, advertise" : "disabled, force",
944 (ADVERTISE_100FULL|ADVERTISE_100HALF))?
947 (ADVERTISE_100FULL|ADVERTISE_10FULL))?
950 if (netif_msg_probe(np))
952 "natsemi %s: Transceiver status %#04x advertising %#04x.\n",
953 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR),
956 /* save the silicon revision for later querying */
957 np->srr = readl(ioaddr + SiliconRev);
958 if (netif_msg_hw(np))
959 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n",
960 pci_name(np->pci_dev), np->srr);
962 i = register_netdev(dev);
964 goto err_register_netdev;
966 if (netif_msg_drv(np)) {
967 printk(KERN_INFO "natsemi %s: %s at %#08lx (%s), ",
968 dev->name, natsemi_pci_info[chip_idx].name, ioaddr,
969 pci_name(np->pci_dev));
970 for (i = 0; i < ETH_ALEN-1; i++)
971 printk("%02x:", dev->dev_addr[i]);
972 printk("%02x, IRQ %d", dev->dev_addr[i], irq);
973 if (dev->if_port == PORT_TP)
974 printk(", port TP.\n");
976 printk(", port MII, phy ad %d.\n", np->phy_addr_external);
981 iounmap ((void *) dev->base_addr);
984 pci_release_regions(pdev);
985 pci_set_drvdata(pdev, NULL);
987 err_pci_request_regions:
993 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
994 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */
996 /* Delay between EEPROM clock transitions.
997 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
998 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
999 made udelay() unreliable.
1000 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
1003 #define eeprom_delay(ee_addr) readl(ee_addr)
1005 #define EE_Write0 (EE_ChipSelect)
1006 #define EE_Write1 (EE_ChipSelect | EE_DataIn)
1008 /* The EEPROM commands include the alway-set leading bit. */
1010 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
1013 static int eeprom_read(long addr, int location)
1017 long ee_addr = addr + EECtrl;
1018 int read_cmd = location | EE_ReadCmd;
1019 writel(EE_Write0, ee_addr);
1021 /* Shift the read command bits out. */
1022 for (i = 10; i >= 0; i--) {
1023 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
1024 writel(dataval, ee_addr);
1025 eeprom_delay(ee_addr);
1026 writel(dataval | EE_ShiftClk, ee_addr);
1027 eeprom_delay(ee_addr);
1029 writel(EE_ChipSelect, ee_addr);
1030 eeprom_delay(ee_addr);
1032 for (i = 0; i < 16; i++) {
1033 writel(EE_ChipSelect | EE_ShiftClk, ee_addr);
1034 eeprom_delay(ee_addr);
1035 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0;
1036 writel(EE_ChipSelect, ee_addr);
1037 eeprom_delay(ee_addr);
1040 /* Terminate the EEPROM access. */
1041 writel(EE_Write0, ee_addr);
1046 /* MII transceiver control section.
1047 * The 83815 series has an internal transceiver, and we present the
1048 * internal management registers as if they were MII connected.
1049 * External Phy registers are referenced through the MII interface.
1052 /* clock transitions >= 20ns (25MHz)
1053 * One readl should be good to PCI @ 100MHz
1055 #define mii_delay(dev) readl(dev->base_addr + EECtrl)
1057 static int mii_getbit (struct net_device *dev)
1061 writel(MII_ShiftClk, dev->base_addr + EECtrl);
1062 data = readl(dev->base_addr + EECtrl);
1063 writel(0, dev->base_addr + EECtrl);
1065 return (data & MII_Data)? 1 : 0;
1068 static void mii_send_bits (struct net_device *dev, u32 data, int len)
1072 for (i = (1 << (len-1)); i; i >>= 1)
1074 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0);
1075 writel(mdio_val, dev->base_addr + EECtrl);
1077 writel(mdio_val | MII_ShiftClk, dev->base_addr + EECtrl);
1080 writel(0, dev->base_addr + EECtrl);
1084 static int miiport_read(struct net_device *dev, int phy_id, int reg)
1091 mii_send_bits (dev, 0xffffffff, 32);
1092 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1093 /* ST,OP = 0110'b for read operation */
1094 cmd = (0x06 << 10) | (phy_id << 5) | reg;
1095 mii_send_bits (dev, cmd, 14);
1097 if (mii_getbit (dev))
1100 for (i = 0; i < 16; i++) {
1102 retval |= mii_getbit (dev);
1109 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data)
1114 mii_send_bits (dev, 0xffffffff, 32);
1115 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1116 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1117 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data;
1118 mii_send_bits (dev, cmd, 32);
1123 static int mdio_read(struct net_device *dev, int reg)
1125 struct netdev_private *np = netdev_priv(dev);
1127 /* The 83815 series has two ports:
1128 * - an internal transceiver
1129 * - an external mii bus
1131 if (dev->if_port == PORT_TP)
1132 return readw(dev->base_addr+BasicControl+(reg<<2));
1134 return miiport_read(dev, np->phy_addr_external, reg);
1137 static void mdio_write(struct net_device *dev, int reg, u16 data)
1139 struct netdev_private *np = netdev_priv(dev);
1141 /* The 83815 series has an internal transceiver; handle separately */
1142 if (dev->if_port == PORT_TP)
1143 writew(data, dev->base_addr+BasicControl+(reg<<2));
1145 miiport_write(dev, np->phy_addr_external, reg, data);
1148 static void init_phy_fixup(struct net_device *dev)
1150 struct netdev_private *np = netdev_priv(dev);
1151 long ioaddr = dev->base_addr;
1156 /* restore stuff lost when power was out */
1157 tmp = mdio_read(dev, MII_BMCR);
1158 if (np->autoneg == AUTONEG_ENABLE) {
1159 /* renegotiate if something changed */
1160 if ((tmp & BMCR_ANENABLE) == 0
1161 || np->advertising != mdio_read(dev, MII_ADVERTISE))
1163 /* turn on autonegotiation and force negotiation */
1164 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART);
1165 mdio_write(dev, MII_ADVERTISE, np->advertising);
1168 /* turn off auto negotiation, set speed and duplexity */
1169 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1170 if (np->speed == SPEED_100)
1171 tmp |= BMCR_SPEED100;
1172 if (np->duplex == DUPLEX_FULL)
1173 tmp |= BMCR_FULLDPLX;
1175 * Note: there is no good way to inform the link partner
1176 * that our capabilities changed. The user has to unplug
1177 * and replug the network cable after some changes, e.g.
1178 * after switching from 10HD, autoneg off to 100 HD,
1182 mdio_write(dev, MII_BMCR, tmp);
1183 readl(dev->base_addr + ChipConfig);
1186 /* find out what phy this is */
1187 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1188 + mdio_read(dev, MII_PHYSID2);
1190 /* handle external phys here */
1192 case PHYID_AM79C874:
1193 /* phy specific configuration for fibre/tp operation */
1194 tmp = mdio_read(dev, MII_MCTRL);
1195 tmp &= ~(MII_FX_SEL | MII_EN_SCRM);
1196 if (dev->if_port == PORT_FIBRE)
1200 mdio_write(dev, MII_MCTRL, tmp);
1205 cfg = readl(dev->base_addr + ChipConfig);
1206 if (cfg & CfgExtPhy)
1209 /* On page 78 of the spec, they recommend some settings for "optimum
1210 performance" to be done in sequence. These settings optimize some
1211 of the 100Mbit autodetection circuitry. They say we only want to
1212 do this for rev C of the chip, but engineers at NSC (Bradley
1213 Kennedy) recommends always setting them. If you don't, you get
1214 errors on some autonegotiations that make the device unusable.
1216 It seems that the DSP needs a few usec to reinitialize after
1217 the start of the phy. Just retry writing these values until they
1220 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1223 writew(1, ioaddr + PGSEL);
1224 writew(PMDCSR_VAL, ioaddr + PMDCSR);
1225 writew(TSTDAT_VAL, ioaddr + TSTDAT);
1226 np->dspcfg = DSPCFG_VAL;
1227 writew(np->dspcfg, ioaddr + DSPCFG);
1228 writew(SDCFG_VAL, ioaddr + SDCFG);
1229 writew(0, ioaddr + PGSEL);
1230 readl(ioaddr + ChipConfig);
1233 writew(1, ioaddr + PGSEL);
1234 dspcfg = readw(ioaddr + DSPCFG);
1235 writew(0, ioaddr + PGSEL);
1236 if (np->dspcfg == dspcfg)
1240 if (netif_msg_link(np)) {
1241 if (i==NATSEMI_HW_TIMEOUT) {
1243 "%s: DSPCFG mismatch after retrying for %d usec.\n",
1247 "%s: DSPCFG accepted after %d usec.\n",
1252 * Enable PHY Specific event based interrupts. Link state change
1253 * and Auto-Negotiation Completion are among the affected.
1254 * Read the intr status to clear it (needed for wake events).
1256 readw(ioaddr + MIntrStatus);
1257 writew(MICRIntEn, ioaddr + MIntrCtrl);
1260 static int switch_port_external(struct net_device *dev)
1262 struct netdev_private *np = netdev_priv(dev);
1265 cfg = readl(dev->base_addr + ChipConfig);
1266 if (cfg & CfgExtPhy)
1269 if (netif_msg_link(np)) {
1270 printk(KERN_INFO "%s: switching to external transceiver.\n",
1274 /* 1) switch back to external phy */
1275 writel(cfg | (CfgExtPhy | CfgPhyDis), dev->base_addr + ChipConfig);
1276 readl(dev->base_addr + ChipConfig);
1279 /* 2) reset the external phy: */
1280 /* resetting the external PHY has been known to cause a hub supplying
1281 * power over Ethernet to kill the power. We don't want to kill
1282 * power to this computer, so we avoid resetting the phy.
1285 /* 3) reinit the phy fixup, it got lost during power down. */
1286 move_int_phy(dev, np->phy_addr_external);
1287 init_phy_fixup(dev);
1292 static int switch_port_internal(struct net_device *dev)
1294 struct netdev_private *np = netdev_priv(dev);
1299 cfg = readl(dev->base_addr + ChipConfig);
1300 if (!(cfg &CfgExtPhy))
1303 if (netif_msg_link(np)) {
1304 printk(KERN_INFO "%s: switching to internal transceiver.\n",
1307 /* 1) switch back to internal phy: */
1308 cfg = cfg & ~(CfgExtPhy | CfgPhyDis);
1309 writel(cfg, dev->base_addr + ChipConfig);
1310 readl(dev->base_addr + ChipConfig);
1313 /* 2) reset the internal phy: */
1314 bmcr = readw(dev->base_addr+BasicControl+(MII_BMCR<<2));
1315 writel(bmcr | BMCR_RESET, dev->base_addr+BasicControl+(MII_BMCR<<2));
1316 readl(dev->base_addr + ChipConfig);
1318 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1319 bmcr = readw(dev->base_addr+BasicControl+(MII_BMCR<<2));
1320 if (!(bmcr & BMCR_RESET))
1324 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) {
1326 "%s: phy reset did not complete in %d usec.\n",
1329 /* 3) reinit the phy fixup, it got lost during power down. */
1330 init_phy_fixup(dev);
1335 /* Scan for a PHY on the external mii bus.
1336 * There are two tricky points:
1337 * - Do not scan while the internal phy is enabled. The internal phy will
1338 * crash: e.g. reads from the DSPCFG register will return odd values and
1339 * the nasty random phy reset code will reset the nic every few seconds.
1340 * - The internal phy must be moved around, an external phy could
1341 * have the same address as the internal phy.
1343 static int find_mii(struct net_device *dev)
1345 struct netdev_private *np = netdev_priv(dev);
1350 /* Switch to external phy */
1351 did_switch = switch_port_external(dev);
1353 /* Scan the possible phy addresses:
1355 * PHY address 0 means that the phy is in isolate mode. Not yet
1356 * supported due to lack of test hardware. User space should
1357 * handle it through ethtool.
1359 for (i = 1; i <= 31; i++) {
1360 move_int_phy(dev, i);
1361 tmp = miiport_read(dev, i, MII_BMSR);
1362 if (tmp != 0xffff && tmp != 0x0000) {
1363 /* found something! */
1364 np->mii = (mdio_read(dev, MII_PHYSID1) << 16)
1365 + mdio_read(dev, MII_PHYSID2);
1366 if (netif_msg_probe(np)) {
1367 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n",
1368 pci_name(np->pci_dev), np->mii, i);
1373 /* And switch back to internal phy: */
1375 switch_port_internal(dev);
1379 /* CFG bits [13:16] [18:23] */
1380 #define CFG_RESET_SAVE 0xfde000
1381 /* WCSR bits [0:4] [9:10] */
1382 #define WCSR_RESET_SAVE 0x61f
1383 /* RFCR bits [20] [22] [27:31] */
1384 #define RFCR_RESET_SAVE 0xf8500000;
1386 static void natsemi_reset(struct net_device *dev)
1394 struct netdev_private *np = netdev_priv(dev);
1397 * Resetting the chip causes some registers to be lost.
1398 * Natsemi suggests NOT reloading the EEPROM while live, so instead
1399 * we save the state that would have been loaded from EEPROM
1400 * on a normal power-up (see the spec EEPROM map). This assumes
1401 * whoever calls this will follow up with init_registers() eventually.
1405 cfg = readl(dev->base_addr + ChipConfig) & CFG_RESET_SAVE;
1407 wcsr = readl(dev->base_addr + WOLCmd) & WCSR_RESET_SAVE;
1409 rfcr = readl(dev->base_addr + RxFilterAddr) & RFCR_RESET_SAVE;
1411 for (i = 0; i < 3; i++) {
1412 writel(i*2, dev->base_addr + RxFilterAddr);
1413 pmatch[i] = readw(dev->base_addr + RxFilterData);
1416 for (i = 0; i < 3; i++) {
1417 writel(0xa+(i*2), dev->base_addr + RxFilterAddr);
1418 sopass[i] = readw(dev->base_addr + RxFilterData);
1421 /* now whack the chip */
1422 writel(ChipReset, dev->base_addr + ChipCmd);
1423 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1424 if (!(readl(dev->base_addr + ChipCmd) & ChipReset))
1428 if (i==NATSEMI_HW_TIMEOUT) {
1429 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n",
1431 } else if (netif_msg_hw(np)) {
1432 printk(KERN_DEBUG "%s: reset completed in %d usec.\n",
1437 cfg |= readl(dev->base_addr + ChipConfig) & ~CFG_RESET_SAVE;
1438 /* turn on external phy if it was selected */
1439 if (dev->if_port == PORT_TP)
1440 cfg &= ~(CfgExtPhy | CfgPhyDis);
1442 cfg |= (CfgExtPhy | CfgPhyDis);
1443 writel(cfg, dev->base_addr + ChipConfig);
1445 wcsr |= readl(dev->base_addr + WOLCmd) & ~WCSR_RESET_SAVE;
1446 writel(wcsr, dev->base_addr + WOLCmd);
1448 rfcr |= readl(dev->base_addr + RxFilterAddr) & ~RFCR_RESET_SAVE;
1449 /* restore PMATCH */
1450 for (i = 0; i < 3; i++) {
1451 writel(i*2, dev->base_addr + RxFilterAddr);
1452 writew(pmatch[i], dev->base_addr + RxFilterData);
1454 for (i = 0; i < 3; i++) {
1455 writel(0xa+(i*2), dev->base_addr + RxFilterAddr);
1456 writew(sopass[i], dev->base_addr + RxFilterData);
1459 writel(rfcr, dev->base_addr + RxFilterAddr);
1462 static void natsemi_reload_eeprom(struct net_device *dev)
1464 struct netdev_private *np = netdev_priv(dev);
1467 writel(EepromReload, dev->base_addr + PCIBusCfg);
1468 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) {
1470 if (!(readl(dev->base_addr + PCIBusCfg) & EepromReload))
1473 if (i==NATSEMI_HW_TIMEOUT) {
1474 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n",
1475 pci_name(np->pci_dev), i*50);
1476 } else if (netif_msg_hw(np)) {
1477 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n",
1478 pci_name(np->pci_dev), i*50);
1482 static void natsemi_stop_rxtx(struct net_device *dev)
1484 long ioaddr = dev->base_addr;
1485 struct netdev_private *np = netdev_priv(dev);
1488 writel(RxOff | TxOff, ioaddr + ChipCmd);
1489 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) {
1490 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0)
1494 if (i==NATSEMI_HW_TIMEOUT) {
1495 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n",
1497 } else if (netif_msg_hw(np)) {
1498 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n",
1503 static int netdev_open(struct net_device *dev)
1505 struct netdev_private *np = netdev_priv(dev);
1506 long ioaddr = dev->base_addr;
1509 /* Reset the chip, just in case. */
1512 i = request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev);
1515 if (netif_msg_ifup(np))
1516 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
1517 dev->name, dev->irq);
1518 i = alloc_ring(dev);
1520 free_irq(dev->irq, dev);
1524 spin_lock_irq(&np->lock);
1525 init_registers(dev);
1526 /* now set the MAC address according to dev->dev_addr */
1527 for (i = 0; i < 3; i++) {
1528 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i];
1530 writel(i*2, ioaddr + RxFilterAddr);
1531 writew(mac, ioaddr + RxFilterData);
1533 writel(np->cur_rx_mode, ioaddr + RxFilterAddr);
1534 spin_unlock_irq(&np->lock);
1536 netif_start_queue(dev);
1538 if (netif_msg_ifup(np))
1539 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n",
1540 dev->name, (int)readl(ioaddr + ChipCmd));
1542 /* Set the timer to check for link beat. */
1543 init_timer(&np->timer);
1544 np->timer.expires = jiffies + NATSEMI_TIMER_FREQ;
1545 np->timer.data = (unsigned long)dev;
1546 np->timer.function = &netdev_timer; /* timer handler */
1547 add_timer(&np->timer);
1552 static void do_cable_magic(struct net_device *dev)
1554 struct netdev_private *np = netdev_priv(dev);
1556 if (dev->if_port != PORT_TP)
1559 if (np->srr >= SRR_DP83816_A5)
1563 * 100 MBit links with short cables can trip an issue with the chip.
1564 * The problem manifests as lots of CRC errors and/or flickering
1565 * activity LED while idle. This process is based on instructions
1566 * from engineers at National.
1568 if (readl(dev->base_addr + ChipConfig) & CfgSpeed100) {
1571 writew(1, dev->base_addr + PGSEL);
1573 * coefficient visibility should already be enabled via
1576 data = readw(dev->base_addr + TSTDAT) & 0xff;
1578 * the value must be negative, and within certain values
1579 * (these values all come from National)
1581 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) {
1582 struct netdev_private *np = netdev_priv(dev);
1584 /* the bug has been triggered - fix the coefficient */
1585 writew(TSTDAT_FIXED, dev->base_addr + TSTDAT);
1586 /* lock the value */
1587 data = readw(dev->base_addr + DSPCFG);
1588 np->dspcfg = data | DSPCFG_LOCK;
1589 writew(np->dspcfg, dev->base_addr + DSPCFG);
1591 writew(0, dev->base_addr + PGSEL);
1595 static void undo_cable_magic(struct net_device *dev)
1598 struct netdev_private *np = netdev_priv(dev);
1600 if (dev->if_port != PORT_TP)
1603 if (np->srr >= SRR_DP83816_A5)
1606 writew(1, dev->base_addr + PGSEL);
1607 /* make sure the lock bit is clear */
1608 data = readw(dev->base_addr + DSPCFG);
1609 np->dspcfg = data & ~DSPCFG_LOCK;
1610 writew(np->dspcfg, dev->base_addr + DSPCFG);
1611 writew(0, dev->base_addr + PGSEL);
1614 static void check_link(struct net_device *dev)
1616 struct netdev_private *np = netdev_priv(dev);
1617 long ioaddr = dev->base_addr;
1621 /* The link status field is latched: it remains low after a temporary
1622 * link failure until it's read. We need the current link status,
1625 mdio_read(dev, MII_BMSR);
1626 bmsr = mdio_read(dev, MII_BMSR);
1628 if (!(bmsr & BMSR_LSTATUS)) {
1629 if (netif_carrier_ok(dev)) {
1630 if (netif_msg_link(np))
1631 printk(KERN_NOTICE "%s: link down.\n",
1633 netif_carrier_off(dev);
1634 undo_cable_magic(dev);
1638 if (!netif_carrier_ok(dev)) {
1639 if (netif_msg_link(np))
1640 printk(KERN_NOTICE "%s: link up.\n", dev->name);
1641 netif_carrier_on(dev);
1642 do_cable_magic(dev);
1645 duplex = np->full_duplex;
1647 if (bmsr & BMSR_ANEGCOMPLETE) {
1648 int tmp = mii_nway_result(
1649 np->advertising & mdio_read(dev, MII_LPA));
1650 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
1652 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX)
1656 /* if duplex is set then bit 28 must be set, too */
1657 if (duplex ^ !!(np->rx_config & RxAcceptTx)) {
1658 if (netif_msg_link(np))
1660 "%s: Setting %s-duplex based on negotiated "
1661 "link capability.\n", dev->name,
1662 duplex ? "full" : "half");
1664 np->rx_config |= RxAcceptTx;
1665 np->tx_config |= TxCarrierIgn | TxHeartIgn;
1667 np->rx_config &= ~RxAcceptTx;
1668 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn);
1670 writel(np->tx_config, ioaddr + TxConfig);
1671 writel(np->rx_config, ioaddr + RxConfig);
1675 static void init_registers(struct net_device *dev)
1677 struct netdev_private *np = netdev_priv(dev);
1678 long ioaddr = dev->base_addr;
1680 init_phy_fixup(dev);
1682 /* clear any interrupts that are pending, such as wake events */
1683 readl(ioaddr + IntrStatus);
1685 writel(np->ring_dma, ioaddr + RxRingPtr);
1686 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc),
1687 ioaddr + TxRingPtr);
1689 /* Initialize other registers.
1690 * Configure the PCI bus bursts and FIFO thresholds.
1691 * Configure for standard, in-spec Ethernet.
1692 * Start with half-duplex. check_link will update
1693 * to the correct settings.
1696 /* DRTH: 2: start tx if 64 bytes are in the fifo
1697 * FLTH: 0x10: refill with next packet if 512 bytes are free
1698 * MXDMA: 0: up to 256 byte bursts.
1699 * MXDMA must be <= FLTH
1703 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 |
1704 TX_FLTH_VAL | TX_DRTH_VAL_START;
1705 writel(np->tx_config, ioaddr + TxConfig);
1707 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo
1708 * MXDMA 0: up to 256 byte bursts
1710 np->rx_config = RxMxdma_256 | RX_DRTH_VAL;
1711 /* if receive ring now has bigger buffers than normal, enable jumbo */
1712 if (np->rx_buf_sz > NATSEMI_LONGPKT)
1713 np->rx_config |= RxAcceptLong;
1715 writel(np->rx_config, ioaddr + RxConfig);
1718 * The PME bit is initialized from the EEPROM contents.
1719 * PCI cards probably have PME disabled, but motherboard
1720 * implementations may have PME set to enable WakeOnLan.
1721 * With PME set the chip will scan incoming packets but
1722 * nothing will be written to memory. */
1723 np->SavedClkRun = readl(ioaddr + ClkRun);
1724 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun);
1725 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) {
1726 printk(KERN_NOTICE "%s: Wake-up event %#08x\n",
1727 dev->name, readl(ioaddr + WOLCmd));
1733 /* Enable interrupts by setting the interrupt mask. */
1734 writel(DEFAULT_INTR, ioaddr + IntrMask);
1735 writel(1, ioaddr + IntrEnable);
1737 writel(RxOn | TxOn, ioaddr + ChipCmd);
1738 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */
1744 * 1) check for link changes. Usually they are handled by the MII interrupt
1745 * but it doesn't hurt to check twice.
1746 * 2) check for sudden death of the NIC:
1747 * It seems that a reference set for this chip went out with incorrect info,
1748 * and there exist boards that aren't quite right. An unexpected voltage
1749 * drop can cause the PHY to get itself in a weird state (basically reset).
1750 * NOTE: this only seems to affect revC chips.
1751 * 3) check of death of the RX path due to OOM
1753 static void netdev_timer(unsigned long data)
1755 struct net_device *dev = (struct net_device *)data;
1756 struct netdev_private *np = netdev_priv(dev);
1757 int next_tick = 5*HZ;
1759 if (netif_msg_timer(np)) {
1760 /* DO NOT read the IntrStatus register,
1761 * a read clears any pending interrupts.
1763 printk(KERN_DEBUG "%s: Media selection timer tick.\n",
1767 if (dev->if_port == PORT_TP) {
1768 long ioaddr = dev->base_addr;
1771 spin_lock_irq(&np->lock);
1772 /* check for a nasty random phy-reset - use dspcfg as a flag */
1773 writew(1, ioaddr+PGSEL);
1774 dspcfg = readw(ioaddr+DSPCFG);
1775 writew(0, ioaddr+PGSEL);
1776 if (dspcfg != np->dspcfg) {
1777 if (!netif_queue_stopped(dev)) {
1778 spin_unlock_irq(&np->lock);
1779 if (netif_msg_hw(np))
1780 printk(KERN_NOTICE "%s: possible phy reset: "
1781 "re-initializing\n", dev->name);
1782 disable_irq(dev->irq);
1783 spin_lock_irq(&np->lock);
1784 natsemi_stop_rxtx(dev);
1787 init_registers(dev);
1788 spin_unlock_irq(&np->lock);
1789 enable_irq(dev->irq);
1793 spin_unlock_irq(&np->lock);
1796 /* init_registers() calls check_link() for the above case */
1798 spin_unlock_irq(&np->lock);
1801 spin_lock_irq(&np->lock);
1803 spin_unlock_irq(&np->lock);
1806 disable_irq(dev->irq);
1809 enable_irq(dev->irq);
1811 writel(RxOn, dev->base_addr + ChipCmd);
1816 mod_timer(&np->timer, jiffies + next_tick);
1819 static void dump_ring(struct net_device *dev)
1821 struct netdev_private *np = netdev_priv(dev);
1823 if (netif_msg_pktdata(np)) {
1825 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring);
1826 for (i = 0; i < TX_RING_SIZE; i++) {
1827 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1828 i, np->tx_ring[i].next_desc,
1829 np->tx_ring[i].cmd_status,
1830 np->tx_ring[i].addr);
1832 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1833 for (i = 0; i < RX_RING_SIZE; i++) {
1834 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n",
1835 i, np->rx_ring[i].next_desc,
1836 np->rx_ring[i].cmd_status,
1837 np->rx_ring[i].addr);
1842 static void tx_timeout(struct net_device *dev)
1844 struct netdev_private *np = netdev_priv(dev);
1845 long ioaddr = dev->base_addr;
1847 disable_irq(dev->irq);
1848 spin_lock_irq(&np->lock);
1849 if (!np->hands_off) {
1850 if (netif_msg_tx_err(np))
1852 "%s: Transmit timed out, status %#08x,"
1854 dev->name, readl(ioaddr + IntrStatus));
1859 init_registers(dev);
1862 "%s: tx_timeout while in hands_off state?\n",
1865 spin_unlock_irq(&np->lock);
1866 enable_irq(dev->irq);
1868 dev->trans_start = jiffies;
1869 np->stats.tx_errors++;
1870 netif_wake_queue(dev);
1873 static int alloc_ring(struct net_device *dev)
1875 struct netdev_private *np = netdev_priv(dev);
1876 np->rx_ring = pci_alloc_consistent(np->pci_dev,
1877 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
1881 np->tx_ring = &np->rx_ring[RX_RING_SIZE];
1885 static void refill_rx(struct net_device *dev)
1887 struct netdev_private *np = netdev_priv(dev);
1889 /* Refill the Rx ring buffers. */
1890 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1891 struct sk_buff *skb;
1892 int entry = np->dirty_rx % RX_RING_SIZE;
1893 if (np->rx_skbuff[entry] == NULL) {
1894 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING;
1895 skb = dev_alloc_skb(buflen);
1896 np->rx_skbuff[entry] = skb;
1898 break; /* Better luck next round. */
1899 skb->dev = dev; /* Mark as being used by this device. */
1900 np->rx_dma[entry] = pci_map_single(np->pci_dev,
1901 skb->tail, buflen, PCI_DMA_FROMDEVICE);
1902 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]);
1904 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz);
1906 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) {
1907 if (netif_msg_rx_err(np))
1908 printk(KERN_WARNING "%s: going OOM.\n", dev->name);
1913 static void set_bufsize(struct net_device *dev)
1915 struct netdev_private *np = netdev_priv(dev);
1916 if (dev->mtu <= ETH_DATA_LEN)
1917 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS;
1919 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS;
1922 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1923 static void init_ring(struct net_device *dev)
1925 struct netdev_private *np = netdev_priv(dev);
1929 np->dirty_tx = np->cur_tx = 0;
1930 for (i = 0; i < TX_RING_SIZE; i++) {
1931 np->tx_skbuff[i] = NULL;
1932 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1933 +sizeof(struct netdev_desc)
1934 *((i+1)%TX_RING_SIZE+RX_RING_SIZE));
1935 np->tx_ring[i].cmd_status = 0;
1940 np->cur_rx = RX_RING_SIZE;
1944 np->rx_head_desc = &np->rx_ring[0];
1946 /* Please be carefull before changing this loop - at least gcc-2.95.1
1947 * miscompiles it otherwise.
1949 /* Initialize all Rx descriptors. */
1950 for (i = 0; i < RX_RING_SIZE; i++) {
1951 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma
1952 +sizeof(struct netdev_desc)
1953 *((i+1)%RX_RING_SIZE));
1954 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
1955 np->rx_skbuff[i] = NULL;
1961 static void drain_tx(struct net_device *dev)
1963 struct netdev_private *np = netdev_priv(dev);
1966 for (i = 0; i < TX_RING_SIZE; i++) {
1967 if (np->tx_skbuff[i]) {
1968 pci_unmap_single(np->pci_dev,
1969 np->tx_dma[i], np->tx_skbuff[i]->len,
1971 dev_kfree_skb(np->tx_skbuff[i]);
1972 np->stats.tx_dropped++;
1974 np->tx_skbuff[i] = NULL;
1978 static void drain_rx(struct net_device *dev)
1980 struct netdev_private *np = netdev_priv(dev);
1981 unsigned int buflen = np->rx_buf_sz;
1984 /* Free all the skbuffs in the Rx queue. */
1985 for (i = 0; i < RX_RING_SIZE; i++) {
1986 np->rx_ring[i].cmd_status = 0;
1987 np->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
1988 if (np->rx_skbuff[i]) {
1989 pci_unmap_single(np->pci_dev,
1990 np->rx_dma[i], buflen,
1991 PCI_DMA_FROMDEVICE);
1992 dev_kfree_skb(np->rx_skbuff[i]);
1994 np->rx_skbuff[i] = NULL;
1998 static void drain_ring(struct net_device *dev)
2004 static void free_ring(struct net_device *dev)
2006 struct netdev_private *np = netdev_priv(dev);
2007 pci_free_consistent(np->pci_dev,
2008 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE),
2009 np->rx_ring, np->ring_dma);
2012 static void reinit_rx(struct net_device *dev)
2014 struct netdev_private *np = netdev_priv(dev);
2019 np->cur_rx = RX_RING_SIZE;
2020 np->rx_head_desc = &np->rx_ring[0];
2021 /* Initialize all Rx descriptors. */
2022 for (i = 0; i < RX_RING_SIZE; i++)
2023 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn);
2028 static void reinit_ring(struct net_device *dev)
2030 struct netdev_private *np = netdev_priv(dev);
2035 np->dirty_tx = np->cur_tx = 0;
2036 for (i=0;i<TX_RING_SIZE;i++)
2037 np->tx_ring[i].cmd_status = 0;
2042 static int start_tx(struct sk_buff *skb, struct net_device *dev)
2044 struct netdev_private *np = netdev_priv(dev);
2047 /* Note: Ordering is important here, set the field with the
2048 "ownership" bit last, and only then increment cur_tx. */
2050 /* Calculate the next Tx descriptor entry. */
2051 entry = np->cur_tx % TX_RING_SIZE;
2053 np->tx_skbuff[entry] = skb;
2054 np->tx_dma[entry] = pci_map_single(np->pci_dev,
2055 skb->data,skb->len, PCI_DMA_TODEVICE);
2057 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]);
2059 spin_lock_irq(&np->lock);
2061 if (!np->hands_off) {
2062 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len);
2063 /* StrongARM: Explicitly cache flush np->tx_ring and
2064 * skb->data,skb->len. */
2067 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) {
2068 netdev_tx_done(dev);
2069 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1)
2070 netif_stop_queue(dev);
2072 /* Wake the potentially-idle transmit channel. */
2073 writel(TxOn, dev->base_addr + ChipCmd);
2075 dev_kfree_skb_irq(skb);
2076 np->stats.tx_dropped++;
2078 spin_unlock_irq(&np->lock);
2080 dev->trans_start = jiffies;
2082 if (netif_msg_tx_queued(np)) {
2083 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
2084 dev->name, np->cur_tx, entry);
2089 static void netdev_tx_done(struct net_device *dev)
2091 struct netdev_private *np = netdev_priv(dev);
2093 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
2094 int entry = np->dirty_tx % TX_RING_SIZE;
2095 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn))
2097 if (netif_msg_tx_done(np))
2099 "%s: tx frame #%d finished, status %#08x.\n",
2100 dev->name, np->dirty_tx,
2101 le32_to_cpu(np->tx_ring[entry].cmd_status));
2102 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) {
2103 np->stats.tx_packets++;
2104 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
2105 } else { /* Various Tx errors */
2107 le32_to_cpu(np->tx_ring[entry].cmd_status);
2108 if (tx_status & (DescTxAbort|DescTxExcColl))
2109 np->stats.tx_aborted_errors++;
2110 if (tx_status & DescTxFIFO)
2111 np->stats.tx_fifo_errors++;
2112 if (tx_status & DescTxCarrier)
2113 np->stats.tx_carrier_errors++;
2114 if (tx_status & DescTxOOWCol)
2115 np->stats.tx_window_errors++;
2116 np->stats.tx_errors++;
2118 pci_unmap_single(np->pci_dev,np->tx_dma[entry],
2119 np->tx_skbuff[entry]->len,
2121 /* Free the original skb. */
2122 dev_kfree_skb_irq(np->tx_skbuff[entry]);
2123 np->tx_skbuff[entry] = NULL;
2125 if (netif_queue_stopped(dev)
2126 && np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
2127 /* The ring is no longer full, wake queue. */
2128 netif_wake_queue(dev);
2132 /* The interrupt handler does all of the Rx thread work and cleans up
2133 after the Tx thread. */
2134 static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *rgs)
2136 struct net_device *dev = dev_instance;
2137 struct netdev_private *np = netdev_priv(dev);
2138 long ioaddr = dev->base_addr;
2139 int boguscnt = max_interrupt_work;
2140 unsigned int handled = 0;
2145 /* Reading automatically acknowledges all int sources. */
2146 u32 intr_status = readl(ioaddr + IntrStatus);
2148 if (netif_msg_intr(np))
2150 "%s: Interrupt, status %#08x, mask %#08x.\n",
2151 dev->name, intr_status,
2152 readl(ioaddr + IntrMask));
2154 if (intr_status == 0)
2159 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver |
2160 IntrRxErr | IntrRxOverrun)) {
2165 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) {
2166 spin_lock(&np->lock);
2167 netdev_tx_done(dev);
2168 spin_unlock(&np->lock);
2171 /* Abnormal error summary/uncommon events handlers. */
2172 if (intr_status & IntrAbnormalSummary)
2173 netdev_error(dev, intr_status);
2175 if (--boguscnt < 0) {
2176 if (netif_msg_intr(np))
2178 "%s: Too much work at interrupt, "
2180 dev->name, intr_status);
2185 if (netif_msg_intr(np))
2186 printk(KERN_DEBUG "%s: exiting interrupt.\n", dev->name);
2188 return IRQ_RETVAL(handled);
2191 /* This routine is logically part of the interrupt handler, but separated
2192 for clarity and better register allocation. */
2193 static void netdev_rx(struct net_device *dev)
2195 struct netdev_private *np = netdev_priv(dev);
2196 int entry = np->cur_rx % RX_RING_SIZE;
2197 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
2198 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2199 unsigned int buflen = np->rx_buf_sz;
2201 /* If the driver owns the next entry it's a new packet. Send it up. */
2202 while (desc_status < 0) { /* e.g. & DescOwn */
2204 if (netif_msg_rx_status(np))
2206 " netdev_rx() entry %d status was %#08x.\n",
2207 entry, desc_status);
2210 pkt_len = (desc_status & DescSizeMask) - 4;
2211 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){
2212 if (desc_status & DescMore) {
2213 if (netif_msg_rx_err(np))
2215 "%s: Oversized(?) Ethernet "
2216 "frame spanned multiple "
2217 "buffers, entry %#08x "
2218 "status %#08x.\n", dev->name,
2219 np->cur_rx, desc_status);
2220 np->stats.rx_length_errors++;
2222 /* There was an error. */
2223 np->stats.rx_errors++;
2224 if (desc_status & (DescRxAbort|DescRxOver))
2225 np->stats.rx_over_errors++;
2226 if (desc_status & (DescRxLong|DescRxRunt))
2227 np->stats.rx_length_errors++;
2228 if (desc_status & (DescRxInvalid|DescRxAlign))
2229 np->stats.rx_frame_errors++;
2230 if (desc_status & DescRxCRC)
2231 np->stats.rx_crc_errors++;
2233 } else if (pkt_len > np->rx_buf_sz) {
2234 /* if this is the tail of a double buffer
2235 * packet, we've already counted the error
2236 * on the first part. Ignore the second half.
2239 struct sk_buff *skb;
2240 /* Omit CRC size. */
2241 /* Check if the packet is long enough to accept
2242 * without copying to a minimally-sized skbuff. */
2243 if (pkt_len < rx_copybreak
2244 && (skb = dev_alloc_skb(pkt_len + RX_OFFSET)) != NULL) {
2246 /* 16 byte align the IP header */
2247 skb_reserve(skb, RX_OFFSET);
2248 pci_dma_sync_single_for_cpu(np->pci_dev,
2251 PCI_DMA_FROMDEVICE);
2252 eth_copy_and_sum(skb,
2253 np->rx_skbuff[entry]->tail, pkt_len, 0);
2254 skb_put(skb, pkt_len);
2255 pci_dma_sync_single_for_device(np->pci_dev,
2258 PCI_DMA_FROMDEVICE);
2260 pci_unmap_single(np->pci_dev, np->rx_dma[entry],
2261 buflen, PCI_DMA_FROMDEVICE);
2262 skb_put(skb = np->rx_skbuff[entry], pkt_len);
2263 np->rx_skbuff[entry] = NULL;
2265 skb->protocol = eth_type_trans(skb, dev);
2267 dev->last_rx = jiffies;
2268 np->stats.rx_packets++;
2269 np->stats.rx_bytes += pkt_len;
2271 entry = (++np->cur_rx) % RX_RING_SIZE;
2272 np->rx_head_desc = &np->rx_ring[entry];
2273 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status);
2277 /* Restart Rx engine if stopped. */
2279 mod_timer(&np->timer, jiffies + 1);
2281 writel(RxOn, dev->base_addr + ChipCmd);
2284 static void netdev_error(struct net_device *dev, int intr_status)
2286 struct netdev_private *np = netdev_priv(dev);
2287 long ioaddr = dev->base_addr;
2289 spin_lock(&np->lock);
2290 if (intr_status & LinkChange) {
2291 u16 lpa = mdio_read(dev, MII_LPA);
2292 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE
2293 && netif_msg_link(np)) {
2295 "%s: Autonegotiation advertising"
2296 " %#04x partner %#04x.\n", dev->name,
2297 np->advertising, lpa);
2300 /* read MII int status to clear the flag */
2301 readw(ioaddr + MIntrStatus);
2304 if (intr_status & StatsMax) {
2307 if (intr_status & IntrTxUnderrun) {
2308 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) {
2309 np->tx_config += TX_DRTH_VAL_INC;
2310 if (netif_msg_tx_err(np))
2312 "%s: increased tx threshold, txcfg %#08x.\n",
2313 dev->name, np->tx_config);
2315 if (netif_msg_tx_err(np))
2317 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n",
2318 dev->name, np->tx_config);
2320 writel(np->tx_config, ioaddr + TxConfig);
2322 if (intr_status & WOLPkt && netif_msg_wol(np)) {
2323 int wol_status = readl(ioaddr + WOLCmd);
2324 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n",
2325 dev->name, wol_status);
2327 if (intr_status & RxStatusFIFOOver) {
2328 if (netif_msg_rx_err(np) && netif_msg_intr(np)) {
2329 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n",
2332 np->stats.rx_fifo_errors++;
2334 /* Hmmmmm, it's not clear how to recover from PCI faults. */
2335 if (intr_status & IntrPCIErr) {
2336 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name,
2337 intr_status & IntrPCIErr);
2338 np->stats.tx_fifo_errors++;
2339 np->stats.rx_fifo_errors++;
2341 spin_unlock(&np->lock);
2344 static void __get_stats(struct net_device *dev)
2346 long ioaddr = dev->base_addr;
2347 struct netdev_private *np = netdev_priv(dev);
2349 /* The chip only need report frame silently dropped. */
2350 np->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs);
2351 np->stats.rx_missed_errors += readl(ioaddr + RxMissed);
2354 static struct net_device_stats *get_stats(struct net_device *dev)
2356 struct netdev_private *np = netdev_priv(dev);
2358 /* The chip only need report frame silently dropped. */
2359 spin_lock_irq(&np->lock);
2360 if (netif_running(dev) && !np->hands_off)
2362 spin_unlock_irq(&np->lock);
2367 #define HASH_TABLE 0x200
2368 static void __set_rx_mode(struct net_device *dev)
2370 long ioaddr = dev->base_addr;
2371 struct netdev_private *np = netdev_priv(dev);
2372 u8 mc_filter[64]; /* Multicast hash filter */
2375 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2376 /* Unconditionally log net taps. */
2377 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2379 rx_mode = RxFilterEnable | AcceptBroadcast
2380 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys;
2381 } else if ((dev->mc_count > multicast_filter_limit)
2382 || (dev->flags & IFF_ALLMULTI)) {
2383 rx_mode = RxFilterEnable | AcceptBroadcast
2384 | AcceptAllMulticast | AcceptMyPhys;
2386 struct dev_mc_list *mclist;
2388 memset(mc_filter, 0, sizeof(mc_filter));
2389 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2390 i++, mclist = mclist->next) {
2391 int i = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 23) & 0x1ff;
2392 mc_filter[i/8] |= (1 << (i & 0x07));
2394 rx_mode = RxFilterEnable | AcceptBroadcast
2395 | AcceptMulticast | AcceptMyPhys;
2396 for (i = 0; i < 64; i += 2) {
2397 writew(HASH_TABLE + i, ioaddr + RxFilterAddr);
2398 writew((mc_filter[i+1]<<8) + mc_filter[i],
2399 ioaddr + RxFilterData);
2402 writel(rx_mode, ioaddr + RxFilterAddr);
2403 np->cur_rx_mode = rx_mode;
2406 static int natsemi_change_mtu(struct net_device *dev, int new_mtu)
2408 if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS)
2413 /* synchronized against open : rtnl_lock() held by caller */
2414 if (netif_running(dev)) {
2415 struct netdev_private *np = netdev_priv(dev);
2416 long ioaddr = dev->base_addr;
2418 disable_irq(dev->irq);
2419 spin_lock(&np->lock);
2421 natsemi_stop_rxtx(dev);
2422 /* drain rx queue */
2424 /* change buffers */
2427 writel(np->ring_dma, ioaddr + RxRingPtr);
2428 /* restart engines */
2429 writel(RxOn | TxOn, ioaddr + ChipCmd);
2430 spin_unlock(&np->lock);
2431 enable_irq(dev->irq);
2436 static void set_rx_mode(struct net_device *dev)
2438 struct netdev_private *np = netdev_priv(dev);
2439 spin_lock_irq(&np->lock);
2442 spin_unlock_irq(&np->lock);
2445 static int netdev_ethtool_ioctl(struct net_device *dev, void __user *useraddr)
2447 struct netdev_private *np = netdev_priv(dev);
2450 if (get_user(cmd, (u32 __user *)useraddr))
2454 /* get driver info */
2455 case ETHTOOL_GDRVINFO: {
2456 struct ethtool_drvinfo info = {ETHTOOL_GDRVINFO};
2457 strncpy(info.driver, DRV_NAME, ETHTOOL_BUSINFO_LEN);
2458 strncpy(info.version, DRV_VERSION, ETHTOOL_BUSINFO_LEN);
2459 info.fw_version[0] = '\0';
2460 strncpy(info.bus_info, pci_name(np->pci_dev),
2461 ETHTOOL_BUSINFO_LEN);
2462 info.eedump_len = NATSEMI_EEPROM_SIZE;
2463 info.regdump_len = NATSEMI_REGS_SIZE;
2464 if (copy_to_user(useraddr, &info, sizeof(info)))
2469 case ETHTOOL_GSET: {
2470 struct ethtool_cmd ecmd = { ETHTOOL_GSET };
2471 spin_lock_irq(&np->lock);
2472 netdev_get_ecmd(dev, &ecmd);
2473 spin_unlock_irq(&np->lock);
2474 if (copy_to_user(useraddr, &ecmd, sizeof(ecmd)))
2479 case ETHTOOL_SSET: {
2480 struct ethtool_cmd ecmd;
2482 if (copy_from_user(&ecmd, useraddr, sizeof(ecmd)))
2484 spin_lock_irq(&np->lock);
2485 r = netdev_set_ecmd(dev, &ecmd);
2486 spin_unlock_irq(&np->lock);
2489 /* get wake-on-lan */
2490 case ETHTOOL_GWOL: {
2491 struct ethtool_wolinfo wol = {ETHTOOL_GWOL};
2492 spin_lock_irq(&np->lock);
2493 netdev_get_wol(dev, &wol.supported, &wol.wolopts);
2494 netdev_get_sopass(dev, wol.sopass);
2495 spin_unlock_irq(&np->lock);
2496 if (copy_to_user(useraddr, &wol, sizeof(wol)))
2500 /* set wake-on-lan */
2501 case ETHTOOL_SWOL: {
2502 struct ethtool_wolinfo wol;
2504 if (copy_from_user(&wol, useraddr, sizeof(wol)))
2506 spin_lock_irq(&np->lock);
2507 netdev_set_wol(dev, wol.wolopts);
2508 r = netdev_set_sopass(dev, wol.sopass);
2509 spin_unlock_irq(&np->lock);
2513 case ETHTOOL_GREGS: {
2514 struct ethtool_regs regs;
2515 u8 regbuf[NATSEMI_REGS_SIZE];
2518 if (copy_from_user(®s, useraddr, sizeof(regs)))
2521 if (regs.len > NATSEMI_REGS_SIZE) {
2522 regs.len = NATSEMI_REGS_SIZE;
2524 regs.version = NATSEMI_REGS_VER;
2525 if (copy_to_user(useraddr, ®s, sizeof(regs)))
2528 useraddr += offsetof(struct ethtool_regs, data);
2530 spin_lock_irq(&np->lock);
2531 r = netdev_get_regs(dev, regbuf);
2532 spin_unlock_irq(&np->lock);
2536 if (copy_to_user(useraddr, regbuf, regs.len))
2540 /* get message-level */
2541 case ETHTOOL_GMSGLVL: {
2542 struct ethtool_value edata = {ETHTOOL_GMSGLVL};
2543 edata.data = np->msg_enable;
2544 if (copy_to_user(useraddr, &edata, sizeof(edata)))
2548 /* set message-level */
2549 case ETHTOOL_SMSGLVL: {
2550 struct ethtool_value edata;
2551 if (copy_from_user(&edata, useraddr, sizeof(edata)))
2553 np->msg_enable = edata.data;
2556 /* restart autonegotiation */
2557 case ETHTOOL_NWAY_RST: {
2560 /* if autoneg is off, it's an error */
2561 tmp = mdio_read(dev, MII_BMCR);
2562 if (tmp & BMCR_ANENABLE) {
2563 tmp |= (BMCR_ANRESTART);
2564 mdio_write(dev, MII_BMCR, tmp);
2569 /* get link status */
2570 case ETHTOOL_GLINK: {
2571 struct ethtool_value edata = {ETHTOOL_GLINK};
2572 /* LSTATUS is latched low until a read - so read twice */
2573 mdio_read(dev, MII_BMSR);
2574 edata.data = (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0;
2575 if (copy_to_user(useraddr, &edata, sizeof(edata)))
2580 case ETHTOOL_GEEPROM: {
2581 struct ethtool_eeprom eeprom;
2582 u8 eebuf[NATSEMI_EEPROM_SIZE];
2585 if (copy_from_user(&eeprom, useraddr, sizeof(eeprom)))
2588 if (eeprom.offset > eeprom.offset+eeprom.len)
2591 if ((eeprom.offset+eeprom.len) > NATSEMI_EEPROM_SIZE) {
2592 eeprom.len = NATSEMI_EEPROM_SIZE-eeprom.offset;
2594 eeprom.magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16);
2595 if (copy_to_user(useraddr, &eeprom, sizeof(eeprom)))
2598 useraddr += offsetof(struct ethtool_eeprom, data);
2600 spin_lock_irq(&np->lock);
2601 r = netdev_get_eeprom(dev, eebuf);
2602 spin_unlock_irq(&np->lock);
2606 if (copy_to_user(useraddr, eebuf+eeprom.offset, eeprom.len))
2616 static int netdev_set_wol(struct net_device *dev, u32 newval)
2618 struct netdev_private *np = netdev_priv(dev);
2619 u32 data = readl(dev->base_addr + WOLCmd) & ~WakeOptsSummary;
2621 /* translate to bitmasks this chip understands */
2622 if (newval & WAKE_PHY)
2624 if (newval & WAKE_UCAST)
2625 data |= WakeUnicast;
2626 if (newval & WAKE_MCAST)
2627 data |= WakeMulticast;
2628 if (newval & WAKE_BCAST)
2629 data |= WakeBroadcast;
2630 if (newval & WAKE_ARP)
2632 if (newval & WAKE_MAGIC)
2634 if (np->srr >= SRR_DP83815_D) {
2635 if (newval & WAKE_MAGICSECURE) {
2636 data |= WakeMagicSecure;
2640 writel(data, dev->base_addr + WOLCmd);
2645 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur)
2647 struct netdev_private *np = netdev_priv(dev);
2648 u32 regval = readl(dev->base_addr + WOLCmd);
2650 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST
2651 | WAKE_ARP | WAKE_MAGIC);
2653 if (np->srr >= SRR_DP83815_D) {
2654 /* SOPASS works on revD and higher */
2655 *supported |= WAKE_MAGICSECURE;
2659 /* translate from chip bitmasks */
2660 if (regval & WakePhy)
2662 if (regval & WakeUnicast)
2664 if (regval & WakeMulticast)
2666 if (regval & WakeBroadcast)
2668 if (regval & WakeArp)
2670 if (regval & WakeMagic)
2672 if (regval & WakeMagicSecure) {
2673 /* this can be on in revC, but it's broken */
2674 *cur |= WAKE_MAGICSECURE;
2680 static int netdev_set_sopass(struct net_device *dev, u8 *newval)
2682 struct netdev_private *np = netdev_priv(dev);
2683 u16 *sval = (u16 *)newval;
2686 if (np->srr < SRR_DP83815_D) {
2690 /* enable writing to these registers by disabling the RX filter */
2691 addr = readl(dev->base_addr + RxFilterAddr) & ~RFCRAddressMask;
2692 addr &= ~RxFilterEnable;
2693 writel(addr, dev->base_addr + RxFilterAddr);
2695 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */
2696 writel(addr | 0xa, dev->base_addr + RxFilterAddr);
2697 writew(sval[0], dev->base_addr + RxFilterData);
2699 writel(addr | 0xc, dev->base_addr + RxFilterAddr);
2700 writew(sval[1], dev->base_addr + RxFilterData);
2702 writel(addr | 0xe, dev->base_addr + RxFilterAddr);
2703 writew(sval[2], dev->base_addr + RxFilterData);
2705 /* re-enable the RX filter */
2706 writel(addr | RxFilterEnable, dev->base_addr + RxFilterAddr);
2711 static int netdev_get_sopass(struct net_device *dev, u8 *data)
2713 struct netdev_private *np = netdev_priv(dev);
2714 u16 *sval = (u16 *)data;
2717 if (np->srr < SRR_DP83815_D) {
2718 sval[0] = sval[1] = sval[2] = 0;
2722 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */
2723 addr = readl(dev->base_addr + RxFilterAddr) & ~RFCRAddressMask;
2725 writel(addr | 0xa, dev->base_addr + RxFilterAddr);
2726 sval[0] = readw(dev->base_addr + RxFilterData);
2728 writel(addr | 0xc, dev->base_addr + RxFilterAddr);
2729 sval[1] = readw(dev->base_addr + RxFilterData);
2731 writel(addr | 0xe, dev->base_addr + RxFilterAddr);
2732 sval[2] = readw(dev->base_addr + RxFilterData);
2734 writel(addr, dev->base_addr + RxFilterAddr);
2739 static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2741 struct netdev_private *np = netdev_priv(dev);
2744 ecmd->port = dev->if_port;
2745 ecmd->speed = np->speed;
2746 ecmd->duplex = np->duplex;
2747 ecmd->autoneg = np->autoneg;
2748 ecmd->advertising = 0;
2749 if (np->advertising & ADVERTISE_10HALF)
2750 ecmd->advertising |= ADVERTISED_10baseT_Half;
2751 if (np->advertising & ADVERTISE_10FULL)
2752 ecmd->advertising |= ADVERTISED_10baseT_Full;
2753 if (np->advertising & ADVERTISE_100HALF)
2754 ecmd->advertising |= ADVERTISED_100baseT_Half;
2755 if (np->advertising & ADVERTISE_100FULL)
2756 ecmd->advertising |= ADVERTISED_100baseT_Full;
2757 ecmd->supported = (SUPPORTED_Autoneg |
2758 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2759 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2760 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE);
2761 ecmd->phy_address = np->phy_addr_external;
2763 * We intentionally report the phy address of the external
2764 * phy, even if the internal phy is used. This is necessary
2765 * to work around a deficiency of the ethtool interface:
2766 * It's only possible to query the settings of the active
2768 * # ethtool -s ethX port mii
2769 * actually sends an ioctl to switch to port mii with the
2770 * settings that are used for the current active port.
2771 * If we would report a different phy address in this
2773 * # ethtool -s ethX port tp;ethtool -s ethX port mii
2774 * would unintentionally change the phy address.
2776 * Fortunately the phy address doesn't matter with the
2780 /* set information based on active port type */
2781 switch (ecmd->port) {
2784 ecmd->advertising |= ADVERTISED_TP;
2785 ecmd->transceiver = XCVR_INTERNAL;
2788 ecmd->advertising |= ADVERTISED_MII;
2789 ecmd->transceiver = XCVR_EXTERNAL;
2792 ecmd->advertising |= ADVERTISED_FIBRE;
2793 ecmd->transceiver = XCVR_EXTERNAL;
2797 /* if autonegotiation is on, try to return the active speed/duplex */
2798 if (ecmd->autoneg == AUTONEG_ENABLE) {
2799 ecmd->advertising |= ADVERTISED_Autoneg;
2800 tmp = mii_nway_result(
2801 np->advertising & mdio_read(dev, MII_LPA));
2802 if (tmp == LPA_100FULL || tmp == LPA_100HALF)
2803 ecmd->speed = SPEED_100;
2805 ecmd->speed = SPEED_10;
2806 if (tmp == LPA_100FULL || tmp == LPA_10FULL)
2807 ecmd->duplex = DUPLEX_FULL;
2809 ecmd->duplex = DUPLEX_HALF;
2812 /* ignore maxtxpkt, maxrxpkt for now */
2817 static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd)
2819 struct netdev_private *np = netdev_priv(dev);
2821 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE)
2823 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL)
2825 if (ecmd->autoneg == AUTONEG_ENABLE) {
2826 if ((ecmd->advertising & (ADVERTISED_10baseT_Half |
2827 ADVERTISED_10baseT_Full |
2828 ADVERTISED_100baseT_Half |
2829 ADVERTISED_100baseT_Full)) == 0) {
2832 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2833 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2835 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2842 * maxtxpkt, maxrxpkt: ignored for now.
2845 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always
2846 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and
2847 * selects based on ecmd->port.
2849 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre
2850 * phys that are connected to the mii bus. It's used to apply fibre
2854 /* WHEW! now lets bang some bits */
2856 /* save the parms */
2857 dev->if_port = ecmd->port;
2858 np->autoneg = ecmd->autoneg;
2859 np->phy_addr_external = ecmd->phy_address & PhyAddrMask;
2860 if (np->autoneg == AUTONEG_ENABLE) {
2861 /* advertise only what has been requested */
2862 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2863 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2864 np->advertising |= ADVERTISE_10HALF;
2865 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2866 np->advertising |= ADVERTISE_10FULL;
2867 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2868 np->advertising |= ADVERTISE_100HALF;
2869 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2870 np->advertising |= ADVERTISE_100FULL;
2872 np->speed = ecmd->speed;
2873 np->duplex = ecmd->duplex;
2874 /* user overriding the initial full duplex parm? */
2875 if (np->duplex == DUPLEX_HALF)
2876 np->full_duplex = 0;
2879 /* get the right phy enabled */
2880 if (ecmd->port == PORT_TP)
2881 switch_port_internal(dev);
2883 switch_port_external(dev);
2885 /* set parms and see how this affected our link status */
2886 init_phy_fixup(dev);
2891 static int netdev_get_regs(struct net_device *dev, u8 *buf)
2896 u32 *rbuf = (u32 *)buf;
2898 /* read non-mii page 0 of registers */
2899 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) {
2900 rbuf[i] = readl(dev->base_addr + i*4);
2903 /* read current mii registers */
2904 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++)
2905 rbuf[i] = mdio_read(dev, i & 0x1f);
2907 /* read only the 'magic' registers from page 1 */
2908 writew(1, dev->base_addr + PGSEL);
2909 rbuf[i++] = readw(dev->base_addr + PMDCSR);
2910 rbuf[i++] = readw(dev->base_addr + TSTDAT);
2911 rbuf[i++] = readw(dev->base_addr + DSPCFG);
2912 rbuf[i++] = readw(dev->base_addr + SDCFG);
2913 writew(0, dev->base_addr + PGSEL);
2915 /* read RFCR indexed registers */
2916 rfcr = readl(dev->base_addr + RxFilterAddr);
2917 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) {
2918 writel(j*2, dev->base_addr + RxFilterAddr);
2919 rbuf[i++] = readw(dev->base_addr + RxFilterData);
2921 writel(rfcr, dev->base_addr + RxFilterAddr);
2923 /* the interrupt status is clear-on-read - see if we missed any */
2924 if (rbuf[4] & rbuf[5]) {
2926 "%s: shoot, we dropped an interrupt (%#08x)\n",
2927 dev->name, rbuf[4] & rbuf[5]);
2933 #define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \
2934 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \
2935 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \
2936 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \
2937 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \
2938 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \
2939 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \
2940 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) )
2942 static int netdev_get_eeprom(struct net_device *dev, u8 *buf)
2945 u16 *ebuf = (u16 *)buf;
2947 /* eeprom_read reads 16 bits, and indexes by 16 bits */
2948 for (i = 0; i < NATSEMI_EEPROM_SIZE/2; i++) {
2949 ebuf[i] = eeprom_read(dev->base_addr, i);
2950 /* The EEPROM itself stores data bit-swapped, but eeprom_read
2951 * reads it back "sanely". So we swap it back here in order to
2952 * present it to userland as it is stored. */
2953 ebuf[i] = SWAP_BITS(ebuf[i]);
2958 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2960 struct mii_ioctl_data *data = if_mii(rq);
2961 struct netdev_private *np = netdev_priv(dev);
2965 return netdev_ethtool_ioctl(dev, rq->ifr_data);
2966 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2967 case SIOCDEVPRIVATE: /* for binary compat, remove in 2.5 */
2968 data->phy_id = np->phy_addr_external;
2971 case SIOCGMIIREG: /* Read MII PHY register. */
2972 case SIOCDEVPRIVATE+1: /* for binary compat, remove in 2.5 */
2973 /* The phy_id is not enough to uniquely identify
2974 * the intended target. Therefore the command is sent to
2975 * the given mii on the current port.
2977 if (dev->if_port == PORT_TP) {
2978 if ((data->phy_id & 0x1f) == np->phy_addr_external)
2979 data->val_out = mdio_read(dev,
2980 data->reg_num & 0x1f);
2984 move_int_phy(dev, data->phy_id & 0x1f);
2985 data->val_out = miiport_read(dev, data->phy_id & 0x1f,
2986 data->reg_num & 0x1f);
2990 case SIOCSMIIREG: /* Write MII PHY register. */
2991 case SIOCDEVPRIVATE+2: /* for binary compat, remove in 2.5 */
2992 if (!capable(CAP_NET_ADMIN))
2994 if (dev->if_port == PORT_TP) {
2995 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
2996 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
2997 np->advertising = data->val_in;
2998 mdio_write(dev, data->reg_num & 0x1f,
3002 if ((data->phy_id & 0x1f) == np->phy_addr_external) {
3003 if ((data->reg_num & 0x1f) == MII_ADVERTISE)
3004 np->advertising = data->val_in;
3006 move_int_phy(dev, data->phy_id & 0x1f);
3007 miiport_write(dev, data->phy_id & 0x1f,
3008 data->reg_num & 0x1f,
3017 static void enable_wol_mode(struct net_device *dev, int enable_intr)
3019 long ioaddr = dev->base_addr;
3020 struct netdev_private *np = netdev_priv(dev);
3022 if (netif_msg_wol(np))
3023 printk(KERN_INFO "%s: remaining active for wake-on-lan\n",
3026 /* For WOL we must restart the rx process in silent mode.
3027 * Write NULL to the RxRingPtr. Only possible if
3028 * rx process is stopped
3030 writel(0, ioaddr + RxRingPtr);
3032 /* read WoL status to clear */
3033 readl(ioaddr + WOLCmd);
3035 /* PME on, clear status */
3036 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun);
3038 /* and restart the rx process */
3039 writel(RxOn, ioaddr + ChipCmd);
3042 /* enable the WOL interrupt.
3043 * Could be used to send a netlink message.
3045 writel(WOLPkt | LinkChange, ioaddr + IntrMask);
3046 writel(1, ioaddr + IntrEnable);
3050 static int netdev_close(struct net_device *dev)
3052 long ioaddr = dev->base_addr;
3053 struct netdev_private *np = netdev_priv(dev);
3055 if (netif_msg_ifdown(np))
3057 "%s: Shutting down ethercard, status was %#04x.\n",
3058 dev->name, (int)readl(ioaddr + ChipCmd));
3059 if (netif_msg_pktdata(np))
3061 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
3062 dev->name, np->cur_tx, np->dirty_tx,
3063 np->cur_rx, np->dirty_rx);
3066 * FIXME: what if someone tries to close a device
3067 * that is suspended?
3068 * Should we reenable the nic to switch to
3069 * the final WOL settings?
3072 del_timer_sync(&np->timer);
3073 disable_irq(dev->irq);
3074 spin_lock_irq(&np->lock);
3075 /* Disable interrupts, and flush posted writes */
3076 writel(0, ioaddr + IntrEnable);
3077 readl(ioaddr + IntrEnable);
3079 spin_unlock_irq(&np->lock);
3080 enable_irq(dev->irq);
3082 free_irq(dev->irq, dev);
3084 /* Interrupt disabled, interrupt handler released,
3085 * queue stopped, timer deleted, rtnl_lock held
3086 * All async codepaths that access the driver are disabled.
3088 spin_lock_irq(&np->lock);
3090 readl(ioaddr + IntrMask);
3091 readw(ioaddr + MIntrStatus);
3094 writel(StatsFreeze, ioaddr + StatsCtrl);
3096 /* Stop the chip's Tx and Rx processes. */
3097 natsemi_stop_rxtx(dev);
3100 spin_unlock_irq(&np->lock);
3102 /* clear the carrier last - an interrupt could reenable it otherwise */
3103 netif_carrier_off(dev);
3104 netif_stop_queue(dev);
3111 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3113 /* restart the NIC in WOL mode.
3114 * The nic must be stopped for this.
3116 enable_wol_mode(dev, 0);
3118 /* Restore PME enable bit unmolested */
3119 writel(np->SavedClkRun, ioaddr + ClkRun);
3126 static void __devexit natsemi_remove1 (struct pci_dev *pdev)
3128 struct net_device *dev = pci_get_drvdata(pdev);
3130 unregister_netdev (dev);
3131 pci_release_regions (pdev);
3132 iounmap ((char *) dev->base_addr);
3134 pci_set_drvdata(pdev, NULL);
3140 * The ns83815 chip doesn't have explicit RxStop bits.
3141 * Kicking the Rx or Tx process for a new packet reenables the Rx process
3142 * of the nic, thus this function must be very careful:
3144 * suspend/resume synchronization:
3146 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler,
3147 * start_tx, tx_timeout
3149 * No function accesses the hardware without checking np->hands_off.
3150 * the check occurs under spin_lock_irq(&np->lock);
3152 * * netdev_ioctl: noncritical access.
3153 * * netdev_open: cannot happen due to the device_detach
3154 * * netdev_close: doesn't hurt.
3155 * * netdev_timer: timer stopped by natsemi_suspend.
3156 * * intr_handler: doesn't acquire the spinlock. suspend calls
3157 * disable_irq() to enforce synchronization.
3159 * Interrupts must be disabled, otherwise hands_off can cause irq storms.
3162 static int natsemi_suspend (struct pci_dev *pdev, u32 state)
3164 struct net_device *dev = pci_get_drvdata (pdev);
3165 struct netdev_private *np = netdev_priv(dev);
3166 long ioaddr = dev->base_addr;
3169 if (netif_running (dev)) {
3170 del_timer_sync(&np->timer);
3172 disable_irq(dev->irq);
3173 spin_lock_irq(&np->lock);
3175 writel(0, ioaddr + IntrEnable);
3177 natsemi_stop_rxtx(dev);
3178 netif_stop_queue(dev);
3180 spin_unlock_irq(&np->lock);
3181 enable_irq(dev->irq);
3183 /* Update the error counts. */
3186 /* pci_power_off(pdev, -1); */
3189 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary;
3190 /* Restore PME enable bit */
3192 /* restart the NIC in WOL mode.
3193 * The nic must be stopped for this.
3194 * FIXME: use the WOL interrupt
3196 enable_wol_mode(dev, 0);
3198 /* Restore PME enable bit unmolested */
3199 writel(np->SavedClkRun, ioaddr + ClkRun);
3203 netif_device_detach(dev);
3209 static int natsemi_resume (struct pci_dev *pdev)
3211 struct net_device *dev = pci_get_drvdata (pdev);
3212 struct netdev_private *np = netdev_priv(dev);
3215 if (netif_device_present(dev))
3217 if (netif_running(dev)) {
3218 BUG_ON(!np->hands_off);
3219 pci_enable_device(pdev);
3220 /* pci_power_on(pdev); */
3224 disable_irq(dev->irq);
3225 spin_lock_irq(&np->lock);
3227 init_registers(dev);
3228 netif_device_attach(dev);
3229 spin_unlock_irq(&np->lock);
3230 enable_irq(dev->irq);
3232 mod_timer(&np->timer, jiffies + 1*HZ);
3234 netif_device_attach(dev);
3240 #endif /* CONFIG_PM */
3242 static struct pci_driver natsemi_driver = {
3244 .id_table = natsemi_pci_tbl,
3245 .probe = natsemi_probe1,
3246 .remove = __devexit_p(natsemi_remove1),
3248 .suspend = natsemi_suspend,
3249 .resume = natsemi_resume,
3253 static int __init natsemi_init_mod (void)
3255 /* when a module, this is printed whether or not devices are found in probe */
3260 return pci_module_init (&natsemi_driver);
3263 static void __exit natsemi_exit_mod (void)
3265 pci_unregister_driver (&natsemi_driver);
3268 module_init(natsemi_init_mod);
3269 module_exit(natsemi_exit_mod);