1 #define _VERSION "0.20"
2 /* ns83820.c by Benjamin LaHaise with contributions.
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
6 * $Revision: 1.34.2.23 $
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
11 * Mmmm, chocolate vanilla mocha...
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
63 * - fix missed txok introduced during performance
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
70 * This driver was originally written for the National Semiconductor
71 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
72 * this code will turn out to be a) clean, b) correct, and c) fast.
73 * With that in mind, I'm aiming to split the code up as much as
74 * reasonably possible. At present there are X major sections that
75 * break down into a) packet receive, b) packet transmit, c) link
76 * management, d) initialization and configuration. Where possible,
77 * these code paths are designed to run in parallel.
79 * This driver has been tested and found to work with the following
80 * cards (in no particular order):
82 * Cameo SOHO-GA2000T SOHO-GA2500T
84 * PureData PDP8023Z-TG
85 * SMC SMC9452TX SMC9462TX
88 * Special thanks to SMC for providing hardware to test this driver on.
90 * Reports of success or failure would be greatly appreciated.
92 //#define dprintk printk
93 #define dprintk(x...) do { } while (0)
95 #include <linux/module.h>
96 #include <linux/types.h>
97 #include <linux/pci.h>
98 #include <linux/netdevice.h>
99 #include <linux/etherdevice.h>
100 #include <linux/delay.h>
101 #include <linux/smp_lock.h>
102 #include <linux/workqueue.h>
103 #include <linux/init.h>
104 #include <linux/ip.h> /* for iph */
105 #include <linux/in.h> /* for IPPROTO_... */
106 #include <linux/eeprom.h>
107 #include <linux/compiler.h>
108 #include <linux/prefetch.h>
109 #include <linux/ethtool.h>
110 #include <linux/timer.h>
113 #include <asm/uaccess.h>
114 #include <asm/system.h>
116 /* Global parameters. See MODULE_PARM near the bottom. */
118 static int reset_phy = 0;
119 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
121 /* Dprintk is used for more interesting debug events */
123 #define Dprintk dprintk
125 #if defined(CONFIG_HIGHMEM64G) || defined(__ia64__)
126 #define USE_64BIT_ADDR "+"
129 #if defined(USE_64BIT_ADDR)
130 #define VERSION _VERSION USE_64BIT_ADDR
133 #define VERSION _VERSION
138 #define RX_BUF_SIZE 1500 /* 8192 */
140 /* Must not exceed ~65000. */
141 #define NR_RX_DESC 64
142 #define NR_TX_DESC 128
145 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
147 #define MIN_TX_DESC_FREE 8
149 /* register defines */
152 #define CR_TXE 0x00000001
153 #define CR_TXD 0x00000002
154 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
155 * The Receive engine skips one descriptor and moves
156 * onto the next one!! */
157 #define CR_RXE 0x00000004
158 #define CR_RXD 0x00000008
159 #define CR_TXR 0x00000010
160 #define CR_RXR 0x00000020
161 #define CR_SWI 0x00000080
162 #define CR_RST 0x00000100
164 #define PTSCR_EEBIST_FAIL 0x00000001
165 #define PTSCR_EEBIST_EN 0x00000002
166 #define PTSCR_EELOAD_EN 0x00000004
167 #define PTSCR_RBIST_FAIL 0x000001b8
168 #define PTSCR_RBIST_DONE 0x00000200
169 #define PTSCR_RBIST_EN 0x00000400
170 #define PTSCR_RBIST_RST 0x00002000
172 #define MEAR_EEDI 0x00000001
173 #define MEAR_EEDO 0x00000002
174 #define MEAR_EECLK 0x00000004
175 #define MEAR_EESEL 0x00000008
176 #define MEAR_MDIO 0x00000010
177 #define MEAR_MDDIR 0x00000020
178 #define MEAR_MDC 0x00000040
180 #define ISR_TXDESC3 0x40000000
181 #define ISR_TXDESC2 0x20000000
182 #define ISR_TXDESC1 0x10000000
183 #define ISR_TXDESC0 0x08000000
184 #define ISR_RXDESC3 0x04000000
185 #define ISR_RXDESC2 0x02000000
186 #define ISR_RXDESC1 0x01000000
187 #define ISR_RXDESC0 0x00800000
188 #define ISR_TXRCMP 0x00400000
189 #define ISR_RXRCMP 0x00200000
190 #define ISR_DPERR 0x00100000
191 #define ISR_SSERR 0x00080000
192 #define ISR_RMABT 0x00040000
193 #define ISR_RTABT 0x00020000
194 #define ISR_RXSOVR 0x00010000
195 #define ISR_HIBINT 0x00008000
196 #define ISR_PHY 0x00004000
197 #define ISR_PME 0x00002000
198 #define ISR_SWI 0x00001000
199 #define ISR_MIB 0x00000800
200 #define ISR_TXURN 0x00000400
201 #define ISR_TXIDLE 0x00000200
202 #define ISR_TXERR 0x00000100
203 #define ISR_TXDESC 0x00000080
204 #define ISR_TXOK 0x00000040
205 #define ISR_RXORN 0x00000020
206 #define ISR_RXIDLE 0x00000010
207 #define ISR_RXEARLY 0x00000008
208 #define ISR_RXERR 0x00000004
209 #define ISR_RXDESC 0x00000002
210 #define ISR_RXOK 0x00000001
212 #define TXCFG_CSI 0x80000000
213 #define TXCFG_HBI 0x40000000
214 #define TXCFG_MLB 0x20000000
215 #define TXCFG_ATP 0x10000000
216 #define TXCFG_ECRETRY 0x00800000
217 #define TXCFG_BRST_DIS 0x00080000
218 #define TXCFG_MXDMA1024 0x00000000
219 #define TXCFG_MXDMA512 0x00700000
220 #define TXCFG_MXDMA256 0x00600000
221 #define TXCFG_MXDMA128 0x00500000
222 #define TXCFG_MXDMA64 0x00400000
223 #define TXCFG_MXDMA32 0x00300000
224 #define TXCFG_MXDMA16 0x00200000
225 #define TXCFG_MXDMA8 0x00100000
227 #define CFG_LNKSTS 0x80000000
228 #define CFG_SPDSTS 0x60000000
229 #define CFG_SPDSTS1 0x40000000
230 #define CFG_SPDSTS0 0x20000000
231 #define CFG_DUPSTS 0x10000000
232 #define CFG_TBI_EN 0x01000000
233 #define CFG_MODE_1000 0x00400000
234 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
235 * Read the Phy response and then configure the MAC accordingly */
236 #define CFG_AUTO_1000 0x00200000
237 #define CFG_PINT_CTL 0x001c0000
238 #define CFG_PINT_DUPSTS 0x00100000
239 #define CFG_PINT_LNKSTS 0x00080000
240 #define CFG_PINT_SPDSTS 0x00040000
241 #define CFG_TMRTEST 0x00020000
242 #define CFG_MRM_DIS 0x00010000
243 #define CFG_MWI_DIS 0x00008000
244 #define CFG_T64ADDR 0x00004000
245 #define CFG_PCI64_DET 0x00002000
246 #define CFG_DATA64_EN 0x00001000
247 #define CFG_M64ADDR 0x00000800
248 #define CFG_PHY_RST 0x00000400
249 #define CFG_PHY_DIS 0x00000200
250 #define CFG_EXTSTS_EN 0x00000100
251 #define CFG_REQALG 0x00000080
252 #define CFG_SB 0x00000040
253 #define CFG_POW 0x00000020
254 #define CFG_EXD 0x00000010
255 #define CFG_PESEL 0x00000008
256 #define CFG_BROM_DIS 0x00000004
257 #define CFG_EXT_125 0x00000002
258 #define CFG_BEM 0x00000001
260 #define EXTSTS_UDPPKT 0x00200000
261 #define EXTSTS_TCPPKT 0x00080000
262 #define EXTSTS_IPPKT 0x00020000
264 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
266 #define MIBC_MIBS 0x00000008
267 #define MIBC_ACLR 0x00000004
268 #define MIBC_FRZ 0x00000002
269 #define MIBC_WRN 0x00000001
271 #define PCR_PSEN (1 << 31)
272 #define PCR_PS_MCAST (1 << 30)
273 #define PCR_PS_DA (1 << 29)
274 #define PCR_STHI_8 (3 << 23)
275 #define PCR_STLO_4 (1 << 23)
276 #define PCR_FFHI_8K (3 << 21)
277 #define PCR_FFLO_4K (1 << 21)
278 #define PCR_PAUSE_CNT 0xFFFE
280 #define RXCFG_AEP 0x80000000
281 #define RXCFG_ARP 0x40000000
282 #define RXCFG_STRIPCRC 0x20000000
283 #define RXCFG_RX_FD 0x10000000
284 #define RXCFG_ALP 0x08000000
285 #define RXCFG_AIRL 0x04000000
286 #define RXCFG_MXDMA512 0x00700000
287 #define RXCFG_DRTH 0x0000003e
288 #define RXCFG_DRTH0 0x00000002
290 #define RFCR_RFEN 0x80000000
291 #define RFCR_AAB 0x40000000
292 #define RFCR_AAM 0x20000000
293 #define RFCR_AAU 0x10000000
294 #define RFCR_APM 0x08000000
295 #define RFCR_APAT 0x07800000
296 #define RFCR_APAT3 0x04000000
297 #define RFCR_APAT2 0x02000000
298 #define RFCR_APAT1 0x01000000
299 #define RFCR_APAT0 0x00800000
300 #define RFCR_AARP 0x00400000
301 #define RFCR_MHEN 0x00200000
302 #define RFCR_UHEN 0x00100000
303 #define RFCR_ULM 0x00080000
305 #define VRCR_RUDPE 0x00000080
306 #define VRCR_RTCPE 0x00000040
307 #define VRCR_RIPE 0x00000020
308 #define VRCR_IPEN 0x00000010
309 #define VRCR_DUTF 0x00000008
310 #define VRCR_DVTF 0x00000004
311 #define VRCR_VTREN 0x00000002
312 #define VRCR_VTDEN 0x00000001
314 #define VTCR_PPCHK 0x00000008
315 #define VTCR_GCHK 0x00000004
316 #define VTCR_VPPTI 0x00000002
317 #define VTCR_VGTI 0x00000001
354 #define TBICR_MR_AN_ENABLE 0x00001000
355 #define TBICR_MR_RESTART_AN 0x00000200
357 #define TBISR_MR_LINK_STATUS 0x00000020
358 #define TBISR_MR_AN_COMPLETE 0x00000004
360 #define TANAR_PS2 0x00000100
361 #define TANAR_PS1 0x00000080
362 #define TANAR_HALF_DUP 0x00000040
363 #define TANAR_FULL_DUP 0x00000020
365 #define GPIOR_GP5_OE 0x00000200
366 #define GPIOR_GP4_OE 0x00000100
367 #define GPIOR_GP3_OE 0x00000080
368 #define GPIOR_GP2_OE 0x00000040
369 #define GPIOR_GP1_OE 0x00000020
370 #define GPIOR_GP3_OUT 0x00000004
371 #define GPIOR_GP1_OUT 0x00000001
373 #define LINK_AUTONEGOTIATE 0x01
374 #define LINK_DOWN 0x02
377 #ifdef USE_64BIT_ADDR
378 #define HW_ADDR_LEN 8
379 #define desc_addr_set(desc, addr) \
381 u64 __addr = (addr); \
382 (desc)[0] = cpu_to_le32(__addr); \
383 (desc)[1] = cpu_to_le32(__addr >> 32); \
385 #define desc_addr_get(desc) \
386 (((u64)le32_to_cpu((desc)[1]) << 32) \
387 | le32_to_cpu((desc)[0]))
389 #define HW_ADDR_LEN 4
390 #define desc_addr_set(desc, addr) ((desc)[0] = cpu_to_le32(addr))
391 #define desc_addr_get(desc) (le32_to_cpu((desc)[0]))
395 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
396 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
397 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
399 #define CMDSTS_OWN 0x80000000
400 #define CMDSTS_MORE 0x40000000
401 #define CMDSTS_INTR 0x20000000
402 #define CMDSTS_ERR 0x10000000
403 #define CMDSTS_OK 0x08000000
404 #define CMDSTS_LEN_MASK 0x0000ffff
406 #define CMDSTS_DEST_MASK 0x01800000
407 #define CMDSTS_DEST_SELF 0x00800000
408 #define CMDSTS_DEST_MULTI 0x01000000
410 #define DESC_SIZE 8 /* Should be cache line sized */
417 struct sk_buff *skbs[NR_RX_DESC];
420 u16 next_rx, next_empty;
423 dma_addr_t phy_descs;
428 struct net_device_stats stats;
431 struct pci_dev *pci_dev;
433 struct rx_info rx_info;
434 struct tasklet_struct rx_tasklet;
437 struct work_struct tq_refill;
439 /* protects everything below. irqsave when using. */
440 spinlock_t misc_lock;
454 volatile u16 tx_free_idx; /* idx of free desc chain */
458 struct sk_buff *tx_skbs[NR_TX_DESC];
460 char pad[16] __attribute__((aligned(16)));
462 dma_addr_t tx_phy_descs;
464 struct timer_list tx_watchdog;
467 static inline struct ns83820 *PRIV(struct net_device *dev)
469 return netdev_priv(dev);
472 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
474 static inline void kick_rx(struct net_device *ndev)
476 struct ns83820 *dev = PRIV(ndev);
477 dprintk("kick_rx: maybe kicking\n");
478 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
479 dprintk("actually kicking\n");
480 writel(dev->rx_info.phy_descs +
481 (4 * DESC_SIZE * dev->rx_info.next_rx),
483 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
484 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
490 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
491 #define start_tx_okay(dev) \
492 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
497 * The hardware supports linked lists of receive descriptors for
498 * which ownership is transfered back and forth by means of an
499 * ownership bit. While the hardware does support the use of a
500 * ring for receive descriptors, we only make use of a chain in
501 * an attempt to reduce bus traffic under heavy load scenarios.
502 * This will also make bugs a bit more obvious. The current code
503 * only makes use of a single rx chain; I hope to implement
504 * priority based rx for version 1.0. Goal: even under overload
505 * conditions, still route realtime traffic with as low jitter as
508 static inline void build_rx_desc(struct ns83820 *dev, u32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
510 desc_addr_set(desc + DESC_LINK, link);
511 desc_addr_set(desc + DESC_BUFPTR, buf);
512 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
514 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
517 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
518 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
525 next_empty = dev->rx_info.next_empty;
527 /* don't overrun last rx marker */
528 if (unlikely(nr_rx_empty(dev) <= 2)) {
534 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
535 dev->rx_info.next_empty,
536 dev->rx_info.nr_used,
541 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
542 if (unlikely(NULL != dev->rx_info.skbs[next_empty]))
544 dev->rx_info.skbs[next_empty] = skb;
546 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
547 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
548 buf = pci_map_single(dev->pci_dev, skb->tail,
549 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
550 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
551 /* update link of previous rx */
552 if (likely(next_empty != dev->rx_info.next_rx))
553 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
558 static inline int rx_refill(struct net_device *ndev, int gfp)
560 struct ns83820 *dev = PRIV(ndev);
562 unsigned long flags = 0;
564 if (unlikely(nr_rx_empty(dev) <= 2))
567 dprintk("rx_refill(%p)\n", ndev);
568 if (gfp == GFP_ATOMIC)
569 spin_lock_irqsave(&dev->rx_info.lock, flags);
570 for (i=0; i<NR_RX_DESC; i++) {
573 /* extra 16 bytes for alignment */
574 skb = __dev_alloc_skb(REAL_RX_BUF_SIZE+16, gfp);
578 res = (long)skb->tail & 0xf;
581 skb_reserve(skb, res);
584 if (gfp != GFP_ATOMIC)
585 spin_lock_irqsave(&dev->rx_info.lock, flags);
586 res = ns83820_add_rx_skb(dev, skb);
587 if (gfp != GFP_ATOMIC)
588 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
594 if (gfp == GFP_ATOMIC)
595 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
597 return i ? 0 : -ENOMEM;
600 static void FASTCALL(rx_refill_atomic(struct net_device *ndev));
601 static void fastcall rx_refill_atomic(struct net_device *ndev)
603 rx_refill(ndev, GFP_ATOMIC);
607 static inline void queue_refill(void *_dev)
609 struct net_device *ndev = _dev;
610 struct ns83820 *dev = PRIV(ndev);
612 rx_refill(ndev, GFP_KERNEL);
617 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
619 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
622 static void FASTCALL(phy_intr(struct net_device *ndev));
623 static void fastcall phy_intr(struct net_device *ndev)
625 struct ns83820 *dev = PRIV(ndev);
626 static char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
628 u32 tbisr, tanar, tanlpar;
629 int speed, fullduplex, newlinkstate;
631 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
633 if (dev->CFG_cache & CFG_TBI_EN) {
634 /* we have an optical transceiver */
635 tbisr = readl(dev->base + TBISR);
636 tanar = readl(dev->base + TANAR);
637 tanlpar = readl(dev->base + TANLPAR);
638 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
639 tbisr, tanar, tanlpar);
641 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP)
642 && (tanar & TANAR_FULL_DUP)) ) {
644 /* both of us are full duplex */
645 writel(readl(dev->base + TXCFG)
646 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
648 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
650 /* Light up full duplex LED */
651 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
654 } else if(((tanlpar & TANAR_HALF_DUP)
655 && (tanar & TANAR_HALF_DUP))
656 || ((tanlpar & TANAR_FULL_DUP)
657 && (tanar & TANAR_HALF_DUP))
658 || ((tanlpar & TANAR_HALF_DUP)
659 && (tanar & TANAR_FULL_DUP))) {
661 /* one or both of us are half duplex */
662 writel((readl(dev->base + TXCFG)
663 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
665 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
667 /* Turn off full duplex LED */
668 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
672 speed = 4; /* 1000F */
675 /* we have a copper transceiver */
676 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
678 if (cfg & CFG_SPDSTS1)
679 new_cfg |= CFG_MODE_1000;
681 new_cfg &= ~CFG_MODE_1000;
683 speed = ((cfg / CFG_SPDSTS0) & 3);
684 fullduplex = (cfg & CFG_DUPSTS);
689 if ((cfg & CFG_LNKSTS) &&
690 ((new_cfg ^ dev->CFG_cache) & CFG_MODE_1000)) {
691 writel(new_cfg, dev->base + CFG);
692 dev->CFG_cache = new_cfg;
695 dev->CFG_cache &= ~CFG_SPDSTS;
696 dev->CFG_cache |= cfg & CFG_SPDSTS;
699 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
701 if (newlinkstate & LINK_UP
702 && dev->linkstate != newlinkstate) {
703 netif_start_queue(ndev);
704 netif_wake_queue(ndev);
705 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
708 fullduplex ? "full" : "half");
709 } else if (newlinkstate & LINK_DOWN
710 && dev->linkstate != newlinkstate) {
711 netif_stop_queue(ndev);
712 printk(KERN_INFO "%s: link now down.\n", ndev->name);
715 dev->linkstate = newlinkstate;
718 static int ns83820_setup_rx(struct net_device *ndev)
720 struct ns83820 *dev = PRIV(ndev);
724 dprintk("ns83820_setup_rx(%p)\n", ndev);
726 dev->rx_info.idle = 1;
727 dev->rx_info.next_rx = 0;
728 dev->rx_info.next_rx_desc = dev->rx_info.descs;
729 dev->rx_info.next_empty = 0;
731 for (i=0; i<NR_RX_DESC; i++)
732 clear_rx_desc(dev, i);
734 writel(0, dev->base + RXDP_HI);
735 writel(dev->rx_info.phy_descs, dev->base + RXDP);
737 ret = rx_refill(ndev, GFP_KERNEL);
739 dprintk("starting receiver\n");
740 /* prevent the interrupt handler from stomping on us */
741 spin_lock_irq(&dev->rx_info.lock);
743 writel(0x0001, dev->base + CCSR);
744 writel(0, dev->base + RFCR);
745 writel(0x7fc00000, dev->base + RFCR);
746 writel(0xffc00000, dev->base + RFCR);
752 /* Okay, let it rip */
753 spin_lock_irq(&dev->misc_lock);
754 dev->IMR_cache |= ISR_PHY;
755 dev->IMR_cache |= ISR_RXRCMP;
756 //dev->IMR_cache |= ISR_RXERR;
757 //dev->IMR_cache |= ISR_RXOK;
758 dev->IMR_cache |= ISR_RXORN;
759 dev->IMR_cache |= ISR_RXSOVR;
760 dev->IMR_cache |= ISR_RXDESC;
761 dev->IMR_cache |= ISR_RXIDLE;
762 dev->IMR_cache |= ISR_TXDESC;
763 dev->IMR_cache |= ISR_TXIDLE;
765 writel(dev->IMR_cache, dev->base + IMR);
766 writel(1, dev->base + IER);
767 spin_unlock_irq(&dev->misc_lock);
771 spin_unlock_irq(&dev->rx_info.lock);
776 static void ns83820_cleanup_rx(struct ns83820 *dev)
781 dprintk("ns83820_cleanup_rx(%p)\n", dev);
783 /* disable receive interrupts */
784 spin_lock_irqsave(&dev->misc_lock, flags);
785 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
786 writel(dev->IMR_cache, dev->base + IMR);
787 spin_unlock_irqrestore(&dev->misc_lock, flags);
789 /* synchronize with the interrupt handler and kill it */
791 synchronize_irq(dev->pci_dev->irq);
793 /* touch the pci bus... */
794 readl(dev->base + IMR);
796 /* assumes the transmitter is already disabled and reset */
797 writel(0, dev->base + RXDP_HI);
798 writel(0, dev->base + RXDP);
800 for (i=0; i<NR_RX_DESC; i++) {
801 struct sk_buff *skb = dev->rx_info.skbs[i];
802 dev->rx_info.skbs[i] = NULL;
803 clear_rx_desc(dev, i);
809 static void FASTCALL(ns83820_rx_kick(struct net_device *ndev));
810 static void fastcall ns83820_rx_kick(struct net_device *ndev)
812 struct ns83820 *dev = PRIV(ndev);
813 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
814 if (dev->rx_info.up) {
815 rx_refill_atomic(ndev);
820 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
821 schedule_work(&dev->tq_refill);
824 if (dev->rx_info.idle)
825 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
831 static void FASTCALL(rx_irq(struct net_device *ndev));
832 static void fastcall rx_irq(struct net_device *ndev)
834 struct ns83820 *dev = PRIV(ndev);
835 struct rx_info *info = &dev->rx_info;
841 dprintk("rx_irq(%p)\n", ndev);
842 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
843 readl(dev->base + RXDP),
844 (long)(dev->rx_info.phy_descs),
845 (int)dev->rx_info.next_rx,
846 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
847 (int)dev->rx_info.next_empty,
848 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
851 spin_lock_irqsave(&info->lock, flags);
855 dprintk("walking descs\n");
856 next_rx = info->next_rx;
857 desc = info->next_rx_desc;
858 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
859 (cmdsts != CMDSTS_OWN)) {
861 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
862 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
864 dprintk("cmdsts: %08x\n", cmdsts);
865 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
866 dprintk("extsts: %08x\n", extsts);
868 skb = info->skbs[next_rx];
869 info->skbs[next_rx] = NULL;
870 info->next_rx = (next_rx + 1) % NR_RX_DESC;
873 clear_rx_desc(dev, next_rx);
875 pci_unmap_single(dev->pci_dev, bufptr,
876 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
877 if (likely(CMDSTS_OK & cmdsts)) {
878 int len = cmdsts & 0xffff;
881 goto netdev_mangle_me_harder_failed;
882 if (cmdsts & CMDSTS_DEST_MULTI)
883 dev->stats.multicast ++;
884 dev->stats.rx_packets ++;
885 dev->stats.rx_bytes += len;
886 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
887 skb->ip_summed = CHECKSUM_UNNECESSARY;
889 skb->ip_summed = CHECKSUM_NONE;
891 skb->protocol = eth_type_trans(skb, ndev);
892 if (NET_RX_DROP == netif_rx(skb)) {
893 netdev_mangle_me_harder_failed:
894 dev->stats.rx_dropped ++;
901 next_rx = info->next_rx;
902 desc = info->descs + (DESC_SIZE * next_rx);
904 info->next_rx = next_rx;
905 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
909 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
912 spin_unlock_irqrestore(&info->lock, flags);
915 static void rx_action(unsigned long _dev)
917 struct net_device *ndev = (void *)_dev;
918 struct ns83820 *dev = PRIV(ndev);
920 writel(ihr, dev->base + IHR);
922 spin_lock_irq(&dev->misc_lock);
923 dev->IMR_cache |= ISR_RXDESC;
924 writel(dev->IMR_cache, dev->base + IMR);
925 spin_unlock_irq(&dev->misc_lock);
928 ns83820_rx_kick(ndev);
931 /* Packet Transmit code
933 static inline void kick_tx(struct ns83820 *dev)
935 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
936 dev, dev->tx_idx, dev->tx_free_idx);
937 writel(CR_TXE, dev->base + CR);
940 /* No spinlock needed on the transmit irq path as the interrupt handler is
943 static void do_tx_done(struct net_device *ndev)
945 struct ns83820 *dev = PRIV(ndev);
946 u32 cmdsts, tx_done_idx, *desc;
948 spin_lock_irq(&dev->tx_lock);
950 dprintk("do_tx_done(%p)\n", ndev);
951 tx_done_idx = dev->tx_done_idx;
952 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
954 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
955 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
956 while ((tx_done_idx != dev->tx_free_idx) &&
957 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
962 if (cmdsts & CMDSTS_ERR)
963 dev->stats.tx_errors ++;
964 if (cmdsts & CMDSTS_OK)
965 dev->stats.tx_packets ++;
966 if (cmdsts & CMDSTS_OK)
967 dev->stats.tx_bytes += cmdsts & 0xffff;
969 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
970 tx_done_idx, dev->tx_free_idx, cmdsts);
971 skb = dev->tx_skbs[tx_done_idx];
972 dev->tx_skbs[tx_done_idx] = NULL;
973 dprintk("done(%p)\n", skb);
975 len = cmdsts & CMDSTS_LEN_MASK;
976 addr = desc_addr_get(desc + DESC_BUFPTR);
978 pci_unmap_single(dev->pci_dev,
982 dev_kfree_skb_irq(skb);
983 atomic_dec(&dev->nr_tx_skbs);
985 pci_unmap_page(dev->pci_dev,
990 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
991 dev->tx_done_idx = tx_done_idx;
992 desc[DESC_CMDSTS] = cpu_to_le32(0);
994 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
997 /* Allow network stack to resume queueing packets after we've
998 * finished transmitting at least 1/4 of the packets in the queue.
1000 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1001 dprintk("start_queue(%p)\n", ndev);
1002 netif_start_queue(ndev);
1003 netif_wake_queue(ndev);
1005 spin_unlock_irq(&dev->tx_lock);
1008 static void ns83820_cleanup_tx(struct ns83820 *dev)
1012 for (i=0; i<NR_TX_DESC; i++) {
1013 struct sk_buff *skb = dev->tx_skbs[i];
1014 dev->tx_skbs[i] = NULL;
1016 u32 *desc = dev->tx_descs + (i * DESC_SIZE);
1017 pci_unmap_single(dev->pci_dev,
1018 desc_addr_get(desc + DESC_BUFPTR),
1019 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1021 dev_kfree_skb_irq(skb);
1022 atomic_dec(&dev->nr_tx_skbs);
1026 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1029 /* transmit routine. This code relies on the network layer serializing
1030 * its calls in, but will run happily in parallel with the interrupt
1031 * handler. This code currently has provisions for fragmenting tx buffers
1032 * while trying to track down a bug in either the zero copy code or
1033 * the tx fifo (hence the MAX_FRAG_LEN).
1035 static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1037 struct ns83820 *dev = PRIV(ndev);
1038 u32 free_idx, cmdsts, extsts;
1039 int nr_free, nr_frags;
1040 unsigned tx_done_idx, last_idx;
1046 volatile u32 *first_desc;
1048 dprintk("ns83820_hard_start_xmit\n");
1050 nr_frags = skb_shinfo(skb)->nr_frags;
1052 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1053 netif_stop_queue(ndev);
1054 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1056 netif_start_queue(ndev);
1059 last_idx = free_idx = dev->tx_free_idx;
1060 tx_done_idx = dev->tx_done_idx;
1061 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1063 if (nr_free <= nr_frags) {
1064 dprintk("stop_queue - not enough(%p)\n", ndev);
1065 netif_stop_queue(ndev);
1067 /* Check again: we may have raced with a tx done irq */
1068 if (dev->tx_done_idx != tx_done_idx) {
1069 dprintk("restart queue(%p)\n", ndev);
1070 netif_start_queue(ndev);
1076 if (free_idx == dev->tx_intr_idx) {
1078 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1081 nr_free -= nr_frags;
1082 if (nr_free < MIN_TX_DESC_FREE) {
1083 dprintk("stop_queue - last entry(%p)\n", ndev);
1084 netif_stop_queue(ndev);
1088 frag = skb_shinfo(skb)->frags;
1092 if (skb->ip_summed == CHECKSUM_HW) {
1093 extsts |= EXTSTS_IPPKT;
1094 if (IPPROTO_TCP == skb->nh.iph->protocol)
1095 extsts |= EXTSTS_TCPPKT;
1096 else if (IPPROTO_UDP == skb->nh.iph->protocol)
1097 extsts |= EXTSTS_UDPPKT;
1102 len -= skb->data_len;
1103 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1105 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1108 volatile u32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1111 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1112 (unsigned long long)buf);
1113 last_idx = free_idx;
1114 free_idx = (free_idx + 1) % NR_TX_DESC;
1115 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1116 desc_addr_set(desc + DESC_BUFPTR, buf);
1117 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1119 cmdsts = ((nr_frags|residue) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1120 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1122 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1133 buf = pci_map_page(dev->pci_dev, frag->page,
1135 frag->size, PCI_DMA_TODEVICE);
1136 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1137 (long long)buf, (long) page_to_pfn(frag->page),
1143 dprintk("done pkt\n");
1145 spin_lock_irq(&dev->tx_lock);
1146 dev->tx_skbs[last_idx] = skb;
1147 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1148 dev->tx_free_idx = free_idx;
1149 atomic_inc(&dev->nr_tx_skbs);
1150 spin_unlock_irq(&dev->tx_lock);
1154 /* Check again: we may have raced with a tx done irq */
1155 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1156 netif_start_queue(ndev);
1158 /* set the transmit start time to catch transmit timeouts */
1159 ndev->trans_start = jiffies;
1163 static void ns83820_update_stats(struct ns83820 *dev)
1165 u8 *base = dev->base;
1167 /* the DP83820 will freeze counters, so we need to read all of them */
1168 dev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1169 dev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1170 dev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1171 dev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1172 /*dev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1173 dev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1174 dev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1175 /*dev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1176 /*dev->stats.rx_pause_count += */ readl(base + 0x80);
1177 /*dev->stats.tx_pause_count += */ readl(base + 0x84);
1178 dev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1181 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1183 struct ns83820 *dev = PRIV(ndev);
1185 /* somewhat overkill */
1186 spin_lock_irq(&dev->misc_lock);
1187 ns83820_update_stats(dev);
1188 spin_unlock_irq(&dev->misc_lock);
1193 static int ns83820_ethtool_ioctl (struct ns83820 *dev, void *useraddr)
1197 if (copy_from_user(ðcmd, useraddr, sizeof (ethcmd)))
1201 case ETHTOOL_GDRVINFO:
1203 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
1204 strcpy(info.driver, "ns83820");
1205 strcpy(info.version, VERSION);
1206 strcpy(info.bus_info, pci_name(dev->pci_dev));
1207 if (copy_to_user(useraddr, &info, sizeof (info)))
1212 /* get link status */
1213 case ETHTOOL_GLINK: {
1214 struct ethtool_value edata = { ETHTOOL_GLINK };
1215 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1217 if (cfg & CFG_LNKSTS)
1221 if (copy_to_user(useraddr, &edata, sizeof(edata)))
1233 static int ns83820_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1235 struct ns83820 *dev = PRIV(ndev);
1239 return ns83820_ethtool_ioctl(dev, (void *) rq->ifr_data);
1246 static void ns83820_mib_isr(struct ns83820 *dev)
1248 spin_lock(&dev->misc_lock);
1249 ns83820_update_stats(dev);
1250 spin_unlock(&dev->misc_lock);
1253 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1254 static irqreturn_t ns83820_irq(int foo, void *data, struct pt_regs *regs)
1256 struct net_device *ndev = data;
1257 struct ns83820 *dev = PRIV(ndev);
1259 dprintk("ns83820_irq(%p)\n", ndev);
1263 isr = readl(dev->base + ISR);
1264 dprintk("irq: %08x\n", isr);
1265 ns83820_do_isr(ndev, isr);
1269 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1271 struct ns83820 *dev = PRIV(ndev);
1273 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1274 Dprintk("odd isr? 0x%08x\n", isr);
1277 if (ISR_RXIDLE & isr) {
1278 dev->rx_info.idle = 1;
1279 Dprintk("oh dear, we are idle\n");
1280 ns83820_rx_kick(ndev);
1283 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1284 prefetch(dev->rx_info.next_rx_desc);
1286 spin_lock_irq(&dev->misc_lock);
1287 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1288 writel(dev->IMR_cache, dev->base + IMR);
1289 spin_unlock_irq(&dev->misc_lock);
1291 tasklet_schedule(&dev->rx_tasklet);
1293 //writel(4, dev->base + IHR);
1296 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1297 ns83820_rx_kick(ndev);
1299 if (unlikely(ISR_RXSOVR & isr)) {
1300 //printk("overrun: rxsovr\n");
1301 dev->stats.rx_fifo_errors ++;
1304 if (unlikely(ISR_RXORN & isr)) {
1305 //printk("overrun: rxorn\n");
1306 dev->stats.rx_fifo_errors ++;
1309 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1310 writel(CR_RXE, dev->base + CR);
1312 if (ISR_TXIDLE & isr) {
1314 txdp = readl(dev->base + TXDP);
1315 dprintk("txdp: %08x\n", txdp);
1316 txdp -= dev->tx_phy_descs;
1317 dev->tx_idx = txdp / (DESC_SIZE * 4);
1318 if (dev->tx_idx >= NR_TX_DESC) {
1319 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1322 /* The may have been a race between a pci originated read
1323 * and the descriptor update from the cpu. Just in case,
1324 * kick the transmitter if the hardware thinks it is on a
1325 * different descriptor than we are.
1327 if (dev->tx_idx != dev->tx_free_idx)
1331 /* Defer tx ring processing until more than a minimum amount of
1332 * work has accumulated
1334 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1337 /* Disable TxOk if there are no outstanding tx packets.
1339 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1340 (dev->IMR_cache & ISR_TXOK)) {
1341 spin_lock_irq(&dev->misc_lock);
1342 dev->IMR_cache &= ~ISR_TXOK;
1343 writel(dev->IMR_cache, dev->base + IMR);
1344 spin_unlock_irq(&dev->misc_lock);
1348 /* The TxIdle interrupt can come in before the transmit has
1349 * completed. Normally we reap packets off of the combination
1350 * of TxDesc and TxIdle and leave TxOk disabled (since it
1351 * occurs on every packet), but when no further irqs of this
1352 * nature are expected, we must enable TxOk.
1354 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1355 spin_lock_irq(&dev->misc_lock);
1356 dev->IMR_cache |= ISR_TXOK;
1357 writel(dev->IMR_cache, dev->base + IMR);
1358 spin_unlock_irq(&dev->misc_lock);
1361 /* MIB interrupt: one of the statistics counters is about to overflow */
1362 if (unlikely(ISR_MIB & isr))
1363 ns83820_mib_isr(dev);
1365 /* PHY: Link up/down/negotiation state change */
1366 if (unlikely(ISR_PHY & isr))
1369 #if 0 /* Still working on the interrupt mitigation strategy */
1371 writel(dev->ihr, dev->base + IHR);
1375 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1377 Dprintk("resetting chip...\n");
1378 writel(which, dev->base + CR);
1381 } while (readl(dev->base + CR) & which);
1385 static int ns83820_stop(struct net_device *ndev)
1387 struct ns83820 *dev = PRIV(ndev);
1389 /* FIXME: protect against interrupt handler? */
1390 del_timer_sync(&dev->tx_watchdog);
1392 /* disable interrupts */
1393 writel(0, dev->base + IMR);
1394 writel(0, dev->base + IER);
1395 readl(dev->base + IER);
1397 dev->rx_info.up = 0;
1398 synchronize_irq(dev->pci_dev->irq);
1400 ns83820_do_reset(dev, CR_RST);
1402 synchronize_irq(dev->pci_dev->irq);
1404 spin_lock_irq(&dev->misc_lock);
1405 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1406 spin_unlock_irq(&dev->misc_lock);
1408 ns83820_cleanup_rx(dev);
1409 ns83820_cleanup_tx(dev);
1414 static void ns83820_tx_timeout(struct net_device *ndev)
1416 struct ns83820 *dev = PRIV(ndev);
1417 u32 tx_done_idx, *desc;
1418 unsigned long flags;
1420 local_irq_save(flags);
1422 tx_done_idx = dev->tx_done_idx;
1423 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1425 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1427 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1432 isr = readl(dev->base + ISR);
1433 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1434 ns83820_do_isr(ndev, isr);
1440 tx_done_idx = dev->tx_done_idx;
1441 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1443 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1445 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1447 local_irq_restore(flags);
1450 static void ns83820_tx_watch(unsigned long data)
1452 struct net_device *ndev = (void *)data;
1453 struct ns83820 *dev = PRIV(ndev);
1456 printk("ns83820_tx_watch: %u %u %d\n",
1457 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1461 if (time_after(jiffies, ndev->trans_start + 1*HZ) &&
1462 dev->tx_done_idx != dev->tx_free_idx) {
1463 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1465 dev->tx_done_idx, dev->tx_free_idx,
1466 atomic_read(&dev->nr_tx_skbs));
1467 ns83820_tx_timeout(ndev);
1470 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1473 static int ns83820_open(struct net_device *ndev)
1475 struct ns83820 *dev = PRIV(ndev);
1480 dprintk("ns83820_open\n");
1482 writel(0, dev->base + PQCR);
1484 ret = ns83820_setup_rx(ndev);
1488 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1489 for (i=0; i<NR_TX_DESC; i++) {
1490 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1493 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1497 dev->tx_done_idx = 0;
1498 desc = dev->tx_phy_descs;
1499 writel(0, dev->base + TXDP_HI);
1500 writel(desc, dev->base + TXDP);
1502 init_timer(&dev->tx_watchdog);
1503 dev->tx_watchdog.data = (unsigned long)ndev;
1504 dev->tx_watchdog.function = ns83820_tx_watch;
1505 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1507 netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1516 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1519 for (i=0; i<3; i++) {
1521 #if 0 /* I've left this in as an example of how to use eeprom.h */
1522 data = eeprom_readw(&dev->ee, 0xa + 2 - i);
1524 /* Read from the perfect match memory: this is loaded by
1525 * the chip from the EEPROM via the EELOAD self test.
1527 writel(i*2, dev->base + RFCR);
1528 data = readl(dev->base + RFDR);
1535 static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
1537 if (new_mtu > RX_BUF_SIZE)
1539 ndev->mtu = new_mtu;
1543 static void ns83820_set_multicast(struct net_device *ndev)
1545 struct ns83820 *dev = PRIV(ndev);
1546 u8 *rfcr = dev->base + RFCR;
1547 u32 and_mask = 0xffffffff;
1551 if (ndev->flags & IFF_PROMISC)
1552 or_mask |= RFCR_AAU | RFCR_AAM;
1554 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1556 if (ndev->flags & IFF_ALLMULTI)
1557 or_mask |= RFCR_AAM;
1559 and_mask &= ~RFCR_AAM;
1561 spin_lock_irq(&dev->misc_lock);
1562 val = (readl(rfcr) & and_mask) | or_mask;
1563 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1564 writel(val & ~RFCR_RFEN, rfcr);
1566 spin_unlock_irq(&dev->misc_lock);
1569 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1571 struct ns83820 *dev = PRIV(ndev);
1577 dprintk("%s: start %s\n", ndev->name, name);
1581 writel(enable, dev->base + PTSCR);
1584 status = readl(dev->base + PTSCR);
1585 if (!(status & enable))
1591 if ((jiffies - start) >= HZ) {
1595 set_current_state(TASK_UNINTERRUPTIBLE);
1596 schedule_timeout(1);
1600 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1601 ndev->name, name, status, fail);
1603 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1604 ndev->name, name, status);
1606 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1609 #ifdef PHY_CODE_IS_FINISHED
1610 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1613 dev->MEAR_cache &= ~MEAR_MDC;
1614 writel(dev->MEAR_cache, dev->base + MEAR);
1615 readl(dev->base + MEAR);
1617 /* enable output, set bit */
1618 dev->MEAR_cache |= MEAR_MDDIR;
1620 dev->MEAR_cache |= MEAR_MDIO;
1622 dev->MEAR_cache &= ~MEAR_MDIO;
1624 /* set the output bit */
1625 writel(dev->MEAR_cache, dev->base + MEAR);
1626 readl(dev->base + MEAR);
1628 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1631 /* drive MDC high causing the data bit to be latched */
1632 dev->MEAR_cache |= MEAR_MDC;
1633 writel(dev->MEAR_cache, dev->base + MEAR);
1634 readl(dev->base + MEAR);
1640 static int ns83820_mii_read_bit(struct ns83820 *dev)
1644 /* drive MDC low, disable output */
1645 dev->MEAR_cache &= ~MEAR_MDC;
1646 dev->MEAR_cache &= ~MEAR_MDDIR;
1647 writel(dev->MEAR_cache, dev->base + MEAR);
1648 readl(dev->base + MEAR);
1650 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1653 /* drive MDC high causing the data bit to be latched */
1654 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1655 dev->MEAR_cache |= MEAR_MDC;
1656 writel(dev->MEAR_cache, dev->base + MEAR);
1664 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1669 /* read some garbage so that we eventually sync up */
1670 for (i=0; i<64; i++)
1671 ns83820_mii_read_bit(dev);
1673 ns83820_mii_write_bit(dev, 0); /* start */
1674 ns83820_mii_write_bit(dev, 1);
1675 ns83820_mii_write_bit(dev, 1); /* opcode read */
1676 ns83820_mii_write_bit(dev, 0);
1678 /* write out the phy address: 5 bits, msb first */
1680 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1682 /* write out the register address, 5 bits, msb first */
1684 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1686 ns83820_mii_read_bit(dev); /* turn around cycles */
1687 ns83820_mii_read_bit(dev);
1689 /* read in the register data, 16 bits msb first */
1690 for (i=0; i<16; i++) {
1692 data |= ns83820_mii_read_bit(dev);
1698 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1702 /* read some garbage so that we eventually sync up */
1703 for (i=0; i<64; i++)
1704 ns83820_mii_read_bit(dev);
1706 ns83820_mii_write_bit(dev, 0); /* start */
1707 ns83820_mii_write_bit(dev, 1);
1708 ns83820_mii_write_bit(dev, 0); /* opcode read */
1709 ns83820_mii_write_bit(dev, 1);
1711 /* write out the phy address: 5 bits, msb first */
1713 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1715 /* write out the register address, 5 bits, msb first */
1717 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1719 ns83820_mii_read_bit(dev); /* turn around cycles */
1720 ns83820_mii_read_bit(dev);
1722 /* read in the register data, 16 bits msb first */
1723 for (i=0; i<16; i++)
1724 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1729 static void ns83820_probe_phy(struct net_device *ndev)
1731 struct ns83820 *dev = PRIV(ndev);
1734 #define MII_PHYIDR1 0x02
1735 #define MII_PHYIDR2 0x03
1740 ns83820_mii_read_reg(dev, 1, 0x09);
1741 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1743 tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1744 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1746 ns83820_mii_read_reg(dev, 1, 0x09);
1751 for (i=1; i<2; i++) {
1754 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1755 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1757 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1758 // ndev->name, i, a, b);
1760 for (j=0; j<0x16; j+=4) {
1761 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1763 ns83820_mii_read_reg(dev, i, 0 + j),
1764 ns83820_mii_read_reg(dev, i, 1 + j),
1765 ns83820_mii_read_reg(dev, i, 2 + j),
1766 ns83820_mii_read_reg(dev, i, 3 + j)
1772 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1773 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1774 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1775 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1777 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1778 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1779 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1780 dprintk("version: 0x%04x 0x%04x\n", a, b);
1785 static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_device_id *id)
1787 struct net_device *ndev;
1788 struct ns83820 *dev;
1793 /* See if we can set the dma mask early on; failure is fatal. */
1794 if (TRY_DAC && !pci_set_dma_mask(pci_dev, 0xffffffffffffffffULL)) {
1796 } else if (!pci_set_dma_mask(pci_dev, 0xffffffff)) {
1799 printk(KERN_WARNING "ns83820.c: pci_set_dma_mask failed!\n");
1803 ndev = alloc_etherdev(sizeof(struct ns83820));
1809 spin_lock_init(&dev->rx_info.lock);
1810 spin_lock_init(&dev->tx_lock);
1811 spin_lock_init(&dev->misc_lock);
1812 dev->pci_dev = pci_dev;
1814 dev->ee.cache = &dev->MEAR_cache;
1815 dev->ee.lock = &dev->misc_lock;
1816 SET_MODULE_OWNER(ndev);
1817 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1819 INIT_WORK(&dev->tq_refill, queue_refill, ndev);
1820 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
1822 err = pci_enable_device(pci_dev);
1824 printk(KERN_INFO "ns83820: pci_enable_dev failed: %d\n", err);
1828 pci_set_master(pci_dev);
1829 addr = pci_resource_start(pci_dev, 1);
1830 dev->base = ioremap_nocache(addr, PAGE_SIZE);
1831 dev->tx_descs = pci_alloc_consistent(pci_dev,
1832 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
1833 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
1834 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
1836 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1839 dprintk("%p: %08lx %p: %08lx\n",
1840 dev->tx_descs, (long)dev->tx_phy_descs,
1841 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
1843 /* disable interrupts */
1844 writel(0, dev->base + IMR);
1845 writel(0, dev->base + IER);
1846 readl(dev->base + IER);
1850 setup_ee_mem_bitbanger(&dev->ee, (long)dev->base + MEAR, 3, 2, 1, 0,
1853 err = request_irq(pci_dev->irq, ns83820_irq, SA_SHIRQ,
1856 printk(KERN_INFO "ns83820: unable to register irq %d\n",
1862 * FIXME: we are holding rtnl_lock() over obscenely long area only
1863 * because some of the setup code uses dev->name. It's Wrong(tm) -
1864 * we should be using driver-specific names for all that stuff.
1865 * For now that will do, but we really need to come back and kill
1866 * most of the dev_alloc_name() users later.
1869 err = dev_alloc_name(ndev, ndev->name);
1871 printk(KERN_INFO "ns83820: unable to get netdev name: %d\n", err);
1875 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
1876 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
1877 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
1879 ndev->open = ns83820_open;
1880 ndev->stop = ns83820_stop;
1881 ndev->hard_start_xmit = ns83820_hard_start_xmit;
1882 ndev->get_stats = ns83820_get_stats;
1883 ndev->change_mtu = ns83820_change_mtu;
1884 ndev->set_multicast_list = ns83820_set_multicast;
1885 ndev->do_ioctl = ns83820_ioctl;
1886 ndev->tx_timeout = ns83820_tx_timeout;
1887 ndev->watchdog_timeo = 5 * HZ;
1889 pci_set_drvdata(pci_dev, ndev);
1891 ns83820_do_reset(dev, CR_RST);
1893 /* Must reset the ram bist before running it */
1894 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
1895 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
1896 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
1897 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
1899 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
1901 /* I love config registers */
1902 dev->CFG_cache = readl(dev->base + CFG);
1904 if ((dev->CFG_cache & CFG_PCI64_DET)) {
1905 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
1907 /*dev->CFG_cache |= CFG_DATA64_EN;*/
1908 if (!(dev->CFG_cache & CFG_DATA64_EN))
1909 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
1912 dev->CFG_cache &= ~(CFG_DATA64_EN);
1914 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
1915 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
1917 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
1918 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
1919 dev->CFG_cache |= CFG_REQALG;
1920 dev->CFG_cache |= CFG_POW;
1921 dev->CFG_cache |= CFG_TMRTEST;
1923 /* When compiled with 64 bit addressing, we must always enable
1924 * the 64 bit descriptor format.
1926 #ifdef USE_64BIT_ADDR
1927 dev->CFG_cache |= CFG_M64ADDR;
1930 dev->CFG_cache |= CFG_T64ADDR;
1932 /* Big endian mode does not seem to do what the docs suggest */
1933 dev->CFG_cache &= ~CFG_BEM;
1935 /* setup optical transceiver if we have one */
1936 if (dev->CFG_cache & CFG_TBI_EN) {
1937 printk(KERN_INFO "%s: enabling optical transceiver\n",
1939 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
1941 /* setup auto negotiation feature advertisement */
1942 writel(readl(dev->base + TANAR)
1943 | TANAR_HALF_DUP | TANAR_FULL_DUP,
1946 /* start auto negotiation */
1947 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1949 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1950 dev->linkstate = LINK_AUTONEGOTIATE;
1952 dev->CFG_cache |= CFG_MODE_1000;
1955 writel(dev->CFG_cache, dev->base + CFG);
1956 dprintk("CFG: %08x\n", dev->CFG_cache);
1959 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
1960 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
1961 set_current_state(TASK_UNINTERRUPTIBLE);
1962 schedule_timeout((HZ+99)/100);
1963 writel(dev->CFG_cache, dev->base + CFG);
1966 #if 0 /* Huh? This sets the PCI latency register. Should be done via
1967 * the PCI layer. FIXME.
1969 if (readl(dev->base + SRR))
1970 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
1973 /* Note! The DMA burst size interacts with packet
1974 * transmission, such that the largest packet that
1975 * can be transmitted is 8192 - FLTH - burst size.
1976 * If only the transmit fifo was larger...
1978 /* Ramit : 1024 DMA is not a good idea, it ends up banging
1979 * some DELL and COMPAQ SMP systems */
1980 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
1981 | ((1600 / 32) * 0x100),
1984 /* Flush the interrupt holdoff timer */
1985 writel(0x000, dev->base + IHR);
1986 writel(0x100, dev->base + IHR);
1987 writel(0x000, dev->base + IHR);
1989 /* Set Rx to full duplex, don't accept runt, errored, long or length
1990 * range errored packets. Use 512 byte DMA.
1992 /* Ramit : 1024 DMA is not a good idea, it ends up banging
1993 * some DELL and COMPAQ SMP systems
1994 * Turn on ALP, only we are accpeting Jumbo Packets */
1995 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
1998 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2000 /* Disable priority queueing */
2001 writel(0, dev->base + PQCR);
2003 /* Enable IP checksum validation and detetion of VLAN headers.
2004 * Note: do not set the reject options as at least the 0x102
2005 * revision of the chip does not properly accept IP fragments
2008 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2009 * the MAC it calculates the packetsize AFTER stripping the VLAN
2010 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2011 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2012 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2013 * it discrards it!. These guys......
2015 writel(VRCR_IPEN | VRCR_VTDEN, dev->base + VRCR);
2017 /* Enable per-packet TCP/UDP/IP checksumming */
2018 writel(VTCR_PPCHK, dev->base + VTCR);
2020 /* Ramit : Enable async and sync pause frames */
2021 /* writel(0, dev->base + PCR); */
2022 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2023 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2026 /* Disable Wake On Lan */
2027 writel(0, dev->base + WCSR);
2029 ns83820_getmac(dev, ndev->dev_addr);
2031 /* Yes, we support dumb IP checksum on transmit */
2032 ndev->features |= NETIF_F_SG;
2033 ndev->features |= NETIF_F_IP_CSUM;
2036 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2038 ndev->features |= NETIF_F_HIGHDMA;
2041 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %02x:%02x:%02x:%02x:%02x:%02x io=0x%08lx irq=%d f=%s\n",
2043 (unsigned)readl(dev->base + SRR) >> 8,
2044 (unsigned)readl(dev->base + SRR) & 0xff,
2045 ndev->dev_addr[0], ndev->dev_addr[1],
2046 ndev->dev_addr[2], ndev->dev_addr[3],
2047 ndev->dev_addr[4], ndev->dev_addr[5],
2049 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2052 #ifdef PHY_CODE_IS_FINISHED
2053 ns83820_probe_phy(ndev);
2056 err = register_netdevice(ndev);
2058 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2066 writel(0, dev->base + IMR); /* paranoia */
2067 writel(0, dev->base + IER);
2068 readl(dev->base + IER);
2071 free_irq(pci_dev->irq, ndev);
2075 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2076 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2077 pci_disable_device(pci_dev);
2080 pci_set_drvdata(pci_dev, NULL);
2085 static void __devexit ns83820_remove_one(struct pci_dev *pci_dev)
2087 struct net_device *ndev = pci_get_drvdata(pci_dev);
2088 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2090 if (!ndev) /* paranoia */
2093 writel(0, dev->base + IMR); /* paranoia */
2094 writel(0, dev->base + IER);
2095 readl(dev->base + IER);
2097 unregister_netdev(ndev);
2098 free_irq(dev->pci_dev->irq, ndev);
2100 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2101 dev->tx_descs, dev->tx_phy_descs);
2102 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2103 dev->rx_info.descs, dev->rx_info.phy_descs);
2104 pci_disable_device(dev->pci_dev);
2106 pci_set_drvdata(pci_dev, NULL);
2109 static struct pci_device_id ns83820_pci_tbl[] = {
2110 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2114 static struct pci_driver driver = {
2116 .id_table = ns83820_pci_tbl,
2117 .probe = ns83820_init_one,
2118 .remove = __devexit_p(ns83820_remove_one),
2119 #if 0 /* FIXME: implement */
2126 static int __init ns83820_init(void)
2128 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2129 return pci_module_init(&driver);
2132 static void __exit ns83820_exit(void)
2134 pci_unregister_driver(&driver);
2137 MODULE_AUTHOR("Benjamin LaHaise <bcrl@redhat.com>");
2138 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2139 MODULE_LICENSE("GPL");
2141 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2143 MODULE_PARM(lnksts, "i");
2144 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2146 MODULE_PARM(ihr, "i");
2147 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2149 MODULE_PARM(reset_phy, "i");
2150 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2152 module_init(ns83820_init);
2153 module_exit(ns83820_exit);