3 drivers/net/pci-skeleton.c
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
7 Original code came from 8139too.c, which in turns was based
8 originally on Donald Becker's rtl8139.c driver, versions 1.11
9 and older. This driver was originally based on rtl8139.c
10 version 1.07. Header of rtl8139.c version 1.11:
14 Written 1997-2000 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
23 This driver is for boards based on the RTL8129 and RTL8139
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
42 -----------------------------------------------------------------------------
46 I. Board Compatibility
48 This device driver is designed for the RealTek RTL8139 series, the RealTek
49 Fast Ethernet controllers for PCI and CardBus. This chip is used on many
50 low-end boards, sometimes with its markings changed.
53 II. Board-specific settings
55 PCI bus devices are configured by the system at boot time, so no jumpers
56 need to be set on the board. The system BIOS will assign the
57 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
63 The receive unit uses a single linear ring buffer rather than the more
64 common (and more efficient) descriptor-based architecture. Incoming frames
65 are sequentially stored into the Rx region, and the host copies them into
68 Comment: While it is theoretically possible to process many frames in place,
69 any delay in Rx processing would cause us to drop frames. More importantly,
70 the Linux protocol stack is not designed to operate in this manner.
74 The RTL8139 uses a fixed set of four Tx descriptors in register space.
75 In a stunningly bad design choice, Tx frames must be 32 bit aligned. Linux
76 aligns the IP header on word boundaries, and 14 byte ethernet header means
77 that almost all frames will need to be copied to an alignment buffer.
81 http://www.realtek.com.tw/cn/cn.html
82 http://www.scyld.com/expert/NWay.html
88 #include <linux/config.h>
89 #include <linux/module.h>
90 #include <linux/kernel.h>
91 #include <linux/pci.h>
92 #include <linux/init.h>
93 #include <linux/ioport.h>
94 #include <linux/netdevice.h>
95 #include <linux/etherdevice.h>
96 #include <linux/delay.h>
97 #include <linux/ethtool.h>
98 #include <linux/mii.h>
99 #include <linux/crc32.h>
102 #define NETDRV_VERSION "1.0.0"
103 #define MODNAME "netdrv"
104 #define NETDRV_DRIVER_LOAD_MSG "MyVendor Fast Ethernet driver " NETDRV_VERSION " loaded"
105 #define PFX MODNAME ": "
107 static char version[] __devinitdata =
108 KERN_INFO NETDRV_DRIVER_LOAD_MSG "\n"
109 KERN_INFO " Support available from http://foo.com/bar/baz.html\n";
111 /* define to 1 to enable PIO instead of MMIO */
114 /* define to 1 to enable copious debugging info */
117 /* define to 1 to disable lightweight runtime debugging checks */
122 /* note: prints function name for you */
123 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
125 # define DPRINTK(fmt, args...)
129 # define assert(expr) do {} while (0)
131 # define assert(expr) \
133 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
134 #expr,__FILE__,__FUNCTION__,__LINE__); \
139 /* A few user-configurable values. */
141 static int media[] = {-1, -1, -1, -1, -1, -1, -1, -1};
143 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
144 static int max_interrupt_work = 20;
146 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
147 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
148 static int multicast_filter_limit = 32;
150 /* Size of the in-memory receive ring. */
151 #define RX_BUF_LEN_IDX 2 /* 0==8K, 1==16K, 2==32K, 3==64K */
152 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
153 #define RX_BUF_PAD 16
154 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
155 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
157 /* Number of Tx descriptor registers. */
158 #define NUM_TX_DESC 4
160 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
161 #define MAX_ETH_FRAME_SIZE 1536
163 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
164 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
165 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
167 /* PCI Tuning Parameters
168 Threshold is bytes transferred to chip before transmission starts. */
169 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
171 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
172 #define RX_FIFO_THRESH 6 /* Rx buffer level before first PCI xfer. */
173 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
174 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
177 /* Operational parameters that usually are not changed. */
178 /* Time in jiffies before concluding the transmitter is hung. */
179 #define TX_TIMEOUT (6*HZ)
183 HAS_CHIP_XCVR = 0x020000,
184 HAS_LNK_CHNG = 0x040000,
187 #define NETDRV_MIN_IO_SIZE 0x80
188 #define RTL8139B_IO_SIZE 256
190 #define NETDRV_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
202 /* indexed by board_t, above */
205 } board_info[] __devinitdata = {
206 { "RealTek RTL8139 Fast Ethernet" },
207 { "RealTek RTL8139B PCI/CardBus" },
208 { "SMC1211TX EZCard 10/100 (RealTek RTL8139)" },
209 /* { MPX5030, "Accton MPX5030 (RealTek RTL8139)" },*/
210 { "Delta Electronics 8139 10/100BaseTX" },
211 { "Addtron Technolgy 8139 10/100BaseTX" },
215 static struct pci_device_id netdrv_pci_tbl[] = {
216 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
217 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, NETDRV_CB },
218 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
219 /* {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
220 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
221 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
224 MODULE_DEVICE_TABLE (pci, netdrv_pci_tbl);
227 /* The rest of these values should never change. */
229 /* Symbolic offsets to registers. */
230 enum NETDRV_registers {
231 MAC0 = 0, /* Ethernet hardware address. */
232 MAR0 = 8, /* Multicast filter. */
233 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
234 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
237 RxEarlyStatus = 0x36,
246 Timer = 0x48, /* A general-purpose counter. */
247 RxMissed = 0x4C, /* 24 bits valid, write clears. */
254 Config4 = 0x5A, /* absent on RTL-8139A */
258 BasicModeCtrl = 0x62,
259 BasicModeStatus = 0x64,
262 NWayExpansion = 0x6A,
263 /* Undocumented registers, but required for proper operation. */
264 FIFOTMS = 0x70, /* FIFO Control and test. */
265 CSCR = 0x74, /* Chip Status and Configuration Register. */
267 PARA7c = 0x7c, /* Magic transceiver parameter register. */
268 Config5 = 0xD8, /* absent on RTL-8139A */
272 MultiIntrClear = 0xF000,
274 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
284 /* Interrupt register bits, using my own meaningful names. */
285 enum IntrStatusBits {
300 TxOutOfWindow = 0x20000000,
301 TxAborted = 0x40000000,
302 TxCarrierLost = 0x80000000,
305 RxMulticast = 0x8000,
307 RxBroadcast = 0x2000,
308 RxBadSymbol = 0x0020,
316 /* Bits in RxConfig. */
320 AcceptBroadcast = 0x08,
321 AcceptMulticast = 0x04,
323 AcceptAllPhys = 0x01,
326 /* Bits in TxConfig. */
327 enum tx_config_bits {
328 TxIFG1 = (1 << 25), /* Interframe Gap Time */
329 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
330 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
331 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
332 TxClearAbt = (1 << 0), /* Clear abort (WO) */
333 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
335 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
338 /* Bits in Config1 */
340 Cfg1_PM_Enable = 0x01,
341 Cfg1_VPD_Enable = 0x02,
345 Cfg1_Driver_Load = 0x20,
351 /* Early Rx threshold, none or X/16 */
352 RxCfgEarlyRxNone = 0,
353 RxCfgEarlyRxShift = 24,
355 /* rx fifo threshold */
357 RxCfgFIFONone = (7 << RxCfgFIFOShift),
361 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
363 /* rx ring buffer length */
365 RxCfgRcv16K = (1 << 11),
366 RxCfgRcv32K = (1 << 12),
367 RxCfgRcv64K = (1 << 11) | (1 << 12),
369 /* Disable packet wrap at end of Rx buffer */
374 /* Twister tuning parameters from RealTek.
375 Completely undocumented, but required to tune bad links. */
377 CSCR_LinkOKBit = 0x0400,
378 CSCR_LinkChangeBit = 0x0800,
379 CSCR_LinkStatusBits = 0x0f000,
380 CSCR_LinkDownOffCmd = 0x003c0,
381 CSCR_LinkDownCmd = 0x0f3c0,
387 Cfg9346_Unlock = 0xC0,
391 #define PARA78_default 0x78fa8388
392 #define PARA7c_default 0xcb38de43 /* param[0][3] */
393 #define PARA7c_xxx 0xcb38de43
394 static const unsigned long param[4][4] = {
395 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
396 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
397 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
398 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
417 /* directly indexed by chip_t, above */
418 const static struct {
420 u8 version; /* from RTL8139C docs */
421 u32 RxConfigMask; /* should clear the bits supported by this chip */
422 } rtl_chip_info[] = {
425 0xf0fe0040, /* XXX copied from RTL8139A, verify */
445 0xf0fe0040, /* XXX copied from RTL8139A, verify */
450 0xf0fc0040, /* XXX copied from RTL8139B, verify */
456 struct netdrv_private {
460 struct pci_dev *pci_dev;
461 struct net_device_stats stats;
462 struct timer_list timer; /* Media selection timer. */
463 unsigned char *rx_ring;
464 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
465 unsigned int tx_flag;
468 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
469 struct ring_info tx_info[NUM_TX_DESC];
470 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
471 unsigned char *tx_bufs; /* Tx bounce buffer region. */
472 dma_addr_t rx_ring_dma;
473 dma_addr_t tx_bufs_dma;
474 char phys[4]; /* MII device addresses. */
475 char twistie, twist_row, twist_col; /* Twister tune state. */
476 unsigned int full_duplex:1; /* Full-duplex operation requested. */
477 unsigned int duplex_lock:1;
478 unsigned int default_port:4; /* Last dev->if_port value. */
479 unsigned int media2:4; /* Secondary monitored media port. */
480 unsigned int medialock:1; /* Don't sense media type. */
481 unsigned int mediasense:1; /* Media sensing in progress. */
486 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
487 MODULE_DESCRIPTION ("Skeleton for a PCI Fast Ethernet driver");
488 MODULE_LICENSE("GPL");
489 MODULE_PARM (multicast_filter_limit, "i");
490 MODULE_PARM (max_interrupt_work, "i");
491 MODULE_PARM (debug, "i");
492 MODULE_PARM (media, "1-" __MODULE_STRING(8) "i");
493 MODULE_PARM_DESC (multicast_filter_limit, "pci-skeleton maximum number of filtered multicast addresses");
494 MODULE_PARM_DESC (max_interrupt_work, "pci-skeleton maximum events handled per interrupt");
495 MODULE_PARM_DESC (media, "pci-skeleton: Bits 0-3: media type, bit 17: full duplex");
496 MODULE_PARM_DESC (debug, "(unused)");
498 static int read_eeprom (void *ioaddr, int location, int addr_len);
499 static int netdrv_open (struct net_device *dev);
500 static int mdio_read (struct net_device *dev, int phy_id, int location);
501 static void mdio_write (struct net_device *dev, int phy_id, int location,
503 static void netdrv_timer (unsigned long data);
504 static void netdrv_tx_timeout (struct net_device *dev);
505 static void netdrv_init_ring (struct net_device *dev);
506 static int netdrv_start_xmit (struct sk_buff *skb,
507 struct net_device *dev);
508 static irqreturn_t netdrv_interrupt (int irq, void *dev_instance,
509 struct pt_regs *regs);
510 static int netdrv_close (struct net_device *dev);
511 static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
512 static struct net_device_stats *netdrv_get_stats (struct net_device *dev);
513 static void netdrv_set_rx_mode (struct net_device *dev);
514 static void netdrv_hw_start (struct net_device *dev);
519 #define NETDRV_R8(reg) inb (((unsigned long)ioaddr) + (reg))
520 #define NETDRV_R16(reg) inw (((unsigned long)ioaddr) + (reg))
521 #define NETDRV_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
522 #define NETDRV_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
523 #define NETDRV_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
524 #define NETDRV_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
525 #define NETDRV_W8_F NETDRV_W8
526 #define NETDRV_W16_F NETDRV_W16
527 #define NETDRV_W32_F NETDRV_W32
534 #define readb(addr) inb((unsigned long)(addr))
535 #define readw(addr) inw((unsigned long)(addr))
536 #define readl(addr) inl((unsigned long)(addr))
537 #define writeb(val,addr) outb((val),(unsigned long)(addr))
538 #define writew(val,addr) outw((val),(unsigned long)(addr))
539 #define writel(val,addr) outl((val),(unsigned long)(addr))
543 /* write MMIO register, with flush */
544 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
545 #define NETDRV_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
546 #define NETDRV_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
547 #define NETDRV_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
550 #if MMIO_FLUSH_AUDIT_COMPLETE
552 /* write MMIO register */
553 #define NETDRV_W8(reg, val8) writeb ((val8), ioaddr + (reg))
554 #define NETDRV_W16(reg, val16) writew ((val16), ioaddr + (reg))
555 #define NETDRV_W32(reg, val32) writel ((val32), ioaddr + (reg))
559 /* write MMIO register, then flush */
560 #define NETDRV_W8 NETDRV_W8_F
561 #define NETDRV_W16 NETDRV_W16_F
562 #define NETDRV_W32 NETDRV_W32_F
564 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
566 /* read MMIO register */
567 #define NETDRV_R8(reg) readb (ioaddr + (reg))
568 #define NETDRV_R16(reg) readw (ioaddr + (reg))
569 #define NETDRV_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
571 #endif /* USE_IO_OPS */
574 static const u16 netdrv_intr_mask =
575 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
576 TxErr | TxOK | RxErr | RxOK;
578 static const unsigned int netdrv_rx_config =
579 RxCfgEarlyRxNone | RxCfgRcv32K | RxNoWrap |
580 (RX_FIFO_THRESH << RxCfgFIFOShift) |
581 (RX_DMA_BURST << RxCfgDMAShift);
584 static int __devinit netdrv_init_board (struct pci_dev *pdev,
585 struct net_device **dev_out,
589 struct net_device *dev;
590 struct netdrv_private *tp;
593 u32 pio_start, pio_end, pio_flags, pio_len;
594 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
599 assert (pdev != NULL);
600 assert (ioaddr_out != NULL);
605 /* dev zeroed in alloc_etherdev */
606 dev = alloc_etherdev (sizeof (*tp));
608 printk (KERN_ERR PFX "unable to alloc new ethernet\n");
609 DPRINTK ("EXIT, returning -ENOMEM\n");
612 SET_MODULE_OWNER(dev);
613 SET_NETDEV_DEV(dev, &pdev->dev);
616 /* enable device (incl. PCI PM wakeup), and bus-mastering */
617 rc = pci_enable_device (pdev);
621 pio_start = pci_resource_start (pdev, 0);
622 pio_end = pci_resource_end (pdev, 0);
623 pio_flags = pci_resource_flags (pdev, 0);
624 pio_len = pci_resource_len (pdev, 0);
626 mmio_start = pci_resource_start (pdev, 1);
627 mmio_end = pci_resource_end (pdev, 1);
628 mmio_flags = pci_resource_flags (pdev, 1);
629 mmio_len = pci_resource_len (pdev, 1);
631 /* set this immediately, we need to know before
632 * we talk to the chip directly */
633 DPRINTK("PIO region size == 0x%02X\n", pio_len);
634 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
636 /* make sure PCI base addr 0 is PIO */
637 if (!(pio_flags & IORESOURCE_IO)) {
638 printk (KERN_ERR PFX "region #0 not a PIO resource, aborting\n");
643 /* make sure PCI base addr 1 is MMIO */
644 if (!(mmio_flags & IORESOURCE_MEM)) {
645 printk (KERN_ERR PFX "region #1 not an MMIO resource, aborting\n");
650 /* check for weird/broken PCI region reporting */
651 if ((pio_len < NETDRV_MIN_IO_SIZE) ||
652 (mmio_len < NETDRV_MIN_IO_SIZE)) {
653 printk (KERN_ERR PFX "Invalid PCI region size(s), aborting\n");
658 rc = pci_request_regions (pdev, "pci-skeleton");
662 pci_set_master (pdev);
665 ioaddr = (void *) pio_start;
667 /* ioremap MMIO region */
668 ioaddr = ioremap (mmio_start, mmio_len);
669 if (ioaddr == NULL) {
670 printk (KERN_ERR PFX "cannot remap MMIO, aborting\n");
672 goto err_out_free_res;
674 #endif /* USE_IO_OPS */
676 /* Soft reset the chip. */
677 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
679 /* Check that the chip has finished the reset. */
680 for (i = 1000; i > 0; i--)
681 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
686 /* Bring the chip out of low-power mode. */
687 /* <insert device-specific code here> */
690 /* sanity checks -- ensure PIO and MMIO registers agree */
691 assert (inb (pio_start+Config0) == readb (ioaddr+Config0));
692 assert (inb (pio_start+Config1) == readb (ioaddr+Config1));
693 assert (inb (pio_start+TxConfig) == readb (ioaddr+TxConfig));
694 assert (inb (pio_start+RxConfig) == readb (ioaddr+RxConfig));
695 #endif /* !USE_IO_OPS */
697 /* identify chip attached to board */
698 tmp = NETDRV_R8 (ChipVersion);
699 for (i = ARRAY_SIZE (rtl_chip_info) - 1; i >= 0; i--)
700 if (tmp == rtl_chip_info[i].version) {
705 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
706 printk (KERN_DEBUG PFX "PCI device %s: unknown chip version, assuming RTL-8139\n",
708 printk (KERN_DEBUG PFX "PCI device %s: TxConfig = 0x%lx\n", pci_name(pdev), NETDRV_R32 (TxConfig));
712 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
715 rtl_chip_info[tp->chipset].name);
717 i = register_netdev (dev);
721 DPRINTK ("EXIT, returning 0\n");
722 *ioaddr_out = ioaddr;
731 pci_release_regions (pdev);
734 DPRINTK ("EXIT, returning %d\n", rc);
739 static int __devinit netdrv_init_one (struct pci_dev *pdev,
740 const struct pci_device_id *ent)
742 struct net_device *dev = NULL;
743 struct netdrv_private *tp;
744 int i, addr_len, option;
746 static int board_idx = -1;
749 /* when built into the kernel, we only print version if device is found */
751 static int printed_version;
752 if (!printed_version++)
758 assert (pdev != NULL);
759 assert (ent != NULL);
763 i = netdrv_init_board (pdev, &dev, &ioaddr);
765 DPRINTK ("EXIT, returning %d\n", i);
771 assert (ioaddr != NULL);
772 assert (dev != NULL);
775 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
776 for (i = 0; i < 3; i++)
777 ((u16 *) (dev->dev_addr))[i] =
778 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
780 /* The Rtl8139-specific entries in the device structure. */
781 dev->open = netdrv_open;
782 dev->hard_start_xmit = netdrv_start_xmit;
783 dev->stop = netdrv_close;
784 dev->get_stats = netdrv_get_stats;
785 dev->set_multicast_list = netdrv_set_rx_mode;
786 dev->do_ioctl = netdrv_ioctl;
787 dev->tx_timeout = netdrv_tx_timeout;
788 dev->watchdog_timeo = TX_TIMEOUT;
790 dev->irq = pdev->irq;
791 dev->base_addr = (unsigned long) ioaddr;
793 /* dev->priv/tp zeroed and aligned in alloc_etherdev */
796 /* note: tp->chipset set in netdrv_init_board */
797 tp->drv_flags = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
798 PCI_COMMAND_MASTER | NETDRV_CAPS;
800 tp->board = ent->driver_data;
801 tp->mmio_addr = ioaddr;
802 tp->lock = SPIN_LOCK_UNLOCKED;
804 pci_set_drvdata(pdev, dev);
808 printk (KERN_INFO "%s: %s at 0x%lx, "
809 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
812 board_info[ent->driver_data].name,
814 dev->dev_addr[0], dev->dev_addr[1],
815 dev->dev_addr[2], dev->dev_addr[3],
816 dev->dev_addr[4], dev->dev_addr[5],
819 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
820 dev->name, rtl_chip_info[tp->chipset].name);
822 /* Put the chip into low-power mode. */
823 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
825 /* The lower four bits are the media type. */
826 option = (board_idx > 7) ? 0 : media[board_idx];
828 tp->full_duplex = (option & 0x200) ? 1 : 0;
829 tp->default_port = option & 15;
830 if (tp->default_port)
834 if (tp->full_duplex) {
836 "%s: Media type forced to Full Duplex.\n",
838 mdio_write (dev, tp->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
842 DPRINTK ("EXIT - returning 0\n");
847 static void __devexit netdrv_remove_one (struct pci_dev *pdev)
849 struct net_device *dev = pci_get_drvdata (pdev);
850 struct netdrv_private *np;
854 assert (dev != NULL);
859 unregister_netdev (dev);
862 iounmap (np->mmio_addr);
863 #endif /* !USE_IO_OPS */
865 pci_release_regions (pdev);
869 pci_set_drvdata (pdev, NULL);
871 pci_power_off (pdev, -1);
877 /* Serial EEPROM section. */
879 /* EEPROM_Ctrl bits. */
880 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
881 #define EE_CS 0x08 /* EEPROM chip select. */
882 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
883 #define EE_WRITE_0 0x00
884 #define EE_WRITE_1 0x02
885 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
886 #define EE_ENB (0x80 | EE_CS)
888 /* Delay between EEPROM clock transitions.
889 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
892 #define eeprom_delay() readl(ee_addr)
894 /* The EEPROM commands include the alway-set leading bit. */
895 #define EE_WRITE_CMD (5)
896 #define EE_READ_CMD (6)
897 #define EE_ERASE_CMD (7)
899 static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
903 void *ee_addr = ioaddr + Cfg9346;
904 int read_cmd = location | (EE_READ_CMD << addr_len);
908 writeb (EE_ENB & ~EE_CS, ee_addr);
909 writeb (EE_ENB, ee_addr);
912 /* Shift the read command bits out. */
913 for (i = 4 + addr_len; i >= 0; i--) {
914 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
915 writeb (EE_ENB | dataval, ee_addr);
917 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
920 writeb (EE_ENB, ee_addr);
923 for (i = 16; i > 0; i--) {
924 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
927 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
929 writeb (EE_ENB, ee_addr);
933 /* Terminate the EEPROM access. */
934 writeb (~EE_CS, ee_addr);
937 DPRINTK ("EXIT - returning %d\n", retval);
941 /* MII serial management: mostly bogus for now. */
942 /* Read and write the MII management registers using software-generated
943 serial MDIO protocol.
944 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
945 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
946 "overclocking" issues. */
947 #define MDIO_DIR 0x80
948 #define MDIO_DATA_OUT 0x04
949 #define MDIO_DATA_IN 0x02
950 #define MDIO_CLK 0x01
951 #define MDIO_WRITE0 (MDIO_DIR)
952 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
954 #define mdio_delay() readb(mdio_addr)
957 static char mii_2_8139_map[8] = {
969 /* Syncronize the MII management interface by shifting 32 one bits out. */
970 static void mdio_sync (void *mdio_addr)
976 for (i = 32; i >= 0; i--) {
977 writeb (MDIO_WRITE1, mdio_addr);
979 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
987 static int mdio_read (struct net_device *dev, int phy_id, int location)
989 struct netdrv_private *tp = dev->priv;
990 void *mdio_addr = tp->mmio_addr + Config4;
991 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
997 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
998 DPRINTK ("EXIT after directly using 8139 internal regs\n");
999 return location < 8 && mii_2_8139_map[location] ?
1000 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
1002 mdio_sync (mdio_addr);
1003 /* Shift the read command bits out. */
1004 for (i = 15; i >= 0; i--) {
1005 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1007 writeb (MDIO_DIR | dataval, mdio_addr);
1009 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1013 /* Read the two transition, 16 data, and wire-idle bits. */
1014 for (i = 19; i > 0; i--) {
1015 writeb (0, mdio_addr);
1018 (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1
1020 writeb (MDIO_CLK, mdio_addr);
1024 DPRINTK ("EXIT, returning %d\n", (retval >> 1) & 0xffff);
1025 return (retval >> 1) & 0xffff;
1029 static void mdio_write (struct net_device *dev, int phy_id, int location,
1032 struct netdrv_private *tp = dev->priv;
1033 void *mdio_addr = tp->mmio_addr + Config4;
1035 (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1038 DPRINTK ("ENTER\n");
1040 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1041 if (location < 8 && mii_2_8139_map[location]) {
1043 tp->mmio_addr + mii_2_8139_map[location]);
1044 readw (tp->mmio_addr + mii_2_8139_map[location]);
1046 DPRINTK ("EXIT after directly using 8139 internal regs\n");
1049 mdio_sync (mdio_addr);
1051 /* Shift the command bits out. */
1052 for (i = 31; i >= 0; i--) {
1054 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1055 writeb (dataval, mdio_addr);
1057 writeb (dataval | MDIO_CLK, mdio_addr);
1061 /* Clear out extra bits. */
1062 for (i = 2; i > 0; i--) {
1063 writeb (0, mdio_addr);
1065 writeb (MDIO_CLK, mdio_addr);
1073 static int netdrv_open (struct net_device *dev)
1075 struct netdrv_private *tp = dev->priv;
1078 void *ioaddr = tp->mmio_addr;
1081 DPRINTK ("ENTER\n");
1083 retval = request_irq (dev->irq, netdrv_interrupt, SA_SHIRQ, dev->name, dev);
1085 DPRINTK ("EXIT, returning %d\n", retval);
1089 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1091 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1093 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1094 free_irq(dev->irq, dev);
1097 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1098 tp->tx_bufs, tp->tx_bufs_dma);
1100 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1101 tp->rx_ring, tp->rx_ring_dma);
1103 DPRINTK ("EXIT, returning -ENOMEM\n");
1108 tp->full_duplex = tp->duplex_lock;
1109 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1111 netdrv_init_ring (dev);
1112 netdrv_hw_start (dev);
1114 DPRINTK ("%s: netdrv_open() ioaddr %#lx IRQ %d"
1115 " GP Pins %2.2x %s-duplex.\n",
1116 dev->name, pci_resource_start (tp->pci_dev, 1),
1117 dev->irq, NETDRV_R8 (MediaStatus),
1118 tp->full_duplex ? "full" : "half");
1120 /* Set the timer to switch to check for link beat and perhaps switch
1121 to an alternate media type. */
1122 init_timer (&tp->timer);
1123 tp->timer.expires = jiffies + 3 * HZ;
1124 tp->timer.data = (unsigned long) dev;
1125 tp->timer.function = &netdrv_timer;
1126 add_timer (&tp->timer);
1128 DPRINTK ("EXIT, returning 0\n");
1133 /* Start the hardware at open or resume. */
1134 static void netdrv_hw_start (struct net_device *dev)
1136 struct netdrv_private *tp = dev->priv;
1137 void *ioaddr = tp->mmio_addr;
1141 DPRINTK ("ENTER\n");
1143 /* Soft reset the chip. */
1144 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
1147 /* Check that the chip has finished the reset. */
1148 for (i = 1000; i > 0; i--)
1149 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
1152 /* Restore our idea of the MAC address. */
1153 NETDRV_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1154 NETDRV_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1156 /* Must enable Tx/Rx before setting transfer thresholds! */
1157 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1158 CmdRxEnb | CmdTxEnb);
1160 i = netdrv_rx_config |
1161 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1162 NETDRV_W32_F (RxConfig, i);
1164 /* Check this value: the documentation for IFG contradicts ifself. */
1165 NETDRV_W32 (TxConfig, (TX_DMA_BURST << TxDMAShift));
1167 /* unlock Config[01234] and BMCR register writes */
1168 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
1173 /* Lock Config[01234] and BMCR register writes */
1174 NETDRV_W8_F (Cfg9346, Cfg9346_Lock);
1177 /* init Rx ring buffer DMA address */
1178 NETDRV_W32_F (RxBuf, tp->rx_ring_dma);
1180 /* init Tx buffer DMA addresses */
1181 for (i = 0; i < NUM_TX_DESC; i++)
1182 NETDRV_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1184 NETDRV_W32_F (RxMissed, 0);
1186 netdrv_set_rx_mode (dev);
1188 /* no early-rx interrupts */
1189 NETDRV_W16 (MultiIntr, NETDRV_R16 (MultiIntr) & MultiIntrClear);
1191 /* make sure RxTx has started */
1192 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1193 CmdRxEnb | CmdTxEnb);
1195 /* Enable all known interrupts by setting the interrupt mask. */
1196 NETDRV_W16_F (IntrMask, netdrv_intr_mask);
1198 netif_start_queue (dev);
1204 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1205 static void netdrv_init_ring (struct net_device *dev)
1207 struct netdrv_private *tp = dev->priv;
1210 DPRINTK ("ENTER\n");
1213 atomic_set (&tp->cur_tx, 0);
1214 atomic_set (&tp->dirty_tx, 0);
1216 for (i = 0; i < NUM_TX_DESC; i++) {
1217 tp->tx_info[i].skb = NULL;
1218 tp->tx_info[i].mapping = 0;
1219 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1226 static void netdrv_timer (unsigned long data)
1228 struct net_device *dev = (struct net_device *) data;
1229 struct netdrv_private *tp = dev->priv;
1230 void *ioaddr = tp->mmio_addr;
1231 int next_tick = 60 * HZ;
1234 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1236 if (!tp->duplex_lock && mii_lpa != 0xffff) {
1237 int duplex = (mii_lpa & LPA_100FULL)
1238 || (mii_lpa & 0x01C0) == 0x0040;
1239 if (tp->full_duplex != duplex) {
1240 tp->full_duplex = duplex;
1242 "%s: Setting %s-duplex based on MII #%d link"
1243 " partner ability of %4.4x.\n", dev->name,
1244 tp->full_duplex ? "full" : "half",
1245 tp->phys[0], mii_lpa);
1246 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1247 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1248 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1252 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1253 dev->name, NETDRV_R16 (NWayLPAR));
1254 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x"
1255 " RxStatus %4.4x.\n", dev->name,
1256 NETDRV_R16 (IntrMask),
1257 NETDRV_R16 (IntrStatus),
1258 NETDRV_R32 (RxEarlyStatus));
1259 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1260 dev->name, NETDRV_R8 (Config0),
1261 NETDRV_R8 (Config1));
1263 tp->timer.expires = jiffies + next_tick;
1264 add_timer (&tp->timer);
1268 static void netdrv_tx_clear (struct netdrv_private *tp)
1272 atomic_set (&tp->cur_tx, 0);
1273 atomic_set (&tp->dirty_tx, 0);
1275 /* Dump the unsent Tx packets. */
1276 for (i = 0; i < NUM_TX_DESC; i++) {
1277 struct ring_info *rp = &tp->tx_info[i];
1278 if (rp->mapping != 0) {
1279 pci_unmap_single (tp->pci_dev, rp->mapping,
1280 rp->skb->len, PCI_DMA_TODEVICE);
1284 dev_kfree_skb (rp->skb);
1286 tp->stats.tx_dropped++;
1292 static void netdrv_tx_timeout (struct net_device *dev)
1294 struct netdrv_private *tp = dev->priv;
1295 void *ioaddr = tp->mmio_addr;
1298 unsigned long flags;
1300 DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
1301 "media %2.2x.\n", dev->name,
1302 NETDRV_R8 (ChipCmd),
1303 NETDRV_R16 (IntrStatus),
1304 NETDRV_R8 (MediaStatus));
1306 /* disable Tx ASAP, if not already */
1307 tmp8 = NETDRV_R8 (ChipCmd);
1308 if (tmp8 & CmdTxEnb)
1309 NETDRV_W8 (ChipCmd, tmp8 & ~CmdTxEnb);
1311 /* Disable interrupts by clearing the interrupt mask. */
1312 NETDRV_W16 (IntrMask, 0x0000);
1314 /* Emit info to figure out what went wrong. */
1315 printk (KERN_DEBUG "%s: Tx queue start entry %d dirty entry %d.\n",
1316 dev->name, atomic_read (&tp->cur_tx),
1317 atomic_read (&tp->dirty_tx));
1318 for (i = 0; i < NUM_TX_DESC; i++)
1319 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1320 dev->name, i, NETDRV_R32 (TxStatus0 + (i * 4)),
1321 i == atomic_read (&tp->dirty_tx) % NUM_TX_DESC ?
1322 " (queue head)" : "");
1324 /* Stop a shared interrupt from scavenging while we are. */
1325 spin_lock_irqsave (&tp->lock, flags);
1327 netdrv_tx_clear (tp);
1329 spin_unlock_irqrestore (&tp->lock, flags);
1331 /* ...and finally, reset everything */
1332 netdrv_hw_start (dev);
1334 netif_wake_queue (dev);
1339 static int netdrv_start_xmit (struct sk_buff *skb, struct net_device *dev)
1341 struct netdrv_private *tp = dev->priv;
1342 void *ioaddr = tp->mmio_addr;
1345 /* Calculate the next Tx descriptor entry. */
1346 entry = atomic_read (&tp->cur_tx) % NUM_TX_DESC;
1348 assert (tp->tx_info[entry].skb == NULL);
1349 assert (tp->tx_info[entry].mapping == 0);
1351 tp->tx_info[entry].skb = skb;
1352 /* tp->tx_info[entry].mapping = 0; */
1353 memcpy (tp->tx_buf[entry], skb->data, skb->len);
1355 /* Note: the chip doesn't have auto-pad! */
1356 NETDRV_W32 (TxStatus0 + (entry * sizeof(u32)),
1357 tp->tx_flag | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1359 dev->trans_start = jiffies;
1360 atomic_inc (&tp->cur_tx);
1361 if ((atomic_read (&tp->cur_tx) - atomic_read (&tp->dirty_tx)) >= NUM_TX_DESC)
1362 netif_stop_queue (dev);
1364 DPRINTK ("%s: Queued Tx packet at %p size %u to slot %d.\n",
1365 dev->name, skb->data, skb->len, entry);
1371 static void netdrv_tx_interrupt (struct net_device *dev,
1372 struct netdrv_private *tp,
1375 int cur_tx, dirty_tx, tx_left;
1377 assert (dev != NULL);
1378 assert (tp != NULL);
1379 assert (ioaddr != NULL);
1381 dirty_tx = atomic_read (&tp->dirty_tx);
1383 cur_tx = atomic_read (&tp->cur_tx);
1384 tx_left = cur_tx - dirty_tx;
1385 while (tx_left > 0) {
1386 int entry = dirty_tx % NUM_TX_DESC;
1389 txstatus = NETDRV_R32 (TxStatus0 + (entry * sizeof (u32)));
1391 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1392 break; /* It still hasn't been Txed */
1394 /* Note: TxCarrierLost is always asserted at 100mbps. */
1395 if (txstatus & (TxOutOfWindow | TxAborted)) {
1396 /* There was an major error, log it. */
1397 DPRINTK ("%s: Transmit error, Tx status %8.8x.\n",
1398 dev->name, txstatus);
1399 tp->stats.tx_errors++;
1400 if (txstatus & TxAborted) {
1401 tp->stats.tx_aborted_errors++;
1402 NETDRV_W32 (TxConfig, TxClearAbt | (TX_DMA_BURST << TxDMAShift));
1404 if (txstatus & TxCarrierLost)
1405 tp->stats.tx_carrier_errors++;
1406 if (txstatus & TxOutOfWindow)
1407 tp->stats.tx_window_errors++;
1409 if (txstatus & TxUnderrun) {
1410 /* Add 64 to the Tx FIFO threshold. */
1411 if (tp->tx_flag < 0x00300000)
1412 tp->tx_flag += 0x00020000;
1413 tp->stats.tx_fifo_errors++;
1415 tp->stats.collisions += (txstatus >> 24) & 15;
1416 tp->stats.tx_bytes += txstatus & 0x7ff;
1417 tp->stats.tx_packets++;
1420 /* Free the original skb. */
1421 if (tp->tx_info[entry].mapping != 0) {
1422 pci_unmap_single(tp->pci_dev,
1423 tp->tx_info[entry].mapping,
1424 tp->tx_info[entry].skb->len,
1426 tp->tx_info[entry].mapping = 0;
1428 dev_kfree_skb_irq (tp->tx_info[entry].skb);
1429 tp->tx_info[entry].skb = NULL;
1431 if (dirty_tx < 0) { /* handle signed int overflow */
1432 atomic_sub (cur_tx, &tp->cur_tx); /* XXX racy? */
1433 dirty_tx = cur_tx - tx_left + 1;
1435 if (netif_queue_stopped (dev))
1436 netif_wake_queue (dev);
1438 cur_tx = atomic_read (&tp->cur_tx);
1439 tx_left = cur_tx - dirty_tx;
1443 #ifndef NETDRV_NDEBUG
1444 if (atomic_read (&tp->cur_tx) - dirty_tx > NUM_TX_DESC) {
1446 "%s: Out-of-sync dirty pointer, %d vs. %d.\n",
1447 dev->name, dirty_tx, atomic_read (&tp->cur_tx));
1448 dirty_tx += NUM_TX_DESC;
1450 #endif /* NETDRV_NDEBUG */
1452 atomic_set (&tp->dirty_tx, dirty_tx);
1456 /* TODO: clean this up! Rx reset need not be this intensive */
1457 static void netdrv_rx_err (u32 rx_status, struct net_device *dev,
1458 struct netdrv_private *tp, void *ioaddr)
1461 int tmp_work = 1000;
1463 DPRINTK ("%s: Ethernet frame had errors, status %8.8x.\n",
1464 dev->name, rx_status);
1465 if (rx_status & RxTooLong) {
1466 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1467 dev->name, rx_status);
1468 /* A.C.: The chip hangs here. */
1470 tp->stats.rx_errors++;
1471 if (rx_status & (RxBadSymbol | RxBadAlign))
1472 tp->stats.rx_frame_errors++;
1473 if (rx_status & (RxRunt | RxTooLong))
1474 tp->stats.rx_length_errors++;
1475 if (rx_status & RxCRCErr)
1476 tp->stats.rx_crc_errors++;
1477 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1480 /* disable receive */
1481 tmp8 = NETDRV_R8 (ChipCmd) & ChipCmdClear;
1482 NETDRV_W8_F (ChipCmd, tmp8 | CmdTxEnb);
1484 /* A.C.: Reset the multicast list. */
1485 netdrv_set_rx_mode (dev);
1487 /* XXX potentially temporary hack to
1488 * restart hung receiver */
1489 while (--tmp_work > 0) {
1490 tmp8 = NETDRV_R8 (ChipCmd);
1491 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1493 NETDRV_W8_F (ChipCmd,
1494 (tmp8 & ChipCmdClear) | CmdRxEnb | CmdTxEnb);
1497 /* G.S.: Re-enable receiver */
1498 /* XXX temporary hack to work around receiver hang */
1499 netdrv_set_rx_mode (dev);
1502 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1506 /* The data sheet doesn't describe the Rx ring at all, so I'm guessing at the
1507 field alignments and semantics. */
1508 static void netdrv_rx_interrupt (struct net_device *dev,
1509 struct netdrv_private *tp, void *ioaddr)
1511 unsigned char *rx_ring;
1514 assert (dev != NULL);
1515 assert (tp != NULL);
1516 assert (ioaddr != NULL);
1518 rx_ring = tp->rx_ring;
1519 cur_rx = tp->cur_rx;
1521 DPRINTK ("%s: In netdrv_rx(), current %4.4x BufAddr %4.4x,"
1522 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1523 NETDRV_R16 (RxBufAddr),
1524 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1526 while ((NETDRV_R8 (ChipCmd) & RxBufEmpty) == 0) {
1527 int ring_offset = cur_rx % RX_BUF_LEN;
1529 unsigned int rx_size;
1530 unsigned int pkt_size;
1531 struct sk_buff *skb;
1533 /* read size+status of next frame from DMA ring buffer */
1534 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1535 rx_size = rx_status >> 16;
1536 pkt_size = rx_size - 4;
1538 DPRINTK ("%s: netdrv_rx() status %4.4x, size %4.4x,"
1539 " cur %4.4x.\n", dev->name, rx_status,
1541 #if NETDRV_DEBUG > 2
1544 DPRINTK ("%s: Frame contents ", dev->name);
1545 for (i = 0; i < 70; i++)
1547 rx_ring[ring_offset + i]);
1552 /* If Rx err or invalid rx_size/rx_status received
1553 * (which happens if we get lost in the ring),
1554 * Rx process gets reset, so we abort any further
1557 if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1558 (!(rx_status & RxStatusOK))) {
1559 netdrv_rx_err (rx_status, dev, tp, ioaddr);
1563 /* Malloc up new buffer, compatible with net-2e. */
1564 /* Omit the four octet CRC from the length. */
1566 /* TODO: consider allocating skb's outside of
1567 * interrupt context, both to speed interrupt processing,
1568 * and also to reduce the chances of having to
1569 * drop packets here under memory pressure.
1572 skb = dev_alloc_skb (pkt_size + 2);
1575 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
1577 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
1578 skb_put (skb, pkt_size);
1580 skb->protocol = eth_type_trans (skb, dev);
1582 dev->last_rx = jiffies;
1583 tp->stats.rx_bytes += pkt_size;
1584 tp->stats.rx_packets++;
1586 printk (KERN_WARNING
1587 "%s: Memory squeeze, dropping packet.\n",
1589 tp->stats.rx_dropped++;
1592 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
1593 NETDRV_W16_F (RxBufPtr, cur_rx - 16);
1596 DPRINTK ("%s: Done netdrv_rx(), current %4.4x BufAddr %4.4x,"
1597 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1598 NETDRV_R16 (RxBufAddr),
1599 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1601 tp->cur_rx = cur_rx;
1605 static void netdrv_weird_interrupt (struct net_device *dev,
1606 struct netdrv_private *tp,
1608 int status, int link_changed)
1610 printk (KERN_DEBUG "%s: Abnormal interrupt, status %8.8x.\n",
1613 assert (dev != NULL);
1614 assert (tp != NULL);
1615 assert (ioaddr != NULL);
1617 /* Update the error count. */
1618 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1619 NETDRV_W32 (RxMissed, 0);
1621 if ((status & RxUnderrun) && link_changed &&
1622 (tp->drv_flags & HAS_LNK_CHNG)) {
1623 /* Really link-change on new chips. */
1624 int lpar = NETDRV_R16 (NWayLPAR);
1625 int duplex = (lpar & 0x0100) || (lpar & 0x01C0) == 0x0040
1627 if (tp->full_duplex != duplex) {
1628 tp->full_duplex = duplex;
1629 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1630 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1631 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1633 status &= ~RxUnderrun;
1636 /* XXX along with netdrv_rx_err, are we double-counting errors? */
1638 (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
1639 tp->stats.rx_errors++;
1641 if (status & (PCSTimeout))
1642 tp->stats.rx_length_errors++;
1643 if (status & (RxUnderrun | RxFIFOOver))
1644 tp->stats.rx_fifo_errors++;
1645 if (status & RxOverflow) {
1646 tp->stats.rx_over_errors++;
1647 tp->cur_rx = NETDRV_R16 (RxBufAddr) % RX_BUF_LEN;
1648 NETDRV_W16_F (RxBufPtr, tp->cur_rx - 16);
1650 if (status & PCIErr) {
1652 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
1654 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
1655 dev->name, pci_cmd_status);
1660 /* The interrupt handler does all of the Rx thread work and cleans up
1661 after the Tx thread. */
1662 static irqreturn_t netdrv_interrupt (int irq, void *dev_instance,
1663 struct pt_regs *regs)
1665 struct net_device *dev = (struct net_device *) dev_instance;
1666 struct netdrv_private *tp = dev->priv;
1667 int boguscnt = max_interrupt_work;
1668 void *ioaddr = tp->mmio_addr;
1669 int status = 0, link_changed = 0; /* avoid bogus "uninit" warning */
1672 spin_lock (&tp->lock);
1675 status = NETDRV_R16 (IntrStatus);
1677 /* h/w no longer present (hotplug?) or major error, bail */
1678 if (status == 0xFFFF)
1682 /* Acknowledge all of the current interrupt sources ASAP */
1683 NETDRV_W16_F (IntrStatus, status);
1685 DPRINTK ("%s: interrupt status=%#4.4x new intstat=%#4.4x.\n",
1687 NETDRV_R16 (IntrStatus));
1690 (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1691 RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
1694 /* Check uncommon events with one test. */
1695 if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1696 RxFIFOOver | TxErr | RxErr))
1697 netdrv_weird_interrupt (dev, tp, ioaddr,
1698 status, link_changed);
1700 if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver)) /* Rx interrupt */
1701 netdrv_rx_interrupt (dev, tp, ioaddr);
1703 if (status & (TxOK | TxErr))
1704 netdrv_tx_interrupt (dev, tp, ioaddr);
1707 } while (boguscnt > 0);
1709 if (boguscnt <= 0) {
1710 printk (KERN_WARNING
1711 "%s: Too much work at interrupt, "
1712 "IntrStatus=0x%4.4x.\n", dev->name,
1715 /* Clear all interrupt sources. */
1716 NETDRV_W16 (IntrStatus, 0xffff);
1719 spin_unlock (&tp->lock);
1721 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
1722 dev->name, NETDRV_R16 (IntrStatus));
1723 return IRQ_RETVAL(handled);
1727 static int netdrv_close (struct net_device *dev)
1729 struct netdrv_private *tp = dev->priv;
1730 void *ioaddr = tp->mmio_addr;
1731 unsigned long flags;
1733 DPRINTK ("ENTER\n");
1735 netif_stop_queue (dev);
1737 DPRINTK ("%s: Shutting down ethercard, status was 0x%4.4x.\n",
1738 dev->name, NETDRV_R16 (IntrStatus));
1740 del_timer_sync (&tp->timer);
1742 spin_lock_irqsave (&tp->lock, flags);
1744 /* Stop the chip's Tx and Rx DMA processes. */
1745 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1747 /* Disable interrupts by clearing the interrupt mask. */
1748 NETDRV_W16 (IntrMask, 0x0000);
1750 /* Update the error counts. */
1751 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1752 NETDRV_W32 (RxMissed, 0);
1754 spin_unlock_irqrestore (&tp->lock, flags);
1757 free_irq (dev->irq, dev);
1759 netdrv_tx_clear (tp);
1761 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1762 tp->rx_ring, tp->rx_ring_dma);
1763 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1764 tp->tx_bufs, tp->tx_bufs_dma);
1768 /* Green! Put the chip in low-power mode. */
1769 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1770 NETDRV_W8 (Config1, 0x03);
1771 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1778 static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1780 struct netdrv_private *tp = dev->priv;
1781 struct mii_ioctl_data *data = (struct mii_ioctl_data *) & rq->ifr_data;
1782 unsigned long flags;
1785 DPRINTK ("ENTER\n");
1788 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1789 data->phy_id = tp->phys[0] & 0x3f;
1792 case SIOCGMIIREG: /* Read MII PHY register. */
1793 spin_lock_irqsave (&tp->lock, flags);
1794 data->val_out = mdio_read (dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1795 spin_unlock_irqrestore (&tp->lock, flags);
1798 case SIOCSMIIREG: /* Write MII PHY register. */
1799 if (!capable (CAP_NET_ADMIN)) {
1804 spin_lock_irqsave (&tp->lock, flags);
1805 mdio_write (dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1806 spin_unlock_irqrestore (&tp->lock, flags);
1814 DPRINTK ("EXIT, returning %d\n", rc);
1819 static struct net_device_stats *netdrv_get_stats (struct net_device *dev)
1821 struct netdrv_private *tp = dev->priv;
1822 void *ioaddr = tp->mmio_addr;
1824 DPRINTK ("ENTER\n");
1826 assert (tp != NULL);
1828 if (netif_running(dev)) {
1829 unsigned long flags;
1831 spin_lock_irqsave (&tp->lock, flags);
1833 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1834 NETDRV_W32 (RxMissed, 0);
1836 spin_unlock_irqrestore (&tp->lock, flags);
1843 /* Set or clear the multicast filter for this adaptor.
1844 This routine is not state sensitive and need not be SMP locked. */
1846 static void netdrv_set_rx_mode (struct net_device *dev)
1848 struct netdrv_private *tp = dev->priv;
1849 void *ioaddr = tp->mmio_addr;
1850 u32 mc_filter[2]; /* Multicast hash filter */
1854 DPRINTK ("ENTER\n");
1856 DPRINTK ("%s: netdrv_set_rx_mode(%4.4x) done -- Rx config %8.8x.\n",
1857 dev->name, dev->flags, NETDRV_R32 (RxConfig));
1859 /* Note: do not reorder, GCC is clever about common statements. */
1860 if (dev->flags & IFF_PROMISC) {
1861 /* Unconditionally log net taps. */
1862 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
1865 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1867 mc_filter[1] = mc_filter[0] = 0xffffffff;
1868 } else if ((dev->mc_count > multicast_filter_limit)
1869 || (dev->flags & IFF_ALLMULTI)) {
1870 /* Too many to filter perfectly -- accept all multicasts. */
1871 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1872 mc_filter[1] = mc_filter[0] = 0xffffffff;
1874 struct dev_mc_list *mclist;
1875 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1876 mc_filter[1] = mc_filter[0] = 0;
1877 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1878 i++, mclist = mclist->next)
1879 set_bit (ether_crc (ETH_ALEN, mclist->dmi_addr) >> 26,
1883 /* if called from irq handler, lock already acquired */
1885 spin_lock_irq (&tp->lock);
1887 /* We can safely update without stopping the chip. */
1888 tmp = netdrv_rx_config | rx_mode |
1889 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1890 NETDRV_W32_F (RxConfig, tmp);
1891 NETDRV_W32_F (MAR0 + 0, mc_filter[0]);
1892 NETDRV_W32_F (MAR0 + 4, mc_filter[1]);
1895 spin_unlock_irq (&tp->lock);
1903 static int netdrv_suspend (struct pci_dev *pdev, u32 state)
1905 struct net_device *dev = pci_get_drvdata (pdev);
1906 struct netdrv_private *tp = dev->priv;
1907 void *ioaddr = tp->mmio_addr;
1908 unsigned long flags;
1910 if (!netif_running(dev))
1912 netif_device_detach (dev);
1914 spin_lock_irqsave (&tp->lock, flags);
1916 /* Disable interrupts, stop Tx and Rx. */
1917 NETDRV_W16 (IntrMask, 0x0000);
1918 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1920 /* Update the error counts. */
1921 tp->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1922 NETDRV_W32 (RxMissed, 0);
1924 spin_unlock_irqrestore (&tp->lock, flags);
1926 pci_power_off (pdev, -1);
1932 static int netdrv_resume (struct pci_dev *pdev)
1934 struct net_device *dev = pci_get_drvdata (pdev);
1936 if (!netif_running(dev))
1938 pci_power_on (pdev);
1939 netif_device_attach (dev);
1940 netdrv_hw_start (dev);
1945 #endif /* CONFIG_PM */
1948 static struct pci_driver netdrv_pci_driver = {
1950 .id_table = netdrv_pci_tbl,
1951 .probe = netdrv_init_one,
1952 .remove = __devexit_p(netdrv_remove_one),
1954 .suspend = netdrv_suspend,
1955 .resume = netdrv_resume,
1956 #endif /* CONFIG_PM */
1960 static int __init netdrv_init_module (void)
1962 /* when a module, this is printed whether or not devices are found in probe */
1966 return pci_module_init (&netdrv_pci_driver);
1970 static void __exit netdrv_cleanup_module (void)
1972 pci_unregister_driver (&netdrv_pci_driver);
1976 module_init(netdrv_init_module);
1977 module_exit(netdrv_cleanup_module);