1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
3 * Copyright 1996-1999 Thomas Bogendoerfer
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
13 * This driver is for PCnet32 and PCnetPCI based ethercards
15 /**************************************************************************
17 * Fixed a few bugs, related to running the controller in 32bit mode.
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
22 *************************************************************************/
24 #define DRV_NAME "pcnet32"
25 #define DRV_VERSION "1.29"
26 #define DRV_RELDATE "04.06.2004"
27 #define PFX DRV_NAME ": "
29 static const char *version =
30 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/string.h>
35 #include <linux/errno.h>
36 #include <linux/ioport.h>
37 #include <linux/slab.h>
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/init.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/crc32.h>
45 #include <linux/netdevice.h>
46 #include <linux/etherdevice.h>
47 #include <linux/skbuff.h>
48 #include <linux/spinlock.h>
50 #include <asm/bitops.h>
53 #include <asm/uaccess.h>
57 * PCI device identifiers for "new style" Linux PCI Device Drivers
59 static struct pci_device_id pcnet32_pci_tbl[] = {
60 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
61 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
63 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
64 * the incorrect vendor id.
66 { PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE, PCI_ANY_ID, PCI_ANY_ID,
67 PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, 0 },
71 MODULE_DEVICE_TABLE (pci, pcnet32_pci_tbl);
73 static int cards_found;
78 static unsigned int pcnet32_portlist[] __initdata =
79 { 0x300, 0x320, 0x340, 0x360, 0 };
83 static int pcnet32_debug = 0;
84 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
85 static int pcnet32vlb; /* check for VLB cards ? */
87 static struct net_device *pcnet32_dev;
89 static int max_interrupt_work = 80;
90 static int rx_copybreak = 200;
92 #define PCNET32_PORT_AUI 0x00
93 #define PCNET32_PORT_10BT 0x01
94 #define PCNET32_PORT_GPSI 0x02
95 #define PCNET32_PORT_MII 0x03
97 #define PCNET32_PORT_PORTSEL 0x03
98 #define PCNET32_PORT_ASEL 0x04
99 #define PCNET32_PORT_100 0x40
100 #define PCNET32_PORT_FD 0x80
102 #define PCNET32_DMA_MASK 0xffffffff
104 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
105 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
108 * table to translate option values from tulip
109 * to internal options
111 static unsigned char options_mapping[] = {
112 PCNET32_PORT_ASEL, /* 0 Auto-select */
113 PCNET32_PORT_AUI, /* 1 BNC/AUI */
114 PCNET32_PORT_AUI, /* 2 AUI/BNC */
115 PCNET32_PORT_ASEL, /* 3 not supported */
116 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
117 PCNET32_PORT_ASEL, /* 5 not supported */
118 PCNET32_PORT_ASEL, /* 6 not supported */
119 PCNET32_PORT_ASEL, /* 7 not supported */
120 PCNET32_PORT_ASEL, /* 8 not supported */
121 PCNET32_PORT_MII, /* 9 MII 10baseT */
122 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
123 PCNET32_PORT_MII, /* 11 MII (autosel) */
124 PCNET32_PORT_10BT, /* 12 10BaseT */
125 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
126 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, /* 14 MII 100BaseTx-FD */
127 PCNET32_PORT_ASEL /* 15 not supported */
130 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
131 "Loopback test (offline)"
133 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
135 #define MAX_UNITS 8 /* More are supported, limit only on options */
136 static int options[MAX_UNITS];
137 static int full_duplex[MAX_UNITS];
140 * Theory of Operation
142 * This driver uses the same software structure as the normal lance
143 * driver. So look for a verbose description in lance.c. The differences
144 * to the normal lance driver is the use of the 32bit mode of PCnet32
145 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
146 * 16MB limitation and we don't need bounce buffers.
151 * v0.01: Initial version
152 * only tested on Alpha Noname Board
153 * v0.02: changed IRQ handling for new interrupt scheme (dev_id)
154 * tested on a ASUS SP3G
155 * v0.10: fixed an odd problem with the 79C974 in a Compaq Deskpro XL
156 * looks like the 974 doesn't like stopping and restarting in a
157 * short period of time; now we do a reinit of the lance; the
158 * bug was triggered by doing ifconfig eth0 <ip> broadcast <addr>
159 * and hangs the machine (thanks to Klaus Liedl for debugging)
160 * v0.12: by suggestion from Donald Becker: Renamed driver to pcnet32,
161 * made it standalone (no need for lance.c)
162 * v0.13: added additional PCI detecting for special PCI devices (Compaq)
163 * v0.14: stripped down additional PCI probe (thanks to David C Niemi
164 * and sveneric@xs4all.nl for testing this on their Compaq boxes)
165 * v0.15: added 79C965 (VLB) probe
166 * added interrupt sharing for PCI chips
167 * v0.16: fixed set_multicast_list on Alpha machines
168 * v0.17: removed hack from dev.c; now pcnet32 uses ethif_probe in Space.c
169 * v0.19: changed setting of autoselect bit
170 * v0.20: removed additional Compaq PCI probe; there is now a working one
171 * in arch/i386/bios32.c
172 * v0.21: added endian conversion for ppc, from work by cort@cs.nmt.edu
173 * v0.22: added printing of status to ring dump
174 * v0.23: changed enet_statistics to net_devive_stats
175 * v0.90: added multicast filter
176 * added module support
177 * changed irq probe to new style
178 * added PCnetFast chip id
179 * added fix for receive stalls with Intel saturn chipsets
180 * added in-place rx skbs like in the tulip driver
182 * v0.91: added PCnetFast+ chip id
184 * v1.00: added some stuff from Donald Becker's 2.0.34 version
185 * added support for byte counters in net_dev_stats
186 * v1.01: do ring dumps, only when debugging the driver
187 * increased the transmit timeout
188 * v1.02: fixed memory leak in pcnet32_init_ring()
189 * v1.10: workaround for stopped transmitter
190 * added port selection for modules
191 * detect special T1/E1 WAN card and setup port selection
192 * v1.11: fixed wrong checking of Tx errors
193 * v1.20: added check of return value kmalloc (cpeterso@cs.washington.edu)
194 * added save original kmalloc addr for freeing (mcr@solidum.com)
195 * added support for PCnetHome chip (joe@MIT.EDU)
196 * rewritten PCI card detection
197 * added dwio mode to get driver working on some PPC machines
198 * v1.21: added mii selection and mii ioctl
199 * v1.22: changed pci scanning code to make PPC people happy
200 * fixed switching to 32bit mode in pcnet32_open() (thanks
201 * to Michael Richard <mcr@solidum.com> for noticing this one)
202 * added sub vendor/device id matching (thanks again to
203 * Michael Richard <mcr@solidum.com>)
204 * added chip id for 79c973/975 (thanks to Zach Brown <zab@zabbo.net>)
205 * v1.23 fixed small bug, when manual selecting MII speed/duplex
206 * v1.24 Applied Thomas' patch to use TxStartPoint and thus decrease TxFIFO
207 * underflows. Added tx_start_pt module parameter. Increased
208 * TX_RING_SIZE from 16 to 32. Added #ifdef'd code to use DXSUFLO
209 * for FAST[+] chipsets. <kaf@fc.hp.com>
210 * v1.24ac Added SMP spinlocking - Alan Cox <alan@redhat.com>
211 * v1.25kf Added No Interrupt on successful Tx for some Tx's <kaf@fc.hp.com>
212 * v1.26 Converted to pci_alloc_consistent, Jamey Hicks / George France
213 * <jamey@crl.dec.com>
214 * - Fixed a few bugs, related to running the controller in 32bit mode.
215 * 23 Oct, 2000. Carsten Langgaard, carstenl@mips.com
216 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
217 * v1.26p Fix oops on rmmod+insmod; plug i/o resource leak - Paul Gortmaker
218 * v1.27 improved CSR/PROM address detection, lots of cleanups,
219 * new pcnet32vlb module option, HP-PARISC support,
220 * added module parameter descriptions,
221 * initial ethtool support - Helge Deller <deller@gmx.de>
222 * v1.27a Sun Feb 10 2002 Go Taniguchi <go@turbolinux.co.jp>
223 * use alloc_etherdev and register_netdev
224 * fix pci probe not increment cards_found
225 * FD auto negotiate error workaround for xSeries250
226 * clean up and using new mii module
227 * v1.27b Sep 30 2002 Kent Yoder <yoder1@us.ibm.com>
228 * Added timer for cable connection state changes.
229 * v1.28 20 Feb 2004 Don Fry <brazilnut@us.ibm.com>
230 * Jon Mason <jonmason@us.ibm.com>, Chinmay Albal <albal@in.ibm.com>
231 * Now uses ethtool_ops, netif_msg_* and generic_mii_ioctl.
232 * Fixes bogus 'Bus master arbitration failure', pci_[un]map_single
233 * length errors, and transmit hangs. Cleans up after errors in open.
234 * Jim Lewis <jklewis@us.ibm.com> added ethernet loopback test.
235 * Thomas Munck Steenholdt <tmus@tmus.dk> non-mii ioctl corrections.
236 * v1.29 6 Apr 2004 Jim Lewis <jklewis@us.ibm.com> added physical
237 * identification code (blink led's).
242 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
243 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
244 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
246 #ifndef PCNET32_LOG_TX_BUFFERS
247 #define PCNET32_LOG_TX_BUFFERS 4
248 #define PCNET32_LOG_RX_BUFFERS 5
251 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
252 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
253 #define TX_RING_LEN_BITS ((PCNET32_LOG_TX_BUFFERS) << 12)
255 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
256 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
257 #define RX_RING_LEN_BITS ((PCNET32_LOG_RX_BUFFERS) << 4)
259 #define PKT_BUF_SZ 1544
261 /* Offsets from base I/O address. */
262 #define PCNET32_WIO_RDP 0x10
263 #define PCNET32_WIO_RAP 0x12
264 #define PCNET32_WIO_RESET 0x14
265 #define PCNET32_WIO_BDP 0x16
267 #define PCNET32_DWIO_RDP 0x10
268 #define PCNET32_DWIO_RAP 0x14
269 #define PCNET32_DWIO_RESET 0x18
270 #define PCNET32_DWIO_BDP 0x1C
272 #define PCNET32_TOTAL_SIZE 0x20
274 /* The PCNET32 Rx and Tx ring descriptors. */
275 struct pcnet32_rx_head {
283 struct pcnet32_tx_head {
291 /* The PCNET32 32-Bit initialization block, described in databook. */
292 struct pcnet32_init_block {
298 /* Receive and transmit ring base, along with extra bits. */
303 /* PCnet32 access functions */
304 struct pcnet32_access {
305 u16 (*read_csr)(unsigned long, int);
306 void (*write_csr)(unsigned long, int, u16);
307 u16 (*read_bcr)(unsigned long, int);
308 void (*write_bcr)(unsigned long, int, u16);
309 u16 (*read_rap)(unsigned long);
310 void (*write_rap)(unsigned long, u16);
311 void (*reset)(unsigned long);
315 * The first three fields of pcnet32_private are read by the ethernet device
316 * so we allocate the structure should be allocated by pci_alloc_consistent().
318 struct pcnet32_private {
319 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
320 struct pcnet32_rx_head rx_ring[RX_RING_SIZE];
321 struct pcnet32_tx_head tx_ring[TX_RING_SIZE];
322 struct pcnet32_init_block init_block;
323 dma_addr_t dma_addr; /* DMA address of beginning of this
325 pci_alloc_consistent */
326 struct pci_dev *pci_dev; /* Pointer to the associated pci device
329 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
330 struct sk_buff *tx_skbuff[TX_RING_SIZE];
331 struct sk_buff *rx_skbuff[RX_RING_SIZE];
332 dma_addr_t tx_dma_addr[TX_RING_SIZE];
333 dma_addr_t rx_dma_addr[RX_RING_SIZE];
334 struct pcnet32_access a;
335 spinlock_t lock; /* Guard lock */
336 unsigned int cur_rx, cur_tx; /* The next free ring entry */
337 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
338 struct net_device_stats stats;
341 int shared_irq:1, /* shared irq possible */
342 ltint:1, /* enable TxDone-intr inhibitor */
343 dxsuflo:1, /* disable transmit stop on uflo */
344 mii:1; /* mii port available */
345 struct net_device *next;
346 struct mii_if_info mii_if;
347 struct timer_list watchdog_timer;
348 struct timer_list blink_timer;
349 u32 msg_enable; /* debug message level */
352 static void pcnet32_probe_vlbus(void);
353 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
354 static int pcnet32_probe1(unsigned long, unsigned int, int, struct pci_dev *);
355 static int pcnet32_open(struct net_device *);
356 static int pcnet32_init_ring(struct net_device *);
357 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
358 static int pcnet32_rx(struct net_device *);
359 static void pcnet32_tx_timeout (struct net_device *dev);
360 static irqreturn_t pcnet32_interrupt(int, void *, struct pt_regs *);
361 static int pcnet32_close(struct net_device *);
362 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
363 static void pcnet32_load_multicast(struct net_device *dev);
364 static void pcnet32_set_multicast_list(struct net_device *);
365 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
366 static void pcnet32_watchdog(struct net_device *);
367 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
368 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val);
369 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
370 static void pcnet32_ethtool_test(struct net_device *dev,
371 struct ethtool_test *eth_test, u64 *data);
372 static int pcnet32_loopback_test(struct net_device *dev, uint64_t *data1);
373 static int pcnet32_phys_id(struct net_device *dev, u32 data);
374 static void pcnet32_led_blink_callback(struct net_device *dev);
377 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
378 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
382 static u16 pcnet32_wio_read_csr (unsigned long addr, int index)
384 outw (index, addr+PCNET32_WIO_RAP);
385 return inw (addr+PCNET32_WIO_RDP);
388 static void pcnet32_wio_write_csr (unsigned long addr, int index, u16 val)
390 outw (index, addr+PCNET32_WIO_RAP);
391 outw (val, addr+PCNET32_WIO_RDP);
394 static u16 pcnet32_wio_read_bcr (unsigned long addr, int index)
396 outw (index, addr+PCNET32_WIO_RAP);
397 return inw (addr+PCNET32_WIO_BDP);
400 static void pcnet32_wio_write_bcr (unsigned long addr, int index, u16 val)
402 outw (index, addr+PCNET32_WIO_RAP);
403 outw (val, addr+PCNET32_WIO_BDP);
406 static u16 pcnet32_wio_read_rap (unsigned long addr)
408 return inw (addr+PCNET32_WIO_RAP);
411 static void pcnet32_wio_write_rap (unsigned long addr, u16 val)
413 outw (val, addr+PCNET32_WIO_RAP);
416 static void pcnet32_wio_reset (unsigned long addr)
418 inw (addr+PCNET32_WIO_RESET);
421 static int pcnet32_wio_check (unsigned long addr)
423 outw (88, addr+PCNET32_WIO_RAP);
424 return (inw (addr+PCNET32_WIO_RAP) == 88);
427 static struct pcnet32_access pcnet32_wio = {
428 .read_csr = pcnet32_wio_read_csr,
429 .write_csr = pcnet32_wio_write_csr,
430 .read_bcr = pcnet32_wio_read_bcr,
431 .write_bcr = pcnet32_wio_write_bcr,
432 .read_rap = pcnet32_wio_read_rap,
433 .write_rap = pcnet32_wio_write_rap,
434 .reset = pcnet32_wio_reset
437 static u16 pcnet32_dwio_read_csr (unsigned long addr, int index)
439 outl (index, addr+PCNET32_DWIO_RAP);
440 return (inl (addr+PCNET32_DWIO_RDP) & 0xffff);
443 static void pcnet32_dwio_write_csr (unsigned long addr, int index, u16 val)
445 outl (index, addr+PCNET32_DWIO_RAP);
446 outl (val, addr+PCNET32_DWIO_RDP);
449 static u16 pcnet32_dwio_read_bcr (unsigned long addr, int index)
451 outl (index, addr+PCNET32_DWIO_RAP);
452 return (inl (addr+PCNET32_DWIO_BDP) & 0xffff);
455 static void pcnet32_dwio_write_bcr (unsigned long addr, int index, u16 val)
457 outl (index, addr+PCNET32_DWIO_RAP);
458 outl (val, addr+PCNET32_DWIO_BDP);
461 static u16 pcnet32_dwio_read_rap (unsigned long addr)
463 return (inl (addr+PCNET32_DWIO_RAP) & 0xffff);
466 static void pcnet32_dwio_write_rap (unsigned long addr, u16 val)
468 outl (val, addr+PCNET32_DWIO_RAP);
471 static void pcnet32_dwio_reset (unsigned long addr)
473 inl (addr+PCNET32_DWIO_RESET);
476 static int pcnet32_dwio_check (unsigned long addr)
478 outl (88, addr+PCNET32_DWIO_RAP);
479 return ((inl (addr+PCNET32_DWIO_RAP) & 0xffff) == 88);
482 static struct pcnet32_access pcnet32_dwio = {
483 .read_csr = pcnet32_dwio_read_csr,
484 .write_csr = pcnet32_dwio_write_csr,
485 .read_bcr = pcnet32_dwio_read_bcr,
486 .write_bcr = pcnet32_dwio_write_bcr,
487 .read_rap = pcnet32_dwio_read_rap,
488 .write_rap = pcnet32_dwio_write_rap,
489 .reset = pcnet32_dwio_reset
492 #ifdef CONFIG_NET_POLL_CONTROLLER
493 static void pcnet32_poll_controller(struct net_device *dev)
495 disable_irq(dev->irq);
496 pcnet32_interrupt(0, dev, NULL);
497 enable_irq(dev->irq);
502 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
504 struct pcnet32_private *lp = dev->priv;
509 spin_lock_irqsave(&lp->lock, flags);
510 mii_ethtool_gset(&lp->mii_if, cmd);
511 spin_unlock_irqrestore(&lp->lock, flags);
517 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
519 struct pcnet32_private *lp = dev->priv;
524 spin_lock_irqsave(&lp->lock, flags);
525 r = mii_ethtool_sset(&lp->mii_if, cmd);
526 spin_unlock_irqrestore(&lp->lock, flags);
531 static void pcnet32_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
533 struct pcnet32_private *lp = dev->priv;
535 strcpy (info->driver, DRV_NAME);
536 strcpy (info->version, DRV_VERSION);
538 strcpy (info->bus_info, pci_name(lp->pci_dev));
540 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
543 static u32 pcnet32_get_link(struct net_device *dev)
545 struct pcnet32_private *lp = dev->priv;
549 spin_lock_irqsave(&lp->lock, flags);
551 r = mii_link_ok(&lp->mii_if);
553 ulong ioaddr = dev->base_addr; /* card base I/O address */
554 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
556 spin_unlock_irqrestore(&lp->lock, flags);
561 static u32 pcnet32_get_msglevel(struct net_device *dev)
563 struct pcnet32_private *lp = dev->priv;
564 return lp->msg_enable;
567 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
569 struct pcnet32_private *lp = dev->priv;
570 lp->msg_enable = value;
573 static int pcnet32_nway_reset(struct net_device *dev)
575 struct pcnet32_private *lp = dev->priv;
580 spin_lock_irqsave(&lp->lock, flags);
581 r = mii_nway_restart(&lp->mii_if);
582 spin_unlock_irqrestore(&lp->lock, flags);
587 static void pcnet32_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
589 struct pcnet32_private *lp = dev->priv;
591 ering->tx_max_pending = TX_RING_SIZE - 1;
592 ering->tx_pending = lp->cur_tx - lp->dirty_tx;
593 ering->rx_max_pending = RX_RING_SIZE - 1;
594 ering->rx_pending = lp->cur_rx & RX_RING_MOD_MASK;
597 static void pcnet32_get_strings(struct net_device *dev, u32 stringset, u8 *data)
599 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
602 static int pcnet32_self_test_count(struct net_device *dev)
604 return PCNET32_TEST_LEN;
607 static void pcnet32_ethtool_test(struct net_device *dev,
608 struct ethtool_test *test, u64 *data)
610 struct pcnet32_private *lp = dev->priv;
613 if (test->flags == ETH_TEST_FL_OFFLINE) {
614 rc = pcnet32_loopback_test(dev, data);
616 if (netif_msg_hw(lp))
617 printk(KERN_DEBUG "%s: Loopback test failed.\n", dev->name);
618 test->flags |= ETH_TEST_FL_FAILED;
619 } else if (netif_msg_hw(lp))
620 printk(KERN_DEBUG "%s: Loopback test passed.\n", dev->name);
621 } else if (netif_msg_hw(lp))
622 printk(KERN_DEBUG "%s: No tests to run (specify 'Offline' on ethtool).", dev->name);
623 } /* end pcnet32_ethtool_test */
625 static int pcnet32_loopback_test(struct net_device *dev, uint64_t *data1)
627 struct pcnet32_private *lp = dev->priv;
628 struct pcnet32_access *a = &lp->a; /* access to registers */
629 ulong ioaddr = dev->base_addr; /* card base I/O address */
630 struct sk_buff *skb; /* sk buff */
631 int x, i; /* counters */
632 int numbuffs = 4; /* number of TX/RX buffers and descs */
633 u16 status = 0x8300; /* TX ring status */
634 u16 teststatus; /* test of ring status */
635 int rc; /* return code */
636 int size; /* size of packets */
637 unsigned char *packet; /* source packet data */
638 static int data_len = 60; /* length of source packets */
642 *data1 = 1; /* status of test, default to fail */
643 rc = 1; /* default to fail */
645 if (netif_running(dev))
648 spin_lock_irqsave(&lp->lock, flags);
650 /* Reset the PCNET32 */
651 lp->a.reset (ioaddr);
653 /* switch pcnet32 to 32bit mode */
654 lp->a.write_bcr (ioaddr, 20, 2);
656 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
657 lp->init_block.filter[0] = 0;
658 lp->init_block.filter[1] = 0;
660 /* purge & init rings but don't actually restart */
661 pcnet32_restart(dev, 0x0000);
663 lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */
665 /* Initialize Transmit buffers. */
666 size = data_len + 15;
667 for (x=0; x<numbuffs; x++) {
668 if (!(skb = dev_alloc_skb(size))) {
669 if (netif_msg_hw(lp))
670 printk(KERN_DEBUG "%s: Cannot allocate skb at line: %d!\n",
671 dev->name, __LINE__);
675 skb_put(skb, size); /* create space for data */
676 lp->tx_skbuff[x] = skb;
677 lp->tx_ring[x].length = le16_to_cpu(-skb->len);
678 lp->tx_ring[x].misc = 0;
680 /* put DA and SA into the skb */
682 *packet++ = dev->dev_addr[i];
684 *packet++ = dev->dev_addr[i];
690 /* fill packet with data */
691 for (i=0; i<data_len; i++)
694 lp->tx_dma_addr[x] = pci_map_single(lp->pci_dev, skb->data,
695 skb->len, PCI_DMA_TODEVICE);
696 lp->tx_ring[x].base = (u32)le32_to_cpu(lp->tx_dma_addr[x]);
697 wmb(); /* Make sure owner changes after all others are visible */
698 lp->tx_ring[x].status = le16_to_cpu(status);
702 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BSR32 */
704 a->write_bcr(ioaddr, 32, x);
706 lp->a.write_csr (ioaddr, 15, 0x0044); /* set int loopback in CSR15 */
708 teststatus = le16_to_cpu(0x8000);
709 lp->a.write_csr(ioaddr, 0, 0x0002); /* Set STRT bit */
711 /* Check status of descriptors */
712 for (x=0; x<numbuffs; x++) {
715 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
716 spin_unlock_irqrestore(&lp->lock, flags);
718 spin_lock_irqsave(&lp->lock, flags);
723 if (netif_msg_hw(lp))
724 printk("%s: Desc %d failed to reset!\n",dev->name,x);
729 lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */
731 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
732 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
734 for (x=0; x<numbuffs; x++) {
735 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
736 skb = lp->rx_skbuff[x];
737 for (i=0; i<size; i++) {
738 printk("%02x ", *(skb->data+i));
746 while (x<numbuffs && !rc) {
747 skb = lp->rx_skbuff[x];
748 packet = lp->tx_skbuff[x]->data;
749 for (i=0; i<size; i++) {
750 if (*(skb->data+i) != packet[i]) {
751 if (netif_msg_hw(lp))
752 printk(KERN_DEBUG "%s: Error in compare! %2x - %02x %02x\n",
753 dev->name, i, *(skb->data+i), packet[i]);
765 x = a->read_csr(ioaddr, 15) & 0xFFFF;
766 a->write_csr(ioaddr, 15, (x & ~0x0044)); /* reset bits 6 and 2 */
768 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
770 a->write_bcr(ioaddr, 32, x);
772 spin_unlock_irqrestore(&lp->lock, flags);
774 if (netif_running(dev)) {
777 lp->a.write_bcr (ioaddr, 20, 4); /* return to 16bit mode */
781 } /* end pcnet32_loopback_test */
783 static void pcnet32_led_blink_callback(struct net_device *dev)
785 struct pcnet32_private *lp = dev->priv;
786 struct pcnet32_access *a = &lp->a;
787 ulong ioaddr = dev->base_addr;
791 spin_lock_irqsave(&lp->lock, flags);
792 for (i=4; i<8; i++) {
793 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
795 spin_unlock_irqrestore(&lp->lock, flags);
797 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
800 static int pcnet32_phys_id(struct net_device *dev, u32 data)
802 struct pcnet32_private *lp = dev->priv;
803 struct pcnet32_access *a = &lp->a;
804 ulong ioaddr = dev->base_addr;
808 if (!lp->blink_timer.function) {
809 init_timer(&lp->blink_timer);
810 lp->blink_timer.function = (void *) pcnet32_led_blink_callback;
811 lp->blink_timer.data = (unsigned long) dev;
814 /* Save the current value of the bcrs */
815 spin_lock_irqsave(&lp->lock, flags);
816 for (i=4; i<8; i++) {
817 regs[i-4] = a->read_bcr(ioaddr, i);
819 spin_unlock_irqrestore(&lp->lock, flags);
821 mod_timer(&lp->blink_timer, jiffies);
822 set_current_state(TASK_INTERRUPTIBLE);
824 if ((!data) || (data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ)))
825 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
827 schedule_timeout(data * HZ);
828 del_timer_sync(&lp->blink_timer);
830 /* Restore the original value of the bcrs */
831 spin_lock_irqsave(&lp->lock, flags);
832 for (i=4; i<8; i++) {
833 a->write_bcr(ioaddr, i, regs[i-4]);
835 spin_unlock_irqrestore(&lp->lock, flags);
840 static struct ethtool_ops pcnet32_ethtool_ops = {
841 .get_settings = pcnet32_get_settings,
842 .set_settings = pcnet32_set_settings,
843 .get_drvinfo = pcnet32_get_drvinfo,
844 .get_msglevel = pcnet32_get_msglevel,
845 .set_msglevel = pcnet32_set_msglevel,
846 .nway_reset = pcnet32_nway_reset,
847 .get_link = pcnet32_get_link,
848 .get_ringparam = pcnet32_get_ringparam,
849 .get_tx_csum = ethtool_op_get_tx_csum,
850 .get_sg = ethtool_op_get_sg,
851 .get_tso = ethtool_op_get_tso,
852 .get_strings = pcnet32_get_strings,
853 .self_test_count = pcnet32_self_test_count,
854 .self_test = pcnet32_ethtool_test,
855 .phys_id = pcnet32_phys_id,
858 /* only probes for non-PCI devices, the rest are handled by
859 * pci_register_driver via pcnet32_probe_pci */
861 static void __devinit
862 pcnet32_probe_vlbus(void)
864 unsigned int *port, ioaddr;
866 /* search for PCnet32 VLB cards at known addresses */
867 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
868 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
869 /* check if there is really a pcnet chip on that ioaddr */
870 if ((inb(ioaddr + 14) == 0x57) && (inb(ioaddr + 15) == 0x57)) {
871 pcnet32_probe1(ioaddr, 0, 0, NULL);
873 release_region(ioaddr, PCNET32_TOTAL_SIZE);
881 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
883 unsigned long ioaddr;
886 err = pci_enable_device(pdev);
888 if (pcnet32_debug & NETIF_MSG_PROBE)
889 printk(KERN_ERR PFX "failed to enable device -- err=%d\n", err);
892 pci_set_master(pdev);
894 ioaddr = pci_resource_start (pdev, 0);
896 if (pcnet32_debug & NETIF_MSG_PROBE)
897 printk (KERN_ERR PFX "card has no PCI IO resources, aborting\n");
901 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
902 if (pcnet32_debug & NETIF_MSG_PROBE)
903 printk(KERN_ERR PFX "architecture does not support 32bit PCI busmaster DMA\n");
906 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") == NULL) {
907 if (pcnet32_debug & NETIF_MSG_PROBE)
908 printk(KERN_ERR PFX "io address range already allocated\n");
912 return pcnet32_probe1(ioaddr, pdev->irq, 1, pdev);
917 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
918 * pdev will be NULL when called from pcnet32_probe_vlbus.
921 pcnet32_probe1(unsigned long ioaddr, unsigned int irq_line, int shared,
922 struct pci_dev *pdev)
924 struct pcnet32_private *lp;
925 dma_addr_t lp_dma_addr;
927 int fdx, mii, fset, dxsuflo, ltint;
930 struct net_device *dev;
931 struct pcnet32_access *a = NULL;
936 pcnet32_wio_reset(ioaddr);
938 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
939 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
942 pcnet32_dwio_reset(ioaddr);
943 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && pcnet32_dwio_check(ioaddr)) {
946 goto err_release_region;
949 chip_version = a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr,89) << 16);
950 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
951 printk(KERN_INFO " PCnet chip version is %#x.\n", chip_version);
952 if ((chip_version & 0xfff) != 0x003) {
953 if (pcnet32_debug & NETIF_MSG_PROBE)
954 printk(KERN_INFO PFX "Unsupported chip version.\n");
955 goto err_release_region;
958 /* initialize variables */
959 fdx = mii = fset = dxsuflo = ltint = 0;
960 chip_version = (chip_version >> 12) & 0xffff;
962 switch (chip_version) {
964 chipname = "PCnet/PCI 79C970"; /* PCI */
968 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
970 chipname = "PCnet/32 79C965"; /* 486/VL bus */
973 chipname = "PCnet/PCI II 79C970A"; /* PCI */
977 chipname = "PCnet/FAST 79C971"; /* PCI */
978 fdx = 1; mii = 1; fset = 1;
982 chipname = "PCnet/FAST+ 79C972"; /* PCI */
983 fdx = 1; mii = 1; fset = 1;
986 chipname = "PCnet/FAST III 79C973"; /* PCI */
990 chipname = "PCnet/Home 79C978"; /* PCI */
993 * This is based on specs published at www.amd.com. This section
994 * assumes that a card with a 79C978 wants to go into 1Mb HomePNA
995 * mode. The 79C978 can also go into standard ethernet, and there
996 * probably should be some sort of module option to select the
997 * mode by which the card should operate
999 /* switch to home wiring mode */
1000 media = a->read_bcr(ioaddr, 49);
1001 if (pcnet32_debug & NETIF_MSG_PROBE)
1002 printk(KERN_DEBUG PFX "media reset to %#x.\n", media);
1003 a->write_bcr(ioaddr, 49, media);
1006 chipname = "PCnet/FAST III 79C975"; /* PCI */
1010 chipname = "PCnet/FAST III 79C976";
1014 if (pcnet32_debug & NETIF_MSG_PROBE)
1015 printk(KERN_INFO PFX "PCnet version %#x, no PCnet32 chip.\n",
1017 goto err_release_region;
1021 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1022 * starting until the packet is loaded. Strike one for reliability, lose
1023 * one for latency - although on PCI this isnt a big loss. Older chips
1024 * have FIFO's smaller than a packet, so you can't do this.
1025 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1029 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1030 a->write_csr(ioaddr, 80, (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1035 dev = alloc_etherdev(0);
1037 if (pcnet32_debug & NETIF_MSG_PROBE)
1038 printk(KERN_ERR PFX "Memory allocation failed.\n");
1040 goto err_release_region;
1042 SET_NETDEV_DEV(dev, &pdev->dev);
1044 if (pcnet32_debug & NETIF_MSG_PROBE)
1045 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1047 /* In most chips, after a chip reset, the ethernet address is read from the
1048 * station address PROM at the base address and programmed into the
1049 * "Physical Address Registers" CSR12-14.
1050 * As a precautionary measure, we read the PROM values and complain if
1051 * they disagree with the CSRs. Either way, we use the CSR values, and
1052 * double check that they are valid.
1054 for (i = 0; i < 3; i++) {
1056 val = a->read_csr(ioaddr, i+12) & 0x0ffff;
1057 /* There may be endianness issues here. */
1058 dev->dev_addr[2*i] = val & 0x0ff;
1059 dev->dev_addr[2*i+1] = (val >> 8) & 0x0ff;
1062 /* read PROM address and compare with CSR address */
1063 for (i = 0; i < 6; i++)
1064 promaddr[i] = inb(ioaddr + i);
1066 if (memcmp(promaddr, dev->dev_addr, 6)
1067 || !is_valid_ether_addr(dev->dev_addr)) {
1069 if (is_valid_ether_addr(promaddr)) {
1071 if (!is_valid_ether_addr(dev->dev_addr)
1072 && is_valid_ether_addr(promaddr)) {
1074 if (pcnet32_debug & NETIF_MSG_PROBE) {
1075 printk(" warning: CSR address invalid,\n");
1076 printk(KERN_INFO " using instead PROM address of");
1078 memcpy(dev->dev_addr, promaddr, 6);
1082 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1083 if (!is_valid_ether_addr(dev->dev_addr))
1084 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1086 if (pcnet32_debug & NETIF_MSG_PROBE) {
1087 for (i = 0; i < 6; i++)
1088 printk(" %2.2x", dev->dev_addr[i]);
1090 /* Version 0x2623 and 0x2624 */
1091 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1092 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1093 printk("\n" KERN_INFO " tx_start_pt(0x%04x):",i);
1095 case 0: printk(" 20 bytes,"); break;
1096 case 1: printk(" 64 bytes,"); break;
1097 case 2: printk(" 128 bytes,"); break;
1098 case 3: printk("~220 bytes,"); break;
1100 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1101 printk(" BCR18(%x):",i&0xffff);
1102 if (i & (1<<5)) printk("BurstWrEn ");
1103 if (i & (1<<6)) printk("BurstRdEn ");
1104 if (i & (1<<7)) printk("DWordIO ");
1105 if (i & (1<<11)) printk("NoUFlow ");
1106 i = a->read_bcr(ioaddr, 25);
1107 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,",i<<8);
1108 i = a->read_bcr(ioaddr, 26);
1109 printk(" SRAM_BND=0x%04x,",i<<8);
1110 i = a->read_bcr(ioaddr, 27);
1111 if (i & (1<<14)) printk("LowLatRx");
1115 dev->base_addr = ioaddr;
1116 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1117 if ((lp = pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) {
1118 if (pcnet32_debug & NETIF_MSG_PROBE)
1119 printk(KERN_ERR PFX "Consistent memory allocation failed.\n");
1121 goto err_free_netdev;
1124 memset(lp, 0, sizeof(*lp));
1125 lp->dma_addr = lp_dma_addr;
1128 spin_lock_init(&lp->lock);
1130 SET_MODULE_OWNER(dev);
1131 SET_NETDEV_DEV(dev, &pdev->dev);
1133 lp->name = chipname;
1134 lp->shared_irq = shared;
1135 lp->mii_if.full_duplex = fdx;
1136 lp->mii_if.phy_id_mask = 0x1f;
1137 lp->mii_if.reg_num_mask = 0x1f;
1138 lp->dxsuflo = dxsuflo;
1141 lp->msg_enable = pcnet32_debug;
1142 if ((cards_found >= MAX_UNITS) || (options[cards_found] > sizeof(options_mapping)))
1143 lp->options = PCNET32_PORT_ASEL;
1145 lp->options = options_mapping[options[cards_found]];
1146 lp->mii_if.dev = dev;
1147 lp->mii_if.mdio_read = mdio_read;
1148 lp->mii_if.mdio_write = mdio_write;
1150 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1151 ((cards_found>=MAX_UNITS) || full_duplex[cards_found]))
1152 lp->options |= PCNET32_PORT_FD;
1155 if (pcnet32_debug & NETIF_MSG_PROBE)
1156 printk(KERN_ERR PFX "No access methods\n");
1158 goto err_free_consistent;
1162 /* detect special T1/E1 WAN card by checking for MAC address */
1163 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1164 && dev->dev_addr[2] == 0x75)
1165 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1167 lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1168 lp->init_block.tlen_rlen = le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS);
1169 for (i = 0; i < 6; i++)
1170 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1171 lp->init_block.filter[0] = 0x00000000;
1172 lp->init_block.filter[1] = 0x00000000;
1173 lp->init_block.rx_ring = (u32)le32_to_cpu(lp->dma_addr +
1174 offsetof(struct pcnet32_private, rx_ring));
1175 lp->init_block.tx_ring = (u32)le32_to_cpu(lp->dma_addr +
1176 offsetof(struct pcnet32_private, tx_ring));
1178 /* switch pcnet32 to 32bit mode */
1179 a->write_bcr(ioaddr, 20, 2);
1181 a->write_csr(ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private,
1182 init_block)) & 0xffff);
1183 a->write_csr(ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private,
1184 init_block)) >> 16);
1187 dev->irq = irq_line;
1190 if (dev->irq >= 2) {
1191 if (pcnet32_debug & NETIF_MSG_PROBE)
1192 printk(" assigned IRQ %d.\n", dev->irq);
1194 unsigned long irq_mask = probe_irq_on();
1197 * To auto-IRQ we enable the initialization-done and DMA error
1198 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1201 /* Trigger an initialization just for the interrupt. */
1202 a->write_csr (ioaddr, 0, 0x41);
1205 dev->irq = probe_irq_off (irq_mask);
1207 if (pcnet32_debug & NETIF_MSG_PROBE)
1208 printk(", failed to detect IRQ line.\n");
1210 goto err_free_consistent;
1212 if (pcnet32_debug & NETIF_MSG_PROBE)
1213 printk(", probed IRQ %d.\n", dev->irq);
1216 /* Set the mii phy_id so that we can query the link state */
1218 lp->mii_if.phy_id = ((lp->a.read_bcr (ioaddr, 33)) >> 5) & 0x1f;
1220 init_timer (&lp->watchdog_timer);
1221 lp->watchdog_timer.data = (unsigned long) dev;
1222 lp->watchdog_timer.function = (void *) &pcnet32_watchdog;
1224 /* The PCNET32-specific entries in the device structure. */
1225 dev->open = &pcnet32_open;
1226 dev->hard_start_xmit = &pcnet32_start_xmit;
1227 dev->stop = &pcnet32_close;
1228 dev->get_stats = &pcnet32_get_stats;
1229 dev->set_multicast_list = &pcnet32_set_multicast_list;
1230 dev->do_ioctl = &pcnet32_ioctl;
1231 dev->ethtool_ops = &pcnet32_ethtool_ops;
1232 dev->tx_timeout = pcnet32_tx_timeout;
1233 dev->watchdog_timeo = (5*HZ);
1235 #ifdef CONFIG_NET_POLL_CONTROLLER
1236 dev->poll_controller = pcnet32_poll_controller;
1239 /* Fill in the generic fields of the device structure. */
1240 if (register_netdev(dev))
1241 goto err_free_consistent;
1244 pci_set_drvdata(pdev, dev);
1246 lp->next = pcnet32_dev;
1250 if (pcnet32_debug & NETIF_MSG_PROBE)
1251 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1254 a->write_bcr(ioaddr, 2, 0x1002); /* enable LED writes */
1258 err_free_consistent:
1259 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
1263 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1269 pcnet32_open(struct net_device *dev)
1271 struct pcnet32_private *lp = dev->priv;
1272 unsigned long ioaddr = dev->base_addr;
1276 unsigned long flags;
1278 if (dev->irq == 0 ||
1279 request_irq(dev->irq, &pcnet32_interrupt,
1280 lp->shared_irq ? SA_SHIRQ : 0, dev->name, (void *)dev)) {
1284 spin_lock_irqsave(&lp->lock, flags);
1285 /* Check for a valid station address */
1286 if (!is_valid_ether_addr(dev->dev_addr)) {
1291 /* Reset the PCNET32 */
1292 lp->a.reset (ioaddr);
1294 /* switch pcnet32 to 32bit mode */
1295 lp->a.write_bcr (ioaddr, 20, 2);
1297 if (netif_msg_ifup(lp))
1298 printk(KERN_DEBUG "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
1299 dev->name, dev->irq,
1300 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, tx_ring)),
1301 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, rx_ring)),
1302 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, init_block)));
1304 /* set/reset autoselect bit */
1305 val = lp->a.read_bcr (ioaddr, 2) & ~2;
1306 if (lp->options & PCNET32_PORT_ASEL)
1308 lp->a.write_bcr (ioaddr, 2, val);
1310 /* handle full duplex setting */
1311 if (lp->mii_if.full_duplex) {
1312 val = lp->a.read_bcr (ioaddr, 9) & ~3;
1313 if (lp->options & PCNET32_PORT_FD) {
1315 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
1317 } else if (lp->options & PCNET32_PORT_ASEL) {
1318 /* workaround of xSeries250, turn on for 79C975 only */
1319 i = ((lp->a.read_csr(ioaddr, 88) |
1320 (lp->a.read_csr(ioaddr,89) << 16)) >> 12) & 0xffff;
1324 lp->a.write_bcr (ioaddr, 9, val);
1327 /* set/reset GPSI bit in test register */
1328 val = lp->a.read_csr (ioaddr, 124) & ~0x10;
1329 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
1331 lp->a.write_csr (ioaddr, 124, val);
1333 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
1334 /* disable Auto Negotiation, set 10Mpbs, HD */
1335 val = lp->a.read_bcr (ioaddr, 32) & ~0x38;
1336 if (lp->options & PCNET32_PORT_FD)
1338 if (lp->options & PCNET32_PORT_100)
1340 lp->a.write_bcr (ioaddr, 32, val);
1342 if (lp->options & PCNET32_PORT_ASEL) {
1343 /* enable auto negotiate, setup, disable fd */
1344 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
1346 lp->a.write_bcr(ioaddr, 32, val);
1351 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
1352 val = lp->a.read_csr (ioaddr, 3);
1354 lp->a.write_csr (ioaddr, 3, val);
1358 if (lp->ltint) { /* Enable TxDone-intr inhibitor */
1359 val = lp->a.read_csr (ioaddr, 5);
1361 lp->a.write_csr (ioaddr, 5, val);
1364 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
1365 pcnet32_load_multicast(dev);
1367 if (pcnet32_init_ring(dev)) {
1372 /* Re-initialize the PCNET32, and start it when done. */
1373 lp->a.write_csr (ioaddr, 1, (lp->dma_addr +
1374 offsetof(struct pcnet32_private, init_block)) & 0xffff);
1375 lp->a.write_csr (ioaddr, 2, (lp->dma_addr +
1376 offsetof(struct pcnet32_private, init_block)) >> 16);
1378 lp->a.write_csr (ioaddr, 4, 0x0915);
1379 lp->a.write_csr (ioaddr, 0, 0x0001);
1381 netif_start_queue(dev);
1383 /* If we have mii, print the link status and start the watchdog */
1385 mii_check_media (&lp->mii_if, netif_msg_link(lp), 1);
1386 mod_timer (&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
1391 if (lp->a.read_csr (ioaddr, 0) & 0x0100)
1394 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
1395 * reports that doing so triggers a bug in the '974.
1397 lp->a.write_csr (ioaddr, 0, 0x0042);
1399 if (netif_msg_ifup(lp))
1400 printk(KERN_DEBUG "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
1401 dev->name, i, (u32) (lp->dma_addr +
1402 offsetof(struct pcnet32_private, init_block)),
1403 lp->a.read_csr(ioaddr, 0));
1405 spin_unlock_irqrestore(&lp->lock, flags);
1407 return 0; /* Always succeed */
1410 /* free any allocated skbuffs */
1411 for (i = 0; i < RX_RING_SIZE; i++) {
1412 lp->rx_ring[i].status = 0;
1413 if (lp->rx_skbuff[i]) {
1414 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], PKT_BUF_SZ-2,
1415 PCI_DMA_FROMDEVICE);
1416 dev_kfree_skb(lp->rx_skbuff[i]);
1418 lp->rx_skbuff[i] = NULL;
1419 lp->rx_dma_addr[i] = 0;
1422 * Switch back to 16bit mode to avoid problems with dumb
1423 * DOS packet driver after a warm reboot
1425 lp->a.write_bcr (ioaddr, 20, 4);
1428 spin_unlock_irqrestore(&lp->lock, flags);
1429 free_irq(dev->irq, dev);
1434 * The LANCE has been halted for one reason or another (busmaster memory
1435 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
1436 * etc.). Modern LANCE variants always reload their ring-buffer
1437 * configuration when restarted, so we must reinitialize our ring
1438 * context before restarting. As part of this reinitialization,
1439 * find all packets still on the Tx ring and pretend that they had been
1440 * sent (in effect, drop the packets on the floor) - the higher-level
1441 * protocols will time out and retransmit. It'd be better to shuffle
1442 * these skbs to a temp list and then actually re-Tx them after
1443 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
1447 pcnet32_purge_tx_ring(struct net_device *dev)
1449 struct pcnet32_private *lp = dev->priv;
1452 for (i = 0; i < TX_RING_SIZE; i++) {
1453 if (lp->tx_skbuff[i]) {
1454 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
1455 lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
1456 dev_kfree_skb_any(lp->tx_skbuff[i]);
1457 lp->tx_skbuff[i] = NULL;
1458 lp->tx_dma_addr[i] = 0;
1464 /* Initialize the PCNET32 Rx and Tx rings. */
1466 pcnet32_init_ring(struct net_device *dev)
1468 struct pcnet32_private *lp = dev->priv;
1472 lp->cur_rx = lp->cur_tx = 0;
1473 lp->dirty_rx = lp->dirty_tx = 0;
1475 for (i = 0; i < RX_RING_SIZE; i++) {
1476 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
1477 if (rx_skbuff == NULL) {
1478 if (!(rx_skbuff = lp->rx_skbuff[i] = dev_alloc_skb (PKT_BUF_SZ))) {
1479 /* there is not much, we can do at this point */
1480 if (pcnet32_debug & NETIF_MSG_DRV)
1481 printk(KERN_ERR "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
1485 skb_reserve (rx_skbuff, 2);
1488 if (lp->rx_dma_addr[i] == 0)
1489 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev, rx_skbuff->tail,
1490 PKT_BUF_SZ-2, PCI_DMA_FROMDEVICE);
1491 lp->rx_ring[i].base = (u32)le32_to_cpu(lp->rx_dma_addr[i]);
1492 lp->rx_ring[i].buf_length = le16_to_cpu(2-PKT_BUF_SZ);
1493 lp->rx_ring[i].status = le16_to_cpu(0x8000);
1495 /* The Tx buffer address is filled in as needed, but we do need to clear
1496 * the upper ownership bit. */
1497 for (i = 0; i < TX_RING_SIZE; i++) {
1498 lp->tx_ring[i].base = 0;
1499 lp->tx_ring[i].status = 0;
1500 lp->tx_dma_addr[i] = 0;
1502 wmb(); /* Make sure all changes are visible */
1504 lp->init_block.tlen_rlen = le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS);
1505 for (i = 0; i < 6; i++)
1506 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1507 lp->init_block.rx_ring = (u32)le32_to_cpu(lp->dma_addr +
1508 offsetof(struct pcnet32_private, rx_ring));
1509 lp->init_block.tx_ring = (u32)le32_to_cpu(lp->dma_addr +
1510 offsetof(struct pcnet32_private, tx_ring));
1515 pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1517 struct pcnet32_private *lp = dev->priv;
1518 unsigned long ioaddr = dev->base_addr;
1521 pcnet32_purge_tx_ring(dev);
1522 if (pcnet32_init_ring(dev))
1526 lp->a.write_csr (ioaddr, 0, 1);
1529 if (lp->a.read_csr (ioaddr, 0) & 0x0100)
1532 lp->a.write_csr (ioaddr, 0, csr0_bits);
1537 pcnet32_tx_timeout (struct net_device *dev)
1539 struct pcnet32_private *lp = dev->priv;
1540 unsigned long ioaddr = dev->base_addr, flags;
1542 spin_lock_irqsave(&lp->lock, flags);
1543 /* Transmitter timeout, serious problems. */
1544 if (pcnet32_debug & NETIF_MSG_DRV)
1545 printk(KERN_ERR "%s: transmit timed out, status %4.4x, resetting.\n",
1546 dev->name, lp->a.read_csr(ioaddr, 0));
1547 lp->a.write_csr (ioaddr, 0, 0x0004);
1548 lp->stats.tx_errors++;
1549 if (netif_msg_tx_err(lp)) {
1551 printk(KERN_DEBUG " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
1552 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
1554 for (i = 0 ; i < RX_RING_SIZE; i++)
1555 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
1556 lp->rx_ring[i].base, -lp->rx_ring[i].buf_length,
1557 lp->rx_ring[i].msg_length, (unsigned)lp->rx_ring[i].status);
1558 for (i = 0 ; i < TX_RING_SIZE; i++)
1559 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
1560 lp->tx_ring[i].base, -lp->tx_ring[i].length,
1561 lp->tx_ring[i].misc, (unsigned)lp->tx_ring[i].status);
1564 pcnet32_restart(dev, 0x0042);
1566 dev->trans_start = jiffies;
1567 netif_wake_queue(dev);
1569 spin_unlock_irqrestore(&lp->lock, flags);
1574 pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
1576 struct pcnet32_private *lp = dev->priv;
1577 unsigned long ioaddr = dev->base_addr;
1580 unsigned long flags;
1582 if (netif_msg_tx_queued(lp)) {
1583 printk(KERN_DEBUG "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
1584 dev->name, lp->a.read_csr(ioaddr, 0));
1587 spin_lock_irqsave(&lp->lock, flags);
1589 /* Default status -- will not enable Successful-TxDone
1590 * interrupt when that option is available to us.
1593 entry = (lp->cur_tx - lp->dirty_tx) & TX_RING_MOD_MASK;
1595 ((entry == TX_RING_SIZE/3) ||
1596 (entry == (TX_RING_SIZE*2)/3) ||
1597 (entry >= TX_RING_SIZE-2)))
1599 /* Enable Successful-TxDone interrupt if we have
1600 * 1/3, 2/3 or nearly all of, our ring buffer Tx'd
1601 * but not yet cleaned up. Thus, most of the time,
1602 * we will not enable Successful-TxDone interrupts.
1607 /* Fill in a Tx ring entry */
1609 /* Mask to ring buffer boundary. */
1610 entry = lp->cur_tx & TX_RING_MOD_MASK;
1612 /* Caution: the write order is important here, set the status
1613 * with the "ownership" bits last. */
1615 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
1617 lp->tx_ring[entry].misc = 0x00000000;
1619 lp->tx_skbuff[entry] = skb;
1620 lp->tx_dma_addr[entry] = pci_map_single(lp->pci_dev, skb->data, skb->len,
1622 lp->tx_ring[entry].base = (u32)le32_to_cpu(lp->tx_dma_addr[entry]);
1623 wmb(); /* Make sure owner changes after all others are visible */
1624 lp->tx_ring[entry].status = le16_to_cpu(status);
1627 lp->stats.tx_bytes += skb->len;
1629 /* Trigger an immediate send poll. */
1630 lp->a.write_csr (ioaddr, 0, 0x0048);
1632 dev->trans_start = jiffies;
1634 if (lp->tx_ring[(entry+1) & TX_RING_MOD_MASK].base != 0) {
1636 netif_stop_queue(dev);
1638 spin_unlock_irqrestore(&lp->lock, flags);
1642 /* The PCNET32 interrupt handler. */
1644 pcnet32_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1646 struct net_device *dev = dev_id;
1647 struct pcnet32_private *lp;
1648 unsigned long ioaddr;
1650 int boguscnt = max_interrupt_work;
1654 if (pcnet32_debug & NETIF_MSG_INTR)
1655 printk (KERN_DEBUG "%s(): irq %d for unknown device\n",
1660 ioaddr = dev->base_addr;
1663 spin_lock(&lp->lock);
1665 rap = lp->a.read_rap(ioaddr);
1666 while ((csr0 = lp->a.read_csr (ioaddr, 0)) & 0x8600 && --boguscnt >= 0) {
1667 if (csr0 == 0xffff) {
1668 break; /* PCMCIA remove happened */
1670 /* Acknowledge all of the current interrupt sources ASAP. */
1671 lp->a.write_csr (ioaddr, 0, csr0 & ~0x004f);
1675 if (netif_msg_intr(lp))
1676 printk(KERN_DEBUG "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
1677 dev->name, csr0, lp->a.read_csr (ioaddr, 0));
1679 if (csr0 & 0x0400) /* Rx interrupt */
1682 if (csr0 & 0x0200) { /* Tx-done interrupt */
1683 unsigned int dirty_tx = lp->dirty_tx;
1686 while (dirty_tx != lp->cur_tx) {
1687 int entry = dirty_tx & TX_RING_MOD_MASK;
1688 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1691 break; /* It still hasn't been Txed */
1693 lp->tx_ring[entry].base = 0;
1695 if (status & 0x4000) {
1696 /* There was an major error, log it. */
1697 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1698 lp->stats.tx_errors++;
1699 if (err_status & 0x04000000) lp->stats.tx_aborted_errors++;
1700 if (err_status & 0x08000000) lp->stats.tx_carrier_errors++;
1701 if (err_status & 0x10000000) lp->stats.tx_window_errors++;
1703 if (err_status & 0x40000000) {
1704 lp->stats.tx_fifo_errors++;
1705 /* Ackk! On FIFO errors the Tx unit is turned off! */
1706 /* Remove this verbosity later! */
1707 if (netif_msg_tx_err(lp))
1708 printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n",
1713 if (err_status & 0x40000000) {
1714 lp->stats.tx_fifo_errors++;
1715 if (! lp->dxsuflo) { /* If controller doesn't recover ... */
1716 /* Ackk! On FIFO errors the Tx unit is turned off! */
1717 /* Remove this verbosity later! */
1718 if (netif_msg_tx_err(lp))
1719 printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n",
1726 if (status & 0x1800)
1727 lp->stats.collisions++;
1728 lp->stats.tx_packets++;
1731 /* We must free the original skb */
1732 if (lp->tx_skbuff[entry]) {
1733 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[entry],
1734 lp->tx_skbuff[entry]->len, PCI_DMA_TODEVICE);
1735 dev_kfree_skb_irq(lp->tx_skbuff[entry]);
1736 lp->tx_skbuff[entry] = 0;
1737 lp->tx_dma_addr[entry] = 0;
1742 delta = (lp->cur_tx - dirty_tx) & (TX_RING_MOD_MASK + TX_RING_SIZE);
1743 if (delta >= TX_RING_SIZE) {
1744 if (netif_msg_drv(lp))
1745 printk(KERN_ERR "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1746 dev->name, dirty_tx, lp->cur_tx, lp->tx_full);
1747 dirty_tx += TX_RING_SIZE;
1748 delta -= TX_RING_SIZE;
1752 netif_queue_stopped(dev) &&
1753 delta < TX_RING_SIZE - 2) {
1754 /* The ring is no longer full, clear tbusy. */
1756 netif_wake_queue (dev);
1758 lp->dirty_tx = dirty_tx;
1761 /* Log misc errors. */
1762 if (csr0 & 0x4000) lp->stats.tx_errors++; /* Tx babble. */
1763 if (csr0 & 0x1000) {
1765 * this happens when our receive ring is full. This shouldn't
1766 * be a problem as we will see normal rx interrupts for the frames
1767 * in the receive ring. But there are some PCI chipsets (I can
1768 * reproduce this on SP3G with Intel saturn chipset) which have
1769 * sometimes problems and will fill up the receive ring with
1770 * error descriptors. In this situation we don't get a rx
1771 * interrupt, but a missed frame interrupt sooner or later.
1772 * So we try to clean up our receive ring here.
1775 lp->stats.rx_errors++; /* Missed a Rx frame. */
1777 if (csr0 & 0x0800) {
1778 if (netif_msg_drv(lp))
1779 printk(KERN_ERR "%s: Bus master arbitration failure, status %4.4x.\n",
1781 /* unlike for the lance, there is no restart needed */
1785 /* stop the chip to clear the error condition, then restart */
1786 lp->a.write_csr (ioaddr, 0, 0x0004);
1787 pcnet32_restart(dev, 0x0002);
1791 /* Clear any other interrupt, and set interrupt enable. */
1792 lp->a.write_csr (ioaddr, 0, 0x7940);
1793 lp->a.write_rap (ioaddr,rap);
1795 if (netif_msg_intr(lp))
1796 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
1797 dev->name, lp->a.read_csr (ioaddr, 0));
1799 spin_unlock(&lp->lock);
1805 pcnet32_rx(struct net_device *dev)
1807 struct pcnet32_private *lp = dev->priv;
1808 int entry = lp->cur_rx & RX_RING_MOD_MASK;
1810 /* If we own the next entry, it's a new packet. Send it up. */
1811 while ((short)le16_to_cpu(lp->rx_ring[entry].status) >= 0) {
1812 int status = (short)le16_to_cpu(lp->rx_ring[entry].status) >> 8;
1814 if (status != 0x03) { /* There was an error. */
1816 * There is a tricky error noted by John Murphy,
1817 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1818 * buffers it's possible for a jabber packet to use two
1819 * buffers, with only the last correctly noting the error.
1821 if (status & 0x01) /* Only count a general error at the */
1822 lp->stats.rx_errors++; /* end of a packet.*/
1823 if (status & 0x20) lp->stats.rx_frame_errors++;
1824 if (status & 0x10) lp->stats.rx_over_errors++;
1825 if (status & 0x08) lp->stats.rx_crc_errors++;
1826 if (status & 0x04) lp->stats.rx_fifo_errors++;
1827 lp->rx_ring[entry].status &= le16_to_cpu(0x03ff);
1829 /* Malloc up new buffer, compatible with net-2e. */
1830 short pkt_len = (le32_to_cpu(lp->rx_ring[entry].msg_length) & 0xfff)-4;
1831 struct sk_buff *skb;
1834 if (netif_msg_rx_err(lp))
1835 printk(KERN_ERR "%s: Runt packet!\n", dev->name);
1836 lp->stats.rx_errors++;
1838 int rx_in_place = 0;
1840 if (pkt_len > rx_copybreak) {
1841 struct sk_buff *newskb;
1843 if ((newskb = dev_alloc_skb(PKT_BUF_SZ))) {
1844 skb_reserve (newskb, 2);
1845 skb = lp->rx_skbuff[entry];
1846 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[entry],
1847 PKT_BUF_SZ-2, PCI_DMA_FROMDEVICE);
1848 skb_put (skb, pkt_len);
1849 lp->rx_skbuff[entry] = newskb;
1851 lp->rx_dma_addr[entry] =
1852 pci_map_single(lp->pci_dev, newskb->tail,
1853 PKT_BUF_SZ-2, PCI_DMA_FROMDEVICE);
1854 lp->rx_ring[entry].base = le32_to_cpu(lp->rx_dma_addr[entry]);
1859 skb = dev_alloc_skb(pkt_len+2);
1864 if (netif_msg_drv(lp))
1865 printk(KERN_ERR "%s: Memory squeeze, deferring packet.\n",
1867 for (i = 0; i < RX_RING_SIZE; i++)
1868 if ((short)le16_to_cpu(lp->rx_ring[(entry+i)
1869 & RX_RING_MOD_MASK].status) < 0)
1872 if (i > RX_RING_SIZE -2) {
1873 lp->stats.rx_dropped++;
1874 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
1881 skb_reserve(skb,2); /* 16 byte align */
1882 skb_put(skb,pkt_len); /* Make room */
1883 pci_dma_sync_single_for_cpu(lp->pci_dev,
1884 lp->rx_dma_addr[entry],
1886 PCI_DMA_FROMDEVICE);
1887 eth_copy_and_sum(skb,
1888 (unsigned char *)(lp->rx_skbuff[entry]->tail),
1890 pci_dma_sync_single_for_device(lp->pci_dev,
1891 lp->rx_dma_addr[entry],
1893 PCI_DMA_FROMDEVICE);
1895 lp->stats.rx_bytes += skb->len;
1896 skb->protocol=eth_type_trans(skb,dev);
1898 dev->last_rx = jiffies;
1899 lp->stats.rx_packets++;
1903 * The docs say that the buffer length isn't touched, but Andrew Boyd
1904 * of QNX reports that some revs of the 79C965 clear it.
1906 lp->rx_ring[entry].buf_length = le16_to_cpu(2-PKT_BUF_SZ);
1907 wmb(); /* Make sure owner changes after all others are visible */
1908 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
1909 entry = (++lp->cur_rx) & RX_RING_MOD_MASK;
1916 pcnet32_close(struct net_device *dev)
1918 unsigned long ioaddr = dev->base_addr;
1919 struct pcnet32_private *lp = dev->priv;
1921 unsigned long flags;
1923 del_timer_sync(&lp->watchdog_timer);
1925 netif_stop_queue(dev);
1927 spin_lock_irqsave(&lp->lock, flags);
1929 lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112);
1931 if (netif_msg_ifdown(lp))
1932 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1933 dev->name, lp->a.read_csr (ioaddr, 0));
1935 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
1936 lp->a.write_csr (ioaddr, 0, 0x0004);
1939 * Switch back to 16bit mode to avoid problems with dumb
1940 * DOS packet driver after a warm reboot
1942 lp->a.write_bcr (ioaddr, 20, 4);
1944 spin_unlock_irqrestore(&lp->lock, flags);
1946 free_irq(dev->irq, dev);
1948 /* free all allocated skbuffs */
1949 for (i = 0; i < RX_RING_SIZE; i++) {
1950 lp->rx_ring[i].status = 0;
1951 if (lp->rx_skbuff[i]) {
1952 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], PKT_BUF_SZ-2,
1953 PCI_DMA_FROMDEVICE);
1954 dev_kfree_skb(lp->rx_skbuff[i]);
1956 lp->rx_skbuff[i] = NULL;
1957 lp->rx_dma_addr[i] = 0;
1960 for (i = 0; i < TX_RING_SIZE; i++) {
1961 if (lp->tx_skbuff[i]) {
1962 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
1963 lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
1964 dev_kfree_skb(lp->tx_skbuff[i]);
1966 lp->tx_skbuff[i] = NULL;
1967 lp->tx_dma_addr[i] = 0;
1973 static struct net_device_stats *
1974 pcnet32_get_stats(struct net_device *dev)
1976 struct pcnet32_private *lp = dev->priv;
1977 unsigned long ioaddr = dev->base_addr;
1979 unsigned long flags;
1981 spin_lock_irqsave(&lp->lock, flags);
1982 saved_addr = lp->a.read_rap(ioaddr);
1983 lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112);
1984 lp->a.write_rap(ioaddr, saved_addr);
1985 spin_unlock_irqrestore(&lp->lock, flags);
1990 /* taken from the sunlance driver, which it took from the depca driver */
1991 static void pcnet32_load_multicast (struct net_device *dev)
1993 struct pcnet32_private *lp = dev->priv;
1994 volatile struct pcnet32_init_block *ib = &lp->init_block;
1995 volatile u16 *mcast_table = (u16 *)&ib->filter;
1996 struct dev_mc_list *dmi=dev->mc_list;
2001 /* set all multicast bits */
2002 if (dev->flags & IFF_ALLMULTI) {
2003 ib->filter[0] = 0xffffffff;
2004 ib->filter[1] = 0xffffffff;
2007 /* clear the multicast filter */
2012 for (i = 0; i < dev->mc_count; i++) {
2013 addrs = dmi->dmi_addr;
2016 /* multicast address? */
2020 crc = ether_crc_le(6, addrs);
2022 mcast_table [crc >> 4] = le16_to_cpu(
2023 le16_to_cpu(mcast_table [crc >> 4]) | (1 << (crc & 0xf)));
2030 * Set or clear the multicast filter for this adaptor.
2032 static void pcnet32_set_multicast_list(struct net_device *dev)
2034 unsigned long ioaddr = dev->base_addr, flags;
2035 struct pcnet32_private *lp = dev->priv;
2037 spin_lock_irqsave(&lp->lock, flags);
2038 if (dev->flags&IFF_PROMISC) {
2039 /* Log any net taps. */
2040 if (netif_msg_hw(lp))
2041 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
2042 lp->init_block.mode = le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << 7);
2044 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2045 pcnet32_load_multicast (dev);
2048 lp->a.write_csr (ioaddr, 0, 0x0004); /* Temporarily stop the lance. */
2050 pcnet32_restart(dev, 0x0042); /* Resume normal operation */
2051 spin_unlock_irqrestore(&lp->lock, flags);
2054 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2056 struct pcnet32_private *lp = dev->priv;
2057 unsigned long ioaddr = dev->base_addr;
2064 phyaddr = lp->a.read_bcr(ioaddr, 33);
2066 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2067 val_out = lp->a.read_bcr(ioaddr, 34);
2068 lp->a.write_bcr(ioaddr, 33, phyaddr);
2073 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2075 struct pcnet32_private *lp = dev->priv;
2076 unsigned long ioaddr = dev->base_addr;
2082 phyaddr = lp->a.read_bcr(ioaddr, 33);
2084 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2085 lp->a.write_bcr(ioaddr, 34, val);
2086 lp->a.write_bcr(ioaddr, 33, phyaddr);
2089 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2091 struct pcnet32_private *lp = dev->priv;
2092 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&rq->ifr_data;
2094 unsigned long flags;
2096 /* SIOC[GS]MIIxxx ioctls */
2098 spin_lock_irqsave(&lp->lock, flags);
2099 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
2100 spin_unlock_irqrestore(&lp->lock, flags);
2108 static void pcnet32_watchdog(struct net_device *dev)
2110 struct pcnet32_private *lp = dev->priv;
2111 unsigned long flags;
2113 /* Print the link status if it has changed */
2115 spin_lock_irqsave(&lp->lock, flags);
2116 mii_check_media (&lp->mii_if, netif_msg_link(lp), 0);
2117 spin_unlock_irqrestore(&lp->lock, flags);
2120 mod_timer (&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2123 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2125 struct net_device *dev = pci_get_drvdata(pdev);
2128 struct pcnet32_private *lp = dev->priv;
2130 unregister_netdev(dev);
2131 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2132 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2134 pci_set_drvdata(pdev, NULL);
2138 static struct pci_driver pcnet32_driver = {
2140 .probe = pcnet32_probe_pci,
2141 .remove = __devexit_p(pcnet32_remove_one),
2142 .id_table = pcnet32_pci_tbl,
2145 MODULE_PARM(debug, "i");
2146 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2147 MODULE_PARM(max_interrupt_work, "i");
2148 MODULE_PARM_DESC(max_interrupt_work, DRV_NAME " maximum events handled per interrupt");
2149 MODULE_PARM(rx_copybreak, "i");
2150 MODULE_PARM_DESC(rx_copybreak, DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2151 MODULE_PARM(tx_start_pt, "i");
2152 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2153 MODULE_PARM(pcnet32vlb, "i");
2154 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2155 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
2156 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2157 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
2158 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2160 MODULE_AUTHOR("Thomas Bogendoerfer");
2161 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2162 MODULE_LICENSE("GPL");
2164 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2166 /* An additional parameter that may be passed in... */
2167 static int debug = -1;
2168 static int tx_start_pt = -1;
2169 static int pcnet32_have_pci;
2171 static int __init pcnet32_init_module(void)
2173 printk(KERN_INFO "%s", version);
2175 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
2177 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2178 tx_start = tx_start_pt;
2180 /* find the PCI devices */
2181 if (!pci_module_init(&pcnet32_driver))
2182 pcnet32_have_pci = 1;
2184 /* should we find any remaining VLbus devices ? */
2186 pcnet32_probe_vlbus();
2188 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
2189 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
2191 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
2194 static void __exit pcnet32_cleanup_module(void)
2196 struct net_device *next_dev;
2198 while (pcnet32_dev) {
2199 struct pcnet32_private *lp = pcnet32_dev->priv;
2200 next_dev = lp->next;
2201 unregister_netdev(pcnet32_dev);
2202 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
2203 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2204 free_netdev(pcnet32_dev);
2205 pcnet32_dev = next_dev;
2208 if (pcnet32_have_pci)
2209 pci_unregister_driver(&pcnet32_driver);
2212 module_init(pcnet32_init_module);
2213 module_exit(pcnet32_cleanup_module);