2 =========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
9 =========================================================================
10 1. The media can be forced in 5 modes.
11 Command: 'insmod r8169 media = SET_MEDIA'
12 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
22 =========================================================================
23 VERSION 1.1 <2002/10/4>
25 The bit4:0 of MII register 4 is called "selector field", and have to be
26 00001b to indicate support of IEEE std 802.3 during NWay process of
27 exchanging Link Code Word (FLP).
29 VERSION 1.2 <2002/11/30>
32 - Use ether_crc in stock kernel (linux/crc32.h)
33 - Copy mc_filter setup code from 8139cp
34 (includes an optimization, and avoids set_bit use)
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/netdevice.h>
41 #include <linux/etherdevice.h>
42 #include <linux/delay.h>
43 #include <linux/ethtool.h>
44 #include <linux/crc32.h>
45 #include <linux/init.h>
46 #include <linux/dma-mapping.h>
50 #define RTL8169_VERSION "1.2"
51 #define MODULENAME "r8169"
52 #define RTL8169_DRIVER_NAME MODULENAME " Gigabit Ethernet driver " RTL8169_VERSION
53 #define PFX MODULENAME ": "
56 #define assert(expr) \
58 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
59 #expr,__FILE__,__FUNCTION__,__LINE__); \
61 #define dprintk(fmt, args...) do { printk(PFX fmt, ## args) } while (0)
63 #define assert(expr) do {} while (0)
64 #define dprintk(fmt, args...) do {} while (0)
65 #endif /* RTL8169_DEBUG */
69 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
71 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
72 static int max_interrupt_work = 20;
74 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
75 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
76 static int multicast_filter_limit = 32;
78 /* MAC address length*/
79 #define MAC_ADDR_LEN 6
81 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
82 #define MAX_ETH_FRAME_SIZE 1536
84 #define TX_FIFO_THRESH 256 /* In bytes */
86 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
87 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
88 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
89 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
90 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
91 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
93 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
94 #define NUM_RX_DESC 64 /* Number of Rx descriptor registers */
95 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
96 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
97 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
99 #define RTL_MIN_IO_SIZE 0x80
100 #define RTL8169_TX_TIMEOUT (6*HZ)
101 #define RTL8169_PHY_TIMEOUT (HZ)
103 /* write/read MMIO register */
104 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
105 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
106 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
107 #define RTL_R8(reg) readb (ioaddr + (reg))
108 #define RTL_R16(reg) readw (ioaddr + (reg))
109 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
112 RTL_GIGA_MAC_VER_B = 0x00,
113 /* RTL_GIGA_MAC_VER_C = 0x03, */
114 RTL_GIGA_MAC_VER_D = 0x01,
115 RTL_GIGA_MAC_VER_E = 0x02
119 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
120 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
121 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
122 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
123 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
127 #define _R(NAME,MAC,MASK) \
128 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
130 const static struct {
133 u32 RxConfigMask; /* Clears the bits supported by this chip */
134 } rtl_chip_info[] = {
135 _R("RTL8169", RTL_GIGA_MAC_VER_B, 0xff7e1880),
136 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_D, 0xff7e1880),
137 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_E, 0xff7e1880)
141 static struct pci_device_id rtl8169_pci_tbl[] = {
142 {0x10ec, 0x8169, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
146 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
148 static int rx_copybreak = 200;
150 enum RTL8169_registers {
151 MAC0 = 0, /* Ethernet hardware address. */
152 MAR0 = 8, /* Multicast filter. */
153 TxDescStartAddrLow = 0x20,
154 TxDescStartAddrHigh = 0x24,
155 TxHDescStartAddrLow = 0x28,
156 TxHDescStartAddrHigh = 0x2c,
181 RxDescAddrLow = 0xE4,
182 RxDescAddrHigh = 0xE8,
185 FuncEventMask = 0xF4,
186 FuncPresetState = 0xF8,
187 FuncForceEvent = 0xFC,
190 enum RTL8169_register_content {
191 /*InterruptStatusBits */
195 TxDescUnavail = 0x80,
218 Cfg9346_Unlock = 0xC0,
223 AcceptBroadcast = 0x08,
224 AcceptMulticast = 0x04,
226 AcceptAllPhys = 0x01,
233 TxInterFrameGapShift = 24,
234 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
242 /*rtl8169_PHYstatus */
252 /*GIGABIT_PHY_registers */
255 PHY_AUTO_NEGO_REG = 4,
256 PHY_1000_CTRL_REG = 9,
258 /*GIGABIT_PHY_REG_BIT */
259 PHY_Restart_Auto_Nego = 0x0200,
260 PHY_Enable_Auto_Nego = 0x1000,
263 PHY_Auto_Neco_Comp = 0x0020,
265 //PHY_AUTO_NEGO_REG = 4;
266 PHY_Cap_10_Half = 0x0020,
267 PHY_Cap_10_Full = 0x0040,
268 PHY_Cap_100_Half = 0x0080,
269 PHY_Cap_100_Full = 0x0100,
271 //PHY_1000_CTRL_REG = 9;
272 PHY_Cap_1000_Full = 0x0200,
284 TBILinkOK = 0x02000000,
287 enum _DescStatusBit {
294 #define RsvdMask 0x3fffc000
308 struct rtl8169_private {
309 void *mmio_addr; /* memory map physical address */
310 struct pci_dev *pci_dev; /* Index of PCI device */
311 struct net_device_stats stats; /* statistics of net device */
312 spinlock_t lock; /* spin lock flag */
316 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
317 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
320 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
321 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
322 dma_addr_t TxPhyAddr;
323 dma_addr_t RxPhyAddr;
324 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
325 struct sk_buff *Tx_skbuff[NUM_TX_DESC]; /* Index of Transmit data buffer */
326 struct timer_list timer;
327 unsigned long phy_link_down_cnt;
331 MODULE_AUTHOR("Realtek");
332 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
333 MODULE_PARM(media, "1-" __MODULE_STRING(MAX_UNITS) "i");
334 MODULE_PARM(rx_copybreak, "i");
335 MODULE_LICENSE("GPL");
337 static int rtl8169_open(struct net_device *dev);
338 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
339 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance,
340 struct pt_regs *regs);
341 static int rtl8169_init_ring(struct net_device *dev);
342 static void rtl8169_hw_start(struct net_device *dev);
343 static int rtl8169_close(struct net_device *dev);
344 static void rtl8169_set_rx_mode(struct net_device *dev);
345 static void rtl8169_tx_timeout(struct net_device *dev);
346 static struct net_device_stats *rtl8169_get_stats(struct net_device *netdev);
348 static const u16 rtl8169_intr_mask =
349 RxUnderrun | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
350 static const unsigned int rtl8169_rx_config =
351 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
353 #define PHY_Cap_10_Half_Or_Less PHY_Cap_10_Half
354 #define PHY_Cap_10_Full_Or_Less PHY_Cap_10_Full | PHY_Cap_10_Half_Or_Less
355 #define PHY_Cap_100_Half_Or_Less PHY_Cap_100_Half | PHY_Cap_10_Full_Or_Less
356 #define PHY_Cap_100_Full_Or_Less PHY_Cap_100_Full | PHY_Cap_100_Half_Or_Less
358 static void mdio_write(void *ioaddr, int RegAddr, int value)
362 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
365 for (i = 2000; i > 0; i--) {
366 // Check if the RTL8169 has completed writing to the specified MII register
367 if (!(RTL_R32(PHYAR) & 0x80000000)) {
375 static int mdio_read(void *ioaddr, int RegAddr)
379 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
382 for (i = 2000; i > 0; i--) {
383 // Check if the RTL8169 has completed retrieving data from the specified MII register
384 if (RTL_R32(PHYAR) & 0x80000000) {
385 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
393 static void rtl8169_get_drvinfo(struct net_device *dev,
394 struct ethtool_drvinfo *info)
396 struct rtl8169_private *tp = dev->priv;
398 strcpy(info->driver, RTL8169_DRIVER_NAME);
399 strcpy(info->version, RTL8169_VERSION );
400 strcpy(info->bus_info, pci_name(tp->pci_dev));
403 static struct ethtool_ops rtl8169_ethtool_ops = {
404 .get_drvinfo = rtl8169_get_drvinfo,
407 static void rtl8169_write_gmii_reg_bit(void *ioaddr, int reg, int bitnum,
412 val = mdio_read(ioaddr, reg);
413 val = (bitval == 1) ?
414 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
415 mdio_write(ioaddr, reg, val & 0xffff);
418 static void rtl8169_get_mac_version(struct rtl8169_private *tp, void *ioaddr)
424 { 0x1 << 26, RTL_GIGA_MAC_VER_E },
425 { 0x1 << 23, RTL_GIGA_MAC_VER_D },
426 { 0x00000000, RTL_GIGA_MAC_VER_B } /* Catch-all */
430 reg = RTL_R32(TxConfig) & 0x7c800000;
431 while ((reg & p->mask) != p->mask)
433 tp->mac_version = p->mac_version;
436 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
442 { RTL_GIGA_MAC_VER_E, "RTL_GIGA_MAC_VER_E" },
443 { RTL_GIGA_MAC_VER_D, "RTL_GIGA_MAC_VER_D" },
444 { RTL_GIGA_MAC_VER_B, "RTL_GIGA_MAC_VER_B" },
448 for (p = mac_print; p->msg; p++) {
449 if (tp->mac_version == p->version) {
450 dprintk("mac_version == %s (%04d)\n", p->msg,
455 dprintk("mac_version == Unknown\n");
458 static void rtl8169_get_phy_version(struct rtl8169_private *tp, void *ioaddr)
465 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
466 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
467 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
468 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
472 reg = mdio_read(ioaddr, 3) & 0xffff;
473 while ((reg & p->mask) != p->set)
475 tp->phy_version = p->phy_version;
478 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
485 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
486 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
487 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
488 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
492 for (p = phy_print; p->msg; p++) {
493 if (tp->phy_version == p->version) {
494 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
498 dprintk("phy_version == Unknown\n");
501 static void rtl8169_hw_phy_config(struct net_device *dev)
503 struct rtl8169_private *tp = dev->priv;
504 void *ioaddr = tp->mmio_addr;
506 u16 regs[5]; /* Beware of bit-sign propagation */
508 { 0x0000, //w 4 15 12 0
509 0x00a1, //w 3 15 0 00a1
510 0x0008, //w 2 15 0 0008
511 0x1020, //w 1 15 0 1020
512 0x1000 } },{ //w 0 15 0 1000
513 { 0x7000, //w 4 15 12 7
514 0xff41, //w 3 15 0 ff41
515 0xde60, //w 2 15 0 de60
516 0x0140, //w 1 15 0 0140
517 0x0077 } },{ //w 0 15 0 0077
518 { 0xa000, //w 4 15 12 a
519 0xdf01, //w 3 15 0 df01
520 0xdf20, //w 2 15 0 df20
521 0xff95, //w 1 15 0 ff95
522 0xfa00 } },{ //w 0 15 0 fa00
523 { 0xb000, //w 4 15 12 b
524 0xff41, //w 3 15 0 ff41
525 0xde20, //w 2 15 0 de20
526 0x0140, //w 1 15 0 0140
527 0x00bb } },{ //w 0 15 0 00bb
528 { 0xf000, //w 4 15 12 f
529 0xdf01, //w 3 15 0 df01
530 0xdf20, //w 2 15 0 df20
531 0xff95, //w 1 15 0 ff95
532 0xbf00 } //w 0 15 0 bf00
537 rtl8169_print_mac_version(tp);
538 rtl8169_print_phy_version(tp);
540 if (tp->mac_version <= RTL_GIGA_MAC_VER_B)
542 if (tp->phy_version >= RTL_GIGA_PHY_VER_F)
545 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
546 dprintk("Do final_reg2.cfg\n");
550 // phy config for RTL8169s mac_version C chip
551 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
552 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
553 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
554 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
556 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
559 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
560 mdio_write(ioaddr, pos, val);
562 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
563 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
564 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
566 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
569 static void rtl8169_hw_phy_reset(struct net_device *dev)
571 struct rtl8169_private *tp = dev->priv;
572 void *ioaddr = tp->mmio_addr;
575 printk(KERN_WARNING PFX "%s: Reset RTL8169s PHY\n", dev->name);
577 val = (mdio_read(ioaddr, 0) | 0x8000) & 0xffff;
578 mdio_write(ioaddr, 0, val);
580 for (i = 50; i >= 0; i--) {
581 if (!(mdio_read(ioaddr, 0) & 0x8000))
583 udelay(100); /* Gross */
587 printk(KERN_WARNING PFX "%s: no PHY Reset ack. Giving up.\n",
592 static void rtl8169_phy_timer(unsigned long __opaque)
594 struct net_device *dev = (struct net_device *)__opaque;
595 struct rtl8169_private *tp = dev->priv;
596 struct timer_list *timer = &tp->timer;
597 void *ioaddr = tp->mmio_addr;
599 assert(tp->mac_version > RTL_GIGA_MAC_VER_B);
600 assert(tp->phy_version < RTL_GIGA_PHY_VER_G);
602 if (RTL_R8(PHYstatus) & LinkStatus)
603 tp->phy_link_down_cnt = 0;
605 tp->phy_link_down_cnt++;
606 if (tp->phy_link_down_cnt >= 12) {
609 // If link on 1000, perform phy reset.
610 reg = mdio_read(ioaddr, PHY_1000_CTRL_REG);
611 if (reg & PHY_Cap_1000_Full)
612 rtl8169_hw_phy_reset(dev);
614 tp->phy_link_down_cnt = 0;
618 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
621 static inline void rtl8169_delete_timer(struct net_device *dev)
623 struct rtl8169_private *tp = dev->priv;
624 struct timer_list *timer = &tp->timer;
626 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
627 (tp->phy_version >= RTL_GIGA_PHY_VER_G))
630 del_timer_sync(timer);
632 tp->phy_link_down_cnt = 0;
635 static inline void rtl8169_request_timer(struct net_device *dev)
637 struct rtl8169_private *tp = dev->priv;
638 struct timer_list *timer = &tp->timer;
640 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
641 (tp->phy_version >= RTL_GIGA_PHY_VER_G))
644 tp->phy_link_down_cnt = 0;
647 timer->expires = jiffies + RTL8169_PHY_TIMEOUT;
648 timer->data = (unsigned long)(dev);
649 timer->function = rtl8169_phy_timer;
654 rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
658 struct net_device *dev;
659 struct rtl8169_private *tp;
660 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
661 int rc, i, acpi_idle_state = 0, pm_cap;
664 assert(pdev != NULL);
665 assert(ioaddr_out != NULL);
670 // dev zeroed in alloc_etherdev
671 dev = alloc_etherdev(sizeof (*tp));
673 printk(KERN_ERR PFX "unable to alloc new ethernet\n");
677 SET_MODULE_OWNER(dev);
678 SET_NETDEV_DEV(dev, &pdev->dev);
681 // enable device (incl. PCI PM wakeup and hotplug setup)
682 rc = pci_enable_device(pdev);
684 printk(KERN_ERR PFX "%s: unable to enable device\n", pdev->slot_name);
688 /* save power state before pci_enable_device overwrites it */
689 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
693 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
694 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
696 printk(KERN_ERR PFX "Cannot find PowerManagement capability, aborting.\n");
697 goto err_out_free_res;
700 mmio_start = pci_resource_start(pdev, 1);
701 mmio_end = pci_resource_end(pdev, 1);
702 mmio_flags = pci_resource_flags(pdev, 1);
703 mmio_len = pci_resource_len(pdev, 1);
705 // make sure PCI base addr 1 is MMIO
706 if (!(mmio_flags & IORESOURCE_MEM)) {
708 "region #1 not an MMIO resource, aborting\n");
710 goto err_out_disable;
712 // check for weird/broken PCI region reporting
713 if (mmio_len < RTL_MIN_IO_SIZE) {
714 printk(KERN_ERR PFX "Invalid PCI region size(s), aborting\n");
716 goto err_out_disable;
719 rc = pci_request_regions(pdev, dev->name);
721 printk(KERN_ERR PFX "%s: Could not request regions.\n", pdev->slot_name);
722 goto err_out_disable;
725 tp->cp_cmd = PCIMulRW | RxChkSum;
727 if ((sizeof(dma_addr_t) > 32) &&
728 !pci_set_dma_mask(pdev, DMA_64BIT_MASK))
729 tp->cp_cmd |= PCIDAC;
731 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
733 printk(KERN_ERR PFX "DMA configuration failed.\n");
734 goto err_out_free_res;
739 // enable PCI bus-mastering
740 pci_set_master(pdev);
742 // ioremap MMIO region
743 ioaddr = ioremap(mmio_start, mmio_len);
744 if (ioaddr == NULL) {
745 printk(KERN_ERR PFX "cannot remap MMIO, aborting\n");
747 goto err_out_free_res;
750 // Soft reset the chip.
751 RTL_W8(ChipCmd, CmdReset);
753 // Check that the chip has finished the reset.
754 for (i = 1000; i > 0; i--) {
755 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
760 // Identify chip attached to board
761 rtl8169_get_mac_version(tp, ioaddr);
762 rtl8169_get_phy_version(tp, ioaddr);
764 rtl8169_print_mac_version(tp);
765 rtl8169_print_phy_version(tp);
767 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
768 if (tp->mac_version == rtl_chip_info[i].mac_version)
772 /* Unknown chip: assume array element #0, original RTL-8169 */
773 printk(KERN_DEBUG PFX
774 "PCI device %s: unknown chip version, assuming %s\n",
775 pci_name(pdev), rtl_chip_info[0].name);
780 *ioaddr_out = ioaddr;
785 pci_release_regions(pdev);
788 pci_disable_device(pdev);
796 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
798 struct net_device *dev = NULL;
799 struct rtl8169_private *tp = NULL;
801 static int board_idx = -1;
802 static int printed_version = 0;
804 int option = -1, Cap10_100 = 0, Cap1000 = 0;
806 assert(pdev != NULL);
811 if (!printed_version) {
812 printk(KERN_INFO RTL8169_DRIVER_NAME " loaded\n");
816 rc = rtl8169_init_board(pdev, &dev, &ioaddr);
821 assert(ioaddr != NULL);
825 // Get MAC address. FIXME: read EEPROM
826 for (i = 0; i < MAC_ADDR_LEN; i++)
827 dev->dev_addr[i] = RTL_R8(MAC0 + i);
829 dev->open = rtl8169_open;
830 dev->hard_start_xmit = rtl8169_start_xmit;
831 dev->get_stats = rtl8169_get_stats;
832 dev->ethtool_ops = &rtl8169_ethtool_ops;
833 dev->stop = rtl8169_close;
834 dev->tx_timeout = rtl8169_tx_timeout;
835 dev->set_multicast_list = rtl8169_set_rx_mode;
836 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
837 dev->irq = pdev->irq;
838 dev->base_addr = (unsigned long) ioaddr;
839 // dev->do_ioctl = mii_ioctl;
841 tp = dev->priv; // private data //
843 tp->mmio_addr = ioaddr;
845 spin_lock_init(&tp->lock);
847 rc = register_netdev(dev);
850 pci_release_regions(pdev);
851 pci_disable_device(pdev);
856 printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n", dev->name,
857 rtl_chip_info[tp->chipset].name);
859 pci_set_drvdata(pdev, dev);
861 printk(KERN_INFO "%s: %s at 0x%lx, "
862 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
865 rtl_chip_info[ent->driver_data].name,
867 dev->dev_addr[0], dev->dev_addr[1],
868 dev->dev_addr[2], dev->dev_addr[3],
869 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
871 rtl8169_hw_phy_config(dev);
873 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
876 if (tp->mac_version < RTL_GIGA_MAC_VER_E) {
877 dprintk("Set PCI Latency=0x40\n");
878 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
881 if (tp->mac_version == RTL_GIGA_MAC_VER_D) {
882 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
884 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
885 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
888 // if TBI is not endbled
889 if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
890 int val = mdio_read(ioaddr, PHY_AUTO_NEGO_REG);
892 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
893 // Force RTL8169 in 10/100/1000 Full/Half mode.
895 printk(KERN_INFO "%s: Force-mode Enabled.\n",
897 Cap10_100 = 0, Cap1000 = 0;
900 Cap10_100 = PHY_Cap_10_Half_Or_Less;
901 Cap1000 = PHY_Cap_Null;
904 Cap10_100 = PHY_Cap_10_Full_Or_Less;
905 Cap1000 = PHY_Cap_Null;
908 Cap10_100 = PHY_Cap_100_Half_Or_Less;
909 Cap1000 = PHY_Cap_Null;
912 Cap10_100 = PHY_Cap_100_Full_Or_Less;
913 Cap1000 = PHY_Cap_Null;
916 Cap10_100 = PHY_Cap_100_Full_Or_Less;
917 Cap1000 = PHY_Cap_1000_Full;
922 mdio_write(ioaddr, PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); //leave PHY_AUTO_NEGO_REG bit4:0 unchanged
923 mdio_write(ioaddr, PHY_1000_CTRL_REG, Cap1000);
925 printk(KERN_INFO "%s: Auto-negotiation Enabled.\n",
928 // enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged
929 mdio_write(ioaddr, PHY_AUTO_NEGO_REG,
930 PHY_Cap_100_Full_Or_Less | (val & 0x1f));
932 // enable 1000 Full Mode
933 mdio_write(ioaddr, PHY_1000_CTRL_REG,
938 // Enable auto-negotiation and restart auto-nigotiation
939 mdio_write(ioaddr, PHY_CTRL_REG,
940 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
943 // wait for auto-negotiation process
944 for (i = 10000; i > 0; i--) {
945 //check if auto-negotiation complete
946 if (mdio_read(ioaddr, PHY_STAT_REG) &
947 PHY_Auto_Neco_Comp) {
949 option = RTL_R8(PHYstatus);
950 if (option & _1000bpsF) {
952 "%s: 1000Mbps Full-duplex operation.\n",
956 "%s: %sMbps %s-duplex operation.\n",
958 (option & _100bps) ? "100" :
960 (option & FullDup) ? "Full" :
967 } // end for-loop to wait for auto-negotiation process
972 "%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
974 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
981 static void __devexit
982 rtl8169_remove_one(struct pci_dev *pdev)
984 struct net_device *dev = pci_get_drvdata(pdev);
985 struct rtl8169_private *tp = dev->priv;
990 unregister_netdev(dev);
991 iounmap(tp->mmio_addr);
992 pci_release_regions(pdev);
994 pci_disable_device(pdev);
996 pci_set_drvdata(pdev, NULL);
1001 static int rtl8169_suspend(struct pci_dev *pdev, u32 state)
1003 struct net_device *dev = pci_get_drvdata(pdev);
1004 struct rtl8169_private *tp = dev->priv;
1005 void *ioaddr = tp->mmio_addr;
1006 unsigned long flags;
1008 if (!netif_running(dev))
1011 netif_device_detach(dev);
1012 netif_stop_queue(dev);
1013 spin_lock_irqsave(&tp->lock, flags);
1015 /* Disable interrupts, stop Rx and Tx */
1016 RTL_W16(IntrMask, 0);
1019 /* Update the error counts. */
1020 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
1021 RTL_W32(RxMissed, 0);
1022 spin_unlock_irqrestore(&tp->lock, flags);
1027 static int rtl8169_resume(struct pci_dev *pdev)
1029 struct net_device *dev = pci_get_drvdata(pdev);
1031 if (!netif_running(dev))
1034 netif_device_attach(dev);
1035 rtl8169_hw_start(dev);
1040 #endif /* CONFIG_PM */
1043 rtl8169_open(struct net_device *dev)
1045 struct rtl8169_private *tp = dev->priv;
1046 struct pci_dev *pdev = tp->pci_dev;
1050 request_irq(dev->irq, rtl8169_interrupt, SA_SHIRQ, dev->name, dev);
1057 * Rx and Tx desscriptors needs 256 bytes alignment.
1058 * pci_alloc_consistent provides more.
1060 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1062 if (!tp->TxDescArray)
1065 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1067 if (!tp->RxDescArray)
1070 retval = rtl8169_init_ring(dev);
1074 rtl8169_hw_start(dev);
1076 rtl8169_request_timer(dev);
1081 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1084 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1087 free_irq(dev->irq, dev);
1092 rtl8169_hw_start(struct net_device *dev)
1094 struct rtl8169_private *tp = dev->priv;
1095 void *ioaddr = tp->mmio_addr;
1098 /* Soft reset the chip. */
1099 RTL_W8(ChipCmd, CmdReset);
1101 /* Check that the chip has finished the reset. */
1102 for (i = 1000; i > 0; i--) {
1103 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1109 RTL_W8(Cfg9346, Cfg9346_Unlock);
1110 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1111 RTL_W8(EarlyTxThres, EarlyTxThld);
1113 // For gigabit rtl8169
1114 RTL_W16(RxMaxSize, RxPacketMaxSize);
1116 // Set Rx Config register
1117 i = rtl8169_rx_config | (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].
1119 RTL_W32(RxConfig, i);
1121 /* Set DMA burst size and Interframe Gap Time */
1123 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
1124 TxInterFrameGapShift));
1125 tp->cp_cmd |= RTL_R16(CPlusCmd);
1126 RTL_W16(CPlusCmd, tp->cp_cmd);
1128 if (tp->mac_version == RTL_GIGA_MAC_VER_D) {
1129 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14 MUST be 1\n");
1130 tp->cp_cmd |= (1 << 14) | PCIMulRW;
1131 RTL_W16(CPlusCmd, tp->cp_cmd);
1136 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1137 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
1138 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1139 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
1140 RTL_W8(Cfg9346, Cfg9346_Lock);
1143 RTL_W32(RxMissed, 0);
1145 rtl8169_set_rx_mode(dev);
1147 /* no early-rx interrupts */
1148 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1150 /* Enable all known interrupts by setting the interrupt mask. */
1151 RTL_W16(IntrMask, rtl8169_intr_mask);
1153 netif_start_queue(dev);
1157 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
1159 desc->addr = 0x0badbadbadbadbad;
1160 desc->status &= ~cpu_to_le32(OWNbit | RsvdMask);
1163 static void rtl8169_free_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
1164 struct RxDesc *desc)
1166 pci_unmap_single(pdev, le64_to_cpu(desc->addr), RX_BUF_SIZE,
1167 PCI_DMA_FROMDEVICE);
1168 dev_kfree_skb(*sk_buff);
1170 rtl8169_make_unusable_by_asic(desc);
1173 static inline void rtl8169_return_to_asic(struct RxDesc *desc)
1175 desc->status |= cpu_to_le32(OWNbit + RX_BUF_SIZE);
1178 static inline void rtl8169_give_to_asic(struct RxDesc *desc, dma_addr_t mapping)
1180 desc->addr = cpu_to_le64(mapping);
1181 desc->status |= cpu_to_le32(OWNbit + RX_BUF_SIZE);
1184 static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct net_device *dev,
1185 struct sk_buff **sk_buff, struct RxDesc *desc)
1187 struct sk_buff *skb;
1191 skb = dev_alloc_skb(RX_BUF_SIZE);
1196 skb_reserve(skb, 2);
1199 mapping = pci_map_single(pdev, skb->tail, RX_BUF_SIZE,
1200 PCI_DMA_FROMDEVICE);
1202 rtl8169_give_to_asic(desc, mapping);
1209 rtl8169_make_unusable_by_asic(desc);
1213 static void rtl8169_rx_clear(struct rtl8169_private *tp)
1217 for (i = 0; i < NUM_RX_DESC; i++) {
1218 if (tp->Rx_skbuff[i]) {
1219 rtl8169_free_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
1220 tp->RxDescArray + i);
1225 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
1230 for (cur = start; end - cur > 0; cur++) {
1231 int ret, i = cur % NUM_RX_DESC;
1233 if (tp->Rx_skbuff[i])
1236 ret = rtl8169_alloc_rx_skb(tp->pci_dev, dev, tp->Rx_skbuff + i,
1237 tp->RxDescArray + i);
1244 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1246 desc->status |= cpu_to_le32(EORbit);
1249 static int rtl8169_init_ring(struct net_device *dev)
1251 struct rtl8169_private *tp = dev->priv;
1253 tp->cur_rx = tp->dirty_rx = 0;
1254 tp->cur_tx = tp->dirty_tx = 0;
1255 memset(tp->TxDescArray, 0x0, NUM_TX_DESC * sizeof (struct TxDesc));
1256 memset(tp->RxDescArray, 0x0, NUM_RX_DESC * sizeof (struct RxDesc));
1258 memset(tp->Tx_skbuff, 0x0, NUM_TX_DESC * sizeof(struct sk_buff *));
1259 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
1261 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
1264 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
1269 rtl8169_rx_clear(tp);
1273 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
1274 struct TxDesc *desc)
1276 u32 len = sk_buff[0]->len;
1278 pci_unmap_single(pdev, le64_to_cpu(desc->addr),
1279 len < ETH_ZLEN ? ETH_ZLEN : len, PCI_DMA_TODEVICE);
1285 rtl8169_tx_clear(struct rtl8169_private *tp)
1290 for (i = 0; i < NUM_TX_DESC; i++) {
1291 struct sk_buff *skb = tp->Tx_skbuff[i];
1294 rtl8169_unmap_tx_skb(tp->pci_dev, tp->Tx_skbuff + i,
1295 tp->TxDescArray + i);
1297 tp->stats.tx_dropped++;
1303 rtl8169_tx_timeout(struct net_device *dev)
1305 struct rtl8169_private *tp = dev->priv;
1306 void *ioaddr = tp->mmio_addr;
1309 /* disable Tx, if not already */
1310 tmp8 = RTL_R8(ChipCmd);
1311 if (tmp8 & CmdTxEnb)
1312 RTL_W8(ChipCmd, tmp8 & ~CmdTxEnb);
1314 /* Disable interrupts by clearing the interrupt mask. */
1315 RTL_W16(IntrMask, 0x0000);
1317 /* Stop a shared interrupt from scavenging while we are. */
1318 spin_lock_irq(&tp->lock);
1319 rtl8169_tx_clear(tp);
1320 spin_unlock_irq(&tp->lock);
1322 /* ...and finally, reset everything */
1323 rtl8169_hw_start(dev);
1325 netif_wake_queue(dev);
1329 rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
1331 struct rtl8169_private *tp = dev->priv;
1332 void *ioaddr = tp->mmio_addr;
1333 int entry = tp->cur_tx % NUM_TX_DESC;
1336 if (unlikely(skb->len < ETH_ZLEN)) {
1337 skb = skb_padto(skb, ETH_ZLEN);
1339 goto err_update_stats;
1343 spin_lock_irq(&tp->lock);
1345 if (!(le32_to_cpu(tp->TxDescArray[entry].status) & OWNbit)) {
1348 mapping = pci_map_single(tp->pci_dev, skb->data, len,
1351 tp->Tx_skbuff[entry] = skb;
1352 tp->TxDescArray[entry].addr = cpu_to_le64(mapping);
1354 tp->TxDescArray[entry].status = cpu_to_le32(OWNbit | FSbit |
1355 LSbit | len | (EORbit * !((entry + 1) % NUM_TX_DESC)));
1357 RTL_W8(TxPoll, 0x40); //set polling bit
1359 dev->trans_start = jiffies;
1366 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx) {
1367 netif_stop_queue(dev);
1370 spin_unlock_irq(&tp->lock);
1377 tp->stats.tx_dropped++;
1382 rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
1385 unsigned long dirty_tx, tx_left;
1387 assert(dev != NULL);
1389 assert(ioaddr != NULL);
1391 dirty_tx = tp->dirty_tx;
1392 tx_left = tp->cur_tx - dirty_tx;
1394 while (tx_left > 0) {
1395 int entry = dirty_tx % NUM_TX_DESC;
1396 struct sk_buff *skb = tp->Tx_skbuff[entry];
1400 status = le32_to_cpu(tp->TxDescArray[entry].status);
1401 if (status & OWNbit)
1404 /* FIXME: is it really accurate for TxErr ? */
1405 tp->stats.tx_bytes += skb->len >= ETH_ZLEN ?
1406 skb->len : ETH_ZLEN;
1407 tp->stats.tx_packets++;
1408 rtl8169_unmap_tx_skb(tp->pci_dev, tp->Tx_skbuff + entry,
1409 tp->TxDescArray + entry);
1410 dev_kfree_skb_irq(skb);
1411 tp->Tx_skbuff[entry] = NULL;
1416 if (tp->dirty_tx != dirty_tx) {
1417 tp->dirty_tx = dirty_tx;
1418 if (netif_queue_stopped(dev))
1419 netif_wake_queue(dev);
1423 static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
1424 struct RxDesc *desc,
1425 struct net_device *dev)
1429 if (pkt_size < rx_copybreak) {
1430 struct sk_buff *skb;
1432 skb = dev_alloc_skb(pkt_size + 2);
1435 skb_reserve(skb, 2);
1436 eth_copy_and_sum(skb, sk_buff[0]->tail, pkt_size, 0);
1438 rtl8169_return_to_asic(desc);
1446 rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
1449 unsigned long cur_rx, rx_left;
1452 assert(dev != NULL);
1454 assert(ioaddr != NULL);
1456 cur_rx = tp->cur_rx;
1457 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
1459 while (rx_left > 0) {
1460 int entry = cur_rx % NUM_RX_DESC;
1464 status = le32_to_cpu(tp->RxDescArray[entry].status);
1466 if (status & OWNbit)
1468 if (status & RxRES) {
1469 printk(KERN_INFO "%s: Rx ERROR!!!\n", dev->name);
1470 tp->stats.rx_errors++;
1471 if (status & (RxRWT | RxRUNT))
1472 tp->stats.rx_length_errors++;
1474 tp->stats.rx_crc_errors++;
1476 struct RxDesc *desc = tp->RxDescArray + entry;
1477 struct sk_buff *skb = tp->Rx_skbuff[entry];
1478 int pkt_size = (status & 0x00001FFF) - 4;
1479 void (*pci_action)(struct pci_dev *, dma_addr_t,
1480 size_t, int) = pci_dma_sync_single_for_device;
1483 pci_dma_sync_single_for_cpu(tp->pci_dev,
1484 le64_to_cpu(desc->addr), RX_BUF_SIZE,
1485 PCI_DMA_FROMDEVICE);
1487 if (rtl8169_try_rx_copy(&skb, pkt_size, desc, dev)) {
1488 pci_action = pci_unmap_single;
1489 tp->Rx_skbuff[entry] = NULL;
1492 pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
1493 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1495 skb_put(skb, pkt_size);
1496 skb->protocol = eth_type_trans(skb, dev);
1499 dev->last_rx = jiffies;
1500 tp->stats.rx_bytes += pkt_size;
1501 tp->stats.rx_packets++;
1508 tp->cur_rx = cur_rx;
1510 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
1512 tp->dirty_rx += delta;
1514 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
1517 * FIXME: until there is periodic timer to try and refill the ring,
1518 * a temporary shortage may definitely kill the Rx process.
1519 * - disable the asic to try and avoid an overflow and kick it again
1521 * - how do others driver handle this condition (Uh oh...).
1523 if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
1524 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
1527 /* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
1529 rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1531 struct net_device *dev = (struct net_device *) dev_instance;
1532 struct rtl8169_private *tp = dev->priv;
1533 int boguscnt = max_interrupt_work;
1534 void *ioaddr = tp->mmio_addr;
1539 status = RTL_R16(IntrStatus);
1541 /* hotplug/major error/no more work/shared irq */
1542 if ((status == 0xFFFF) || !status)
1547 if (status & RxUnderrun)
1548 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
1551 (status & RxFIFOOver) ? (status | RxOverflow) : status);
1553 if (!(status & rtl8169_intr_mask))
1557 if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver)) {
1558 rtl8169_rx_interrupt(dev, tp, ioaddr);
1561 if (status & (TxOK | TxErr)) {
1562 spin_lock(&tp->lock);
1563 rtl8169_tx_interrupt(dev, tp, ioaddr);
1564 spin_unlock(&tp->lock);
1568 } while (boguscnt > 0);
1570 if (boguscnt <= 0) {
1571 printk(KERN_WARNING "%s: Too much work at interrupt!\n",
1573 /* Clear all interrupt sources. */
1574 RTL_W16(IntrStatus, 0xffff);
1576 return IRQ_RETVAL(handled);
1580 rtl8169_close(struct net_device *dev)
1582 struct rtl8169_private *tp = dev->priv;
1583 struct pci_dev *pdev = tp->pci_dev;
1584 void *ioaddr = tp->mmio_addr;
1586 netif_stop_queue(dev);
1588 rtl8169_delete_timer(dev);
1590 spin_lock_irq(&tp->lock);
1592 /* Stop the chip's Tx and Rx DMA processes. */
1593 RTL_W8(ChipCmd, 0x00);
1595 /* Disable interrupts by clearing the interrupt mask. */
1596 RTL_W16(IntrMask, 0x0000);
1598 /* Update the error counts. */
1599 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
1600 RTL_W32(RxMissed, 0);
1602 spin_unlock_irq(&tp->lock);
1604 synchronize_irq(dev->irq);
1605 free_irq(dev->irq, dev);
1607 rtl8169_tx_clear(tp);
1609 rtl8169_rx_clear(tp);
1611 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1613 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1615 tp->TxDescArray = NULL;
1616 tp->RxDescArray = NULL;
1622 rtl8169_set_rx_mode(struct net_device *dev)
1624 struct rtl8169_private *tp = dev->priv;
1625 void *ioaddr = tp->mmio_addr;
1626 unsigned long flags;
1627 u32 mc_filter[2]; /* Multicast hash filter */
1631 if (dev->flags & IFF_PROMISC) {
1632 /* Unconditionally log net taps. */
1633 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
1636 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1638 mc_filter[1] = mc_filter[0] = 0xffffffff;
1639 } else if ((dev->mc_count > multicast_filter_limit)
1640 || (dev->flags & IFF_ALLMULTI)) {
1641 /* Too many to filter perfectly -- accept all multicasts. */
1642 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1643 mc_filter[1] = mc_filter[0] = 0xffffffff;
1645 struct dev_mc_list *mclist;
1646 rx_mode = AcceptBroadcast | AcceptMyPhys;
1647 mc_filter[1] = mc_filter[0] = 0;
1648 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1649 i++, mclist = mclist->next) {
1650 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1651 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1652 rx_mode |= AcceptMulticast;
1656 spin_lock_irqsave(&tp->lock, flags);
1659 rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
1660 rtl_chip_info[tp->chipset].
1663 RTL_W32(RxConfig, tmp);
1664 RTL_W32(MAR0 + 0, mc_filter[0]);
1665 RTL_W32(MAR0 + 4, mc_filter[1]);
1667 spin_unlock_irqrestore(&tp->lock, flags);
1671 * rtl8169_get_stats - Get rtl8169 read/write statistics
1672 * @dev: The Ethernet Device to get statistics for
1674 * Get TX/RX statistics for rtl8169
1676 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
1678 struct rtl8169_private *tp = dev->priv;
1679 void *ioaddr = tp->mmio_addr;
1680 unsigned long flags;
1682 if (netif_running(dev)) {
1683 spin_lock_irqsave(&tp->lock, flags);
1684 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
1685 RTL_W32(RxMissed, 0);
1686 spin_unlock_irqrestore(&tp->lock, flags);
1692 static struct pci_driver rtl8169_pci_driver = {
1694 .id_table = rtl8169_pci_tbl,
1695 .probe = rtl8169_init_one,
1696 .remove = __devexit_p(rtl8169_remove_one),
1698 .suspend = rtl8169_suspend,
1699 .resume = rtl8169_resume,
1704 rtl8169_init_module(void)
1706 return pci_module_init(&rtl8169_pci_driver);
1710 rtl8169_cleanup_module(void)
1712 pci_unregister_driver(&rtl8169_pci_driver);
1715 module_init(rtl8169_init_module);
1716 module_exit(rtl8169_cleanup_module);