1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
3 * Copyright(c) 2002-2005 S2IO Technologies
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
29 * rx_ring_num : This can be used to program the number of receive rings used
31 * rx_ring_len: This defines the number of descriptors each ring can have. This
32 * is also an array of size 8.
33 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
34 * tx_fifo_len: This too is an array of 8. Each element defines the number of
35 * Tx descriptors that can be associated with each corresponding FIFO.
36 * in PCI Configuration space.
37 ************************************************************************/
39 #include<linux/config.h>
40 #include<linux/module.h>
41 #include<linux/types.h>
42 #include<linux/errno.h>
43 #include<linux/ioport.h>
45 #include<linux/kernel.h>
46 #include<linux/netdevice.h>
47 #include<linux/etherdevice.h>
48 #include<linux/skbuff.h>
49 #include<linux/init.h>
50 #include<linux/delay.h>
51 #include<linux/stddef.h>
52 #include<linux/ioctl.h>
53 #include<linux/timex.h>
54 #include<linux/sched.h>
55 #include<linux/ethtool.h>
56 #include<asm/system.h>
57 #include<asm/uaccess.h>
58 #include<linux/version.h>
60 #include<linux/workqueue.h>
64 #include "s2io-regs.h"
66 /* S2io Driver name & version. */
67 static char s2io_driver_name[] = "s2io";
68 static char s2io_driver_version[] = "Version 1.7.5.1";
71 * Cards with following subsystem_id have a link state indication
72 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
73 * macro below identifies these cards given the subsystem_id.
75 #define CARDS_WITH_FAULTY_LINK_INDICATORS(subid) \
76 (((subid >= 0x600B) && (subid <= 0x600D)) || \
77 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0
79 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
80 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
81 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
84 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
87 if ((sp->pkt_cnt[ring] - rxb_size) > 16) {
89 if ((sp->pkt_cnt[ring] - rxb_size) < MAX_RXDS_PER_BLOCK) {
97 /* Ethtool related variables and Macros. */
98 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
99 "Register test\t(offline)",
100 "Eeprom test\t(offline)",
101 "Link test\t(online)",
102 "RLDRAM test\t(offline)",
103 "BIST Test\t(offline)"
106 static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
108 {"tmac_data_octets"},
112 {"tmac_pause_ctrl_frms"},
113 {"tmac_any_err_frms"},
114 {"tmac_vld_ip_octets"},
122 {"rmac_data_octets"},
123 {"rmac_fcs_err_frms"},
125 {"rmac_vld_mcst_frms"},
126 {"rmac_vld_bcst_frms"},
127 {"rmac_in_rng_len_err_frms"},
129 {"rmac_pause_ctrl_frms"},
130 {"rmac_discarded_frms"},
131 {"rmac_usized_frms"},
132 {"rmac_osized_frms"},
134 {"rmac_jabber_frms"},
142 {"rmac_err_drp_udp"},
144 {"rmac_accepted_ip"},
148 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
149 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
151 #define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
152 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
156 * Constants to be programmed into the Xena's registers, to configure
160 #define SWITCH_SIGN 0xA5A5A5A5A5A5A5A5ULL
163 static u64 default_mdio_cfg[] = {
165 0xC001010000000000ULL, 0xC0010100000000E0ULL,
166 0xC0010100008000E4ULL,
167 /* Remove Reset from PMA PLL */
168 0xC001010000000000ULL, 0xC0010100000000E0ULL,
169 0xC0010100000000E4ULL,
173 static u64 default_dtx_cfg[] = {
174 0x8000051500000000ULL, 0x80000515000000E0ULL,
175 0x80000515D93500E4ULL, 0x8001051500000000ULL,
176 0x80010515000000E0ULL, 0x80010515001E00E4ULL,
177 0x8002051500000000ULL, 0x80020515000000E0ULL,
178 0x80020515F21000E4ULL,
179 /* Set PADLOOPBACKN */
180 0x8002051500000000ULL, 0x80020515000000E0ULL,
181 0x80020515B20000E4ULL, 0x8003051500000000ULL,
182 0x80030515000000E0ULL, 0x80030515B20000E4ULL,
183 0x8004051500000000ULL, 0x80040515000000E0ULL,
184 0x80040515B20000E4ULL, 0x8005051500000000ULL,
185 0x80050515000000E0ULL, 0x80050515B20000E4ULL,
187 /* Remove PADLOOPBACKN */
188 0x8002051500000000ULL, 0x80020515000000E0ULL,
189 0x80020515F20000E4ULL, 0x8003051500000000ULL,
190 0x80030515000000E0ULL, 0x80030515F20000E4ULL,
191 0x8004051500000000ULL, 0x80040515000000E0ULL,
192 0x80040515F20000E4ULL, 0x8005051500000000ULL,
193 0x80050515000000E0ULL, 0x80050515F20000E4ULL,
199 * Constants for Fixing the MacAddress problem seen mostly on
202 static u64 fix_mac[] = {
203 0x0060000000000000ULL, 0x0060600000000000ULL,
204 0x0040600000000000ULL, 0x0000600000000000ULL,
205 0x0020600000000000ULL, 0x0060600000000000ULL,
206 0x0020600000000000ULL, 0x0060600000000000ULL,
207 0x0020600000000000ULL, 0x0060600000000000ULL,
208 0x0020600000000000ULL, 0x0060600000000000ULL,
209 0x0020600000000000ULL, 0x0060600000000000ULL,
210 0x0020600000000000ULL, 0x0060600000000000ULL,
211 0x0020600000000000ULL, 0x0060600000000000ULL,
212 0x0020600000000000ULL, 0x0060600000000000ULL,
213 0x0020600000000000ULL, 0x0060600000000000ULL,
214 0x0020600000000000ULL, 0x0060600000000000ULL,
215 0x0020600000000000ULL, 0x0000600000000000ULL,
216 0x0040600000000000ULL, 0x0060600000000000ULL,
220 /* Module Loadable parameters. */
221 static unsigned int tx_fifo_num = 1;
222 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
223 {[0 ...(MAX_TX_FIFOS - 1)] = 0 };
224 static unsigned int rx_ring_num = 1;
225 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
226 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
227 static unsigned int Stats_refresh_time = 4;
228 static unsigned int rmac_pause_time = 65535;
229 static unsigned int mc_pause_threshold_q0q3 = 187;
230 static unsigned int mc_pause_threshold_q4q7 = 187;
231 static unsigned int shared_splits;
232 static unsigned int tmac_util_period = 5;
233 static unsigned int rmac_util_period = 5;
234 #ifndef CONFIG_S2IO_NAPI
235 static unsigned int indicate_max_pkts;
240 * This table lists all the devices that this driver supports.
242 static struct pci_device_id s2io_tbl[] __devinitdata = {
243 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
244 PCI_ANY_ID, PCI_ANY_ID},
245 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
246 PCI_ANY_ID, PCI_ANY_ID},
250 MODULE_DEVICE_TABLE(pci, s2io_tbl);
252 static struct pci_driver s2io_driver = {
254 .id_table = s2io_tbl,
255 .probe = s2io_init_nic,
256 .remove = __devexit_p(s2io_rem_nic),
259 /* A simplifier macro used both by init and free shared_mem Fns(). */
260 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
263 * init_shared_mem - Allocation and Initialization of Memory
264 * @nic: Device private variable.
265 * Description: The function allocates all the memory areas shared
266 * between the NIC and the driver. This includes Tx descriptors,
267 * Rx descriptors and the statistics block.
270 static int init_shared_mem(struct s2io_nic *nic)
273 void *tmp_v_addr, *tmp_v_addr_next;
274 dma_addr_t tmp_p_addr, tmp_p_addr_next;
275 RxD_block_t *pre_rxd_blk = NULL;
277 int lst_size, lst_per_page;
278 struct net_device *dev = nic->dev;
279 #ifdef CONFIG_2BUFF_MODE
284 mac_info_t *mac_control;
285 struct config_param *config;
287 mac_control = &nic->mac_control;
288 config = &nic->config;
291 /* Allocation and initialization of TXDLs in FIOFs */
293 for (i = 0; i < config->tx_fifo_num; i++) {
294 size += config->tx_cfg[i].fifo_len;
296 if (size > MAX_AVAILABLE_TXDS) {
297 DBG_PRINT(ERR_DBG, "%s: Total number of Tx FIFOs ",
299 DBG_PRINT(ERR_DBG, "exceeds the maximum value ");
300 DBG_PRINT(ERR_DBG, "that can be used\n");
304 lst_size = (sizeof(TxD_t) * config->max_txds);
305 lst_per_page = PAGE_SIZE / lst_size;
307 for (i = 0; i < config->tx_fifo_num; i++) {
308 int fifo_len = config->tx_cfg[i].fifo_len;
309 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
310 nic->list_info[i] = kmalloc(list_holder_size, GFP_KERNEL);
311 if (!nic->list_info[i]) {
313 "Malloc failed for list_info\n");
316 memset(nic->list_info[i], 0, list_holder_size);
318 for (i = 0; i < config->tx_fifo_num; i++) {
319 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
321 mac_control->tx_curr_put_info[i].offset = 0;
322 mac_control->tx_curr_put_info[i].fifo_len =
323 config->tx_cfg[i].fifo_len - 1;
324 mac_control->tx_curr_get_info[i].offset = 0;
325 mac_control->tx_curr_get_info[i].fifo_len =
326 config->tx_cfg[i].fifo_len - 1;
327 for (j = 0; j < page_num; j++) {
331 tmp_v = pci_alloc_consistent(nic->pdev,
335 "pci_alloc_consistent ");
336 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
339 while (k < lst_per_page) {
340 int l = (j * lst_per_page) + k;
341 if (l == config->tx_cfg[i].fifo_len)
343 nic->list_info[i][l].list_virt_addr =
344 tmp_v + (k * lst_size);
345 nic->list_info[i][l].list_phy_addr =
346 tmp_p + (k * lst_size);
353 /* Allocation and initialization of RXDs in Rings */
355 for (i = 0; i < config->rx_ring_num; i++) {
356 if (config->rx_cfg[i].num_rxd % (MAX_RXDS_PER_BLOCK + 1)) {
357 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
358 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
360 DBG_PRINT(ERR_DBG, "RxDs per Block");
363 size += config->rx_cfg[i].num_rxd;
364 nic->block_count[i] =
365 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
367 config->rx_cfg[i].num_rxd - nic->block_count[i];
370 for (i = 0; i < config->rx_ring_num; i++) {
371 mac_control->rx_curr_get_info[i].block_index = 0;
372 mac_control->rx_curr_get_info[i].offset = 0;
373 mac_control->rx_curr_get_info[i].ring_len =
374 config->rx_cfg[i].num_rxd - 1;
375 mac_control->rx_curr_put_info[i].block_index = 0;
376 mac_control->rx_curr_put_info[i].offset = 0;
377 mac_control->rx_curr_put_info[i].ring_len =
378 config->rx_cfg[i].num_rxd - 1;
380 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
381 /* Allocating all the Rx blocks */
382 for (j = 0; j < blk_cnt; j++) {
383 #ifndef CONFIG_2BUFF_MODE
384 size = (MAX_RXDS_PER_BLOCK + 1) * (sizeof(RxD_t));
386 size = SIZE_OF_BLOCK;
388 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
390 if (tmp_v_addr == NULL) {
392 * In case of failure, free_shared_mem()
393 * is called, which should free any
394 * memory that was alloced till the
397 nic->rx_blocks[i][j].block_virt_addr =
401 memset(tmp_v_addr, 0, size);
402 nic->rx_blocks[i][j].block_virt_addr = tmp_v_addr;
403 nic->rx_blocks[i][j].block_dma_addr = tmp_p_addr;
405 /* Interlinking all Rx Blocks */
406 for (j = 0; j < blk_cnt; j++) {
407 tmp_v_addr = nic->rx_blocks[i][j].block_virt_addr;
409 nic->rx_blocks[i][(j + 1) %
410 blk_cnt].block_virt_addr;
411 tmp_p_addr = nic->rx_blocks[i][j].block_dma_addr;
413 nic->rx_blocks[i][(j + 1) %
414 blk_cnt].block_dma_addr;
416 pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
417 pre_rxd_blk->reserved_1 = END_OF_BLOCK; /* last RxD
420 #ifndef CONFIG_2BUFF_MODE
421 pre_rxd_blk->reserved_2_pNext_RxD_block =
422 (unsigned long) tmp_v_addr_next;
424 pre_rxd_blk->pNext_RxD_Blk_physical =
425 (u64) tmp_p_addr_next;
429 #ifdef CONFIG_2BUFF_MODE
431 * Allocation of Storages for buffer addresses in 2BUFF mode
432 * and the buffers as well.
434 for (i = 0; i < config->rx_ring_num; i++) {
436 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
437 nic->ba[i] = kmalloc((sizeof(buffAdd_t *) * blk_cnt),
441 for (j = 0; j < blk_cnt; j++) {
443 nic->ba[i][j] = kmalloc((sizeof(buffAdd_t) *
444 (MAX_RXDS_PER_BLOCK + 1)),
448 while (k != MAX_RXDS_PER_BLOCK) {
449 ba = &nic->ba[i][j][k];
451 ba->ba_0_org = kmalloc
452 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
455 tmp = (unsigned long) ba->ba_0_org;
457 tmp &= ~((unsigned long) ALIGN_SIZE);
458 ba->ba_0 = (void *) tmp;
460 ba->ba_1_org = kmalloc
461 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
464 tmp = (unsigned long) ba->ba_1_org;
466 tmp &= ~((unsigned long) ALIGN_SIZE);
467 ba->ba_1 = (void *) tmp;
474 /* Allocation and initialization of Statistics block */
475 size = sizeof(StatInfo_t);
476 mac_control->stats_mem = pci_alloc_consistent
477 (nic->pdev, size, &mac_control->stats_mem_phy);
479 if (!mac_control->stats_mem) {
481 * In case of failure, free_shared_mem() is called, which
482 * should free any memory that was alloced till the
487 mac_control->stats_mem_sz = size;
489 tmp_v_addr = mac_control->stats_mem;
490 mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
491 memset(tmp_v_addr, 0, size);
493 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
494 (unsigned long long) tmp_p_addr);
500 * free_shared_mem - Free the allocated Memory
501 * @nic: Device private variable.
502 * Description: This function is to free all memory locations allocated by
503 * the init_shared_mem() function and return it to the kernel.
506 static void free_shared_mem(struct s2io_nic *nic)
508 int i, j, blk_cnt, size;
510 dma_addr_t tmp_p_addr;
511 mac_info_t *mac_control;
512 struct config_param *config;
513 int lst_size, lst_per_page;
519 mac_control = &nic->mac_control;
520 config = &nic->config;
522 lst_size = (sizeof(TxD_t) * config->max_txds);
523 lst_per_page = PAGE_SIZE / lst_size;
525 for (i = 0; i < config->tx_fifo_num; i++) {
526 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
528 for (j = 0; j < page_num; j++) {
529 int mem_blks = (j * lst_per_page);
530 if (!nic->list_info[i][mem_blks].list_virt_addr)
532 pci_free_consistent(nic->pdev, PAGE_SIZE,
533 nic->list_info[i][mem_blks].
535 nic->list_info[i][mem_blks].
538 kfree(nic->list_info[i]);
541 #ifndef CONFIG_2BUFF_MODE
542 size = (MAX_RXDS_PER_BLOCK + 1) * (sizeof(RxD_t));
544 size = SIZE_OF_BLOCK;
546 for (i = 0; i < config->rx_ring_num; i++) {
547 blk_cnt = nic->block_count[i];
548 for (j = 0; j < blk_cnt; j++) {
549 tmp_v_addr = nic->rx_blocks[i][j].block_virt_addr;
550 tmp_p_addr = nic->rx_blocks[i][j].block_dma_addr;
551 if (tmp_v_addr == NULL)
553 pci_free_consistent(nic->pdev, size,
554 tmp_v_addr, tmp_p_addr);
558 #ifdef CONFIG_2BUFF_MODE
559 /* Freeing buffer storage addresses in 2BUFF mode. */
560 for (i = 0; i < config->rx_ring_num; i++) {
562 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
565 for (j = 0; j < blk_cnt; j++) {
567 if (!nic->ba[i][j]) {
571 while (k != MAX_RXDS_PER_BLOCK) {
572 buffAdd_t *ba = &nic->ba[i][j][k];
573 if (!ba || !ba->ba_0_org || !ba->ba_1_org)
576 kfree(nic->ba[i][j]);
587 kfree(nic->ba[i][j]);
594 if (mac_control->stats_mem) {
595 pci_free_consistent(nic->pdev,
596 mac_control->stats_mem_sz,
597 mac_control->stats_mem,
598 mac_control->stats_mem_phy);
603 * init_nic - Initialization of hardware
604 * @nic: device peivate variable
605 * Description: The function sequentially configures every block
606 * of the H/W from their reset values.
607 * Return Value: SUCCESS on success and
608 * '-1' on failure (endian settings incorrect).
611 static int init_nic(struct s2io_nic *nic)
613 XENA_dev_config_t __iomem *bar0 = nic->bar0;
614 struct net_device *dev = nic->dev;
615 register u64 val64 = 0;
619 mac_info_t *mac_control;
620 struct config_param *config;
621 int mdio_cnt = 0, dtx_cnt = 0;
622 unsigned long long print_var, mem_share;
624 mac_control = &nic->mac_control;
625 config = &nic->config;
628 * Set proper endian settings and verify the same by
629 * reading the PIF Feed-back register.
633 * The device by default set to a big endian format, so
634 * a big endian driver need not set anything.
636 writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
637 val64 = (SWAPPER_CTRL_PIF_R_FE |
638 SWAPPER_CTRL_PIF_R_SE |
639 SWAPPER_CTRL_PIF_W_FE |
640 SWAPPER_CTRL_PIF_W_SE |
641 SWAPPER_CTRL_TXP_FE |
642 SWAPPER_CTRL_TXP_SE |
643 SWAPPER_CTRL_TXD_R_FE |
644 SWAPPER_CTRL_TXD_W_FE |
645 SWAPPER_CTRL_TXF_R_FE |
646 SWAPPER_CTRL_RXD_R_FE |
647 SWAPPER_CTRL_RXD_W_FE |
648 SWAPPER_CTRL_RXF_W_FE |
649 SWAPPER_CTRL_XMSI_FE |
650 SWAPPER_CTRL_XMSI_SE |
651 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
652 writeq(val64, &bar0->swapper_ctrl);
655 * Initially we enable all bits to make it accessible by
656 * the driver, then we selectively enable only those bits
657 * that we want to set.
659 writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
660 val64 = (SWAPPER_CTRL_PIF_R_FE |
661 SWAPPER_CTRL_PIF_R_SE |
662 SWAPPER_CTRL_PIF_W_FE |
663 SWAPPER_CTRL_PIF_W_SE |
664 SWAPPER_CTRL_TXP_FE |
665 SWAPPER_CTRL_TXP_SE |
666 SWAPPER_CTRL_TXD_R_FE |
667 SWAPPER_CTRL_TXD_R_SE |
668 SWAPPER_CTRL_TXD_W_FE |
669 SWAPPER_CTRL_TXD_W_SE |
670 SWAPPER_CTRL_TXF_R_FE |
671 SWAPPER_CTRL_RXD_R_FE |
672 SWAPPER_CTRL_RXD_R_SE |
673 SWAPPER_CTRL_RXD_W_FE |
674 SWAPPER_CTRL_RXD_W_SE |
675 SWAPPER_CTRL_RXF_W_FE |
676 SWAPPER_CTRL_XMSI_FE |
677 SWAPPER_CTRL_XMSI_SE |
678 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
679 writeq(val64, &bar0->swapper_ctrl);
683 * Verifying if endian settings are accurate by
684 * reading a feedback register.
686 val64 = readq(&bar0->pif_rd_swapper_fb);
687 if (val64 != 0x0123456789ABCDEFULL) {
688 /* Endian settings are incorrect, calls for another dekko. */
689 print_var = (unsigned long long) val64;
690 DBG_PRINT(INIT_DBG, "%s: Endian settings are wrong",
692 DBG_PRINT(ERR_DBG, ", feedback read %llx\n", print_var);
697 /* Remove XGXS from reset state */
699 writeq(val64, &bar0->sw_reset);
700 val64 = readq(&bar0->sw_reset);
701 set_current_state(TASK_UNINTERRUPTIBLE);
702 schedule_timeout(HZ / 2);
704 /* Enable Receiving broadcasts */
705 add = &bar0->mac_cfg;
706 val64 = readq(&bar0->mac_cfg);
707 val64 |= MAC_RMAC_BCAST_ENABLE;
708 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
709 writel((u32) val64, add);
710 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
711 writel((u32) (val64 >> 32), (add + 4));
713 /* Read registers in all blocks */
714 val64 = readq(&bar0->mac_int_mask);
715 val64 = readq(&bar0->mc_int_mask);
716 val64 = readq(&bar0->xgxs_int_mask);
720 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
723 * Configuring the XAUI Interface of Xena.
724 * ***************************************
725 * To Configure the Xena's XAUI, one has to write a series
726 * of 64 bit values into two registers in a particular
727 * sequence. Hence a macro 'SWITCH_SIGN' has been defined
728 * which will be defined in the array of configuration values
729 * (default_dtx_cfg & default_mdio_cfg) at appropriate places
730 * to switch writing from one regsiter to another. We continue
731 * writing these values until we encounter the 'END_SIGN' macro.
732 * For example, After making a series of 21 writes into
733 * dtx_control register the 'SWITCH_SIGN' appears and hence we
734 * start writing into mdio_control until we encounter END_SIGN.
738 while (default_dtx_cfg[dtx_cnt] != END_SIGN) {
739 if (default_dtx_cfg[dtx_cnt] == SWITCH_SIGN) {
743 SPECIAL_REG_WRITE(default_dtx_cfg[dtx_cnt],
744 &bar0->dtx_control, UF);
745 val64 = readq(&bar0->dtx_control);
749 while (default_mdio_cfg[mdio_cnt] != END_SIGN) {
750 if (default_mdio_cfg[mdio_cnt] == SWITCH_SIGN) {
754 SPECIAL_REG_WRITE(default_mdio_cfg[mdio_cnt],
755 &bar0->mdio_control, UF);
756 val64 = readq(&bar0->mdio_control);
759 if ((default_dtx_cfg[dtx_cnt] == END_SIGN) &&
760 (default_mdio_cfg[mdio_cnt] == END_SIGN)) {
767 /* Tx DMA Initialization */
769 writeq(val64, &bar0->tx_fifo_partition_0);
770 writeq(val64, &bar0->tx_fifo_partition_1);
771 writeq(val64, &bar0->tx_fifo_partition_2);
772 writeq(val64, &bar0->tx_fifo_partition_3);
775 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
777 vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
778 13) | vBIT(config->tx_cfg[i].fifo_priority,
781 if (i == (config->tx_fifo_num - 1)) {
788 writeq(val64, &bar0->tx_fifo_partition_0);
792 writeq(val64, &bar0->tx_fifo_partition_1);
796 writeq(val64, &bar0->tx_fifo_partition_2);
800 writeq(val64, &bar0->tx_fifo_partition_3);
805 /* Enable Tx FIFO partition 0. */
806 val64 = readq(&bar0->tx_fifo_partition_0);
807 val64 |= BIT(0); /* To enable the FIFO partition. */
808 writeq(val64, &bar0->tx_fifo_partition_0);
810 val64 = readq(&bar0->tx_fifo_partition_0);
811 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
812 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
815 * Initialization of Tx_PA_CONFIG register to ignore packet
816 * integrity checking.
818 val64 = readq(&bar0->tx_pa_cfg);
819 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
820 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
821 writeq(val64, &bar0->tx_pa_cfg);
823 /* Rx DMA intialization. */
825 for (i = 0; i < config->rx_ring_num; i++) {
827 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
830 writeq(val64, &bar0->rx_queue_priority);
833 * Allocating equal share of memory to all the
837 for (i = 0; i < config->rx_ring_num; i++) {
840 mem_share = (64 / config->rx_ring_num +
841 64 % config->rx_ring_num);
842 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
845 mem_share = (64 / config->rx_ring_num);
846 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
849 mem_share = (64 / config->rx_ring_num);
850 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
853 mem_share = (64 / config->rx_ring_num);
854 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
857 mem_share = (64 / config->rx_ring_num);
858 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
861 mem_share = (64 / config->rx_ring_num);
862 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
865 mem_share = (64 / config->rx_ring_num);
866 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
869 mem_share = (64 / config->rx_ring_num);
870 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
874 writeq(val64, &bar0->rx_queue_cfg);
877 * Initializing the Tx round robin registers to 0.
878 * Filling Tx and Rx round robin registers as per the
879 * number of FIFOs and Rings is still TODO.
881 writeq(0, &bar0->tx_w_round_robin_0);
882 writeq(0, &bar0->tx_w_round_robin_1);
883 writeq(0, &bar0->tx_w_round_robin_2);
884 writeq(0, &bar0->tx_w_round_robin_3);
885 writeq(0, &bar0->tx_w_round_robin_4);
889 * Disable Rx steering. Hard coding all packets be steered to
892 val64 = 0x8080808080808080ULL;
893 writeq(val64, &bar0->rts_qos_steering);
897 for (i = 1; i < 8; i++)
898 writeq(val64, &bar0->rts_frm_len_n[i]);
900 /* Set rts_frm_len register for fifo 0 */
901 writeq(MAC_RTS_FRM_LEN_SET(dev->mtu + 22),
902 &bar0->rts_frm_len_n[0]);
904 /* Enable statistics */
905 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
906 val64 = SET_UPDT_PERIOD(Stats_refresh_time) |
907 STAT_CFG_STAT_RO | STAT_CFG_STAT_EN;
908 writeq(val64, &bar0->stat_cfg);
911 * Initializing the sampling rate for the device to calculate the
912 * bandwidth utilization.
914 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
915 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
916 writeq(val64, &bar0->mac_link_util);
920 * Initializing the Transmit and Receive Traffic Interrupt
923 /* TTI Initialization */
924 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0xFFF) |
925 TTI_DATA1_MEM_TX_URNG_A(0xA) |
926 TTI_DATA1_MEM_TX_URNG_B(0x10) |
927 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
928 writeq(val64, &bar0->tti_data1_mem);
930 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
931 TTI_DATA2_MEM_TX_UFC_B(0x20) |
932 TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
933 writeq(val64, &bar0->tti_data2_mem);
935 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
936 writeq(val64, &bar0->tti_command_mem);
939 * Once the operation completes, the Strobe bit of the command
940 * register will be reset. We poll for this particular condition
941 * We wait for a maximum of 500ms for the operation to complete,
942 * if it's not complete by then we return error.
946 val64 = readq(&bar0->tti_command_mem);
947 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
951 DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
955 set_current_state(TASK_UNINTERRUPTIBLE);
956 schedule_timeout(HZ / 20);
960 /* RTI Initialization */
961 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF) |
962 RTI_DATA1_MEM_RX_URNG_A(0xA) |
963 RTI_DATA1_MEM_RX_URNG_B(0x10) |
964 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
966 writeq(val64, &bar0->rti_data1_mem);
968 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
969 RTI_DATA2_MEM_RX_UFC_B(0x2) |
970 RTI_DATA2_MEM_RX_UFC_C(0x40) | RTI_DATA2_MEM_RX_UFC_D(0x80);
971 writeq(val64, &bar0->rti_data2_mem);
973 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD;
974 writeq(val64, &bar0->rti_command_mem);
977 * Once the operation completes, the Strobe bit of the command
978 * register will be reset. We poll for this particular condition
979 * We wait for a maximum of 500ms for the operation to complete,
980 * if it's not complete by then we return error.
984 val64 = readq(&bar0->rti_command_mem);
985 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
989 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
994 set_current_state(TASK_UNINTERRUPTIBLE);
995 schedule_timeout(HZ / 20);
999 * Initializing proper values as Pause threshold into all
1000 * the 8 Queues on Rx side.
1002 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1003 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1005 /* Disable RMAC PAD STRIPPING */
1006 add = &bar0->mac_cfg;
1007 val64 = readq(&bar0->mac_cfg);
1008 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1009 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1010 writel((u32) (val64), add);
1011 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1012 writel((u32) (val64 >> 32), (add + 4));
1013 val64 = readq(&bar0->mac_cfg);
1016 * Set the time value to be inserted in the pause frame
1017 * generated by xena.
1019 val64 = readq(&bar0->rmac_pause_cfg);
1020 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1021 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1022 writeq(val64, &bar0->rmac_pause_cfg);
1025 * Set the Threshold Limit for Generating the pause frame
1026 * If the amount of data in any Queue exceeds ratio of
1027 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1028 * pause frame is generated
1031 for (i = 0; i < 4; i++) {
1033 (((u64) 0xFF00 | nic->mac_control.
1034 mc_pause_threshold_q0q3)
1037 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1040 for (i = 0; i < 4; i++) {
1042 (((u64) 0xFF00 | nic->mac_control.
1043 mc_pause_threshold_q4q7)
1046 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1049 * TxDMA will stop Read request if the number of read split has
1050 * exceeded the limit pointed by shared_splits
1052 val64 = readq(&bar0->pic_control);
1053 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1054 writeq(val64, &bar0->pic_control);
1060 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1061 * @nic: device private variable,
1062 * @mask: A mask indicating which Intr block must be modified and,
1063 * @flag: A flag indicating whether to enable or disable the Intrs.
1064 * Description: This function will either disable or enable the interrupts
1065 * depending on the flag argument. The mask argument can be used to
1066 * enable/disable any Intr block.
1067 * Return Value: NONE.
1070 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1072 XENA_dev_config_t __iomem *bar0 = nic->bar0;
1073 register u64 val64 = 0, temp64 = 0;
1075 /* Top level interrupt classification */
1076 /* PIC Interrupts */
1077 if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1078 /* Enable PIC Intrs in the general intr mask register */
1079 val64 = TXPIC_INT_M | PIC_RX_INT_M;
1080 if (flag == ENABLE_INTRS) {
1081 temp64 = readq(&bar0->general_int_mask);
1082 temp64 &= ~((u64) val64);
1083 writeq(temp64, &bar0->general_int_mask);
1085 * Disabled all PCIX, Flash, MDIO, IIC and GPIO
1086 * interrupts for now.
1089 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1091 * No MSI Support is available presently, so TTI and
1092 * RTI interrupts are also disabled.
1094 } else if (flag == DISABLE_INTRS) {
1096 * Disable PIC Intrs in the general
1097 * intr mask register
1099 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1100 temp64 = readq(&bar0->general_int_mask);
1102 writeq(val64, &bar0->general_int_mask);
1106 /* DMA Interrupts */
1107 /* Enabling/Disabling Tx DMA interrupts */
1108 if (mask & TX_DMA_INTR) {
1109 /* Enable TxDMA Intrs in the general intr mask register */
1110 val64 = TXDMA_INT_M;
1111 if (flag == ENABLE_INTRS) {
1112 temp64 = readq(&bar0->general_int_mask);
1113 temp64 &= ~((u64) val64);
1114 writeq(temp64, &bar0->general_int_mask);
1116 * Keep all interrupts other than PFC interrupt
1117 * and PCC interrupt disabled in DMA level.
1119 val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1121 writeq(val64, &bar0->txdma_int_mask);
1123 * Enable only the MISC error 1 interrupt in PFC block
1125 val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1126 writeq(val64, &bar0->pfc_err_mask);
1128 * Enable only the FB_ECC error interrupt in PCC block
1130 val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1131 writeq(val64, &bar0->pcc_err_mask);
1132 } else if (flag == DISABLE_INTRS) {
1134 * Disable TxDMA Intrs in the general intr mask
1137 writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1138 writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
1139 temp64 = readq(&bar0->general_int_mask);
1141 writeq(val64, &bar0->general_int_mask);
1145 /* Enabling/Disabling Rx DMA interrupts */
1146 if (mask & RX_DMA_INTR) {
1147 /* Enable RxDMA Intrs in the general intr mask register */
1148 val64 = RXDMA_INT_M;
1149 if (flag == ENABLE_INTRS) {
1150 temp64 = readq(&bar0->general_int_mask);
1151 temp64 &= ~((u64) val64);
1152 writeq(temp64, &bar0->general_int_mask);
1154 * All RxDMA block interrupts are disabled for now
1157 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1158 } else if (flag == DISABLE_INTRS) {
1160 * Disable RxDMA Intrs in the general intr mask
1163 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1164 temp64 = readq(&bar0->general_int_mask);
1166 writeq(val64, &bar0->general_int_mask);
1170 /* MAC Interrupts */
1171 /* Enabling/Disabling MAC interrupts */
1172 if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1173 val64 = TXMAC_INT_M | RXMAC_INT_M;
1174 if (flag == ENABLE_INTRS) {
1175 temp64 = readq(&bar0->general_int_mask);
1176 temp64 &= ~((u64) val64);
1177 writeq(temp64, &bar0->general_int_mask);
1179 * All MAC block error interrupts are disabled for now
1180 * except the link status change interrupt.
1183 val64 = MAC_INT_STATUS_RMAC_INT;
1184 temp64 = readq(&bar0->mac_int_mask);
1185 temp64 &= ~((u64) val64);
1186 writeq(temp64, &bar0->mac_int_mask);
1188 val64 = readq(&bar0->mac_rmac_err_mask);
1189 val64 &= ~((u64) RMAC_LINK_STATE_CHANGE_INT);
1190 writeq(val64, &bar0->mac_rmac_err_mask);
1191 } else if (flag == DISABLE_INTRS) {
1193 * Disable MAC Intrs in the general intr mask register
1195 writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1196 writeq(DISABLE_ALL_INTRS,
1197 &bar0->mac_rmac_err_mask);
1199 temp64 = readq(&bar0->general_int_mask);
1201 writeq(val64, &bar0->general_int_mask);
1205 /* XGXS Interrupts */
1206 if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
1207 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
1208 if (flag == ENABLE_INTRS) {
1209 temp64 = readq(&bar0->general_int_mask);
1210 temp64 &= ~((u64) val64);
1211 writeq(temp64, &bar0->general_int_mask);
1213 * All XGXS block error interrupts are disabled for now
1216 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1217 } else if (flag == DISABLE_INTRS) {
1219 * Disable MC Intrs in the general intr mask register
1221 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1222 temp64 = readq(&bar0->general_int_mask);
1224 writeq(val64, &bar0->general_int_mask);
1228 /* Memory Controller(MC) interrupts */
1229 if (mask & MC_INTR) {
1231 if (flag == ENABLE_INTRS) {
1232 temp64 = readq(&bar0->general_int_mask);
1233 temp64 &= ~((u64) val64);
1234 writeq(temp64, &bar0->general_int_mask);
1236 * All MC block error interrupts are disabled for now
1239 writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1240 } else if (flag == DISABLE_INTRS) {
1242 * Disable MC Intrs in the general intr mask register
1244 writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1245 temp64 = readq(&bar0->general_int_mask);
1247 writeq(val64, &bar0->general_int_mask);
1252 /* Tx traffic interrupts */
1253 if (mask & TX_TRAFFIC_INTR) {
1254 val64 = TXTRAFFIC_INT_M;
1255 if (flag == ENABLE_INTRS) {
1256 temp64 = readq(&bar0->general_int_mask);
1257 temp64 &= ~((u64) val64);
1258 writeq(temp64, &bar0->general_int_mask);
1260 * Enable all the Tx side interrupts
1261 * writing 0 Enables all 64 TX interrupt levels
1263 writeq(0x0, &bar0->tx_traffic_mask);
1264 } else if (flag == DISABLE_INTRS) {
1266 * Disable Tx Traffic Intrs in the general intr mask
1269 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1270 temp64 = readq(&bar0->general_int_mask);
1272 writeq(val64, &bar0->general_int_mask);
1276 /* Rx traffic interrupts */
1277 if (mask & RX_TRAFFIC_INTR) {
1278 val64 = RXTRAFFIC_INT_M;
1279 if (flag == ENABLE_INTRS) {
1280 temp64 = readq(&bar0->general_int_mask);
1281 temp64 &= ~((u64) val64);
1282 writeq(temp64, &bar0->general_int_mask);
1283 /* writing 0 Enables all 8 RX interrupt levels */
1284 writeq(0x0, &bar0->rx_traffic_mask);
1285 } else if (flag == DISABLE_INTRS) {
1287 * Disable Rx Traffic Intrs in the general intr mask
1290 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1291 temp64 = readq(&bar0->general_int_mask);
1293 writeq(val64, &bar0->general_int_mask);
1299 * verify_xena_quiescence - Checks whether the H/W is ready
1300 * @val64 : Value read from adapter status register.
1301 * @flag : indicates if the adapter enable bit was ever written once
1303 * Description: Returns whether the H/W is ready to go or not. Depending
1304 * on whether adapter enable bit was written or not the comparison
1305 * differs and the calling function passes the input argument flag to
1307 * Return: 1 If xena is quiescence
1308 * 0 If Xena is not quiescence
1311 static int verify_xena_quiescence(u64 val64, int flag)
1314 u64 tmp64 = ~((u64) val64);
1318 (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
1319 ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY |
1320 ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
1321 ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
1322 ADAPTER_STATUS_P_PLL_LOCK))) {
1323 if (flag == FALSE) {
1324 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1325 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1326 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1332 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1333 ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1334 (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1335 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1336 ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1348 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
1349 * @sp: Pointer to device specifc structure
1351 * New procedure to clear mac address reading problems on Alpha platforms
1355 void fix_mac_address(nic_t * sp)
1357 XENA_dev_config_t __iomem *bar0 = sp->bar0;
1361 while (fix_mac[i] != END_SIGN) {
1362 writeq(fix_mac[i++], &bar0->gpio_control);
1363 val64 = readq(&bar0->gpio_control);
1368 * start_nic - Turns the device on
1369 * @nic : device private variable.
1371 * This function actually turns the device on. Before this function is
1372 * called,all Registers are configured from their reset states
1373 * and shared memory is allocated but the NIC is still quiescent. On
1374 * calling this function, the device interrupts are cleared and the NIC is
1375 * literally switched on by writing into the adapter control register.
1377 * SUCCESS on success and -1 on failure.
1380 static int start_nic(struct s2io_nic *nic)
1382 XENA_dev_config_t __iomem *bar0 = nic->bar0;
1383 struct net_device *dev = nic->dev;
1384 register u64 val64 = 0;
1385 u16 interruptible, i;
1387 mac_info_t *mac_control;
1388 struct config_param *config;
1390 mac_control = &nic->mac_control;
1391 config = &nic->config;
1393 /* PRC Initialization and configuration */
1394 for (i = 0; i < config->rx_ring_num; i++) {
1395 writeq((u64) nic->rx_blocks[i][0].block_dma_addr,
1396 &bar0->prc_rxd0_n[i]);
1398 val64 = readq(&bar0->prc_ctrl_n[i]);
1399 #ifndef CONFIG_2BUFF_MODE
1400 val64 |= PRC_CTRL_RC_ENABLED;
1402 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
1404 writeq(val64, &bar0->prc_ctrl_n[i]);
1407 #ifdef CONFIG_2BUFF_MODE
1408 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
1409 val64 = readq(&bar0->rx_pa_cfg);
1410 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
1411 writeq(val64, &bar0->rx_pa_cfg);
1415 * Enabling MC-RLDRAM. After enabling the device, we timeout
1416 * for around 100ms, which is approximately the time required
1417 * for the device to be ready for operation.
1419 val64 = readq(&bar0->mc_rldram_mrs);
1420 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
1421 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
1422 val64 = readq(&bar0->mc_rldram_mrs);
1424 set_current_state(TASK_UNINTERRUPTIBLE);
1425 schedule_timeout(HZ / 10); /* Delay by around 100 ms. */
1427 /* Enabling ECC Protection. */
1428 val64 = readq(&bar0->adapter_control);
1429 val64 &= ~ADAPTER_ECC_EN;
1430 writeq(val64, &bar0->adapter_control);
1433 * Clearing any possible Link state change interrupts that
1434 * could have popped up just before Enabling the card.
1436 val64 = readq(&bar0->mac_rmac_err_reg);
1438 writeq(val64, &bar0->mac_rmac_err_reg);
1441 * Verify if the device is ready to be enabled, if so enable
1444 val64 = readq(&bar0->adapter_status);
1445 if (!verify_xena_quiescence(val64, nic->device_enabled_once)) {
1446 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
1447 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
1448 (unsigned long long) val64);
1452 /* Enable select interrupts */
1453 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | TX_MAC_INTR |
1455 en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS);
1458 * With some switches, link might be already up at this point.
1459 * Because of this weird behavior, when we enable laser,
1460 * we may not get link. We need to handle this. We cannot
1461 * figure out which switch is misbehaving. So we are forced to
1462 * make a global change.
1465 /* Enabling Laser. */
1466 val64 = readq(&bar0->adapter_control);
1467 val64 |= ADAPTER_EOI_TX_ON;
1468 writeq(val64, &bar0->adapter_control);
1470 /* SXE-002: Initialize link and activity LED */
1471 subid = nic->pdev->subsystem_device;
1472 if ((subid & 0xFF) >= 0x07) {
1473 val64 = readq(&bar0->gpio_control);
1474 val64 |= 0x0000800000000000ULL;
1475 writeq(val64, &bar0->gpio_control);
1476 val64 = 0x0411040400000000ULL;
1477 writeq(val64, (void __iomem *) bar0 + 0x2700);
1481 * Don't see link state interrupts on certain switches, so
1482 * directly scheduling a link state task from here.
1484 schedule_work(&nic->set_link_task);
1487 * Here we are performing soft reset on XGXS to
1488 * force link down. Since link is already up, we will get
1489 * link state change interrupt after this reset
1491 SPECIAL_REG_WRITE(0x80010515001E0000ULL, &bar0->dtx_control, UF);
1492 val64 = readq(&bar0->dtx_control);
1494 SPECIAL_REG_WRITE(0x80010515001E00E0ULL, &bar0->dtx_control, UF);
1495 val64 = readq(&bar0->dtx_control);
1497 SPECIAL_REG_WRITE(0x80070515001F00E4ULL, &bar0->dtx_control, UF);
1498 val64 = readq(&bar0->dtx_control);
1505 * free_tx_buffers - Free all queued Tx buffers
1506 * @nic : device private variable.
1508 * Free all queued Tx buffers.
1509 * Return Value: void
1512 void free_tx_buffers(struct s2io_nic *nic)
1514 struct net_device *dev = nic->dev;
1515 struct sk_buff *skb;
1518 mac_info_t *mac_control;
1519 struct config_param *config;
1522 mac_control = &nic->mac_control;
1523 config = &nic->config;
1525 for (i = 0; i < config->tx_fifo_num; i++) {
1526 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
1527 txdp = (TxD_t *) nic->list_info[i][j].
1530 (struct sk_buff *) ((unsigned long) txdp->
1533 memset(txdp, 0, sizeof(TxD_t));
1537 memset(txdp, 0, sizeof(TxD_t));
1541 "%s:forcibly freeing %d skbs on FIFO%d\n",
1543 mac_control->tx_curr_get_info[i].offset = 0;
1544 mac_control->tx_curr_put_info[i].offset = 0;
1549 * stop_nic - To stop the nic
1550 * @nic ; device private variable.
1552 * This function does exactly the opposite of what the start_nic()
1553 * function does. This function is called to stop the device.
1558 static void stop_nic(struct s2io_nic *nic)
1560 XENA_dev_config_t __iomem *bar0 = nic->bar0;
1561 register u64 val64 = 0;
1562 u16 interruptible, i;
1563 mac_info_t *mac_control;
1564 struct config_param *config;
1566 mac_control = &nic->mac_control;
1567 config = &nic->config;
1569 /* Disable all interrupts */
1570 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | TX_MAC_INTR |
1572 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
1575 for (i = 0; i < config->rx_ring_num; i++) {
1576 val64 = readq(&bar0->prc_ctrl_n[i]);
1577 val64 &= ~((u64) PRC_CTRL_RC_ENABLED);
1578 writeq(val64, &bar0->prc_ctrl_n[i]);
1583 * fill_rx_buffers - Allocates the Rx side skbs
1584 * @nic: device private variable
1585 * @ring_no: ring number
1587 * The function allocates Rx side skbs and puts the physical
1588 * address of these buffers into the RxD buffer pointers, so that the NIC
1589 * can DMA the received frame into these locations.
1590 * The NIC supports 3 receive modes, viz
1592 * 2. three buffer and
1593 * 3. Five buffer modes.
1594 * Each mode defines how many fragments the received frame will be split
1595 * up into by the NIC. The frame is split into L3 header, L4 Header,
1596 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
1597 * is split into 3 fragments. As of now only single buffer mode is
1600 * SUCCESS on success or an appropriate -ve value on failure.
1603 int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1605 struct net_device *dev = nic->dev;
1606 struct sk_buff *skb;
1608 int off, off1, size, block_no, block_no1;
1609 int offset, offset1;
1611 u32 alloc_cnt = nic->pkt_cnt[ring_no] -
1612 atomic_read(&nic->rx_bufs_left[ring_no]);
1613 mac_info_t *mac_control;
1614 struct config_param *config;
1615 #ifdef CONFIG_2BUFF_MODE
1620 dma_addr_t rxdpphys;
1622 #ifndef CONFIG_S2IO_NAPI
1623 unsigned long flags;
1626 mac_control = &nic->mac_control;
1627 config = &nic->config;
1629 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
1630 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
1632 while (alloc_tab < alloc_cnt) {
1633 block_no = mac_control->rx_curr_put_info[ring_no].
1635 block_no1 = mac_control->rx_curr_get_info[ring_no].
1637 off = mac_control->rx_curr_put_info[ring_no].offset;
1638 off1 = mac_control->rx_curr_get_info[ring_no].offset;
1639 #ifndef CONFIG_2BUFF_MODE
1640 offset = block_no * (MAX_RXDS_PER_BLOCK + 1) + off;
1641 offset1 = block_no1 * (MAX_RXDS_PER_BLOCK + 1) + off1;
1643 offset = block_no * (MAX_RXDS_PER_BLOCK) + off;
1644 offset1 = block_no1 * (MAX_RXDS_PER_BLOCK) + off1;
1647 rxdp = nic->rx_blocks[ring_no][block_no].
1648 block_virt_addr + off;
1649 if ((offset == offset1) && (rxdp->Host_Control)) {
1650 DBG_PRINT(INTR_DBG, "%s: Get and Put", dev->name);
1651 DBG_PRINT(INTR_DBG, " info equated\n");
1654 #ifndef CONFIG_2BUFF_MODE
1655 if (rxdp->Control_1 == END_OF_BLOCK) {
1656 mac_control->rx_curr_put_info[ring_no].
1658 mac_control->rx_curr_put_info[ring_no].
1659 block_index %= nic->block_count[ring_no];
1660 block_no = mac_control->rx_curr_put_info
1661 [ring_no].block_index;
1663 off %= (MAX_RXDS_PER_BLOCK + 1);
1664 mac_control->rx_curr_put_info[ring_no].offset =
1666 rxdp = (RxD_t *) ((unsigned long) rxdp->Control_2);
1667 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
1670 #ifndef CONFIG_S2IO_NAPI
1671 spin_lock_irqsave(&nic->put_lock, flags);
1672 nic->put_pos[ring_no] =
1673 (block_no * (MAX_RXDS_PER_BLOCK + 1)) + off;
1674 spin_unlock_irqrestore(&nic->put_lock, flags);
1677 if (rxdp->Host_Control == END_OF_BLOCK) {
1678 mac_control->rx_curr_put_info[ring_no].
1680 mac_control->rx_curr_put_info[ring_no].
1681 block_index %= nic->block_count[ring_no];
1682 block_no = mac_control->rx_curr_put_info
1683 [ring_no].block_index;
1685 DBG_PRINT(INTR_DBG, "%s: block%d at: 0x%llx\n",
1686 dev->name, block_no,
1687 (unsigned long long) rxdp->Control_1);
1688 mac_control->rx_curr_put_info[ring_no].offset =
1690 rxdp = nic->rx_blocks[ring_no][block_no].
1693 #ifndef CONFIG_S2IO_NAPI
1694 spin_lock_irqsave(&nic->put_lock, flags);
1695 nic->put_pos[ring_no] = (block_no *
1696 (MAX_RXDS_PER_BLOCK + 1)) + off;
1697 spin_unlock_irqrestore(&nic->put_lock, flags);
1701 #ifndef CONFIG_2BUFF_MODE
1702 if (rxdp->Control_1 & RXD_OWN_XENA)
1704 if (rxdp->Control_2 & BIT(0))
1707 mac_control->rx_curr_put_info[ring_no].
1711 #ifdef CONFIG_2BUFF_MODE
1713 * RxDs Spanning cache lines will be replenished only
1714 * if the succeeding RxD is also owned by Host. It
1715 * will always be the ((8*i)+3) and ((8*i)+6)
1716 * descriptors for the 48 byte descriptor. The offending
1717 * decsriptor is of-course the 3rd descriptor.
1719 rxdpphys = nic->rx_blocks[ring_no][block_no].
1720 block_dma_addr + (off * sizeof(RxD_t));
1721 if (((u64) (rxdpphys)) % 128 > 80) {
1722 rxdpnext = nic->rx_blocks[ring_no][block_no].
1723 block_virt_addr + (off + 1);
1724 if (rxdpnext->Host_Control == END_OF_BLOCK) {
1725 nextblk = (block_no + 1) %
1726 (nic->block_count[ring_no]);
1727 rxdpnext = nic->rx_blocks[ring_no]
1728 [nextblk].block_virt_addr;
1730 if (rxdpnext->Control_2 & BIT(0))
1735 #ifndef CONFIG_2BUFF_MODE
1736 skb = dev_alloc_skb(size + NET_IP_ALIGN);
1738 skb = dev_alloc_skb(dev->mtu + ALIGN_SIZE + BUF0_LEN + 4);
1741 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
1742 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
1745 #ifndef CONFIG_2BUFF_MODE
1746 skb_reserve(skb, NET_IP_ALIGN);
1747 memset(rxdp, 0, sizeof(RxD_t));
1748 rxdp->Buffer0_ptr = pci_map_single
1749 (nic->pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1750 rxdp->Control_2 &= (~MASK_BUFFER0_SIZE);
1751 rxdp->Control_2 |= SET_BUFFER0_SIZE(size);
1752 rxdp->Host_Control = (unsigned long) (skb);
1753 rxdp->Control_1 |= RXD_OWN_XENA;
1755 off %= (MAX_RXDS_PER_BLOCK + 1);
1756 mac_control->rx_curr_put_info[ring_no].offset = off;
1758 ba = &nic->ba[ring_no][block_no][off];
1759 skb_reserve(skb, BUF0_LEN);
1760 tmp = (unsigned long) skb->data;
1763 skb->data = (void *) tmp;
1764 skb->tail = (void *) tmp;
1766 memset(rxdp, 0, sizeof(RxD_t));
1767 rxdp->Buffer2_ptr = pci_map_single
1768 (nic->pdev, skb->data, dev->mtu + BUF0_LEN + 4,
1769 PCI_DMA_FROMDEVICE);
1771 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
1772 PCI_DMA_FROMDEVICE);
1774 pci_map_single(nic->pdev, ba->ba_1, BUF1_LEN,
1775 PCI_DMA_FROMDEVICE);
1777 rxdp->Control_2 = SET_BUFFER2_SIZE(dev->mtu + 4);
1778 rxdp->Control_2 |= SET_BUFFER0_SIZE(BUF0_LEN);
1779 rxdp->Control_2 |= SET_BUFFER1_SIZE(1); /* dummy. */
1780 rxdp->Control_2 |= BIT(0); /* Set Buffer_Empty bit. */
1781 rxdp->Host_Control = (u64) ((unsigned long) (skb));
1782 rxdp->Control_1 |= RXD_OWN_XENA;
1784 mac_control->rx_curr_put_info[ring_no].offset = off;
1786 atomic_inc(&nic->rx_bufs_left[ring_no]);
1795 * free_rx_buffers - Frees all Rx buffers
1796 * @sp: device private variable.
1798 * This function will free all Rx buffers allocated by host.
1803 static void free_rx_buffers(struct s2io_nic *sp)
1805 struct net_device *dev = sp->dev;
1806 int i, j, blk = 0, off, buf_cnt = 0;
1808 struct sk_buff *skb;
1809 mac_info_t *mac_control;
1810 struct config_param *config;
1811 #ifdef CONFIG_2BUFF_MODE
1815 mac_control = &sp->mac_control;
1816 config = &sp->config;
1818 for (i = 0; i < config->rx_ring_num; i++) {
1819 for (j = 0, blk = 0; j < config->rx_cfg[i].num_rxd; j++) {
1820 off = j % (MAX_RXDS_PER_BLOCK + 1);
1821 rxdp = sp->rx_blocks[i][blk].block_virt_addr + off;
1823 #ifndef CONFIG_2BUFF_MODE
1824 if (rxdp->Control_1 == END_OF_BLOCK) {
1826 (RxD_t *) ((unsigned long) rxdp->
1832 if (rxdp->Host_Control == END_OF_BLOCK) {
1838 if (!(rxdp->Control_1 & RXD_OWN_XENA)) {
1839 memset(rxdp, 0, sizeof(RxD_t));
1844 (struct sk_buff *) ((unsigned long) rxdp->
1847 #ifndef CONFIG_2BUFF_MODE
1848 pci_unmap_single(sp->pdev, (dma_addr_t)
1851 HEADER_ETHERNET_II_802_3_SIZE
1852 + HEADER_802_2_SIZE +
1854 PCI_DMA_FROMDEVICE);
1856 ba = &sp->ba[i][blk][off];
1857 pci_unmap_single(sp->pdev, (dma_addr_t)
1860 PCI_DMA_FROMDEVICE);
1861 pci_unmap_single(sp->pdev, (dma_addr_t)
1864 PCI_DMA_FROMDEVICE);
1865 pci_unmap_single(sp->pdev, (dma_addr_t)
1867 dev->mtu + BUF0_LEN + 4,
1868 PCI_DMA_FROMDEVICE);
1871 atomic_dec(&sp->rx_bufs_left[i]);
1874 memset(rxdp, 0, sizeof(RxD_t));
1876 mac_control->rx_curr_put_info[i].block_index = 0;
1877 mac_control->rx_curr_get_info[i].block_index = 0;
1878 mac_control->rx_curr_put_info[i].offset = 0;
1879 mac_control->rx_curr_get_info[i].offset = 0;
1880 atomic_set(&sp->rx_bufs_left[i], 0);
1881 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
1882 dev->name, buf_cnt, i);
1887 * s2io_poll - Rx interrupt handler for NAPI support
1888 * @dev : pointer to the device structure.
1889 * @budget : The number of packets that were budgeted to be processed
1890 * during one pass through the 'Poll" function.
1892 * Comes into picture only if NAPI support has been incorporated. It does
1893 * the same thing that rx_intr_handler does, but not in a interrupt context
1894 * also It will process only a given number of packets.
1896 * 0 on success and 1 if there are No Rx packets to be processed.
1899 #ifdef CONFIG_S2IO_NAPI
1900 static int s2io_poll(struct net_device *dev, int *budget)
1902 nic_t *nic = dev->priv;
1903 XENA_dev_config_t __iomem *bar0 = nic->bar0;
1904 int pkts_to_process = *budget, pkt_cnt = 0;
1905 register u64 val64 = 0;
1906 rx_curr_get_info_t get_info, put_info;
1907 int i, get_block, put_block, get_offset, put_offset, ring_bufs;
1908 #ifndef CONFIG_2BUFF_MODE
1911 struct sk_buff *skb;
1913 mac_info_t *mac_control;
1914 struct config_param *config;
1915 #ifdef CONFIG_2BUFF_MODE
1919 mac_control = &nic->mac_control;
1920 config = &nic->config;
1922 if (pkts_to_process > dev->quota)
1923 pkts_to_process = dev->quota;
1925 val64 = readq(&bar0->rx_traffic_int);
1926 writeq(val64, &bar0->rx_traffic_int);
1928 for (i = 0; i < config->rx_ring_num; i++) {
1929 get_info = mac_control->rx_curr_get_info[i];
1930 get_block = get_info.block_index;
1931 put_info = mac_control->rx_curr_put_info[i];
1932 put_block = put_info.block_index;
1933 ring_bufs = config->rx_cfg[i].num_rxd;
1934 rxdp = nic->rx_blocks[i][get_block].block_virt_addr +
1936 #ifndef CONFIG_2BUFF_MODE
1937 get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
1939 put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) +
1941 while ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
1942 (((get_offset + 1) % ring_bufs) != put_offset)) {
1943 if (--pkts_to_process < 0) {
1946 if (rxdp->Control_1 == END_OF_BLOCK) {
1948 (RxD_t *) ((unsigned long) rxdp->
1952 (MAX_RXDS_PER_BLOCK + 1);
1954 get_block %= nic->block_count[i];
1955 mac_control->rx_curr_get_info[i].
1956 offset = get_info.offset;
1957 mac_control->rx_curr_get_info[i].
1958 block_index = get_block;
1962 (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
1965 (struct sk_buff *) ((unsigned long) rxdp->
1968 DBG_PRINT(ERR_DBG, "%s: The skb is ",
1970 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
1973 val64 = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
1974 val16 = (u16) (val64 >> 48);
1975 cksum = RXD_GET_L4_CKSUM(rxdp->Control_1);
1976 pci_unmap_single(nic->pdev, (dma_addr_t)
1979 HEADER_ETHERNET_II_802_3_SIZE +
1982 PCI_DMA_FROMDEVICE);
1983 rx_osm_handler(nic, val16, rxdp, i);
1986 get_info.offset %= (MAX_RXDS_PER_BLOCK + 1);
1988 nic->rx_blocks[i][get_block].block_virt_addr +
1990 mac_control->rx_curr_get_info[i].offset =
1994 get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
1996 put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) +
1998 while (((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
1999 !(rxdp->Control_2 & BIT(0))) &&
2000 (((get_offset + 1) % ring_bufs) != put_offset)) {
2001 if (--pkts_to_process < 0) {
2004 skb = (struct sk_buff *) ((unsigned long)
2005 rxdp->Host_Control);
2007 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2009 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2013 pci_unmap_single(nic->pdev, (dma_addr_t)
2015 BUF0_LEN, PCI_DMA_FROMDEVICE);
2016 pci_unmap_single(nic->pdev, (dma_addr_t)
2018 BUF1_LEN, PCI_DMA_FROMDEVICE);
2019 pci_unmap_single(nic->pdev, (dma_addr_t)
2021 dev->mtu + BUF0_LEN + 4,
2022 PCI_DMA_FROMDEVICE);
2023 ba = &nic->ba[i][get_block][get_info.offset];
2025 rx_osm_handler(nic, rxdp, i, ba);
2028 mac_control->rx_curr_get_info[i].offset =
2031 nic->rx_blocks[i][get_block].block_virt_addr +
2034 if (get_info.offset &&
2035 (!(get_info.offset % MAX_RXDS_PER_BLOCK))) {
2036 get_info.offset = 0;
2037 mac_control->rx_curr_get_info[i].
2038 offset = get_info.offset;
2040 get_block %= nic->block_count[i];
2041 mac_control->rx_curr_get_info[i].
2042 block_index = get_block;
2044 nic->rx_blocks[i][get_block].
2048 (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
2057 dev->quota -= pkt_cnt;
2059 netif_rx_complete(dev);
2061 for (i = 0; i < config->rx_ring_num; i++) {
2062 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2063 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2064 DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2068 /* Re enable the Rx interrupts. */
2069 en_dis_able_nic_intrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS);
2073 dev->quota -= pkt_cnt;
2076 for (i = 0; i < config->rx_ring_num; i++) {
2077 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2078 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2079 DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2087 * rx_intr_handler - Rx interrupt handler
2088 * @nic: device private variable.
2090 * If the interrupt is because of a received frame or if the
2091 * receive ring contains fresh as yet un-processed frames,this function is
2092 * called. It picks out the RxD at which place the last Rx processing had
2093 * stopped and sends the skb to the OSM's Rx handler and then increments
2099 static void rx_intr_handler(struct s2io_nic *nic)
2101 struct net_device *dev = (struct net_device *) nic->dev;
2102 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
2103 rx_curr_get_info_t get_info, put_info;
2105 struct sk_buff *skb;
2106 #ifndef CONFIG_2BUFF_MODE
2109 register u64 val64 = 0;
2110 int get_block, get_offset, put_block, put_offset, ring_bufs;
2112 mac_info_t *mac_control;
2113 struct config_param *config;
2114 #ifdef CONFIG_2BUFF_MODE
2118 mac_control = &nic->mac_control;
2119 config = &nic->config;
2122 * rx_traffic_int reg is an R1 register, hence we read and write back
2123 * the samevalue in the register to clear it.
2125 val64 = readq(&bar0->rx_traffic_int);
2126 writeq(val64, &bar0->rx_traffic_int);
2128 for (i = 0; i < config->rx_ring_num; i++) {
2129 get_info = mac_control->rx_curr_get_info[i];
2130 get_block = get_info.block_index;
2131 put_info = mac_control->rx_curr_put_info[i];
2132 put_block = put_info.block_index;
2133 ring_bufs = config->rx_cfg[i].num_rxd;
2134 rxdp = nic->rx_blocks[i][get_block].block_virt_addr +
2136 #ifndef CONFIG_2BUFF_MODE
2137 get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
2139 spin_lock(&nic->put_lock);
2140 put_offset = nic->put_pos[i];
2141 spin_unlock(&nic->put_lock);
2142 while ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
2143 (((get_offset + 1) % ring_bufs) != put_offset)) {
2144 if (rxdp->Control_1 == END_OF_BLOCK) {
2145 rxdp = (RxD_t *) ((unsigned long)
2149 (MAX_RXDS_PER_BLOCK + 1);
2151 get_block %= nic->block_count[i];
2152 mac_control->rx_curr_get_info[i].
2153 offset = get_info.offset;
2154 mac_control->rx_curr_get_info[i].
2155 block_index = get_block;
2159 (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
2161 skb = (struct sk_buff *) ((unsigned long)
2162 rxdp->Host_Control);
2164 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2166 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2169 val64 = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
2170 val16 = (u16) (val64 >> 48);
2171 cksum = RXD_GET_L4_CKSUM(rxdp->Control_1);
2172 pci_unmap_single(nic->pdev, (dma_addr_t)
2175 HEADER_ETHERNET_II_802_3_SIZE +
2178 PCI_DMA_FROMDEVICE);
2179 rx_osm_handler(nic, val16, rxdp, i);
2181 get_info.offset %= (MAX_RXDS_PER_BLOCK + 1);
2183 nic->rx_blocks[i][get_block].block_virt_addr +
2185 mac_control->rx_curr_get_info[i].offset =
2188 if ((indicate_max_pkts)
2189 && (pkt_cnt > indicate_max_pkts))
2193 get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
2195 spin_lock(&nic->put_lock);
2196 put_offset = nic->put_pos[i];
2197 spin_unlock(&nic->put_lock);
2198 while (((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
2199 !(rxdp->Control_2 & BIT(0))) &&
2200 (((get_offset + 1) % ring_bufs) != put_offset)) {
2201 skb = (struct sk_buff *) ((unsigned long)
2202 rxdp->Host_Control);
2204 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2206 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2210 pci_unmap_single(nic->pdev, (dma_addr_t)
2212 BUF0_LEN, PCI_DMA_FROMDEVICE);
2213 pci_unmap_single(nic->pdev, (dma_addr_t)
2215 BUF1_LEN, PCI_DMA_FROMDEVICE);
2216 pci_unmap_single(nic->pdev, (dma_addr_t)
2218 dev->mtu + BUF0_LEN + 4,
2219 PCI_DMA_FROMDEVICE);
2220 ba = &nic->ba[i][get_block][get_info.offset];
2222 rx_osm_handler(nic, rxdp, i, ba);
2225 mac_control->rx_curr_get_info[i].offset =
2228 nic->rx_blocks[i][get_block].block_virt_addr +
2231 if (get_info.offset &&
2232 (!(get_info.offset % MAX_RXDS_PER_BLOCK))) {
2233 get_info.offset = 0;
2234 mac_control->rx_curr_get_info[i].
2235 offset = get_info.offset;
2237 get_block %= nic->block_count[i];
2238 mac_control->rx_curr_get_info[i].
2239 block_index = get_block;
2241 nic->rx_blocks[i][get_block].
2245 (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
2248 if ((indicate_max_pkts)
2249 && (pkt_cnt > indicate_max_pkts))
2253 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2259 * tx_intr_handler - Transmit interrupt handler
2260 * @nic : device private variable
2262 * If an interrupt was raised to indicate DMA complete of the
2263 * Tx packet, this function is called. It identifies the last TxD
2264 * whose buffer was freed and frees all skbs whose data have already
2265 * DMA'ed into the NICs internal memory.
2270 static void tx_intr_handler(struct s2io_nic *nic)
2272 XENA_dev_config_t __iomem *bar0 = nic->bar0;
2273 struct net_device *dev = (struct net_device *) nic->dev;
2274 tx_curr_get_info_t get_info, put_info;
2275 struct sk_buff *skb;
2277 register u64 val64 = 0;
2280 mac_info_t *mac_control;
2281 struct config_param *config;
2283 mac_control = &nic->mac_control;
2284 config = &nic->config;
2287 * tx_traffic_int reg is an R1 register, hence we read and write
2288 * back the samevalue in the register to clear it.
2290 val64 = readq(&bar0->tx_traffic_int);
2291 writeq(val64, &bar0->tx_traffic_int);
2293 for (i = 0; i < config->tx_fifo_num; i++) {
2294 get_info = mac_control->tx_curr_get_info[i];
2295 put_info = mac_control->tx_curr_put_info[i];
2296 txdlp = (TxD_t *) nic->list_info[i][get_info.offset].
2298 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2299 (get_info.offset != put_info.offset) &&
2300 (txdlp->Host_Control)) {
2301 /* Check for TxD errors */
2302 if (txdlp->Control_1 & TXD_T_CODE) {
2303 unsigned long long err;
2304 err = txdlp->Control_1 & TXD_T_CODE;
2305 DBG_PRINT(ERR_DBG, "***TxD error %llx\n",
2309 skb = (struct sk_buff *) ((unsigned long)
2310 txdlp->Host_Control);
2312 DBG_PRINT(ERR_DBG, "%s: Null skb ",
2314 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2317 nic->tx_pkt_count++;
2319 frg_cnt = skb_shinfo(skb)->nr_frags;
2321 /* For unfragmented skb */
2322 pci_unmap_single(nic->pdev, (dma_addr_t)
2323 txdlp->Buffer_Pointer,
2324 skb->len - skb->data_len,
2327 TxD_t *temp = txdlp;
2329 for (j = 0; j < frg_cnt; j++, txdlp++) {
2331 &skb_shinfo(skb)->frags[j];
2332 pci_unmap_page(nic->pdev,
2342 (sizeof(TxD_t) * config->max_txds));
2344 /* Updating the statistics block */
2345 nic->stats.tx_packets++;
2346 nic->stats.tx_bytes += skb->len;
2347 dev_kfree_skb_irq(skb);
2350 get_info.offset %= get_info.fifo_len + 1;
2351 txdlp = (TxD_t *) nic->list_info[i]
2352 [get_info.offset].list_virt_addr;
2353 mac_control->tx_curr_get_info[i].offset =
2358 spin_lock(&nic->tx_lock);
2359 if (netif_queue_stopped(dev))
2360 netif_wake_queue(dev);
2361 spin_unlock(&nic->tx_lock);
2365 * alarm_intr_handler - Alarm Interrrupt handler
2366 * @nic: device private variable
2367 * Description: If the interrupt was neither because of Rx packet or Tx
2368 * complete, this function is called. If the interrupt was to indicate
2369 * a loss of link, the OSM link status handler is invoked for any other
2370 * alarm interrupt the block that raised the interrupt is displayed
2371 * and a H/W reset is issued.
2376 static void alarm_intr_handler(struct s2io_nic *nic)
2378 struct net_device *dev = (struct net_device *) nic->dev;
2379 XENA_dev_config_t __iomem *bar0 = nic->bar0;
2380 register u64 val64 = 0, err_reg = 0;
2382 /* Handling link status change error Intr */
2383 err_reg = readq(&bar0->mac_rmac_err_reg);
2384 writeq(err_reg, &bar0->mac_rmac_err_reg);
2385 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
2386 schedule_work(&nic->set_link_task);
2389 /* In case of a serious error, the device will be Reset. */
2390 val64 = readq(&bar0->serr_source);
2391 if (val64 & SERR_SOURCE_ANY) {
2392 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
2393 DBG_PRINT(ERR_DBG, "serious error!!\n");
2394 netif_stop_queue(dev);
2395 schedule_work(&nic->rst_timer_task);
2399 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
2400 * Error occurs, the adapter will be recycled by disabling the
2401 * adapter enable bit and enabling it again after the device
2402 * becomes Quiescent.
2404 val64 = readq(&bar0->pcc_err_reg);
2405 writeq(val64, &bar0->pcc_err_reg);
2406 if (val64 & PCC_FB_ECC_DB_ERR) {
2407 u64 ac = readq(&bar0->adapter_control);
2408 ac &= ~(ADAPTER_CNTL_EN);
2409 writeq(ac, &bar0->adapter_control);
2410 ac = readq(&bar0->adapter_control);
2411 schedule_work(&nic->set_link_task);
2414 /* Other type of interrupts are not being handled now, TODO */
2418 * wait_for_cmd_complete - waits for a command to complete.
2419 * @sp : private member of the device structure, which is a pointer to the
2420 * s2io_nic structure.
2421 * Description: Function that waits for a command to Write into RMAC
2422 * ADDR DATA registers to be completed and returns either success or
2423 * error depending on whether the command was complete or not.
2425 * SUCCESS on success and FAILURE on failure.
2428 int wait_for_cmd_complete(nic_t * sp)
2430 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2431 int ret = FAILURE, cnt = 0;
2435 val64 = readq(&bar0->rmac_addr_cmd_mem);
2436 if (!(val64 & RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
2440 set_current_state(TASK_UNINTERRUPTIBLE);
2441 schedule_timeout(HZ / 20);
2450 * s2io_reset - Resets the card.
2451 * @sp : private member of the device structure.
2452 * Description: Function to Reset the card. This function then also
2453 * restores the previously saved PCI configuration space registers as
2454 * the card reset also resets the configuration space.
2459 void s2io_reset(nic_t * sp)
2461 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2465 val64 = SW_RESET_ALL;
2466 writeq(val64, &bar0->sw_reset);
2469 * At this stage, if the PCI write is indeed completed, the
2470 * card is reset and so is the PCI Config space of the device.
2471 * So a read cannot be issued at this stage on any of the
2472 * registers to ensure the write into "sw_reset" register
2474 * Question: Is there any system call that will explicitly force
2475 * all the write commands still pending on the bus to be pushed
2477 * As of now I'am just giving a 250ms delay and hoping that the
2478 * PCI write to sw_reset register is done by this time.
2480 set_current_state(TASK_UNINTERRUPTIBLE);
2481 schedule_timeout(HZ / 4);
2483 /* Restore the PCI state saved during initializarion. */
2484 pci_restore_state(sp->pdev);
2487 set_current_state(TASK_UNINTERRUPTIBLE);
2488 schedule_timeout(HZ / 4);
2490 /* SXE-002: Configure link and activity LED to turn it off */
2491 subid = sp->pdev->subsystem_device;
2492 if ((subid & 0xFF) >= 0x07) {
2493 val64 = readq(&bar0->gpio_control);
2494 val64 |= 0x0000800000000000ULL;
2495 writeq(val64, &bar0->gpio_control);
2496 val64 = 0x0411040400000000ULL;
2497 writeq(val64, (void __iomem *) bar0 + 0x2700);
2500 sp->device_enabled_once = FALSE;
2504 * s2io_set_swapper - to set the swapper controle on the card
2505 * @sp : private member of the device structure,
2506 * pointer to the s2io_nic structure.
2507 * Description: Function to set the swapper control on the card
2508 * correctly depending on the 'endianness' of the system.
2510 * SUCCESS on success and FAILURE on failure.
2513 int s2io_set_swapper(nic_t * sp)
2515 struct net_device *dev = sp->dev;
2516 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2520 * Set proper endian settings and verify the same by reading
2521 * the PIF Feed-back register.
2525 * The device by default set to a big endian format, so a
2526 * big endian driver need not set anything.
2528 writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
2529 val64 = (SWAPPER_CTRL_PIF_R_FE |
2530 SWAPPER_CTRL_PIF_R_SE |
2531 SWAPPER_CTRL_PIF_W_FE |
2532 SWAPPER_CTRL_PIF_W_SE |
2533 SWAPPER_CTRL_TXP_FE |
2534 SWAPPER_CTRL_TXP_SE |
2535 SWAPPER_CTRL_TXD_R_FE |
2536 SWAPPER_CTRL_TXD_W_FE |
2537 SWAPPER_CTRL_TXF_R_FE |
2538 SWAPPER_CTRL_RXD_R_FE |
2539 SWAPPER_CTRL_RXD_W_FE |
2540 SWAPPER_CTRL_RXF_W_FE |
2541 SWAPPER_CTRL_XMSI_FE |
2542 SWAPPER_CTRL_XMSI_SE |
2543 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
2544 writeq(val64, &bar0->swapper_ctrl);
2547 * Initially we enable all bits to make it accessible by the
2548 * driver, then we selectively enable only those bits that
2551 writeq(0xffffffffffffffffULL, &bar0->swapper_ctrl);
2552 val64 = (SWAPPER_CTRL_PIF_R_FE |
2553 SWAPPER_CTRL_PIF_R_SE |
2554 SWAPPER_CTRL_PIF_W_FE |
2555 SWAPPER_CTRL_PIF_W_SE |
2556 SWAPPER_CTRL_TXP_FE |
2557 SWAPPER_CTRL_TXP_SE |
2558 SWAPPER_CTRL_TXD_R_FE |
2559 SWAPPER_CTRL_TXD_R_SE |
2560 SWAPPER_CTRL_TXD_W_FE |
2561 SWAPPER_CTRL_TXD_W_SE |
2562 SWAPPER_CTRL_TXF_R_FE |
2563 SWAPPER_CTRL_RXD_R_FE |
2564 SWAPPER_CTRL_RXD_R_SE |
2565 SWAPPER_CTRL_RXD_W_FE |
2566 SWAPPER_CTRL_RXD_W_SE |
2567 SWAPPER_CTRL_RXF_W_FE |
2568 SWAPPER_CTRL_XMSI_FE |
2569 SWAPPER_CTRL_XMSI_SE |
2570 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
2571 writeq(val64, &bar0->swapper_ctrl);
2575 * Verifying if endian settings are accurate by reading a
2576 * feedback register.
2578 val64 = readq(&bar0->pif_rd_swapper_fb);
2579 if (val64 != 0x0123456789ABCDEFULL) {
2580 /* Endian settings are incorrect, calls for another dekko. */
2581 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
2583 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
2584 (unsigned long long) val64);
2591 /* ********************************************************* *
2592 * Functions defined below concern the OS part of the driver *
2593 * ********************************************************* */
2596 * s2io_open - open entry point of the driver
2597 * @dev : pointer to the device structure.
2599 * This function is the open entry point of the driver. It mainly calls a
2600 * function to allocate Rx buffers and inserts them into the buffer
2601 * descriptors and then enables the Rx part of the NIC.
2603 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2607 int s2io_open(struct net_device *dev)
2609 nic_t *sp = dev->priv;
2613 * Make sure you have link off by default every time
2614 * Nic is initialized
2616 netif_carrier_off(dev);
2617 sp->last_link_state = LINK_DOWN;
2619 /* Initialize H/W and enable interrupts */
2620 if (s2io_card_up(sp)) {
2621 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
2626 /* After proper initialization of H/W, register ISR */
2627 err = request_irq((int) sp->irq, s2io_isr, SA_SHIRQ,
2631 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
2636 if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
2637 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
2642 netif_start_queue(dev);
2647 * s2io_close -close entry point of the driver
2648 * @dev : device pointer.
2650 * This is the stop entry point of the driver. It needs to undo exactly
2651 * whatever was done by the open entry point,thus it's usually referred to
2652 * as the close function.Among other things this function mainly stops the
2653 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
2655 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2659 int s2io_close(struct net_device *dev)
2661 nic_t *sp = dev->priv;
2663 flush_scheduled_work();
2664 netif_stop_queue(dev);
2665 /* Reset card, kill tasklet and free Tx and Rx buffers. */
2668 free_irq(dev->irq, dev);
2669 sp->device_close_flag = TRUE; /* Device is shut down. */
2674 * s2io_xmit - Tx entry point of te driver
2675 * @skb : the socket buffer containing the Tx data.
2676 * @dev : device pointer.
2678 * This function is the Tx entry point of the driver. S2IO NIC supports
2679 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
2680 * NOTE: when device cant queue the pkt,just the trans_start variable will
2683 * 0 on success & 1 on failure.
2686 int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
2688 nic_t *sp = dev->priv;
2689 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
2692 TxFIFO_element_t __iomem *tx_fifo;
2693 unsigned long flags;
2697 mac_info_t *mac_control;
2698 struct config_param *config;
2699 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2701 mac_control = &sp->mac_control;
2702 config = &sp->config;
2704 DBG_PRINT(TX_DBG, "%s: In S2IO Tx routine\n", dev->name);
2705 spin_lock_irqsave(&sp->tx_lock, flags);
2707 if (atomic_read(&sp->card_state) == CARD_DOWN) {
2708 DBG_PRINT(ERR_DBG, "%s: Card going down for reset\n",
2710 spin_unlock_irqrestore(&sp->tx_lock, flags);
2715 put_off = (u16) mac_control->tx_curr_put_info[queue].offset;
2716 get_off = (u16) mac_control->tx_curr_get_info[queue].offset;
2717 txdp = (TxD_t *) sp->list_info[queue][put_off].list_virt_addr;
2719 queue_len = mac_control->tx_curr_put_info[queue].fifo_len + 1;
2720 /* Avoid "put" pointer going beyond "get" pointer */
2721 if (txdp->Host_Control || (((put_off + 1) % queue_len) == get_off)) {
2722 DBG_PRINT(ERR_DBG, "Error in xmit, No free TXDs.\n");
2723 netif_stop_queue(dev);
2725 spin_unlock_irqrestore(&sp->tx_lock, flags);
2729 mss = skb_shinfo(skb)->tso_size;
2731 txdp->Control_1 |= TXD_TCP_LSO_EN;
2732 txdp->Control_1 |= TXD_TCP_LSO_MSS(mss);
2736 frg_cnt = skb_shinfo(skb)->nr_frags;
2737 frg_len = skb->len - skb->data_len;
2739 txdp->Host_Control = (unsigned long) skb;
2740 txdp->Buffer_Pointer = pci_map_single
2741 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
2742 if (skb->ip_summed == CHECKSUM_HW) {
2744 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
2748 txdp->Control_2 |= config->tx_intr_type;
2750 txdp->Control_1 |= (TXD_BUFFER0_SIZE(frg_len) |
2751 TXD_GATHER_CODE_FIRST);
2752 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2754 /* For fragmented SKB. */
2755 for (i = 0; i < frg_cnt; i++) {
2756 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2758 txdp->Buffer_Pointer = (u64) pci_map_page
2759 (sp->pdev, frag->page, frag->page_offset,
2760 frag->size, PCI_DMA_TODEVICE);
2761 txdp->Control_1 |= TXD_BUFFER0_SIZE(frag->size);
2763 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
2765 tx_fifo = mac_control->tx_FIFO_start[queue];
2766 val64 = sp->list_info[queue][put_off].list_phy_addr;
2767 writeq(val64, &tx_fifo->TxDL_Pointer);
2769 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
2773 val64 |= TX_FIFO_SPECIAL_FUNC;
2775 writeq(val64, &tx_fifo->List_Control);
2777 /* Perform a PCI read to flush previous writes */
2778 val64 = readq(&bar0->general_int_status);
2781 put_off %= mac_control->tx_curr_put_info[queue].fifo_len + 1;
2782 mac_control->tx_curr_put_info[queue].offset = put_off;
2784 /* Avoid "put" pointer going beyond "get" pointer */
2785 if (((put_off + 1) % queue_len) == get_off) {
2787 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
2789 netif_stop_queue(dev);
2792 dev->trans_start = jiffies;
2793 spin_unlock_irqrestore(&sp->tx_lock, flags);
2799 * s2io_isr - ISR handler of the device .
2800 * @irq: the irq of the device.
2801 * @dev_id: a void pointer to the dev structure of the NIC.
2802 * @pt_regs: pointer to the registers pushed on the stack.
2803 * Description: This function is the ISR handler of the device. It
2804 * identifies the reason for the interrupt and calls the relevant
2805 * service routines. As a contongency measure, this ISR allocates the
2806 * recv buffers, if their numbers are below the panic value which is
2807 * presently set to 25% of the original number of rcv buffers allocated.
2809 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
2810 * IRQ_NONE: will be returned if interrupt is not from our device
2812 static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
2814 struct net_device *dev = (struct net_device *) dev_id;
2815 nic_t *sp = dev->priv;
2816 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2817 #ifndef CONFIG_S2IO_NAPI
2821 mac_info_t *mac_control;
2822 struct config_param *config;
2824 mac_control = &sp->mac_control;
2825 config = &sp->config;
2828 * Identify the cause for interrupt and call the appropriate
2829 * interrupt handler. Causes for the interrupt could be;
2833 * 4. Error in any functional blocks of the NIC.
2835 reason = readq(&bar0->general_int_status);
2838 /* The interrupt was not raised by Xena. */
2842 /* If Intr is because of Tx Traffic */
2843 if (reason & GEN_INTR_TXTRAFFIC) {
2844 tx_intr_handler(sp);
2847 /* If Intr is because of an error */
2848 if (reason & (GEN_ERROR_INTR))
2849 alarm_intr_handler(sp);
2851 #ifdef CONFIG_S2IO_NAPI
2852 if (reason & GEN_INTR_RXTRAFFIC) {
2853 if (netif_rx_schedule_prep(dev)) {
2854 en_dis_able_nic_intrs(sp, RX_TRAFFIC_INTR,
2856 __netif_rx_schedule(dev);
2860 /* If Intr is because of Rx Traffic */
2861 if (reason & GEN_INTR_RXTRAFFIC) {
2862 rx_intr_handler(sp);
2867 * If the Rx buffer count is below the panic threshold then
2868 * reallocate the buffers from the interrupt handler itself,
2869 * else schedule a tasklet to reallocate the buffers.
2871 #ifndef CONFIG_S2IO_NAPI
2872 for (i = 0; i < config->rx_ring_num; i++) {
2873 int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
2874 int level = rx_buffer_level(sp, rxb_size, i);
2876 if ((level == PANIC) && (!TASKLET_IN_USE)) {
2877 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", dev->name);
2878 DBG_PRINT(INTR_DBG, "PANIC levels\n");
2879 if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
2880 DBG_PRINT(ERR_DBG, "%s:Out of memory",
2882 DBG_PRINT(ERR_DBG, " in ISR!!\n");
2883 clear_bit(0, (&sp->tasklet_status));
2886 clear_bit(0, (&sp->tasklet_status));
2887 } else if (level == LOW) {
2888 tasklet_schedule(&sp->task);
2897 * s2io_get_stats - Updates the device statistics structure.
2898 * @dev : pointer to the device structure.
2900 * This function updates the device statistics structure in the s2io_nic
2901 * structure and returns a pointer to the same.
2903 * pointer to the updated net_device_stats structure.
2906 struct net_device_stats *s2io_get_stats(struct net_device *dev)
2908 nic_t *sp = dev->priv;
2909 mac_info_t *mac_control;
2910 struct config_param *config;
2912 mac_control = &sp->mac_control;
2913 config = &sp->config;
2915 sp->stats.tx_errors = mac_control->stats_info->tmac_any_err_frms;
2916 sp->stats.rx_errors = mac_control->stats_info->rmac_drop_frms;
2917 sp->stats.multicast = mac_control->stats_info->rmac_vld_mcst_frms;
2918 sp->stats.rx_length_errors =
2919 mac_control->stats_info->rmac_long_frms;
2921 return (&sp->stats);
2925 * s2io_set_multicast - entry point for multicast address enable/disable.
2926 * @dev : pointer to the device structure
2928 * This function is a driver entry point which gets called by the kernel
2929 * whenever multicast addresses must be enabled/disabled. This also gets
2930 * called to set/reset promiscuous mode. Depending on the deivce flag, we
2931 * determine, if multicast address must be enabled or if promiscuous mode
2932 * is to be disabled etc.
2937 static void s2io_set_multicast(struct net_device *dev)
2940 struct dev_mc_list *mclist;
2941 nic_t *sp = dev->priv;
2942 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2943 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
2945 u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
2948 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
2949 /* Enable all Multicast addresses */
2950 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
2951 &bar0->rmac_addr_data0_mem);
2952 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
2953 &bar0->rmac_addr_data1_mem);
2954 val64 = RMAC_ADDR_CMD_MEM_WE |
2955 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
2956 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
2957 writeq(val64, &bar0->rmac_addr_cmd_mem);
2958 /* Wait till command completes */
2959 wait_for_cmd_complete(sp);
2962 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
2963 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
2964 /* Disable all Multicast addresses */
2965 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
2966 &bar0->rmac_addr_data0_mem);
2967 val64 = RMAC_ADDR_CMD_MEM_WE |
2968 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
2969 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
2970 writeq(val64, &bar0->rmac_addr_cmd_mem);
2971 /* Wait till command completes */
2972 wait_for_cmd_complete(sp);
2975 sp->all_multi_pos = 0;
2978 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
2979 /* Put the NIC into promiscuous mode */
2980 add = &bar0->mac_cfg;
2981 val64 = readq(&bar0->mac_cfg);
2982 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
2984 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
2985 writel((u32) val64, add);
2986 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
2987 writel((u32) (val64 >> 32), (add + 4));
2989 val64 = readq(&bar0->mac_cfg);
2990 sp->promisc_flg = 1;
2991 DBG_PRINT(ERR_DBG, "%s: entered promiscuous mode\n",
2993 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
2994 /* Remove the NIC from promiscuous mode */
2995 add = &bar0->mac_cfg;
2996 val64 = readq(&bar0->mac_cfg);
2997 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
2999 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
3000 writel((u32) val64, add);
3001 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
3002 writel((u32) (val64 >> 32), (add + 4));
3004 val64 = readq(&bar0->mac_cfg);
3005 sp->promisc_flg = 0;
3006 DBG_PRINT(ERR_DBG, "%s: left promiscuous mode\n",
3010 /* Update individual M_CAST address list */
3011 if ((!sp->m_cast_flg) && dev->mc_count) {
3013 (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
3014 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
3016 DBG_PRINT(ERR_DBG, "can be added, please enable ");
3017 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
3021 prev_cnt = sp->mc_addr_count;
3022 sp->mc_addr_count = dev->mc_count;
3024 /* Clear out the previous list of Mc in the H/W. */
3025 for (i = 0; i < prev_cnt; i++) {
3026 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
3027 &bar0->rmac_addr_data0_mem);
3028 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
3029 &bar0->rmac_addr_data1_mem);
3030 val64 = RMAC_ADDR_CMD_MEM_WE |
3031 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
3032 RMAC_ADDR_CMD_MEM_OFFSET
3033 (MAC_MC_ADDR_START_OFFSET + i);
3034 writeq(val64, &bar0->rmac_addr_cmd_mem);
3036 /* Wait for command completes */
3037 if (wait_for_cmd_complete(sp)) {
3038 DBG_PRINT(ERR_DBG, "%s: Adding ",
3040 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
3045 /* Create the new Rx filter list and update the same in H/W. */
3046 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
3047 i++, mclist = mclist->next) {
3048 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
3050 for (j = 0; j < ETH_ALEN; j++) {
3051 mac_addr |= mclist->dmi_addr[j];
3055 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
3056 &bar0->rmac_addr_data0_mem);
3057 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
3058 &bar0->rmac_addr_data1_mem);
3060 val64 = RMAC_ADDR_CMD_MEM_WE |
3061 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
3062 RMAC_ADDR_CMD_MEM_OFFSET
3063 (i + MAC_MC_ADDR_START_OFFSET);
3064 writeq(val64, &bar0->rmac_addr_cmd_mem);
3066 /* Wait for command completes */
3067 if (wait_for_cmd_complete(sp)) {
3068 DBG_PRINT(ERR_DBG, "%s: Adding ",
3070 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
3078 * s2io_set_mac_addr - Programs the Xframe mac address
3079 * @dev : pointer to the device structure.
3080 * @addr: a uchar pointer to the new mac address which is to be set.
3081 * Description : This procedure will program the Xframe to receive
3082 * frames with new Mac Address
3083 * Return value: SUCCESS on success and an appropriate (-)ve integer
3084 * as defined in errno.h file on failure.
3087 int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
3089 nic_t *sp = dev->priv;
3090 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3091 register u64 val64, mac_addr = 0;
3095 * Set the new MAC address as the new unicast filter and reflect this
3096 * change on the device address registered with the OS. It will be
3099 for (i = 0; i < ETH_ALEN; i++) {
3101 mac_addr |= addr[i];
3104 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
3105 &bar0->rmac_addr_data0_mem);
3108 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
3109 RMAC_ADDR_CMD_MEM_OFFSET(0);
3110 writeq(val64, &bar0->rmac_addr_cmd_mem);
3111 /* Wait till command completes */
3112 if (wait_for_cmd_complete(sp)) {
3113 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
3121 * s2io_ethtool_sset - Sets different link parameters.
3122 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
3123 * @info: pointer to the structure with parameters given by ethtool to set
3126 * The function sets different link parameters provided by the user onto
3132 static int s2io_ethtool_sset(struct net_device *dev,
3133 struct ethtool_cmd *info)
3135 nic_t *sp = dev->priv;
3136 if ((info->autoneg == AUTONEG_ENABLE) ||
3137 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
3140 s2io_close(sp->dev);
3148 * s2io_ethtol_gset - Return link specific information.
3149 * @sp : private member of the device structure, pointer to the
3150 * s2io_nic structure.
3151 * @info : pointer to the structure with parameters given by ethtool
3152 * to return link information.
3154 * Returns link specific information like speed, duplex etc.. to ethtool.
3156 * return 0 on success.
3159 int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
3161 nic_t *sp = dev->priv;
3162 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
3163 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
3164 info->port = PORT_FIBRE;
3165 /* info->transceiver?? TODO */
3167 if (netif_carrier_ok(sp->dev)) {
3168 info->speed = 10000;
3169 info->duplex = DUPLEX_FULL;
3175 info->autoneg = AUTONEG_DISABLE;
3180 * s2io_ethtool_gdrvinfo - Returns driver specific information.
3181 * @sp : private member of the device structure, which is a pointer to the
3182 * s2io_nic structure.
3183 * @info : pointer to the structure with parameters given by ethtool to
3184 * return driver information.
3186 * Returns driver specefic information like name, version etc.. to ethtool.
3191 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
3192 struct ethtool_drvinfo *info)
3194 nic_t *sp = dev->priv;
3196 strncpy(info->driver, s2io_driver_name, sizeof(s2io_driver_name));
3197 strncpy(info->version, s2io_driver_version,
3198 sizeof(s2io_driver_version));
3199 strncpy(info->fw_version, "", 32);
3200 strncpy(info->bus_info, sp->pdev->slot_name, 32);
3201 info->regdump_len = XENA_REG_SPACE;
3202 info->eedump_len = XENA_EEPROM_SPACE;
3203 info->testinfo_len = S2IO_TEST_LEN;
3204 info->n_stats = S2IO_STAT_LEN;
3208 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
3209 * @sp: private member of the device structure, which is a pointer to the
3210 * s2io_nic structure.
3211 * @regs : pointer to the structure with parameters given by ethtool for
3212 * dumping the registers.
3213 * @reg_space: The input argumnet into which all the registers are dumped.
3215 * Dumps the entire register space of xFrame NIC into the user given
3221 static void s2io_ethtool_gregs(struct net_device *dev,
3222 struct ethtool_regs *regs, void *space)
3226 u8 *reg_space = (u8 *) space;
3227 nic_t *sp = dev->priv;
3229 regs->len = XENA_REG_SPACE;
3230 regs->version = sp->pdev->subsystem_device;
3232 for (i = 0; i < regs->len; i += 8) {
3233 reg = readq(sp->bar0 + i);
3234 memcpy((reg_space + i), ®, 8);
3239 * s2io_phy_id - timer function that alternates adapter LED.
3240 * @data : address of the private member of the device structure, which
3241 * is a pointer to the s2io_nic structure, provided as an u32.
3242 * Description: This is actually the timer function that alternates the
3243 * adapter LED bit of the adapter control bit to set/reset every time on
3244 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
3245 * once every second.
3247 static void s2io_phy_id(unsigned long data)
3249 nic_t *sp = (nic_t *) data;
3250 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3254 subid = sp->pdev->subsystem_device;
3255 if ((subid & 0xFF) >= 0x07) {
3256 val64 = readq(&bar0->gpio_control);
3257 val64 ^= GPIO_CTRL_GPIO_0;
3258 writeq(val64, &bar0->gpio_control);
3260 val64 = readq(&bar0->adapter_control);
3261 val64 ^= ADAPTER_LED_ON;
3262 writeq(val64, &bar0->adapter_control);
3265 mod_timer(&sp->id_timer, jiffies + HZ / 2);
3269 * s2io_ethtool_idnic - To physically identify the nic on the system.
3270 * @sp : private member of the device structure, which is a pointer to the
3271 * s2io_nic structure.
3272 * @id : pointer to the structure with identification parameters given by
3274 * Description: Used to physically identify the NIC on the system.
3275 * The Link LED will blink for a time specified by the user for
3277 * NOTE: The Link has to be Up to be able to blink the LED. Hence
3278 * identification is possible only if it's link is up.
3280 * int , returns 0 on success
3283 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
3285 u64 val64 = 0, last_gpio_ctrl_val;
3286 nic_t *sp = dev->priv;
3287 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3290 subid = sp->pdev->subsystem_device;
3291 last_gpio_ctrl_val = readq(&bar0->gpio_control);
3292 if ((subid & 0xFF) < 0x07) {
3293 val64 = readq(&bar0->adapter_control);
3294 if (!(val64 & ADAPTER_CNTL_EN)) {
3296 "Adapter Link down, cannot blink LED\n");
3300 if (sp->id_timer.function == NULL) {
3301 init_timer(&sp->id_timer);
3302 sp->id_timer.function = s2io_phy_id;
3303 sp->id_timer.data = (unsigned long) sp;
3305 mod_timer(&sp->id_timer, jiffies);
3306 set_current_state(TASK_INTERRUPTIBLE);
3308 schedule_timeout(data * HZ);
3310 schedule_timeout(MAX_SCHEDULE_TIMEOUT);
3311 del_timer_sync(&sp->id_timer);
3313 if (CARDS_WITH_FAULTY_LINK_INDICATORS(subid)) {
3314 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
3315 last_gpio_ctrl_val = readq(&bar0->gpio_control);
3322 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
3323 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
3324 * @ep : pointer to the structure with pause parameters given by ethtool.
3326 * Returns the Pause frame generation and reception capability of the NIC.
3330 static void s2io_ethtool_getpause_data(struct net_device *dev,
3331 struct ethtool_pauseparam *ep)
3334 nic_t *sp = dev->priv;
3335 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3337 val64 = readq(&bar0->rmac_pause_cfg);
3338 if (val64 & RMAC_PAUSE_GEN_ENABLE)
3339 ep->tx_pause = TRUE;
3340 if (val64 & RMAC_PAUSE_RX_ENABLE)
3341 ep->rx_pause = TRUE;
3342 ep->autoneg = FALSE;
3346 * s2io_ethtool_setpause_data - set/reset pause frame generation.
3347 * @sp : private member of the device structure, which is a pointer to the
3348 * s2io_nic structure.
3349 * @ep : pointer to the structure with pause parameters given by ethtool.
3351 * It can be used to set or reset Pause frame generation or reception
3352 * support of the NIC.
3354 * int, returns 0 on Success
3357 int s2io_ethtool_setpause_data(struct net_device *dev,
3358 struct ethtool_pauseparam *ep)
3361 nic_t *sp = dev->priv;
3362 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3364 val64 = readq(&bar0->rmac_pause_cfg);
3366 val64 |= RMAC_PAUSE_GEN_ENABLE;
3368 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
3370 val64 |= RMAC_PAUSE_RX_ENABLE;
3372 val64 &= ~RMAC_PAUSE_RX_ENABLE;
3373 writeq(val64, &bar0->rmac_pause_cfg);
3378 * read_eeprom - reads 4 bytes of data from user given offset.
3379 * @sp : private member of the device structure, which is a pointer to the
3380 * s2io_nic structure.
3381 * @off : offset at which the data must be written
3382 * @data : Its an output parameter where the data read at the given
3385 * Will read 4 bytes of data from the user given offset and return the
3387 * NOTE: Will allow to read only part of the EEPROM visible through the
3390 * -1 on failure and 0 on success.
3393 #define S2IO_DEV_ID 5
3394 static int read_eeprom(nic_t * sp, int off, u32 * data)
3399 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3401 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
3402 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
3403 I2C_CONTROL_CNTL_START;
3404 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
3406 while (exit_cnt < 5) {
3407 val64 = readq(&bar0->i2c_control);
3408 if (I2C_CONTROL_CNTL_END(val64)) {
3409 *data = I2C_CONTROL_GET_DATA(val64);
3413 set_current_state(TASK_UNINTERRUPTIBLE);
3414 schedule_timeout(HZ / 20);
3422 * write_eeprom - actually writes the relevant part of the data value.
3423 * @sp : private member of the device structure, which is a pointer to the
3424 * s2io_nic structure.
3425 * @off : offset at which the data must be written
3426 * @data : The data that is to be written
3427 * @cnt : Number of bytes of the data that are actually to be written into
3428 * the Eeprom. (max of 3)
3430 * Actually writes the relevant part of the data value into the Eeprom
3431 * through the I2C bus.
3433 * 0 on success, -1 on failure.
3436 static int write_eeprom(nic_t * sp, int off, u32 data, int cnt)
3438 int exit_cnt = 0, ret = -1;
3440 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3442 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
3443 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA(data) |
3444 I2C_CONTROL_CNTL_START;
3445 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
3447 while (exit_cnt < 5) {
3448 val64 = readq(&bar0->i2c_control);
3449 if (I2C_CONTROL_CNTL_END(val64)) {
3450 if (!(val64 & I2C_CONTROL_NACK))
3454 set_current_state(TASK_UNINTERRUPTIBLE);
3455 schedule_timeout(HZ / 20);
3463 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
3464 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
3465 * @eeprom : pointer to the user level structure provided by ethtool,
3466 * containing all relevant information.
3467 * @data_buf : user defined value to be written into Eeprom.
3468 * Description: Reads the values stored in the Eeprom at given offset
3469 * for a given length. Stores these values int the input argument data
3470 * buffer 'data_buf' and returns these to the caller (ethtool.)
3475 int s2io_ethtool_geeprom(struct net_device *dev,
3476 struct ethtool_eeprom *eeprom, u8 * data_buf)
3479 nic_t *sp = dev->priv;
3481 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
3483 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
3484 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
3486 for (i = 0; i < eeprom->len; i += 4) {
3487 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
3488 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
3492 memcpy((data_buf + i), &valid, 4);
3498 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
3499 * @sp : private member of the device structure, which is a pointer to the
3500 * s2io_nic structure.
3501 * @eeprom : pointer to the user level structure provided by ethtool,
3502 * containing all relevant information.
3503 * @data_buf ; user defined value to be written into Eeprom.
3505 * Tries to write the user provided value in the Eeprom, at the offset
3506 * given by the user.
3508 * 0 on success, -EFAULT on failure.
3511 static int s2io_ethtool_seeprom(struct net_device *dev,
3512 struct ethtool_eeprom *eeprom,
3515 int len = eeprom->len, cnt = 0;
3516 u32 valid = 0, data;
3517 nic_t *sp = dev->priv;
3519 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
3521 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
3522 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
3528 data = (u32) data_buf[cnt] & 0x000000FF;
3530 valid = (u32) (data << 24);
3534 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
3536 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
3538 "write into the specified offset\n");
3549 * s2io_register_test - reads and writes into all clock domains.
3550 * @sp : private member of the device structure, which is a pointer to the
3551 * s2io_nic structure.
3552 * @data : variable that returns the result of each of the test conducted b
3555 * Read and write into all clock domains. The NIC has 3 clock domains,
3556 * see that registers in all the three regions are accessible.
3561 static int s2io_register_test(nic_t * sp, uint64_t * data)
3563 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3567 val64 = readq(&bar0->pcc_enable);
3568 if (val64 != 0xff00000000000000ULL) {
3570 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
3573 val64 = readq(&bar0->rmac_pause_cfg);
3574 if (val64 != 0xc000ffff00000000ULL) {
3576 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
3579 val64 = readq(&bar0->rx_queue_cfg);
3580 if (val64 != 0x0808080808080808ULL) {
3582 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
3585 val64 = readq(&bar0->xgxs_efifo_cfg);
3586 if (val64 != 0x000000001923141EULL) {
3588 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
3591 val64 = 0x5A5A5A5A5A5A5A5AULL;
3592 writeq(val64, &bar0->xmsi_data);
3593 val64 = readq(&bar0->xmsi_data);
3594 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
3596 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
3599 val64 = 0xA5A5A5A5A5A5A5A5ULL;
3600 writeq(val64, &bar0->xmsi_data);
3601 val64 = readq(&bar0->xmsi_data);
3602 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
3604 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
3612 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
3613 * @sp : private member of the device structure, which is a pointer to the
3614 * s2io_nic structure.
3615 * @data:variable that returns the result of each of the test conducted by
3618 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
3624 static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
3629 /* Test Write Error at offset 0 */
3630 if (!write_eeprom(sp, 0, 0, 3))
3633 /* Test Write at offset 4f0 */
3634 if (write_eeprom(sp, 0x4F0, 0x01234567, 3))
3636 if (read_eeprom(sp, 0x4F0, &ret_data))
3639 if (ret_data != 0x01234567)
3642 /* Reset the EEPROM data go FFFF */
3643 write_eeprom(sp, 0x4F0, 0xFFFFFFFF, 3);
3645 /* Test Write Request Error at offset 0x7c */
3646 if (!write_eeprom(sp, 0x07C, 0, 3))
3649 /* Test Write Request at offset 0x7fc */
3650 if (write_eeprom(sp, 0x7FC, 0x01234567, 3))
3652 if (read_eeprom(sp, 0x7FC, &ret_data))
3655 if (ret_data != 0x01234567)
3658 /* Reset the EEPROM data go FFFF */
3659 write_eeprom(sp, 0x7FC, 0xFFFFFFFF, 3);
3661 /* Test Write Error at offset 0x80 */
3662 if (!write_eeprom(sp, 0x080, 0, 3))
3665 /* Test Write Error at offset 0xfc */
3666 if (!write_eeprom(sp, 0x0FC, 0, 3))
3669 /* Test Write Error at offset 0x100 */
3670 if (!write_eeprom(sp, 0x100, 0, 3))
3673 /* Test Write Error at offset 4ec */
3674 if (!write_eeprom(sp, 0x4EC, 0, 3))
3682 * s2io_bist_test - invokes the MemBist test of the card .
3683 * @sp : private member of the device structure, which is a pointer to the
3684 * s2io_nic structure.
3685 * @data:variable that returns the result of each of the test conducted by
3688 * This invokes the MemBist test of the card. We give around
3689 * 2 secs time for the Test to complete. If it's still not complete
3690 * within this peiod, we consider that the test failed.
3692 * 0 on success and -1 on failure.
3695 static int s2io_bist_test(nic_t * sp, uint64_t * data)
3698 int cnt = 0, ret = -1;
3700 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
3701 bist |= PCI_BIST_START;
3702 pci_write_config_word(sp->pdev, PCI_BIST, bist);
3705 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
3706 if (!(bist & PCI_BIST_START)) {
3707 *data = (bist & PCI_BIST_CODE_MASK);
3711 set_current_state(TASK_UNINTERRUPTIBLE);
3712 schedule_timeout(HZ / 10);
3720 * s2io-link_test - verifies the link state of the nic
3721 * @sp ; private member of the device structure, which is a pointer to the
3722 * s2io_nic structure.
3723 * @data: variable that returns the result of each of the test conducted by
3726 * The function verifies the link state of the NIC and updates the input
3727 * argument 'data' appropriately.
3732 static int s2io_link_test(nic_t * sp, uint64_t * data)
3734 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3737 val64 = readq(&bar0->adapter_status);
3738 if (val64 & ADAPTER_STATUS_RMAC_LOCAL_FAULT)
3745 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
3746 * @sp - private member of the device structure, which is a pointer to the
3747 * s2io_nic structure.
3748 * @data - variable that returns the result of each of the test
3749 * conducted by the driver.
3751 * This is one of the offline test that tests the read and write
3752 * access to the RldRam chip on the NIC.
3757 static int s2io_rldram_test(nic_t * sp, uint64_t * data)
3759 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3761 int cnt, iteration = 0, test_pass = 0;
3763 val64 = readq(&bar0->adapter_control);
3764 val64 &= ~ADAPTER_ECC_EN;
3765 writeq(val64, &bar0->adapter_control);
3767 val64 = readq(&bar0->mc_rldram_test_ctrl);
3768 val64 |= MC_RLDRAM_TEST_MODE;
3769 writeq(val64, &bar0->mc_rldram_test_ctrl);
3771 val64 = readq(&bar0->mc_rldram_mrs);
3772 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
3773 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
3775 val64 |= MC_RLDRAM_MRS_ENABLE;
3776 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
3778 while (iteration < 2) {
3779 val64 = 0x55555555aaaa0000ULL;
3780 if (iteration == 1) {
3781 val64 ^= 0xFFFFFFFFFFFF0000ULL;
3783 writeq(val64, &bar0->mc_rldram_test_d0);
3785 val64 = 0xaaaa5a5555550000ULL;
3786 if (iteration == 1) {
3787 val64 ^= 0xFFFFFFFFFFFF0000ULL;
3789 writeq(val64, &bar0->mc_rldram_test_d1);
3791 val64 = 0x55aaaaaaaa5a0000ULL;
3792 if (iteration == 1) {
3793 val64 ^= 0xFFFFFFFFFFFF0000ULL;
3795 writeq(val64, &bar0->mc_rldram_test_d2);
3797 val64 = (u64) (0x0000003fffff0000ULL);
3798 writeq(val64, &bar0->mc_rldram_test_add);
3801 val64 = MC_RLDRAM_TEST_MODE;
3802 writeq(val64, &bar0->mc_rldram_test_ctrl);
3805 MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
3807 writeq(val64, &bar0->mc_rldram_test_ctrl);
3809 for (cnt = 0; cnt < 5; cnt++) {
3810 val64 = readq(&bar0->mc_rldram_test_ctrl);
3811 if (val64 & MC_RLDRAM_TEST_DONE)
3813 set_current_state(TASK_UNINTERRUPTIBLE);
3814 schedule_timeout(HZ / 5);
3820 val64 = MC_RLDRAM_TEST_MODE;
3821 writeq(val64, &bar0->mc_rldram_test_ctrl);
3823 val64 |= MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
3824 writeq(val64, &bar0->mc_rldram_test_ctrl);
3826 for (cnt = 0; cnt < 5; cnt++) {
3827 val64 = readq(&bar0->mc_rldram_test_ctrl);
3828 if (val64 & MC_RLDRAM_TEST_DONE)
3830 set_current_state(TASK_UNINTERRUPTIBLE);
3831 schedule_timeout(HZ / 2);
3837 val64 = readq(&bar0->mc_rldram_test_ctrl);
3838 if (val64 & MC_RLDRAM_TEST_PASS)
3853 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
3854 * @sp : private member of the device structure, which is a pointer to the
3855 * s2io_nic structure.
3856 * @ethtest : pointer to a ethtool command specific structure that will be
3857 * returned to the user.
3858 * @data : variable that returns the result of each of the test
3859 * conducted by the driver.
3861 * This function conducts 6 tests ( 4 offline and 2 online) to determine
3862 * the health of the card.
3867 static void s2io_ethtool_test(struct net_device *dev,
3868 struct ethtool_test *ethtest,
3871 nic_t *sp = dev->priv;
3872 int orig_state = netif_running(sp->dev);
3874 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
3875 /* Offline Tests. */
3877 s2io_close(sp->dev);
3878 s2io_set_swapper(sp);
3880 s2io_set_swapper(sp);
3882 if (s2io_register_test(sp, &data[0]))
3883 ethtest->flags |= ETH_TEST_FL_FAILED;
3886 s2io_set_swapper(sp);
3888 if (s2io_rldram_test(sp, &data[3]))
3889 ethtest->flags |= ETH_TEST_FL_FAILED;
3892 s2io_set_swapper(sp);
3894 if (s2io_eeprom_test(sp, &data[1]))
3895 ethtest->flags |= ETH_TEST_FL_FAILED;
3897 if (s2io_bist_test(sp, &data[4]))
3898 ethtest->flags |= ETH_TEST_FL_FAILED;
3908 "%s: is not up, cannot run test\n",
3917 if (s2io_link_test(sp, &data[2]))
3918 ethtest->flags |= ETH_TEST_FL_FAILED;
3927 static void s2io_get_ethtool_stats(struct net_device *dev,
3928 struct ethtool_stats *estats,
3932 nic_t *sp = dev->priv;
3933 StatInfo_t *stat_info = sp->mac_control.stats_info;
3935 tmp_stats[i++] = stat_info->tmac_frms;
3936 tmp_stats[i++] = stat_info->tmac_data_octets;
3937 tmp_stats[i++] = stat_info->tmac_drop_frms;
3938 tmp_stats[i++] = stat_info->tmac_mcst_frms;
3939 tmp_stats[i++] = stat_info->tmac_bcst_frms;
3940 tmp_stats[i++] = stat_info->tmac_pause_ctrl_frms;
3941 tmp_stats[i++] = stat_info->tmac_any_err_frms;
3942 tmp_stats[i++] = stat_info->tmac_vld_ip_octets;
3943 tmp_stats[i++] = stat_info->tmac_vld_ip;
3944 tmp_stats[i++] = stat_info->tmac_drop_ip;
3945 tmp_stats[i++] = stat_info->tmac_icmp;
3946 tmp_stats[i++] = stat_info->tmac_rst_tcp;
3947 tmp_stats[i++] = stat_info->tmac_tcp;
3948 tmp_stats[i++] = stat_info->tmac_udp;
3949 tmp_stats[i++] = stat_info->rmac_vld_frms;
3950 tmp_stats[i++] = stat_info->rmac_data_octets;
3951 tmp_stats[i++] = stat_info->rmac_fcs_err_frms;
3952 tmp_stats[i++] = stat_info->rmac_drop_frms;
3953 tmp_stats[i++] = stat_info->rmac_vld_mcst_frms;
3954 tmp_stats[i++] = stat_info->rmac_vld_bcst_frms;
3955 tmp_stats[i++] = stat_info->rmac_in_rng_len_err_frms;
3956 tmp_stats[i++] = stat_info->rmac_long_frms;
3957 tmp_stats[i++] = stat_info->rmac_pause_ctrl_frms;
3958 tmp_stats[i++] = stat_info->rmac_discarded_frms;
3959 tmp_stats[i++] = stat_info->rmac_usized_frms;
3960 tmp_stats[i++] = stat_info->rmac_osized_frms;
3961 tmp_stats[i++] = stat_info->rmac_frag_frms;
3962 tmp_stats[i++] = stat_info->rmac_jabber_frms;
3963 tmp_stats[i++] = stat_info->rmac_ip;
3964 tmp_stats[i++] = stat_info->rmac_ip_octets;
3965 tmp_stats[i++] = stat_info->rmac_hdr_err_ip;
3966 tmp_stats[i++] = stat_info->rmac_drop_ip;
3967 tmp_stats[i++] = stat_info->rmac_icmp;
3968 tmp_stats[i++] = stat_info->rmac_tcp;
3969 tmp_stats[i++] = stat_info->rmac_udp;
3970 tmp_stats[i++] = stat_info->rmac_err_drp_udp;
3971 tmp_stats[i++] = stat_info->rmac_pause_cnt;
3972 tmp_stats[i++] = stat_info->rmac_accepted_ip;
3973 tmp_stats[i++] = stat_info->rmac_err_tcp;
3976 int s2io_ethtool_get_regs_len(struct net_device *dev)
3978 return (XENA_REG_SPACE);
3982 u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
3984 nic_t *sp = dev->priv;
3986 return (sp->rx_csum);
3988 int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
3990 nic_t *sp = dev->priv;
3999 int s2io_get_eeprom_len(struct net_device *dev)
4001 return (XENA_EEPROM_SPACE);
4004 int s2io_ethtool_self_test_count(struct net_device *dev)
4006 return (S2IO_TEST_LEN);
4008 void s2io_ethtool_get_strings(struct net_device *dev,
4009 u32 stringset, u8 * data)
4011 switch (stringset) {
4013 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
4016 memcpy(data, ðtool_stats_keys,
4017 sizeof(ethtool_stats_keys));
4020 static int s2io_ethtool_get_stats_count(struct net_device *dev)
4022 return (S2IO_STAT_LEN);
4025 int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
4028 dev->features |= NETIF_F_IP_CSUM;
4030 dev->features &= ~NETIF_F_IP_CSUM;
4036 static struct ethtool_ops netdev_ethtool_ops = {
4037 .get_settings = s2io_ethtool_gset,
4038 .set_settings = s2io_ethtool_sset,
4039 .get_drvinfo = s2io_ethtool_gdrvinfo,
4040 .get_regs_len = s2io_ethtool_get_regs_len,
4041 .get_regs = s2io_ethtool_gregs,
4042 .get_link = ethtool_op_get_link,
4043 .get_eeprom_len = s2io_get_eeprom_len,
4044 .get_eeprom = s2io_ethtool_geeprom,
4045 .set_eeprom = s2io_ethtool_seeprom,
4046 .get_pauseparam = s2io_ethtool_getpause_data,
4047 .set_pauseparam = s2io_ethtool_setpause_data,
4048 .get_rx_csum = s2io_ethtool_get_rx_csum,
4049 .set_rx_csum = s2io_ethtool_set_rx_csum,
4050 .get_tx_csum = ethtool_op_get_tx_csum,
4051 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
4052 .get_sg = ethtool_op_get_sg,
4053 .set_sg = ethtool_op_set_sg,
4055 .get_tso = ethtool_op_get_tso,
4056 .set_tso = ethtool_op_set_tso,
4058 .self_test_count = s2io_ethtool_self_test_count,
4059 .self_test = s2io_ethtool_test,
4060 .get_strings = s2io_ethtool_get_strings,
4061 .phys_id = s2io_ethtool_idnic,
4062 .get_stats_count = s2io_ethtool_get_stats_count,
4063 .get_ethtool_stats = s2io_get_ethtool_stats
4067 * s2io_ioctl - Entry point for the Ioctl
4068 * @dev : Device pointer.
4069 * @ifr : An IOCTL specefic structure, that can contain a pointer to
4070 * a proprietary structure used to pass information to the driver.
4071 * @cmd : This is used to distinguish between the different commands that
4072 * can be passed to the IOCTL functions.
4074 * This function has support for ethtool, adding multiple MAC addresses on
4075 * the NIC and some DBG commands for the util tool.
4077 * Currently the IOCTL supports no operations, hence by default this
4078 * function returns OP NOT SUPPORTED value.
4081 int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
4087 * s2io_change_mtu - entry point to change MTU size for the device.
4088 * @dev : device pointer.
4089 * @new_mtu : the new MTU size for the device.
4090 * Description: A driver entry point to change MTU size for the device.
4091 * Before changing the MTU the device must be stopped.
4093 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4097 int s2io_change_mtu(struct net_device *dev, int new_mtu)
4099 nic_t *sp = dev->priv;
4100 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4103 if (netif_running(dev)) {
4104 DBG_PRINT(ERR_DBG, "%s: Must be stopped to ", dev->name);
4105 DBG_PRINT(ERR_DBG, "change its MTU \n");
4109 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
4110 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
4115 /* Set the new MTU into the PYLD register of the NIC */
4117 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
4125 * s2io_tasklet - Bottom half of the ISR.
4126 * @dev_adr : address of the device structure in dma_addr_t format.
4128 * This is the tasklet or the bottom half of the ISR. This is
4129 * an extension of the ISR which is scheduled by the scheduler to be run
4130 * when the load on the CPU is low. All low priority tasks of the ISR can
4131 * be pushed into the tasklet. For now the tasklet is used only to
4132 * replenish the Rx buffers in the Rx buffer descriptors.
4137 static void s2io_tasklet(unsigned long dev_addr)
4139 struct net_device *dev = (struct net_device *) dev_addr;
4140 nic_t *sp = dev->priv;
4142 mac_info_t *mac_control;
4143 struct config_param *config;
4145 mac_control = &sp->mac_control;
4146 config = &sp->config;
4148 if (!TASKLET_IN_USE) {
4149 for (i = 0; i < config->rx_ring_num; i++) {
4150 ret = fill_rx_buffers(sp, i);
4151 if (ret == -ENOMEM) {
4152 DBG_PRINT(ERR_DBG, "%s: Out of ",
4154 DBG_PRINT(ERR_DBG, "memory in tasklet\n");
4156 } else if (ret == -EFILL) {
4158 "%s: Rx Ring %d is full\n",
4163 clear_bit(0, (&sp->tasklet_status));
4168 * s2io_set_link - Set the LInk status
4169 * @data: long pointer to device private structue
4170 * Description: Sets the link status for the adapter
4173 static void s2io_set_link(unsigned long data)
4175 nic_t *nic = (nic_t *) data;
4176 struct net_device *dev = nic->dev;
4177 XENA_dev_config_t __iomem *bar0 = nic->bar0;
4181 if (test_and_set_bit(0, &(nic->link_state))) {
4182 /* The card is being reset, no point doing anything */
4186 subid = nic->pdev->subsystem_device;
4188 * Allow a small delay for the NICs self initiated
4189 * cleanup to complete.
4191 set_current_state(TASK_UNINTERRUPTIBLE);
4192 schedule_timeout(HZ / 10);
4194 val64 = readq(&bar0->adapter_status);
4195 if (verify_xena_quiescence(val64, nic->device_enabled_once)) {
4196 if (LINK_IS_UP(val64)) {
4197 val64 = readq(&bar0->adapter_control);
4198 val64 |= ADAPTER_CNTL_EN;
4199 writeq(val64, &bar0->adapter_control);
4200 if (CARDS_WITH_FAULTY_LINK_INDICATORS(subid)) {
4201 val64 = readq(&bar0->gpio_control);
4202 val64 |= GPIO_CTRL_GPIO_0;
4203 writeq(val64, &bar0->gpio_control);
4204 val64 = readq(&bar0->gpio_control);
4206 val64 |= ADAPTER_LED_ON;
4207 writeq(val64, &bar0->adapter_control);
4209 val64 = readq(&bar0->adapter_status);
4210 if (!LINK_IS_UP(val64)) {
4211 DBG_PRINT(ERR_DBG, "%s:", dev->name);
4212 DBG_PRINT(ERR_DBG, " Link down");
4213 DBG_PRINT(ERR_DBG, "after ");
4214 DBG_PRINT(ERR_DBG, "enabling ");
4215 DBG_PRINT(ERR_DBG, "device \n");
4217 if (nic->device_enabled_once == FALSE) {
4218 nic->device_enabled_once = TRUE;
4220 s2io_link(nic, LINK_UP);
4222 if (CARDS_WITH_FAULTY_LINK_INDICATORS(subid)) {
4223 val64 = readq(&bar0->gpio_control);
4224 val64 &= ~GPIO_CTRL_GPIO_0;
4225 writeq(val64, &bar0->gpio_control);
4226 val64 = readq(&bar0->gpio_control);
4228 s2io_link(nic, LINK_DOWN);
4230 } else { /* NIC is not Quiescent. */
4231 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
4232 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
4233 netif_stop_queue(dev);
4235 clear_bit(0, &(nic->link_state));
4238 static void s2io_card_down(nic_t * sp)
4241 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4242 unsigned long flags;
4243 register u64 val64 = 0;
4245 /* If s2io_set_link task is executing, wait till it completes. */
4246 while (test_and_set_bit(0, &(sp->link_state))) {
4247 set_current_state(TASK_UNINTERRUPTIBLE);
4248 schedule_timeout(HZ / 20);
4250 atomic_set(&sp->card_state, CARD_DOWN);
4252 /* disable Tx and Rx traffic on the NIC */
4256 tasklet_kill(&sp->task);
4258 /* Check if the device is Quiescent and then Reset the NIC */
4260 val64 = readq(&bar0->adapter_status);
4261 if (verify_xena_quiescence(val64, sp->device_enabled_once)) {
4265 set_current_state(TASK_UNINTERRUPTIBLE);
4266 schedule_timeout(HZ / 20);
4270 "s2io_close:Device not Quiescent ");
4271 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
4272 (unsigned long long) val64);
4276 spin_lock_irqsave(&sp->tx_lock, flags);
4279 /* Free all unused Tx and Rx buffers */
4280 free_tx_buffers(sp);
4281 free_rx_buffers(sp);
4283 spin_unlock_irqrestore(&sp->tx_lock, flags);
4284 clear_bit(0, &(sp->link_state));
4287 static int s2io_card_up(nic_t * sp)
4290 mac_info_t *mac_control;
4291 struct config_param *config;
4292 struct net_device *dev = (struct net_device *) sp->dev;
4294 /* Initialize the H/W I/O registers */
4295 if (init_nic(sp) != 0) {
4296 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
4302 * Initializing the Rx buffers. For now we are considering only 1
4303 * Rx ring and initializing buffers into 30 Rx blocks
4305 mac_control = &sp->mac_control;
4306 config = &sp->config;
4308 for (i = 0; i < config->rx_ring_num; i++) {
4309 if ((ret = fill_rx_buffers(sp, i))) {
4310 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
4313 free_rx_buffers(sp);
4316 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
4317 atomic_read(&sp->rx_bufs_left[i]));
4320 /* Setting its receive mode */
4321 s2io_set_multicast(dev);
4323 /* Enable tasklet for the device */
4324 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
4326 /* Enable Rx Traffic and interrupts on the NIC */
4327 if (start_nic(sp)) {
4328 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
4329 tasklet_kill(&sp->task);
4331 free_irq(dev->irq, dev);
4332 free_rx_buffers(sp);
4336 atomic_set(&sp->card_state, CARD_UP);
4341 * s2io_restart_nic - Resets the NIC.
4342 * @data : long pointer to the device private structure
4344 * This function is scheduled to be run by the s2io_tx_watchdog
4345 * function after 0.5 secs to reset the NIC. The idea is to reduce
4346 * the run time of the watch dog routine which is run holding a
4350 static void s2io_restart_nic(unsigned long data)
4352 struct net_device *dev = (struct net_device *) data;
4353 nic_t *sp = dev->priv;
4356 if (s2io_card_up(sp)) {
4357 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
4360 netif_wake_queue(dev);
4361 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
4366 * s2io_tx_watchdog - Watchdog for transmit side.
4367 * @dev : Pointer to net device structure
4369 * This function is triggered if the Tx Queue is stopped
4370 * for a pre-defined amount of time when the Interface is still up.
4371 * If the Interface is jammed in such a situation, the hardware is
4372 * reset (by s2io_close) and restarted again (by s2io_open) to
4373 * overcome any problem that might have been caused in the hardware.
4378 static void s2io_tx_watchdog(struct net_device *dev)
4380 nic_t *sp = dev->priv;
4382 if (netif_carrier_ok(dev)) {
4383 schedule_work(&sp->rst_timer_task);
4388 * rx_osm_handler - To perform some OS related operations on SKB.
4389 * @sp: private member of the device structure,pointer to s2io_nic structure.
4390 * @skb : the socket buffer pointer.
4391 * @len : length of the packet
4392 * @cksum : FCS checksum of the frame.
4393 * @ring_no : the ring from which this RxD was extracted.
4395 * This function is called by the Tx interrupt serivce routine to perform
4396 * some OS related operations on the SKB before passing it to the upper
4397 * layers. It mainly checks if the checksum is OK, if so adds it to the
4398 * SKBs cksum variable, increments the Rx packet count and passes the SKB
4399 * to the upper layer. If the checksum is wrong, it increments the Rx
4400 * packet error count, frees the SKB and returns error.
4402 * SUCCESS on success and -1 on failure.
4404 #ifndef CONFIG_2BUFF_MODE
4405 static int rx_osm_handler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no)
4407 static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no,
4411 struct net_device *dev = (struct net_device *) sp->dev;
4412 struct sk_buff *skb =
4413 (struct sk_buff *) ((unsigned long) rxdp->Host_Control);
4414 u16 l3_csum, l4_csum;
4415 #ifdef CONFIG_2BUFF_MODE
4416 int buf0_len, buf2_len;
4417 unsigned char *buff;
4420 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
4421 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && (sp->rx_csum)) {
4422 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
4423 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
4425 * NIC verifies if the Checksum of the received
4426 * frame is Ok or not and accordingly returns
4427 * a flag in the RxD.
4429 skb->ip_summed = CHECKSUM_UNNECESSARY;
4432 * Packet with erroneous checksum, let the
4433 * upper layers deal with it.
4435 skb->ip_summed = CHECKSUM_NONE;
4438 skb->ip_summed = CHECKSUM_NONE;
4441 if (rxdp->Control_1 & RXD_T_CODE) {
4442 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
4443 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
4446 #ifdef CONFIG_2BUFF_MODE
4447 buf0_len = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
4448 buf2_len = RXD_GET_BUFFER2_SIZE(rxdp->Control_2);
4452 #ifndef CONFIG_2BUFF_MODE
4454 skb->protocol = eth_type_trans(skb, dev);
4456 buff = skb_push(skb, buf0_len);
4457 memcpy(buff, ba->ba_0, buf0_len);
4458 skb_put(skb, buf2_len);
4459 skb->protocol = eth_type_trans(skb, dev);
4462 #ifdef CONFIG_S2IO_NAPI
4463 netif_receive_skb(skb);
4468 dev->last_rx = jiffies;
4470 sp->stats.rx_packets++;
4471 #ifndef CONFIG_2BUFF_MODE
4472 sp->stats.rx_bytes += len;
4474 sp->stats.rx_bytes += buf0_len + buf2_len;
4477 atomic_dec(&sp->rx_bufs_left[ring_no]);
4478 rxdp->Host_Control = 0;
4483 * s2io_link - stops/starts the Tx queue.
4484 * @sp : private member of the device structure, which is a pointer to the
4485 * s2io_nic structure.
4486 * @link : inidicates whether link is UP/DOWN.
4488 * This function stops/starts the Tx queue depending on whether the link
4489 * status of the NIC is is down or up. This is called by the Alarm
4490 * interrupt handler whenever a link change interrupt comes up.
4495 void s2io_link(nic_t * sp, int link)
4497 struct net_device *dev = (struct net_device *) sp->dev;
4499 if (link != sp->last_link_state) {
4500 if (link == LINK_DOWN) {
4501 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
4502 netif_carrier_off(dev);
4504 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
4505 netif_carrier_on(dev);
4508 sp->last_link_state = link;
4512 * get_xena_rev_id - to identify revision ID of xena.
4513 * @pdev : PCI Dev structure
4515 * Function to identify the Revision ID of xena.
4517 * returns the revision ID of the device.
4520 int get_xena_rev_id(struct pci_dev *pdev)
4524 ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
4529 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
4530 * @sp : private member of the device structure, which is a pointer to the
4531 * s2io_nic structure.
4533 * This function initializes a few of the PCI and PCI-X configuration registers
4534 * with recommended values.
4539 static void s2io_init_pci(nic_t * sp)
4543 /* Enable Data Parity Error Recovery in PCI-X command register. */
4544 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4546 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4547 (sp->pcix_cmd | 1));
4548 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4551 /* Set the PErr Response bit in PCI command register. */
4552 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
4553 pci_write_config_word(sp->pdev, PCI_COMMAND,
4554 (pci_cmd | PCI_COMMAND_PARITY));
4555 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
4557 /* Set MMRB count to 1024 in PCI-X Command register. */
4558 sp->pcix_cmd &= 0xFFF3;
4559 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, (sp->pcix_cmd | (0x1 << 2))); /* MMRBC 1K */
4560 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4563 /* Setting Maximum outstanding splits based on system type. */
4564 sp->pcix_cmd &= 0xFF8F;
4566 sp->pcix_cmd |= XENA_MAX_OUTSTANDING_SPLITS(0x1); /* 2 splits. */
4567 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4569 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4571 /* Forcibly disabling relaxed ordering capability of the card. */
4572 sp->pcix_cmd &= 0xfffd;
4573 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4575 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4579 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@s2io.com>");
4580 MODULE_LICENSE("GPL");
4581 module_param(tx_fifo_num, int, 0);
4582 module_param_array(tx_fifo_len, int, NULL, 0);
4583 module_param(rx_ring_num, int, 0);
4584 module_param_array(rx_ring_sz, int, NULL, 0);
4585 module_param(Stats_refresh_time, int, 0);
4586 module_param(rmac_pause_time, int, 0);
4587 module_param(mc_pause_threshold_q0q3, int, 0);
4588 module_param(mc_pause_threshold_q4q7, int, 0);
4589 module_param(shared_splits, int, 0);
4590 module_param(tmac_util_period, int, 0);
4591 module_param(rmac_util_period, int, 0);
4592 #ifndef CONFIG_S2IO_NAPI
4593 module_param(indicate_max_pkts, int, 0);
4596 * s2io_init_nic - Initialization of the adapter .
4597 * @pdev : structure containing the PCI related information of the device.
4598 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
4600 * The function initializes an adapter identified by the pci_dec structure.
4601 * All OS related initialization including memory and device structure and
4602 * initlaization of the device private variable is done. Also the swapper
4603 * control register is initialized to enable read and write into the I/O
4604 * registers of the device.
4606 * returns 0 on success and negative on failure.
4609 static int __devinit
4610 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4613 struct net_device *dev;
4614 char *dev_name = "S2IO 10GE NIC";
4616 int dma_flag = FALSE;
4617 u32 mac_up, mac_down;
4618 u64 val64 = 0, tmp64 = 0;
4619 XENA_dev_config_t __iomem *bar0 = NULL;
4621 mac_info_t *mac_control;
4622 struct config_param *config;
4625 DBG_PRINT(ERR_DBG, "Loading S2IO driver with %s\n",
4626 s2io_driver_version);
4628 if ((ret = pci_enable_device(pdev))) {
4630 "s2io_init_nic: pci_enable_device failed\n");
4634 if (!pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
4635 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
4638 if (pci_set_consistent_dma_mask
4639 (pdev, 0xffffffffffffffffULL)) {
4641 "Unable to obtain 64bit DMA for \
4642 consistent allocations\n");
4643 pci_disable_device(pdev);
4646 } else if (!pci_set_dma_mask(pdev, 0xffffffffUL)) {
4647 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
4649 pci_disable_device(pdev);
4653 if (pci_request_regions(pdev, s2io_driver_name)) {
4654 DBG_PRINT(ERR_DBG, "Request Regions failed\n"),
4655 pci_disable_device(pdev);
4659 dev = alloc_etherdev(sizeof(nic_t));
4661 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
4662 pci_disable_device(pdev);
4663 pci_release_regions(pdev);
4667 pci_set_master(pdev);
4668 pci_set_drvdata(pdev, dev);
4669 SET_MODULE_OWNER(dev);
4670 SET_NETDEV_DEV(dev, &pdev->dev);
4672 /* Private member variable initialized to s2io NIC structure */
4674 memset(sp, 0, sizeof(nic_t));
4677 sp->vendor_id = pdev->vendor;
4678 sp->device_id = pdev->device;
4679 sp->high_dma_flag = dma_flag;
4680 sp->irq = pdev->irq;
4681 sp->device_enabled_once = FALSE;
4682 strcpy(sp->name, dev_name);
4684 /* Initialize some PCI/PCI-X fields of the NIC. */
4688 * Setting the device configuration parameters.
4689 * Most of these parameters can be specified by the user during
4690 * module insertion as they are module loadable parameters. If
4691 * these parameters are not not specified during load time, they
4692 * are initialized with default values.
4694 mac_control = &sp->mac_control;
4695 config = &sp->config;
4697 /* Tx side parameters. */
4698 tx_fifo_len[0] = DEFAULT_FIFO_LEN; /* Default value. */
4699 config->tx_fifo_num = tx_fifo_num;
4700 for (i = 0; i < MAX_TX_FIFOS; i++) {
4701 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
4702 config->tx_cfg[i].fifo_priority = i;
4705 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
4706 for (i = 0; i < config->tx_fifo_num; i++) {
4707 config->tx_cfg[i].f_no_snoop =
4708 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
4709 if (config->tx_cfg[i].fifo_len < 65) {
4710 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
4714 config->max_txds = MAX_SKB_FRAGS;
4716 /* Rx side parameters. */
4717 rx_ring_sz[0] = SMALL_BLK_CNT; /* Default value. */
4718 config->rx_ring_num = rx_ring_num;
4719 for (i = 0; i < MAX_RX_RINGS; i++) {
4720 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
4721 (MAX_RXDS_PER_BLOCK + 1);
4722 config->rx_cfg[i].ring_priority = i;
4725 for (i = 0; i < rx_ring_num; i++) {
4726 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
4727 config->rx_cfg[i].f_no_snoop =
4728 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
4731 /* Setting Mac Control parameters */
4732 mac_control->rmac_pause_time = rmac_pause_time;
4733 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
4734 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
4737 /* Initialize Ring buffer parameters. */
4738 for (i = 0; i < config->rx_ring_num; i++)
4739 atomic_set(&sp->rx_bufs_left[i], 0);
4741 /* initialize the shared memory used by the NIC and the host */
4742 if (init_shared_mem(sp)) {
4743 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
4746 goto mem_alloc_failed;
4749 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
4750 pci_resource_len(pdev, 0));
4752 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n",
4755 goto bar0_remap_failed;
4758 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
4759 pci_resource_len(pdev, 2));
4761 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n",
4764 goto bar1_remap_failed;
4767 dev->irq = pdev->irq;
4768 dev->base_addr = (unsigned long) sp->bar0;
4770 /* Initializing the BAR1 address as the start of the FIFO pointer. */
4771 for (j = 0; j < MAX_TX_FIFOS; j++) {
4772 mac_control->tx_FIFO_start[j] = (TxFIFO_element_t __iomem *)
4773 (sp->bar1 + (j * 0x00020000));
4776 /* Driver entry points */
4777 dev->open = &s2io_open;
4778 dev->stop = &s2io_close;
4779 dev->hard_start_xmit = &s2io_xmit;
4780 dev->get_stats = &s2io_get_stats;
4781 dev->set_multicast_list = &s2io_set_multicast;
4782 dev->do_ioctl = &s2io_ioctl;
4783 dev->change_mtu = &s2io_change_mtu;
4784 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
4786 * will use eth_mac_addr() for dev->set_mac_address
4787 * mac address will be set every time dev->open() is called
4789 #ifdef CONFIG_S2IO_NAPI
4790 dev->poll = s2io_poll;
4794 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
4795 if (sp->high_dma_flag == TRUE)
4796 dev->features |= NETIF_F_HIGHDMA;
4798 dev->features |= NETIF_F_TSO;
4801 dev->tx_timeout = &s2io_tx_watchdog;
4802 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
4803 INIT_WORK(&sp->rst_timer_task,
4804 (void (*)(void *)) s2io_restart_nic, dev);
4805 INIT_WORK(&sp->set_link_task,
4806 (void (*)(void *)) s2io_set_link, sp);
4808 pci_save_state(sp->pdev);
4810 /* Setting swapper control on the NIC, for proper reset operation */
4811 if (s2io_set_swapper(sp)) {
4812 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
4815 goto set_swap_failed;
4818 /* Fix for all "FFs" MAC address problems observed on Alpha platforms */
4819 fix_mac_address(sp);
4823 * Setting swapper control on the NIC, so the MAC address can be read.
4825 if (s2io_set_swapper(sp)) {
4827 "%s: S2IO: swapper settings are wrong\n",
4830 goto set_swap_failed;
4834 * MAC address initialization.
4835 * For now only one mac address will be read and used.
4838 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4839 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
4840 writeq(val64, &bar0->rmac_addr_cmd_mem);
4841 wait_for_cmd_complete(sp);
4843 tmp64 = readq(&bar0->rmac_addr_data0_mem);
4844 mac_down = (u32) tmp64;
4845 mac_up = (u32) (tmp64 >> 32);
4847 memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
4849 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
4850 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
4851 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
4852 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
4853 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
4854 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
4857 "DEFAULT MAC ADDR:0x%02x-%02x-%02x-%02x-%02x-%02x\n",
4858 sp->def_mac_addr[0].mac_addr[0],
4859 sp->def_mac_addr[0].mac_addr[1],
4860 sp->def_mac_addr[0].mac_addr[2],
4861 sp->def_mac_addr[0].mac_addr[3],
4862 sp->def_mac_addr[0].mac_addr[4],
4863 sp->def_mac_addr[0].mac_addr[5]);
4865 /* Set the factory defined MAC address initially */
4866 dev->addr_len = ETH_ALEN;
4867 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
4870 * Initialize the tasklet status and link state flags
4871 * and the card statte parameter
4873 atomic_set(&(sp->card_state), 0);
4874 sp->tasklet_status = 0;
4878 /* Initialize spinlocks */
4879 spin_lock_init(&sp->tx_lock);
4880 #ifndef CONFIG_S2IO_NAPI
4881 spin_lock_init(&sp->put_lock);
4885 * SXE-002: Configure link and activity LED to init state
4888 subid = sp->pdev->subsystem_device;
4889 if ((subid & 0xFF) >= 0x07) {
4890 val64 = readq(&bar0->gpio_control);
4891 val64 |= 0x0000800000000000ULL;
4892 writeq(val64, &bar0->gpio_control);
4893 val64 = 0x0411040400000000ULL;
4894 writeq(val64, (void __iomem *) bar0 + 0x2700);
4895 val64 = readq(&bar0->gpio_control);
4898 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
4900 if (register_netdev(dev)) {
4901 DBG_PRINT(ERR_DBG, "Device registration failed\n");
4903 goto register_failed;
4907 * Make Link state as off at this point, when the Link change
4908 * interrupt comes the state will be automatically changed to
4911 netif_carrier_off(dev);
4912 sp->last_link_state = LINK_DOWN;
4923 free_shared_mem(sp);
4924 pci_disable_device(pdev);
4925 pci_release_regions(pdev);
4926 pci_set_drvdata(pdev, NULL);
4933 * s2io_rem_nic - Free the PCI device
4934 * @pdev: structure containing the PCI related information of the device.
4935 * Description: This function is called by the Pci subsystem to release a
4936 * PCI device and free up all resource held up by the device. This could
4937 * be in response to a Hot plug event or when the driver is to be removed
4941 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
4943 struct net_device *dev =
4944 (struct net_device *) pci_get_drvdata(pdev);
4948 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
4953 unregister_netdev(dev);
4955 free_shared_mem(sp);
4958 pci_disable_device(pdev);
4959 pci_release_regions(pdev);
4960 pci_set_drvdata(pdev, NULL);
4966 * s2io_starter - Entry point for the driver
4967 * Description: This function is the entry point for the driver. It verifies
4968 * the module loadable parameters and initializes PCI configuration space.
4971 int __init s2io_starter(void)
4973 return pci_module_init(&s2io_driver);
4977 * s2io_closer - Cleanup routine for the driver
4978 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
4981 void s2io_closer(void)
4983 pci_unregister_driver(&s2io_driver);
4984 DBG_PRINT(INIT_DBG, "cleanup done\n");
4987 module_init(s2io_starter);
4988 module_exit(s2io_closer);