drivers/net/s2io.c

   1 /************************************************************************
   2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2005 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  *
  13  * Credits:
  14  * Jeff Garzik          : For pointing out the improper error condition
  15  *                        check in the s2io_xmit routine and also some
  16  *                        issues in the Tx watch dog function. Also for
  17  *                        patiently answering all those innumerable
  18  *                        questions regaring the 2.6 porting issues.
  19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
  20  *                        macros available only in 2.6 Kernel.
  21  * Francois Romieu      : For pointing out all code part that were
  22  *                        deprecated and also styling related comments.
  23  * Grant Grundler       : For helping me get rid of some Architecture
  24  *                        dependent code.
  25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
  26  *
  27  * The module loadable parameters that are supported by the driver and a brief
  28  * explaination of all the variables.
  29  * rx_ring_num : This can be used to program the number of receive rings used
  30  * in the driver.
  31  * rx_ring_sz: This defines the number of descriptors each ring can have. This
  32  * is also an array of size 8.
  33  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  34  *              values are 1, 2 and 3.
  35  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  36  * tx_fifo_len: This too is an array of 8. Each element defines the number of
  37  * Tx descriptors that can be associated with each corresponding FIFO.
  38  ************************************************************************/
  39
  40 #include <linux/config.h>
  41 #include <linux/module.h>
  42 #include <linux/types.h>
  43 #include <linux/errno.h>
  44 #include <linux/ioport.h>
  45 #include <linux/pci.h>
  46 #include <linux/dma-mapping.h>
  47 #include <linux/kernel.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/etherdevice.h>
  50 #include <linux/skbuff.h>
  51 #include <linux/init.h>
  52 #include <linux/delay.h>
  53 #include <linux/stddef.h>
  54 #include <linux/ioctl.h>
  55 #include <linux/timex.h>
  56 #include <linux/sched.h>
  57 #include <linux/ethtool.h>
  58 #include <linux/workqueue.h>
  59 #include <linux/if_vlan.h>
  60
  61 #include <asm/system.h>
  62 #include <asm/uaccess.h>
  63 #include <asm/io.h>
  64
  65 /* local include */
  66 #include "s2io.h"
  67 #include "s2io-regs.h"
  68
  69 #define DRV_VERSION "Version 2.0.9.4"
  70
  71 /* S2io Driver name & version. */
  72 static char s2io_driver_name[] = "Neterion";
  73 static char s2io_driver_version[] = DRV_VERSION;
  74
  75 int rxd_size[4] = {32,48,48,64};
  76 int rxd_count[4] = {127,85,85,63};
  77
  78 static inline int RXD_IS_UP2DT(RxD_t *rxdp)
  79 {
  80         int ret;
  81
  82         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
  83                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
  84
  85         return ret;
  86 }
  87
  88 /*
  89  * Cards with following subsystem_id have a link state indication
  90  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
  91  * macro below identifies these cards given the subsystem_id.
  92  */
  93 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
  94         (dev_type == XFRAME_I_DEVICE) ?                 \
  95                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
  96                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
  97
  98 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
  99                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
 100 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
 101 #define PANIC   1
 102 #define LOW     2
 103 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
 104 {
 105         int level = 0;
 106         mac_info_t *mac_control;
 107
 108         mac_control = &sp->mac_control;
 109         if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16) {
 110                 level = LOW;
 111                 if (rxb_size <= rxd_count[sp->rxd_mode]) {
 112                         level = PANIC;
 113                 }
 114         }
 115
 116         return level;
 117 }
 118
 119 /* Ethtool related variables and Macros. */
 120 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
 121         "Register test\t(offline)",
 122         "Eeprom test\t(offline)",
 123         "Link test\t(online)",
 124         "RLDRAM test\t(offline)",
 125         "BIST Test\t(offline)"
 126 };
 127
 128 static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
 129         {"tmac_frms"},
 130         {"tmac_data_octets"},
 131         {"tmac_drop_frms"},
 132         {"tmac_mcst_frms"},
 133         {"tmac_bcst_frms"},
 134         {"tmac_pause_ctrl_frms"},
 135         {"tmac_any_err_frms"},
 136         {"tmac_vld_ip_octets"},
 137         {"tmac_vld_ip"},
 138         {"tmac_drop_ip"},
 139         {"tmac_icmp"},
 140         {"tmac_rst_tcp"},
 141         {"tmac_tcp"},
 142         {"tmac_udp"},
 143         {"rmac_vld_frms"},
 144         {"rmac_data_octets"},
 145         {"rmac_fcs_err_frms"},
 146         {"rmac_drop_frms"},
 147         {"rmac_vld_mcst_frms"},
 148         {"rmac_vld_bcst_frms"},
 149         {"rmac_in_rng_len_err_frms"},
 150         {"rmac_long_frms"},
 151         {"rmac_pause_ctrl_frms"},
 152         {"rmac_discarded_frms"},
 153         {"rmac_usized_frms"},
 154         {"rmac_osized_frms"},
 155         {"rmac_frag_frms"},
 156         {"rmac_jabber_frms"},
 157         {"rmac_ip"},
 158         {"rmac_ip_octets"},
 159         {"rmac_hdr_err_ip"},
 160         {"rmac_drop_ip"},
 161         {"rmac_icmp"},
 162         {"rmac_tcp"},
 163         {"rmac_udp"},
 164         {"rmac_err_drp_udp"},
 165         {"rmac_pause_cnt"},
 166         {"rmac_accepted_ip"},
 167         {"rmac_err_tcp"},
 168         {"\n DRIVER STATISTICS"},
 169         {"single_bit_ecc_errs"},
 170         {"double_bit_ecc_errs"},
 171 };
 172
 173 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
 174 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
 175
 176 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
 177 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
 178
 179 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
 180                         init_timer(&timer);                     \
 181                         timer.function = handle;                \
 182                         timer.data = (unsigned long) arg;       \
 183                         mod_timer(&timer, (jiffies + exp))      \
 184
 185 /* Add the vlan */
 186 static void s2io_vlan_rx_register(struct net_device *dev,
 187                                         struct vlan_group *grp)
 188 {
 189         nic_t *nic = dev->priv;
 190         unsigned long flags;
 191
 192         spin_lock_irqsave(&nic->tx_lock, flags);
 193         nic->vlgrp = grp;
 194         spin_unlock_irqrestore(&nic->tx_lock, flags);
 195 }
 196
 197 /* Unregister the vlan */
 198 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
 199 {
 200         nic_t *nic = dev->priv;
 201         unsigned long flags;
 202
 203         spin_lock_irqsave(&nic->tx_lock, flags);
 204         if (nic->vlgrp)
 205                 nic->vlgrp->vlan_devices[vid] = NULL;
 206         spin_unlock_irqrestore(&nic->tx_lock, flags);
 207 }
 208
 209 /*
 210  * Constants to be programmed into the Xena's registers, to configure
 211  * the XAUI.
 212  */
 213
 214 #define SWITCH_SIGN     0xA5A5A5A5A5A5A5A5ULL
 215 #define END_SIGN        0x0
 216
 217 static u64 herc_act_dtx_cfg[] = {
 218         /* Set address */
 219         0x8000051536750000ULL, 0x80000515367500E0ULL,
 220         /* Write data */
 221         0x8000051536750004ULL, 0x80000515367500E4ULL,
 222         /* Set address */
 223         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
 224         /* Write data */
 225         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
 226         /* Set address */
 227         0x801205150D440000ULL, 0x801205150D4400E0ULL,
 228         /* Write data */
 229         0x801205150D440004ULL, 0x801205150D4400E4ULL,
 230         /* Set address */
 231         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
 232         /* Write data */
 233         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 234         /* Done */
 235         END_SIGN
 236 };
 237
 238 static u64 xena_mdio_cfg[] = {
 239         /* Reset PMA PLL */
 240         0xC001010000000000ULL, 0xC0010100000000E0ULL,
 241         0xC0010100008000E4ULL,
 242         /* Remove Reset from PMA PLL */
 243         0xC001010000000000ULL, 0xC0010100000000E0ULL,
 244         0xC0010100000000E4ULL,
 245         END_SIGN
 246 };
 247
 248 static u64 xena_dtx_cfg[] = {
 249         0x8000051500000000ULL, 0x80000515000000E0ULL,
 250         0x80000515D93500E4ULL, 0x8001051500000000ULL,
 251         0x80010515000000E0ULL, 0x80010515001E00E4ULL,
 252         0x8002051500000000ULL, 0x80020515000000E0ULL,
 253         0x80020515F21000E4ULL,
 254         /* Set PADLOOPBACKN */
 255         0x8002051500000000ULL, 0x80020515000000E0ULL,
 256         0x80020515B20000E4ULL, 0x8003051500000000ULL,
 257         0x80030515000000E0ULL, 0x80030515B20000E4ULL,
 258         0x8004051500000000ULL, 0x80040515000000E0ULL,
 259         0x80040515B20000E4ULL, 0x8005051500000000ULL,
 260         0x80050515000000E0ULL, 0x80050515B20000E4ULL,
 261         SWITCH_SIGN,
 262         /* Remove PADLOOPBACKN */
 263         0x8002051500000000ULL, 0x80020515000000E0ULL,
 264         0x80020515F20000E4ULL, 0x8003051500000000ULL,
 265         0x80030515000000E0ULL, 0x80030515F20000E4ULL,
 266         0x8004051500000000ULL, 0x80040515000000E0ULL,
 267         0x80040515F20000E4ULL, 0x8005051500000000ULL,
 268         0x80050515000000E0ULL, 0x80050515F20000E4ULL,
 269         END_SIGN
 270 };
 271
 272 /*
 273  * Constants for Fixing the MacAddress problem seen mostly on
 274  * Alpha machines.
 275  */
 276 static u64 fix_mac[] = {
 277         0x0060000000000000ULL, 0x0060600000000000ULL,
 278         0x0040600000000000ULL, 0x0000600000000000ULL,
 279         0x0020600000000000ULL, 0x0060600000000000ULL,
 280         0x0020600000000000ULL, 0x0060600000000000ULL,
 281         0x0020600000000000ULL, 0x0060600000000000ULL,
 282         0x0020600000000000ULL, 0x0060600000000000ULL,
 283         0x0020600000000000ULL, 0x0060600000000000ULL,
 284         0x0020600000000000ULL, 0x0060600000000000ULL,
 285         0x0020600000000000ULL, 0x0060600000000000ULL,
 286         0x0020600000000000ULL, 0x0060600000000000ULL,
 287         0x0020600000000000ULL, 0x0060600000000000ULL,
 288         0x0020600000000000ULL, 0x0060600000000000ULL,
 289         0x0020600000000000ULL, 0x0000600000000000ULL,
 290         0x0040600000000000ULL, 0x0060600000000000ULL,
 291         END_SIGN
 292 };
 293
 294 /* Module Loadable parameters. */
 295 static unsigned int tx_fifo_num = 1;
 296 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
 297     {[0 ...(MAX_TX_FIFOS - 1)] = 0 };
 298 static unsigned int rx_ring_num = 1;
 299 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
 300     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 301 static unsigned int rts_frm_len[MAX_RX_RINGS] =
 302     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 303 static unsigned int rx_ring_mode = 1;
 304 static unsigned int use_continuous_tx_intrs = 1;
 305 static unsigned int rmac_pause_time = 65535;
 306 static unsigned int mc_pause_threshold_q0q3 = 187;
 307 static unsigned int mc_pause_threshold_q4q7 = 187;
 308 static unsigned int shared_splits;
 309 static unsigned int tmac_util_period = 5;
 310 static unsigned int rmac_util_period = 5;
 311 static unsigned int bimodal = 0;
 312 static unsigned int l3l4hdr_size = 128;
 313 #ifndef CONFIG_S2IO_NAPI
 314 static unsigned int indicate_max_pkts;
 315 #endif
 316 /* Frequency of Rx desc syncs expressed as power of 2 */
 317 static unsigned int rxsync_frequency = 3;
 318 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
 319 static unsigned int intr_type = 0;
 320
 321 /*
 322  * S2IO device table.
 323  * This table lists all the devices that this driver supports.
 324  */
 325 static struct pci_device_id s2io_tbl[] __devinitdata = {
 326         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
 327          PCI_ANY_ID, PCI_ANY_ID},
 328         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
 329          PCI_ANY_ID, PCI_ANY_ID},
 330         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
 331          PCI_ANY_ID, PCI_ANY_ID},
 332         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
 333          PCI_ANY_ID, PCI_ANY_ID},
 334         {0,}
 335 };
 336
 337 MODULE_DEVICE_TABLE(pci, s2io_tbl);
 338
 339 static struct pci_driver s2io_driver = {
 340       .name = "S2IO",
 341       .id_table = s2io_tbl,
 342       .probe = s2io_init_nic,
 343       .remove = __devexit_p(s2io_rem_nic),
 344 };
 345
 346 /* A simplifier macro used both by init and free shared_mem Fns(). */
 347 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
 348
 349 /**
 350  * init_shared_mem - Allocation and Initialization of Memory
 351  * @nic: Device private variable.
 352  * Description: The function allocates all the memory areas shared
 353  * between the NIC and the driver. This includes Tx descriptors,
 354  * Rx descriptors and the statistics block.
 355  */
 356
 357 static int init_shared_mem(struct s2io_nic *nic)
 358 {
 359         u32 size;
 360         void *tmp_v_addr, *tmp_v_addr_next;
 361         dma_addr_t tmp_p_addr, tmp_p_addr_next;
 362         RxD_block_t *pre_rxd_blk = NULL;
 363         int i, j, blk_cnt, rx_sz, tx_sz;
 364         int lst_size, lst_per_page;
 365         struct net_device *dev = nic->dev;
 366         unsigned long tmp;
 367         buffAdd_t *ba;
 368
 369         mac_info_t *mac_control;
 370         struct config_param *config;
 371
 372         mac_control = &nic->mac_control;
 373         config = &nic->config;
 374
 375
 376         /* Allocation and initialization of TXDLs in FIOFs */
 377         size = 0;
 378         for (i = 0; i < config->tx_fifo_num; i++) {
 379                 size += config->tx_cfg[i].fifo_len;
 380         }
 381         if (size > MAX_AVAILABLE_TXDS) {
 382                 DBG_PRINT(ERR_DBG, "%s: Requested TxDs too high, ",
 383                           __FUNCTION__);
 384                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
 385                 return FAILURE;
 386         }
 387
 388         lst_size = (sizeof(TxD_t) * config->max_txds);
 389         tx_sz = lst_size * size;
 390         lst_per_page = PAGE_SIZE / lst_size;
 391
 392         for (i = 0; i < config->tx_fifo_num; i++) {
 393                 int fifo_len = config->tx_cfg[i].fifo_len;
 394                 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
 395                 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
 396                                                           GFP_KERNEL);
 397                 if (!mac_control->fifos[i].list_info) {
 398                         DBG_PRINT(ERR_DBG,
 399                                   "Malloc failed for list_info\n");
 400                         return -ENOMEM;
 401                 }
 402                 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
 403         }
 404         for (i = 0; i < config->tx_fifo_num; i++) {
 405                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 406                                                 lst_per_page);
 407                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
 408                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
 409                     config->tx_cfg[i].fifo_len - 1;
 410                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
 411                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
 412                     config->tx_cfg[i].fifo_len - 1;
 413                 mac_control->fifos[i].fifo_no = i;
 414                 mac_control->fifos[i].nic = nic;
 415                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
 416
 417                 for (j = 0; j < page_num; j++) {
 418                         int k = 0;
 419                         dma_addr_t tmp_p;
 420                         void *tmp_v;
 421                         tmp_v = pci_alloc_consistent(nic->pdev,
 422                                                      PAGE_SIZE, &tmp_p);
 423                         if (!tmp_v) {
 424                                 DBG_PRINT(ERR_DBG,
 425                                           "pci_alloc_consistent ");
 426                                 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
 427                                 return -ENOMEM;
 428                         }
 429                         /* If we got a zero DMA address(can happen on
 430                          * certain platforms like PPC), reallocate.
 431                          * Store virtual address of page we don't want,
 432                          * to be freed later.
 433                          */
 434                         if (!tmp_p) {
 435                                 mac_control->zerodma_virt_addr = tmp_v;
 436                                 DBG_PRINT(INIT_DBG,
 437                                 "%s: Zero DMA address for TxDL. ", dev->name);
 438                                 DBG_PRINT(INIT_DBG,
 439                                 "Virtual address %p\n", tmp_v);
 440                                 tmp_v = pci_alloc_consistent(nic->pdev,
 441                                                      PAGE_SIZE, &tmp_p);
 442                                 if (!tmp_v) {
 443                                         DBG_PRINT(ERR_DBG,
 444                                           "pci_alloc_consistent ");
 445                                         DBG_PRINT(ERR_DBG, "failed for TxDL\n");
 446                                         return -ENOMEM;
 447                                 }
 448                         }
 449                         while (k < lst_per_page) {
 450                                 int l = (j * lst_per_page) + k;
 451                                 if (l == config->tx_cfg[i].fifo_len)
 452                                         break;
 453                                 mac_control->fifos[i].list_info[l].list_virt_addr =
 454                                     tmp_v + (k * lst_size);
 455                                 mac_control->fifos[i].list_info[l].list_phy_addr =
 456                                     tmp_p + (k * lst_size);
 457                                 k++;
 458                         }
 459                 }
 460         }
 461
 462         nic->ufo_in_band_v = kmalloc((sizeof(u64) * size), GFP_KERNEL);
 463         if (!nic->ufo_in_band_v)
 464                 return -ENOMEM;
 465
 466         /* Allocation and initialization of RXDs in Rings */
 467         size = 0;
 468         for (i = 0; i < config->rx_ring_num; i++) {
 469                 if (config->rx_cfg[i].num_rxd %
 470                     (rxd_count[nic->rxd_mode] + 1)) {
 471                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
 472                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
 473                                   i);
 474                         DBG_PRINT(ERR_DBG, "RxDs per Block");
 475                         return FAILURE;
 476                 }
 477                 size += config->rx_cfg[i].num_rxd;
 478                 mac_control->rings[i].block_count =
 479                         config->rx_cfg[i].num_rxd /
 480                         (rxd_count[nic->rxd_mode] + 1 );
 481                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
 482                         mac_control->rings[i].block_count;
 483         }
 484         if (nic->rxd_mode == RXD_MODE_1)
 485                 size = (size * (sizeof(RxD1_t)));
 486         else
 487                 size = (size * (sizeof(RxD3_t)));
 488         rx_sz = size;
 489
 490         for (i = 0; i < config->rx_ring_num; i++) {
 491                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
 492                 mac_control->rings[i].rx_curr_get_info.offset = 0;
 493                 mac_control->rings[i].rx_curr_get_info.ring_len =
 494                     config->rx_cfg[i].num_rxd - 1;
 495                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
 496                 mac_control->rings[i].rx_curr_put_info.offset = 0;
 497                 mac_control->rings[i].rx_curr_put_info.ring_len =
 498                     config->rx_cfg[i].num_rxd - 1;
 499                 mac_control->rings[i].nic = nic;
 500                 mac_control->rings[i].ring_no = i;
 501
 502                 blk_cnt = config->rx_cfg[i].num_rxd /
 503                                 (rxd_count[nic->rxd_mode] + 1);
 504                 /*  Allocating all the Rx blocks */
 505                 for (j = 0; j < blk_cnt; j++) {
 506                         rx_block_info_t *rx_blocks;
 507                         int l;
 508
 509                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
 510                         size = SIZE_OF_BLOCK; //size is always page size
 511                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
 512                                                           &tmp_p_addr);
 513                         if (tmp_v_addr == NULL) {
 514                                 /*
 515                                  * In case of failure, free_shared_mem()
 516                                  * is called, which should free any
 517                                  * memory that was alloced till the
 518                                  * failure happened.
 519                                  */
 520                                 rx_blocks->block_virt_addr = tmp_v_addr;
 521                                 return -ENOMEM;
 522                         }
 523                         memset(tmp_v_addr, 0, size);
 524                         rx_blocks->block_virt_addr = tmp_v_addr;
 525                         rx_blocks->block_dma_addr = tmp_p_addr;
 526                         rx_blocks->rxds = kmalloc(sizeof(rxd_info_t)*
 527                                                   rxd_count[nic->rxd_mode],
 528                                                   GFP_KERNEL);
 529                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
 530                                 rx_blocks->rxds[l].virt_addr =
 531                                         rx_blocks->block_virt_addr +
 532                                         (rxd_size[nic->rxd_mode] * l);
 533                                 rx_blocks->rxds[l].dma_addr =
 534                                         rx_blocks->block_dma_addr +
 535                                         (rxd_size[nic->rxd_mode] * l);
 536                         }
 537
 538                         mac_control->rings[i].rx_blocks[j].block_virt_addr =
 539                                 tmp_v_addr;
 540                         mac_control->rings[i].rx_blocks[j].block_dma_addr =
 541                                 tmp_p_addr;
 542                 }
 543                 /* Interlinking all Rx Blocks */
 544                 for (j = 0; j < blk_cnt; j++) {
 545                         tmp_v_addr =
 546                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
 547                         tmp_v_addr_next =
 548                                 mac_control->rings[i].rx_blocks[(j + 1) %
 549                                               blk_cnt].block_virt_addr;
 550                         tmp_p_addr =
 551                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
 552                         tmp_p_addr_next =
 553                                 mac_control->rings[i].rx_blocks[(j + 1) %
 554                                               blk_cnt].block_dma_addr;
 555
 556                         pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
 557                         pre_rxd_blk->reserved_2_pNext_RxD_block =
 558                             (unsigned long) tmp_v_addr_next;
 559                         pre_rxd_blk->pNext_RxD_Blk_physical =
 560                             (u64) tmp_p_addr_next;
 561                 }
 562         }
 563         if (nic->rxd_mode >= RXD_MODE_3A) {
 564                 /*
 565                  * Allocation of Storages for buffer addresses in 2BUFF mode
 566                  * and the buffers as well.
 567                  */
 568                 for (i = 0; i < config->rx_ring_num; i++) {
 569                         blk_cnt = config->rx_cfg[i].num_rxd /
 570                            (rxd_count[nic->rxd_mode]+ 1);
 571                         mac_control->rings[i].ba =
 572                                 kmalloc((sizeof(buffAdd_t *) * blk_cnt),
 573                                      GFP_KERNEL);
 574                         if (!mac_control->rings[i].ba)
 575                                 return -ENOMEM;
 576                         for (j = 0; j < blk_cnt; j++) {
 577                                 int k = 0;
 578                                 mac_control->rings[i].ba[j] =
 579                                         kmalloc((sizeof(buffAdd_t) *
 580                                                 (rxd_count[nic->rxd_mode] + 1)),
 581                                                 GFP_KERNEL);
 582                                 if (!mac_control->rings[i].ba[j])
 583                                         return -ENOMEM;
 584                                 while (k != rxd_count[nic->rxd_mode]) {
 585                                         ba = &mac_control->rings[i].ba[j][k];
 586
 587                                         ba->ba_0_org = (void *) kmalloc
 588                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
 589                                         if (!ba->ba_0_org)
 590                                                 return -ENOMEM;
 591                                         tmp = (unsigned long)ba->ba_0_org;
 592                                         tmp += ALIGN_SIZE;
 593                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 594                                         ba->ba_0 = (void *) tmp;
 595
 596                                         ba->ba_1_org = (void *) kmalloc
 597                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
 598                                         if (!ba->ba_1_org)
 599                                                 return -ENOMEM;
 600                                         tmp = (unsigned long) ba->ba_1_org;
 601                                         tmp += ALIGN_SIZE;
 602                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 603                                         ba->ba_1 = (void *) tmp;
 604                                         k++;
 605                                 }
 606                         }
 607                 }
 608         }
 609
 610         /* Allocation and initialization of Statistics block */
 611         size = sizeof(StatInfo_t);
 612         mac_control->stats_mem = pci_alloc_consistent
 613             (nic->pdev, size, &mac_control->stats_mem_phy);
 614
 615         if (!mac_control->stats_mem) {
 616                 /*
 617                  * In case of failure, free_shared_mem() is called, which
 618                  * should free any memory that was alloced till the
 619                  * failure happened.
 620                  */
 621                 return -ENOMEM;
 622         }
 623         mac_control->stats_mem_sz = size;
 624
 625         tmp_v_addr = mac_control->stats_mem;
 626         mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
 627         memset(tmp_v_addr, 0, size);
 628         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
 629                   (unsigned long long) tmp_p_addr);
 630
 631         return SUCCESS;
 632 }
 633
 634 /**
 635  * free_shared_mem - Free the allocated Memory
 636  * @nic:  Device private variable.
 637  * Description: This function is to free all memory locations allocated by
 638  * the init_shared_mem() function and return it to the kernel.
 639  */
 640
 641 static void free_shared_mem(struct s2io_nic *nic)
 642 {
 643         int i, j, blk_cnt, size;
 644         void *tmp_v_addr;
 645         dma_addr_t tmp_p_addr;
 646         mac_info_t *mac_control;
 647         struct config_param *config;
 648         int lst_size, lst_per_page;
 649         struct net_device *dev = nic->dev;
 650
 651         if (!nic)
 652                 return;
 653
 654         mac_control = &nic->mac_control;
 655         config = &nic->config;
 656
 657         lst_size = (sizeof(TxD_t) * config->max_txds);
 658         lst_per_page = PAGE_SIZE / lst_size;
 659
 660         for (i = 0; i < config->tx_fifo_num; i++) {
 661                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 662                                                 lst_per_page);
 663                 for (j = 0; j < page_num; j++) {
 664                         int mem_blks = (j * lst_per_page);
 665                         if (!mac_control->fifos[i].list_info)
 666                                 return;
 667                         if (!mac_control->fifos[i].list_info[mem_blks].
 668                                  list_virt_addr)
 669                                 break;
 670                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 671                                             mac_control->fifos[i].
 672                                             list_info[mem_blks].
 673                                             list_virt_addr,
 674                                             mac_control->fifos[i].
 675                                             list_info[mem_blks].
 676                                             list_phy_addr);
 677                 }
 678                 /* If we got a zero DMA address during allocation,
 679                  * free the page now
 680                  */
 681                 if (mac_control->zerodma_virt_addr) {
 682                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 683                                             mac_control->zerodma_virt_addr,
 684                                             (dma_addr_t)0);
 685                         DBG_PRINT(INIT_DBG,
 686                                 "%s: Freeing TxDL with zero DMA addr. ",
 687                                 dev->name);
 688                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
 689                                 mac_control->zerodma_virt_addr);
 690                 }
 691                 kfree(mac_control->fifos[i].list_info);
 692         }
 693
 694         size = SIZE_OF_BLOCK;
 695         for (i = 0; i < config->rx_ring_num; i++) {
 696                 blk_cnt = mac_control->rings[i].block_count;
 697                 for (j = 0; j < blk_cnt; j++) {
 698                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
 699                                 block_virt_addr;
 700                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
 701                                 block_dma_addr;
 702                         if (tmp_v_addr == NULL)
 703                                 break;
 704                         pci_free_consistent(nic->pdev, size,
 705                                             tmp_v_addr, tmp_p_addr);
 706                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
 707                 }
 708         }
 709
 710         if (nic->rxd_mode >= RXD_MODE_3A) {
 711                 /* Freeing buffer storage addresses in 2BUFF mode. */
 712                 for (i = 0; i < config->rx_ring_num; i++) {
 713                         blk_cnt = config->rx_cfg[i].num_rxd /
 714                             (rxd_count[nic->rxd_mode] + 1);
 715                         for (j = 0; j < blk_cnt; j++) {
 716                                 int k = 0;
 717                                 if (!mac_control->rings[i].ba[j])
 718                                         continue;
 719                                 while (k != rxd_count[nic->rxd_mode]) {
 720                                         buffAdd_t *ba =
 721                                                 &mac_control->rings[i].ba[j][k];
 722                                         kfree(ba->ba_0_org);
 723                                         kfree(ba->ba_1_org);
 724                                         k++;
 725                                 }
 726                                 kfree(mac_control->rings[i].ba[j]);
 727                         }
 728                         kfree(mac_control->rings[i].ba);
 729                 }
 730         }
 731
 732         if (mac_control->stats_mem) {
 733                 pci_free_consistent(nic->pdev,
 734                                     mac_control->stats_mem_sz,
 735                                     mac_control->stats_mem,
 736                                     mac_control->stats_mem_phy);
 737         }
 738         if (nic->ufo_in_band_v)
 739                 kfree(nic->ufo_in_band_v);
 740 }
 741
 742 /**
 743  * s2io_verify_pci_mode -
 744  */
 745
 746 static int s2io_verify_pci_mode(nic_t *nic)
 747 {
 748         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 749         register u64 val64 = 0;
 750         int     mode;
 751
 752         val64 = readq(&bar0->pci_mode);
 753         mode = (u8)GET_PCI_MODE(val64);
 754
 755         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 756                 return -1;      /* Unknown PCI mode */
 757         return mode;
 758 }
 759
 760
 761 /**
 762  * s2io_print_pci_mode -
 763  */
 764 static int s2io_print_pci_mode(nic_t *nic)
 765 {
 766         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 767         register u64 val64 = 0;
 768         int     mode;
 769         struct config_param *config = &nic->config;
 770
 771         val64 = readq(&bar0->pci_mode);
 772         mode = (u8)GET_PCI_MODE(val64);
 773
 774         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 775                 return -1;      /* Unknown PCI mode */
 776
 777         if (val64 & PCI_MODE_32_BITS) {
 778                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
 779         } else {
 780                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
 781         }
 782
 783         switch(mode) {
 784                 case PCI_MODE_PCI_33:
 785                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
 786                         config->bus_speed = 33;
 787                         break;
 788                 case PCI_MODE_PCI_66:
 789                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
 790                         config->bus_speed = 133;
 791                         break;
 792                 case PCI_MODE_PCIX_M1_66:
 793                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
 794                         config->bus_speed = 133; /* Herc doubles the clock rate */
 795                         break;
 796                 case PCI_MODE_PCIX_M1_100:
 797                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
 798                         config->bus_speed = 200;
 799                         break;
 800                 case PCI_MODE_PCIX_M1_133:
 801                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
 802                         config->bus_speed = 266;
 803                         break;
 804                 case PCI_MODE_PCIX_M2_66:
 805                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
 806                         config->bus_speed = 133;
 807                         break;
 808                 case PCI_MODE_PCIX_M2_100:
 809                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
 810                         config->bus_speed = 200;
 811                         break;
 812                 case PCI_MODE_PCIX_M2_133:
 813                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
 814                         config->bus_speed = 266;
 815                         break;
 816                 default:
 817                         return -1;      /* Unsupported bus speed */
 818         }
 819
 820         return mode;
 821 }
 822
 823 /**
 824  *  init_nic - Initialization of hardware
 825  *  @nic: device peivate variable
 826  *  Description: The function sequentially configures every block
 827  *  of the H/W from their reset values.
 828  *  Return Value:  SUCCESS on success and
 829  *  '-1' on failure (endian settings incorrect).
 830  */
 831
 832 static int init_nic(struct s2io_nic *nic)
 833 {
 834         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 835         struct net_device *dev = nic->dev;
 836         register u64 val64 = 0;
 837         void __iomem *add;
 838         u32 time;
 839         int i, j;
 840         mac_info_t *mac_control;
 841         struct config_param *config;
 842         int mdio_cnt = 0, dtx_cnt = 0;
 843         unsigned long long mem_share;
 844         int mem_size;
 845
 846         mac_control = &nic->mac_control;
 847         config = &nic->config;
 848
 849         /* to set the swapper controle on the card */
 850         if(s2io_set_swapper(nic)) {
 851                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
 852                 return -1;
 853         }
 854
 855         /*
 856          * Herc requires EOI to be removed from reset before XGXS, so..
 857          */
 858         if (nic->device_type & XFRAME_II_DEVICE) {
 859                 val64 = 0xA500000000ULL;
 860                 writeq(val64, &bar0->sw_reset);
 861                 msleep(500);
 862                 val64 = readq(&bar0->sw_reset);
 863         }
 864
 865         /* Remove XGXS from reset state */
 866         val64 = 0;
 867         writeq(val64, &bar0->sw_reset);
 868         msleep(500);
 869         val64 = readq(&bar0->sw_reset);
 870
 871         /*  Enable Receiving broadcasts */
 872         add = &bar0->mac_cfg;
 873         val64 = readq(&bar0->mac_cfg);
 874         val64 |= MAC_RMAC_BCAST_ENABLE;
 875         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
 876         writel((u32) val64, add);
 877         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
 878         writel((u32) (val64 >> 32), (add + 4));
 879
 880         /* Read registers in all blocks */
 881         val64 = readq(&bar0->mac_int_mask);
 882         val64 = readq(&bar0->mc_int_mask);
 883         val64 = readq(&bar0->xgxs_int_mask);
 884
 885         /*  Set MTU */
 886         val64 = dev->mtu;
 887         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
 888
 889         /*
 890          * Configuring the XAUI Interface of Xena.
 891          * ***************************************
 892          * To Configure the Xena's XAUI, one has to write a series
 893          * of 64 bit values into two registers in a particular
 894          * sequence. Hence a macro 'SWITCH_SIGN' has been defined
 895          * which will be defined in the array of configuration values
 896          * (xena_dtx_cfg & xena_mdio_cfg) at appropriate places
 897          * to switch writing from one regsiter to another. We continue
 898          * writing these values until we encounter the 'END_SIGN' macro.
 899          * For example, After making a series of 21 writes into
 900          * dtx_control register the 'SWITCH_SIGN' appears and hence we
 901          * start writing into mdio_control until we encounter END_SIGN.
 902          */
 903         if (nic->device_type & XFRAME_II_DEVICE) {
 904                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
 905                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
 906                                           &bar0->dtx_control, UF);
 907                         if (dtx_cnt & 0x1)
 908                                 msleep(1); /* Necessary!! */
 909                         dtx_cnt++;
 910                 }
 911         } else {
 912                 while (1) {
 913                       dtx_cfg:
 914                         while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
 915                                 if (xena_dtx_cfg[dtx_cnt] == SWITCH_SIGN) {
 916                                         dtx_cnt++;
 917                                         goto mdio_cfg;
 918                                 }
 919                                 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
 920                                                   &bar0->dtx_control, UF);
 921                                 val64 = readq(&bar0->dtx_control);
 922                                 dtx_cnt++;
 923                         }
 924                       mdio_cfg:
 925                         while (xena_mdio_cfg[mdio_cnt] != END_SIGN) {
 926                                 if (xena_mdio_cfg[mdio_cnt] == SWITCH_SIGN) {
 927                                         mdio_cnt++;
 928                                         goto dtx_cfg;
 929                                 }
 930                                 SPECIAL_REG_WRITE(xena_mdio_cfg[mdio_cnt],
 931                                                   &bar0->mdio_control, UF);
 932                                 val64 = readq(&bar0->mdio_control);
 933                                 mdio_cnt++;
 934                         }
 935                         if ((xena_dtx_cfg[dtx_cnt] == END_SIGN) &&
 936                             (xena_mdio_cfg[mdio_cnt] == END_SIGN)) {
 937                                 break;
 938                         } else {
 939                                 goto dtx_cfg;
 940                         }
 941                 }
 942         }
 943
 944         /*  Tx DMA Initialization */
 945         val64 = 0;
 946         writeq(val64, &bar0->tx_fifo_partition_0);
 947         writeq(val64, &bar0->tx_fifo_partition_1);
 948         writeq(val64, &bar0->tx_fifo_partition_2);
 949         writeq(val64, &bar0->tx_fifo_partition_3);
 950
 951
 952         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
 953                 val64 |=
 954                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
 955                          13) | vBIT(config->tx_cfg[i].fifo_priority,
 956                                     ((i * 32) + 5), 3);
 957
 958                 if (i == (config->tx_fifo_num - 1)) {
 959                         if (i % 2 == 0)
 960                                 i++;
 961                 }
 962
 963                 switch (i) {
 964                 case 1:
 965                         writeq(val64, &bar0->tx_fifo_partition_0);
 966                         val64 = 0;
 967                         break;
 968                 case 3:
 969                         writeq(val64, &bar0->tx_fifo_partition_1);
 970                         val64 = 0;
 971                         break;
 972                 case 5:
 973                         writeq(val64, &bar0->tx_fifo_partition_2);
 974                         val64 = 0;
 975                         break;
 976                 case 7:
 977                         writeq(val64, &bar0->tx_fifo_partition_3);
 978                         break;
 979                 }
 980         }
 981
 982         /* Enable Tx FIFO partition 0. */
 983         val64 = readq(&bar0->tx_fifo_partition_0);
 984         val64 |= BIT(0);        /* To enable the FIFO partition. */
 985         writeq(val64, &bar0->tx_fifo_partition_0);
 986
 987         /*
 988          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
 989          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
 990          */
 991         if ((nic->device_type == XFRAME_I_DEVICE) &&
 992                 (get_xena_rev_id(nic->pdev) < 4))
 993                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
 994
 995         val64 = readq(&bar0->tx_fifo_partition_0);
 996         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
 997                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
 998
 999         /*
1000          * Initialization of Tx_PA_CONFIG register to ignore packet
1001          * integrity checking.
1002          */
1003         val64 = readq(&bar0->tx_pa_cfg);
1004         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1005             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1006         writeq(val64, &bar0->tx_pa_cfg);
1007
1008         /* Rx DMA intialization. */
1009         val64 = 0;
1010         for (i = 0; i < config->rx_ring_num; i++) {
1011                 val64 |=
1012                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1013                          3);
1014         }
1015         writeq(val64, &bar0->rx_queue_priority);
1016
1017         /*
1018          * Allocating equal share of memory to all the
1019          * configured Rings.
1020          */
1021         val64 = 0;
1022         if (nic->device_type & XFRAME_II_DEVICE)
1023                 mem_size = 32;
1024         else
1025                 mem_size = 64;
1026
1027         for (i = 0; i < config->rx_ring_num; i++) {
1028                 switch (i) {
1029                 case 0:
1030                         mem_share = (mem_size / config->rx_ring_num +
1031                                      mem_size % config->rx_ring_num);
1032                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1033                         continue;
1034                 case 1:
1035                         mem_share = (mem_size / config->rx_ring_num);
1036                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1037                         continue;
1038                 case 2:
1039                         mem_share = (mem_size / config->rx_ring_num);
1040                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1041                         continue;
1042                 case 3:
1043                         mem_share = (mem_size / config->rx_ring_num);
1044                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1045                         continue;
1046                 case 4:
1047                         mem_share = (mem_size / config->rx_ring_num);
1048                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1049                         continue;
1050                 case 5:
1051                         mem_share = (mem_size / config->rx_ring_num);
1052                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1053                         continue;
1054                 case 6:
1055                         mem_share = (mem_size / config->rx_ring_num);
1056                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1057                         continue;
1058                 case 7:
1059                         mem_share = (mem_size / config->rx_ring_num);
1060                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1061                         continue;
1062                 }
1063         }
1064         writeq(val64, &bar0->rx_queue_cfg);
1065
1066         /*
1067          * Filling Tx round robin registers
1068          * as per the number of FIFOs
1069          */
1070         switch (config->tx_fifo_num) {
1071         case 1:
1072                 val64 = 0x0000000000000000ULL;
1073                 writeq(val64, &bar0->tx_w_round_robin_0);
1074                 writeq(val64, &bar0->tx_w_round_robin_1);
1075                 writeq(val64, &bar0->tx_w_round_robin_2);
1076                 writeq(val64, &bar0->tx_w_round_robin_3);
1077                 writeq(val64, &bar0->tx_w_round_robin_4);
1078                 break;
1079         case 2:
1080                 val64 = 0x0000010000010000ULL;
1081                 writeq(val64, &bar0->tx_w_round_robin_0);
1082                 val64 = 0x0100000100000100ULL;
1083                 writeq(val64, &bar0->tx_w_round_robin_1);
1084                 val64 = 0x0001000001000001ULL;
1085                 writeq(val64, &bar0->tx_w_round_robin_2);
1086                 val64 = 0x0000010000010000ULL;
1087                 writeq(val64, &bar0->tx_w_round_robin_3);
1088                 val64 = 0x0100000000000000ULL;
1089                 writeq(val64, &bar0->tx_w_round_robin_4);
1090                 break;
1091         case 3:
1092                 val64 = 0x0001000102000001ULL;
1093                 writeq(val64, &bar0->tx_w_round_robin_0);
1094                 val64 = 0x0001020000010001ULL;
1095                 writeq(val64, &bar0->tx_w_round_robin_1);
1096                 val64 = 0x0200000100010200ULL;
1097                 writeq(val64, &bar0->tx_w_round_robin_2);
1098                 val64 = 0x0001000102000001ULL;
1099                 writeq(val64, &bar0->tx_w_round_robin_3);
1100                 val64 = 0x0001020000000000ULL;
1101                 writeq(val64, &bar0->tx_w_round_robin_4);
1102                 break;
1103         case 4:
1104                 val64 = 0x0001020300010200ULL;
1105                 writeq(val64, &bar0->tx_w_round_robin_0);
1106                 val64 = 0x0100000102030001ULL;
1107                 writeq(val64, &bar0->tx_w_round_robin_1);
1108                 val64 = 0x0200010000010203ULL;
1109                 writeq(val64, &bar0->tx_w_round_robin_2);
1110                 val64 = 0x0001020001000001ULL;
1111                 writeq(val64, &bar0->tx_w_round_robin_3);
1112                 val64 = 0x0203000100000000ULL;
1113                 writeq(val64, &bar0->tx_w_round_robin_4);
1114                 break;
1115         case 5:
1116                 val64 = 0x0001000203000102ULL;
1117                 writeq(val64, &bar0->tx_w_round_robin_0);
1118                 val64 = 0x0001020001030004ULL;
1119                 writeq(val64, &bar0->tx_w_round_robin_1);
1120                 val64 = 0x0001000203000102ULL;
1121                 writeq(val64, &bar0->tx_w_round_robin_2);
1122                 val64 = 0x0001020001030004ULL;
1123                 writeq(val64, &bar0->tx_w_round_robin_3);
1124                 val64 = 0x0001000000000000ULL;
1125                 writeq(val64, &bar0->tx_w_round_robin_4);
1126                 break;
1127         case 6:
1128                 val64 = 0x0001020304000102ULL;
1129                 writeq(val64, &bar0->tx_w_round_robin_0);
1130                 val64 = 0x0304050001020001ULL;
1131                 writeq(val64, &bar0->tx_w_round_robin_1);
1132                 val64 = 0x0203000100000102ULL;
1133                 writeq(val64, &bar0->tx_w_round_robin_2);
1134                 val64 = 0x0304000102030405ULL;
1135                 writeq(val64, &bar0->tx_w_round_robin_3);
1136                 val64 = 0x0001000200000000ULL;
1137                 writeq(val64, &bar0->tx_w_round_robin_4);
1138                 break;
1139         case 7:
1140                 val64 = 0x0001020001020300ULL;
1141                 writeq(val64, &bar0->tx_w_round_robin_0);
1142                 val64 = 0x0102030400010203ULL;
1143                 writeq(val64, &bar0->tx_w_round_robin_1);
1144                 val64 = 0x0405060001020001ULL;
1145                 writeq(val64, &bar0->tx_w_round_robin_2);
1146                 val64 = 0x0304050000010200ULL;
1147                 writeq(val64, &bar0->tx_w_round_robin_3);
1148                 val64 = 0x0102030000000000ULL;
1149                 writeq(val64, &bar0->tx_w_round_robin_4);
1150                 break;
1151         case 8:
1152                 val64 = 0x0001020300040105ULL;
1153                 writeq(val64, &bar0->tx_w_round_robin_0);
1154                 val64 = 0x0200030106000204ULL;
1155                 writeq(val64, &bar0->tx_w_round_robin_1);
1156                 val64 = 0x0103000502010007ULL;
1157                 writeq(val64, &bar0->tx_w_round_robin_2);
1158                 val64 = 0x0304010002060500ULL;
1159                 writeq(val64, &bar0->tx_w_round_robin_3);
1160                 val64 = 0x0103020400000000ULL;
1161                 writeq(val64, &bar0->tx_w_round_robin_4);
1162                 break;
1163         }
1164
1165         /* Filling the Rx round robin registers as per the
1166          * number of Rings and steering based on QoS.
1167          */
1168         switch (config->rx_ring_num) {
1169         case 1:
1170                 val64 = 0x8080808080808080ULL;
1171                 writeq(val64, &bar0->rts_qos_steering);
1172                 break;
1173         case 2:
1174                 val64 = 0x0000010000010000ULL;
1175                 writeq(val64, &bar0->rx_w_round_robin_0);
1176                 val64 = 0x0100000100000100ULL;
1177                 writeq(val64, &bar0->rx_w_round_robin_1);
1178                 val64 = 0x0001000001000001ULL;
1179                 writeq(val64, &bar0->rx_w_round_robin_2);
1180                 val64 = 0x0000010000010000ULL;
1181                 writeq(val64, &bar0->rx_w_round_robin_3);
1182                 val64 = 0x0100000000000000ULL;
1183                 writeq(val64, &bar0->rx_w_round_robin_4);
1184
1185                 val64 = 0x8080808040404040ULL;
1186                 writeq(val64, &bar0->rts_qos_steering);
1187                 break;
1188         case 3:
1189                 val64 = 0x0001000102000001ULL;
1190                 writeq(val64, &bar0->rx_w_round_robin_0);
1191                 val64 = 0x0001020000010001ULL;
1192                 writeq(val64, &bar0->rx_w_round_robin_1);
1193                 val64 = 0x0200000100010200ULL;
1194                 writeq(val64, &bar0->rx_w_round_robin_2);
1195                 val64 = 0x0001000102000001ULL;
1196                 writeq(val64, &bar0->rx_w_round_robin_3);
1197                 val64 = 0x0001020000000000ULL;
1198                 writeq(val64, &bar0->rx_w_round_robin_4);
1199
1200                 val64 = 0x8080804040402020ULL;
1201                 writeq(val64, &bar0->rts_qos_steering);
1202                 break;
1203         case 4:
1204                 val64 = 0x0001020300010200ULL;
1205                 writeq(val64, &bar0->rx_w_round_robin_0);
1206                 val64 = 0x0100000102030001ULL;
1207                 writeq(val64, &bar0->rx_w_round_robin_1);
1208                 val64 = 0x0200010000010203ULL;
1209                 writeq(val64, &bar0->rx_w_round_robin_2);
1210                 val64 = 0x0001020001000001ULL;
1211                 writeq(val64, &bar0->rx_w_round_robin_3);
1212                 val64 = 0x0203000100000000ULL;
1213                 writeq(val64, &bar0->rx_w_round_robin_4);
1214
1215                 val64 = 0x8080404020201010ULL;
1216                 writeq(val64, &bar0->rts_qos_steering);
1217                 break;
1218         case 5:
1219                 val64 = 0x0001000203000102ULL;
1220                 writeq(val64, &bar0->rx_w_round_robin_0);
1221                 val64 = 0x0001020001030004ULL;
1222                 writeq(val64, &bar0->rx_w_round_robin_1);
1223                 val64 = 0x0001000203000102ULL;
1224                 writeq(val64, &bar0->rx_w_round_robin_2);
1225                 val64 = 0x0001020001030004ULL;
1226                 writeq(val64, &bar0->rx_w_round_robin_3);
1227                 val64 = 0x0001000000000000ULL;
1228                 writeq(val64, &bar0->rx_w_round_robin_4);
1229
1230                 val64 = 0x8080404020201008ULL;
1231                 writeq(val64, &bar0->rts_qos_steering);
1232                 break;
1233         case 6:
1234                 val64 = 0x0001020304000102ULL;
1235                 writeq(val64, &bar0->rx_w_round_robin_0);
1236                 val64 = 0x0304050001020001ULL;
1237                 writeq(val64, &bar0->rx_w_round_robin_1);
1238                 val64 = 0x0203000100000102ULL;
1239                 writeq(val64, &bar0->rx_w_round_robin_2);
1240                 val64 = 0x0304000102030405ULL;
1241                 writeq(val64, &bar0->rx_w_round_robin_3);
1242                 val64 = 0x0001000200000000ULL;
1243                 writeq(val64, &bar0->rx_w_round_robin_4);
1244
1245                 val64 = 0x8080404020100804ULL;
1246                 writeq(val64, &bar0->rts_qos_steering);
1247                 break;
1248         case 7:
1249                 val64 = 0x0001020001020300ULL;
1250                 writeq(val64, &bar0->rx_w_round_robin_0);
1251                 val64 = 0x0102030400010203ULL;
1252                 writeq(val64, &bar0->rx_w_round_robin_1);
1253                 val64 = 0x0405060001020001ULL;
1254                 writeq(val64, &bar0->rx_w_round_robin_2);
1255                 val64 = 0x0304050000010200ULL;
1256                 writeq(val64, &bar0->rx_w_round_robin_3);
1257                 val64 = 0x0102030000000000ULL;
1258                 writeq(val64, &bar0->rx_w_round_robin_4);
1259
1260                 val64 = 0x8080402010080402ULL;
1261                 writeq(val64, &bar0->rts_qos_steering);
1262                 break;
1263         case 8:
1264                 val64 = 0x0001020300040105ULL;
1265                 writeq(val64, &bar0->rx_w_round_robin_0);
1266                 val64 = 0x0200030106000204ULL;
1267                 writeq(val64, &bar0->rx_w_round_robin_1);
1268                 val64 = 0x0103000502010007ULL;
1269                 writeq(val64, &bar0->rx_w_round_robin_2);
1270                 val64 = 0x0304010002060500ULL;
1271                 writeq(val64, &bar0->rx_w_round_robin_3);
1272                 val64 = 0x0103020400000000ULL;
1273                 writeq(val64, &bar0->rx_w_round_robin_4);
1274
1275                 val64 = 0x8040201008040201ULL;
1276                 writeq(val64, &bar0->rts_qos_steering);
1277                 break;
1278         }
1279
1280         /* UDP Fix */
1281         val64 = 0;
1282         for (i = 0; i < 8; i++)
1283                 writeq(val64, &bar0->rts_frm_len_n[i]);
1284
1285         /* Set the default rts frame length for the rings configured */
1286         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1287         for (i = 0 ; i < config->rx_ring_num ; i++)
1288                 writeq(val64, &bar0->rts_frm_len_n[i]);
1289
1290         /* Set the frame length for the configured rings
1291          * desired by the user
1292          */
1293         for (i = 0; i < config->rx_ring_num; i++) {
1294                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1295                  * specified frame length steering.
1296                  * If the user provides the frame length then program
1297                  * the rts_frm_len register for those values or else
1298                  * leave it as it is.
1299                  */
1300                 if (rts_frm_len[i] != 0) {
1301                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1302                                 &bar0->rts_frm_len_n[i]);
1303                 }
1304         }
1305
1306         /* Program statistics memory */
1307         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1308
1309         if (nic->device_type == XFRAME_II_DEVICE) {
1310                 val64 = STAT_BC(0x320);
1311                 writeq(val64, &bar0->stat_byte_cnt);
1312         }
1313
1314         /*
1315          * Initializing the sampling rate for the device to calculate the
1316          * bandwidth utilization.
1317          */
1318         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1319             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1320         writeq(val64, &bar0->mac_link_util);
1321
1322
1323         /*
1324          * Initializing the Transmit and Receive Traffic Interrupt
1325          * Scheme.
1326          */
1327         /*
1328          * TTI Initialization. Default Tx timer gets us about
1329          * 250 interrupts per sec. Continuous interrupts are enabled
1330          * by default.
1331          */
1332         if (nic->device_type == XFRAME_II_DEVICE) {
1333                 int count = (nic->config.bus_speed * 125)/2;
1334                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1335         } else {
1336
1337                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1338         }
1339         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1340             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1341             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1342                 if (use_continuous_tx_intrs)
1343                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1344         writeq(val64, &bar0->tti_data1_mem);
1345
1346         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1347             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1348             TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1349         writeq(val64, &bar0->tti_data2_mem);
1350
1351         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1352         writeq(val64, &bar0->tti_command_mem);
1353
1354         /*
1355          * Once the operation completes, the Strobe bit of the command
1356          * register will be reset. We poll for this particular condition
1357          * We wait for a maximum of 500ms for the operation to complete,
1358          * if it's not complete by then we return error.
1359          */
1360         time = 0;
1361         while (TRUE) {
1362                 val64 = readq(&bar0->tti_command_mem);
1363                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1364                         break;
1365                 }
1366                 if (time > 10) {
1367                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1368                                   dev->name);
1369                         return -1;
1370                 }
1371                 msleep(50);
1372                 time++;
1373         }
1374
1375         if (nic->config.bimodal) {
1376                 int k = 0;
1377                 for (k = 0; k < config->rx_ring_num; k++) {
1378                         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1379                         val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1380                         writeq(val64, &bar0->tti_command_mem);
1381
1382                 /*
1383                  * Once the operation completes, the Strobe bit of the command
1384                  * register will be reset. We poll for this particular condition
1385                  * We wait for a maximum of 500ms for the operation to complete,
1386                  * if it's not complete by then we return error.
1387                 */
1388                         time = 0;
1389                         while (TRUE) {
1390                                 val64 = readq(&bar0->tti_command_mem);
1391                                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1392                                         break;
1393                                 }
1394                                 if (time > 10) {
1395                                         DBG_PRINT(ERR_DBG,
1396                                                 "%s: TTI init Failed\n",
1397                                         dev->name);
1398                                         return -1;
1399                                 }
1400                                 time++;
1401                                 msleep(50);
1402                         }
1403                 }
1404         } else {
1405
1406                 /* RTI Initialization */
1407                 if (nic->device_type == XFRAME_II_DEVICE) {
1408                         /*
1409                          * Programmed to generate Apprx 500 Intrs per
1410                          * second
1411                          */
1412                         int count = (nic->config.bus_speed * 125)/4;
1413                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1414                 } else {
1415                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1416                 }
1417                 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1418                     RTI_DATA1_MEM_RX_URNG_B(0x10) |
1419                     RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1420
1421                 writeq(val64, &bar0->rti_data1_mem);
1422
1423                 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1424                     RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1425                 if (nic->intr_type == MSI_X)
1426                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1427                                 RTI_DATA2_MEM_RX_UFC_D(0x40));
1428                 else
1429                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1430                                 RTI_DATA2_MEM_RX_UFC_D(0x80));
1431                 writeq(val64, &bar0->rti_data2_mem);
1432
1433                 for (i = 0; i < config->rx_ring_num; i++) {
1434                         val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1435                                         | RTI_CMD_MEM_OFFSET(i);
1436                         writeq(val64, &bar0->rti_command_mem);
1437
1438                         /*
1439                          * Once the operation completes, the Strobe bit of the
1440                          * command register will be reset. We poll for this
1441                          * particular condition. We wait for a maximum of 500ms
1442                          * for the operation to complete, if it's not complete
1443                          * by then we return error.
1444                          */
1445                         time = 0;
1446                         while (TRUE) {
1447                                 val64 = readq(&bar0->rti_command_mem);
1448                                 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1449                                         break;
1450                                 }
1451                                 if (time > 10) {
1452                                         DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1453                                                   dev->name);
1454                                         return -1;
1455                                 }
1456                                 time++;
1457                                 msleep(50);
1458                         }
1459                 }
1460         }
1461
1462         /*
1463          * Initializing proper values as Pause threshold into all
1464          * the 8 Queues on Rx side.
1465          */
1466         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1467         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1468
1469         /* Disable RMAC PAD STRIPPING */
1470         add = &bar0->mac_cfg;
1471         val64 = readq(&bar0->mac_cfg);
1472         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1473         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1474         writel((u32) (val64), add);
1475         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1476         writel((u32) (val64 >> 32), (add + 4));
1477         val64 = readq(&bar0->mac_cfg);
1478
1479         /*
1480          * Set the time value to be inserted in the pause frame
1481          * generated by xena.
1482          */
1483         val64 = readq(&bar0->rmac_pause_cfg);
1484         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1485         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1486         writeq(val64, &bar0->rmac_pause_cfg);
1487
1488         /*
1489          * Set the Threshold Limit for Generating the pause frame
1490          * If the amount of data in any Queue exceeds ratio of
1491          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1492          * pause frame is generated
1493          */
1494         val64 = 0;
1495         for (i = 0; i < 4; i++) {
1496                 val64 |=
1497                     (((u64) 0xFF00 | nic->mac_control.
1498                       mc_pause_threshold_q0q3)
1499                      << (i * 2 * 8));
1500         }
1501         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1502
1503         val64 = 0;
1504         for (i = 0; i < 4; i++) {
1505                 val64 |=
1506                     (((u64) 0xFF00 | nic->mac_control.
1507                       mc_pause_threshold_q4q7)
1508                      << (i * 2 * 8));
1509         }
1510         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1511
1512         /*
1513          * TxDMA will stop Read request if the number of read split has
1514          * exceeded the limit pointed by shared_splits
1515          */
1516         val64 = readq(&bar0->pic_control);
1517         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1518         writeq(val64, &bar0->pic_control);
1519
1520         /*
1521          * Programming the Herc to split every write transaction
1522          * that does not start on an ADB to reduce disconnects.
1523          */
1524         if (nic->device_type == XFRAME_II_DEVICE) {
1525                 val64 = WREQ_SPLIT_MASK_SET_MASK(255);
1526                 writeq(val64, &bar0->wreq_split_mask);
1527         }
1528
1529         /* Setting Link stability period to 64 ms */
1530         if (nic->device_type == XFRAME_II_DEVICE) {
1531                 val64 = MISC_LINK_STABILITY_PRD(3);
1532                 writeq(val64, &bar0->misc_control);
1533         }
1534
1535         return SUCCESS;
1536 }
1537 #define LINK_UP_DOWN_INTERRUPT          1
1538 #define MAC_RMAC_ERR_TIMER              2
1539
1540 static int s2io_link_fault_indication(nic_t *nic)
1541 {
1542         if (nic->intr_type != INTA)
1543                 return MAC_RMAC_ERR_TIMER;
1544         if (nic->device_type == XFRAME_II_DEVICE)
1545                 return LINK_UP_DOWN_INTERRUPT;
1546         else
1547                 return MAC_RMAC_ERR_TIMER;
1548 }
1549
1550 /**
1551  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1552  *  @nic: device private variable,
1553  *  @mask: A mask indicating which Intr block must be modified and,
1554  *  @flag: A flag indicating whether to enable or disable the Intrs.
1555  *  Description: This function will either disable or enable the interrupts
1556  *  depending on the flag argument. The mask argument can be used to
1557  *  enable/disable any Intr block.
1558  *  Return Value: NONE.
1559  */
1560
1561 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1562 {
1563         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1564         register u64 val64 = 0, temp64 = 0;
1565
1566         /*  Top level interrupt classification */
1567         /*  PIC Interrupts */
1568         if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1569                 /*  Enable PIC Intrs in the general intr mask register */
1570                 val64 = TXPIC_INT_M | PIC_RX_INT_M;
1571                 if (flag == ENABLE_INTRS) {
1572                         temp64 = readq(&bar0->general_int_mask);
1573                         temp64 &= ~((u64) val64);
1574                         writeq(temp64, &bar0->general_int_mask);
1575                         /*
1576                          * If Hercules adapter enable GPIO otherwise
1577                          * disabled all PCIX, Flash, MDIO, IIC and GPIO
1578                          * interrupts for now.
1579                          * TODO
1580                          */
1581                         if (s2io_link_fault_indication(nic) ==
1582                                         LINK_UP_DOWN_INTERRUPT ) {
1583                                 temp64 = readq(&bar0->pic_int_mask);
1584                                 temp64 &= ~((u64) PIC_INT_GPIO);
1585                                 writeq(temp64, &bar0->pic_int_mask);
1586                                 temp64 = readq(&bar0->gpio_int_mask);
1587                                 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1588                                 writeq(temp64, &bar0->gpio_int_mask);
1589                         } else {
1590                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1591                         }
1592                         /*
1593                          * No MSI Support is available presently, so TTI and
1594                          * RTI interrupts are also disabled.
1595                          */
1596                 } else if (flag == DISABLE_INTRS) {
1597                         /*
1598                          * Disable PIC Intrs in the general
1599                          * intr mask register
1600                          */
1601                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1602                         temp64 = readq(&bar0->general_int_mask);
1603                         val64 |= temp64;
1604                         writeq(val64, &bar0->general_int_mask);
1605                 }
1606         }
1607
1608         /*  DMA Interrupts */
1609         /*  Enabling/Disabling Tx DMA interrupts */
1610         if (mask & TX_DMA_INTR) {
1611                 /* Enable TxDMA Intrs in the general intr mask register */
1612                 val64 = TXDMA_INT_M;
1613                 if (flag == ENABLE_INTRS) {
1614                         temp64 = readq(&bar0->general_int_mask);
1615                         temp64 &= ~((u64) val64);
1616                         writeq(temp64, &bar0->general_int_mask);
1617                         /*
1618                          * Keep all interrupts other than PFC interrupt
1619                          * and PCC interrupt disabled in DMA level.
1620                          */
1621                         val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1622                                                       TXDMA_PCC_INT_M);
1623                         writeq(val64, &bar0->txdma_int_mask);
1624                         /*
1625                          * Enable only the MISC error 1 interrupt in PFC block
1626                          */
1627                         val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1628                         writeq(val64, &bar0->pfc_err_mask);
1629                         /*
1630                          * Enable only the FB_ECC error interrupt in PCC block
1631                          */
1632                         val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1633                         writeq(val64, &bar0->pcc_err_mask);
1634                 } else if (flag == DISABLE_INTRS) {
1635                         /*
1636                          * Disable TxDMA Intrs in the general intr mask
1637                          * register
1638                          */
1639                         writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1640                         writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
1641                         temp64 = readq(&bar0->general_int_mask);
1642                         val64 |= temp64;
1643                         writeq(val64, &bar0->general_int_mask);
1644                 }
1645         }
1646
1647         /*  Enabling/Disabling Rx DMA interrupts */
1648         if (mask & RX_DMA_INTR) {
1649                 /*  Enable RxDMA Intrs in the general intr mask register */
1650                 val64 = RXDMA_INT_M;
1651                 if (flag == ENABLE_INTRS) {
1652                         temp64 = readq(&bar0->general_int_mask);
1653                         temp64 &= ~((u64) val64);
1654                         writeq(temp64, &bar0->general_int_mask);
1655                         /*
1656                          * All RxDMA block interrupts are disabled for now
1657                          * TODO
1658                          */
1659                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1660                 } else if (flag == DISABLE_INTRS) {
1661                         /*
1662                          * Disable RxDMA Intrs in the general intr mask
1663                          * register
1664                          */
1665                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1666                         temp64 = readq(&bar0->general_int_mask);
1667                         val64 |= temp64;
1668                         writeq(val64, &bar0->general_int_mask);
1669                 }
1670         }
1671
1672         /*  MAC Interrupts */
1673         /*  Enabling/Disabling MAC interrupts */
1674         if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1675                 val64 = TXMAC_INT_M | RXMAC_INT_M;
1676                 if (flag == ENABLE_INTRS) {
1677                         temp64 = readq(&bar0->general_int_mask);
1678                         temp64 &= ~((u64) val64);
1679                         writeq(temp64, &bar0->general_int_mask);
1680                         /*
1681                          * All MAC block error interrupts are disabled for now
1682                          * TODO
1683                          */
1684                 } else if (flag == DISABLE_INTRS) {
1685                         /*
1686                          * Disable MAC Intrs in the general intr mask register
1687                          */
1688                         writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1689                         writeq(DISABLE_ALL_INTRS,
1690                                &bar0->mac_rmac_err_mask);
1691
1692                         temp64 = readq(&bar0->general_int_mask);
1693                         val64 |= temp64;
1694                         writeq(val64, &bar0->general_int_mask);
1695                 }
1696         }
1697
1698         /*  XGXS Interrupts */
1699         if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
1700                 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
1701                 if (flag == ENABLE_INTRS) {
1702                         temp64 = readq(&bar0->general_int_mask);
1703                         temp64 &= ~((u64) val64);
1704                         writeq(temp64, &bar0->general_int_mask);
1705                         /*
1706                          * All XGXS block error interrupts are disabled for now
1707                          * TODO
1708                          */
1709                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1710                 } else if (flag == DISABLE_INTRS) {
1711                         /*
1712                          * Disable MC Intrs in the general intr mask register
1713                          */
1714                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1715                         temp64 = readq(&bar0->general_int_mask);
1716                         val64 |= temp64;
1717                         writeq(val64, &bar0->general_int_mask);
1718                 }
1719         }
1720
1721         /*  Memory Controller(MC) interrupts */
1722         if (mask & MC_INTR) {
1723                 val64 = MC_INT_M;
1724                 if (flag == ENABLE_INTRS) {
1725                         temp64 = readq(&bar0->general_int_mask);
1726                         temp64 &= ~((u64) val64);
1727                         writeq(temp64, &bar0->general_int_mask);
1728                         /*
1729                          * Enable all MC Intrs.
1730                          */
1731                         writeq(0x0, &bar0->mc_int_mask);
1732                         writeq(0x0, &bar0->mc_err_mask);
1733                 } else if (flag == DISABLE_INTRS) {
1734                         /*
1735                          * Disable MC Intrs in the general intr mask register
1736                          */
1737                         writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1738                         temp64 = readq(&bar0->general_int_mask);
1739                         val64 |= temp64;
1740                         writeq(val64, &bar0->general_int_mask);
1741                 }
1742         }
1743
1744
1745         /*  Tx traffic interrupts */
1746         if (mask & TX_TRAFFIC_INTR) {
1747                 val64 = TXTRAFFIC_INT_M;
1748                 if (flag == ENABLE_INTRS) {
1749                         temp64 = readq(&bar0->general_int_mask);
1750                         temp64 &= ~((u64) val64);
1751                         writeq(temp64, &bar0->general_int_mask);
1752                         /*
1753                          * Enable all the Tx side interrupts
1754                          * writing 0 Enables all 64 TX interrupt levels
1755                          */
1756                         writeq(0x0, &bar0->tx_traffic_mask);
1757                 } else if (flag == DISABLE_INTRS) {
1758                         /*
1759                          * Disable Tx Traffic Intrs in the general intr mask
1760                          * register.
1761                          */
1762                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1763                         temp64 = readq(&bar0->general_int_mask);
1764                         val64 |= temp64;
1765                         writeq(val64, &bar0->general_int_mask);
1766                 }
1767         }
1768
1769         /*  Rx traffic interrupts */
1770         if (mask & RX_TRAFFIC_INTR) {
1771                 val64 = RXTRAFFIC_INT_M;
1772                 if (flag == ENABLE_INTRS) {
1773                         temp64 = readq(&bar0->general_int_mask);
1774                         temp64 &= ~((u64) val64);
1775                         writeq(temp64, &bar0->general_int_mask);
1776                         /* writing 0 Enables all 8 RX interrupt levels */
1777                         writeq(0x0, &bar0->rx_traffic_mask);
1778                 } else if (flag == DISABLE_INTRS) {
1779                         /*
1780                          * Disable Rx Traffic Intrs in the general intr mask
1781                          * register.
1782                          */
1783                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1784                         temp64 = readq(&bar0->general_int_mask);
1785                         val64 |= temp64;
1786                         writeq(val64, &bar0->general_int_mask);
1787                 }
1788         }
1789 }
1790
1791 static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
1792 {
1793         int ret = 0;
1794
1795         if (flag == FALSE) {
1796                 if ((!herc && (rev_id >= 4)) || herc) {
1797                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1798                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1799                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1800                                 ret = 1;
1801                         }
1802                 }else {
1803                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1804                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1805                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1806                                 ret = 1;
1807                         }
1808                 }
1809         } else {
1810                 if ((!herc && (rev_id >= 4)) || herc) {
1811                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1812                              ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1813                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1814                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1815                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1816                                 ret = 1;
1817                         }
1818                 } else {
1819                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1820                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1821                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1822                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1823                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1824                                 ret = 1;
1825                         }
1826                 }
1827         }
1828
1829         return ret;
1830 }
1831 /**
1832  *  verify_xena_quiescence - Checks whether the H/W is ready
1833  *  @val64 :  Value read from adapter status register.
1834  *  @flag : indicates if the adapter enable bit was ever written once
1835  *  before.
1836  *  Description: Returns whether the H/W is ready to go or not. Depending
1837  *  on whether adapter enable bit was written or not the comparison
1838  *  differs and the calling function passes the input argument flag to
1839  *  indicate this.
1840  *  Return: 1 If xena is quiescence
1841  *          0 If Xena is not quiescence
1842  */
1843
1844 static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
1845 {
1846         int ret = 0, herc;
1847         u64 tmp64 = ~((u64) val64);
1848         int rev_id = get_xena_rev_id(sp->pdev);
1849
1850         herc = (sp->device_type == XFRAME_II_DEVICE);
1851         if (!
1852             (tmp64 &
1853              (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
1854               ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY |
1855               ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
1856               ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
1857               ADAPTER_STATUS_P_PLL_LOCK))) {
1858                 ret = check_prc_pcc_state(val64, flag, rev_id, herc);
1859         }
1860
1861         return ret;
1862 }
1863
1864 /**
1865  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
1866  * @sp: Pointer to device specifc structure
1867  * Description :
1868  * New procedure to clear mac address reading  problems on Alpha platforms
1869  *
1870  */
1871
1872 static void fix_mac_address(nic_t * sp)
1873 {
1874         XENA_dev_config_t __iomem *bar0 = sp->bar0;
1875         u64 val64;
1876         int i = 0;
1877
1878         while (fix_mac[i] != END_SIGN) {
1879                 writeq(fix_mac[i++], &bar0->gpio_control);
1880                 udelay(10);
1881                 val64 = readq(&bar0->gpio_control);
1882         }
1883 }
1884
1885 /**
1886  *  start_nic - Turns the device on
1887  *  @nic : device private variable.
1888  *  Description:
1889  *  This function actually turns the device on. Before this  function is
1890  *  called,all Registers are configured from their reset states
1891  *  and shared memory is allocated but the NIC is still quiescent. On
1892  *  calling this function, the device interrupts are cleared and the NIC is
1893  *  literally switched on by writing into the adapter control register.
1894  *  Return Value:
1895  *  SUCCESS on success and -1 on failure.
1896  */
1897
1898 static int start_nic(struct s2io_nic *nic)
1899 {
1900         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1901         struct net_device *dev = nic->dev;
1902         register u64 val64 = 0;
1903         u16 interruptible;
1904         u16 subid, i;
1905         mac_info_t *mac_control;
1906         struct config_param *config;
1907
1908         mac_control = &nic->mac_control;
1909         config = &nic->config;
1910
1911         /*  PRC Initialization and configuration */
1912         for (i = 0; i < config->rx_ring_num; i++) {
1913                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1914                        &bar0->prc_rxd0_n[i]);
1915
1916                 val64 = readq(&bar0->prc_ctrl_n[i]);
1917                 if (nic->config.bimodal)
1918                         val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
1919                 if (nic->rxd_mode == RXD_MODE_1)
1920                         val64 |= PRC_CTRL_RC_ENABLED;
1921                 else
1922                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
1923                 writeq(val64, &bar0->prc_ctrl_n[i]);
1924         }
1925
1926         if (nic->rxd_mode == RXD_MODE_3B) {
1927                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
1928                 val64 = readq(&bar0->rx_pa_cfg);
1929                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
1930                 writeq(val64, &bar0->rx_pa_cfg);
1931         }
1932
1933         /*
1934          * Enabling MC-RLDRAM. After enabling the device, we timeout
1935          * for around 100ms, which is approximately the time required
1936          * for the device to be ready for operation.
1937          */
1938         val64 = readq(&bar0->mc_rldram_mrs);
1939         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
1940         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
1941         val64 = readq(&bar0->mc_rldram_mrs);
1942
1943         msleep(100);    /* Delay by around 100 ms. */
1944
1945         /* Enabling ECC Protection. */
1946         val64 = readq(&bar0->adapter_control);
1947         val64 &= ~ADAPTER_ECC_EN;
1948         writeq(val64, &bar0->adapter_control);
1949
1950         /*
1951          * Clearing any possible Link state change interrupts that
1952          * could have popped up just before Enabling the card.
1953          */
1954         val64 = readq(&bar0->mac_rmac_err_reg);
1955         if (val64)
1956                 writeq(val64, &bar0->mac_rmac_err_reg);
1957
1958         /*
1959          * Verify if the device is ready to be enabled, if so enable
1960          * it.
1961          */
1962         val64 = readq(&bar0->adapter_status);
1963         if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
1964                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
1965                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
1966                           (unsigned long long) val64);
1967                 return FAILURE;
1968         }
1969
1970         /*  Enable select interrupts */
1971         if (nic->intr_type != INTA)
1972                 en_dis_able_nic_intrs(nic, ENA_ALL_INTRS, DISABLE_INTRS);
1973         else {
1974                 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
1975                 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
1976                 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
1977                 en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS);
1978         }
1979
1980         /*
1981          * With some switches, link might be already up at this point.
1982          * Because of this weird behavior, when we enable laser,
1983          * we may not get link. We need to handle this. We cannot
1984          * figure out which switch is misbehaving. So we are forced to
1985          * make a global change.
1986          */
1987
1988         /* Enabling Laser. */
1989         val64 = readq(&bar0->adapter_control);
1990         val64 |= ADAPTER_EOI_TX_ON;
1991         writeq(val64, &bar0->adapter_control);
1992
1993         /* SXE-002: Initialize link and activity LED */
1994         subid = nic->pdev->subsystem_device;
1995         if (((subid & 0xFF) >= 0x07) &&
1996             (nic->device_type == XFRAME_I_DEVICE)) {
1997                 val64 = readq(&bar0->gpio_control);
1998                 val64 |= 0x0000800000000000ULL;
1999                 writeq(val64, &bar0->gpio_control);
2000                 val64 = 0x0411040400000000ULL;
2001                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2002         }
2003
2004         /*
2005          * Don't see link state interrupts on certain switches, so
2006          * directly scheduling a link state task from here.
2007          */
2008         schedule_work(&nic->set_link_task);
2009
2010         return SUCCESS;
2011 }
2012 /**
2013  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2014  */
2015 static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, int get_off)
2016 {
2017         nic_t *nic = fifo_data->nic;
2018         struct sk_buff *skb;
2019         TxD_t *txds;
2020         u16 j, frg_cnt;
2021
2022         txds = txdlp;
2023         if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2024                 pci_unmap_single(nic->pdev, (dma_addr_t)
2025                         txds->Buffer_Pointer, sizeof(u64),
2026                         PCI_DMA_TODEVICE);
2027                 txds++;
2028         }
2029
2030         skb = (struct sk_buff *) ((unsigned long)
2031                         txds->Host_Control);
2032         if (!skb) {
2033                 memset(txdlp, 0, (sizeof(TxD_t) * fifo_data->max_txds));
2034                 return NULL;
2035         }
2036         pci_unmap_single(nic->pdev, (dma_addr_t)
2037                          txds->Buffer_Pointer,
2038                          skb->len - skb->data_len,
2039                          PCI_DMA_TODEVICE);
2040         frg_cnt = skb_shinfo(skb)->nr_frags;
2041         if (frg_cnt) {
2042                 txds++;
2043                 for (j = 0; j < frg_cnt; j++, txds++) {
2044                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2045                         if (!txds->Buffer_Pointer)
2046                                 break;
2047                         pci_unmap_page(nic->pdev, (dma_addr_t)
2048                                         txds->Buffer_Pointer,
2049                                        frag->size, PCI_DMA_TODEVICE);
2050                 }
2051         }
2052         txdlp->Host_Control = 0;
2053         return(skb);
2054 }
2055
2056 /**
2057  *  free_tx_buffers - Free all queued Tx buffers
2058  *  @nic : device private variable.
2059  *  Description:
2060  *  Free all queued Tx buffers.
2061  *  Return Value: void
2062 */
2063
2064 static void free_tx_buffers(struct s2io_nic *nic)
2065 {
2066         struct net_device *dev = nic->dev;
2067         struct sk_buff *skb;
2068         TxD_t *txdp;
2069         int i, j;
2070         mac_info_t *mac_control;
2071         struct config_param *config;
2072         int cnt = 0;
2073
2074         mac_control = &nic->mac_control;
2075         config = &nic->config;
2076
2077         for (i = 0; i < config->tx_fifo_num; i++) {
2078                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2079                         txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
2080                             list_virt_addr;
2081                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2082                         if (skb) {
2083                                 dev_kfree_skb(skb);
2084                                 cnt++;
2085                         }
2086                 }
2087                 DBG_PRINT(INTR_DBG,
2088                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2089                           dev->name, cnt, i);
2090                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2091                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2092         }
2093 }
2094
2095 /**
2096  *   stop_nic -  To stop the nic
2097  *   @nic ; device private variable.
2098  *   Description:
2099  *   This function does exactly the opposite of what the start_nic()
2100  *   function does. This function is called to stop the device.
2101  *   Return Value:
2102  *   void.
2103  */
2104
2105 static void stop_nic(struct s2io_nic *nic)
2106 {
2107         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2108         register u64 val64 = 0;
2109         u16 interruptible, i;
2110         mac_info_t *mac_control;
2111         struct config_param *config;
2112
2113         mac_control = &nic->mac_control;
2114         config = &nic->config;
2115
2116         /*  Disable all interrupts */
2117         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2118         interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2119         interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2120         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2121
2122         /*  Disable PRCs */
2123         for (i = 0; i < config->rx_ring_num; i++) {
2124                 val64 = readq(&bar0->prc_ctrl_n[i]);
2125                 val64 &= ~((u64) PRC_CTRL_RC_ENABLED);
2126                 writeq(val64, &bar0->prc_ctrl_n[i]);
2127         }
2128 }
2129
2130 int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
2131 {
2132         struct net_device *dev = nic->dev;
2133         struct sk_buff *frag_list;
2134         void *tmp;
2135
2136         /* Buffer-1 receives L3/L4 headers */
2137         ((RxD3_t*)rxdp)->Buffer1_ptr = pci_map_single
2138                         (nic->pdev, skb->data, l3l4hdr_size + 4,
2139                         PCI_DMA_FROMDEVICE);
2140
2141         /* skb_shinfo(skb)->frag_list will have L4 data payload */
2142         skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2143         if (skb_shinfo(skb)->frag_list == NULL) {
2144                 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2145                 return -ENOMEM ;
2146         }
2147         frag_list = skb_shinfo(skb)->frag_list;
2148         frag_list->next = NULL;
2149         tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2150         frag_list->data = tmp;
2151         frag_list->tail = tmp;
2152
2153         /* Buffer-2 receives L4 data payload */
2154         ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2155                                 frag_list->data, dev->mtu,
2156                                 PCI_DMA_FROMDEVICE);
2157         rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2158         rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2159
2160         return SUCCESS;
2161 }
2162
2163 /**
2164  *  fill_rx_buffers - Allocates the Rx side skbs
2165  *  @nic:  device private variable
2166  *  @ring_no: ring number
2167  *  Description:
2168  *  The function allocates Rx side skbs and puts the physical
2169  *  address of these buffers into the RxD buffer pointers, so that the NIC
2170  *  can DMA the received frame into these locations.
2171  *  The NIC supports 3 receive modes, viz
2172  *  1. single buffer,
2173  *  2. three buffer and
2174  *  3. Five buffer modes.
2175  *  Each mode defines how many fragments the received frame will be split
2176  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2177  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2178  *  is split into 3 fragments. As of now only single buffer mode is
2179  *  supported.
2180  *   Return Value:
2181  *  SUCCESS on success or an appropriate -ve value on failure.
2182  */
2183
2184 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2185 {
2186         struct net_device *dev = nic->dev;
2187         struct sk_buff *skb;
2188         RxD_t *rxdp;
2189         int off, off1, size, block_no, block_no1;
2190         u32 alloc_tab = 0;
2191         u32 alloc_cnt;
2192         mac_info_t *mac_control;
2193         struct config_param *config;
2194         u64 tmp;
2195         buffAdd_t *ba;
2196 #ifndef CONFIG_S2IO_NAPI
2197         unsigned long flags;
2198 #endif
2199         RxD_t *first_rxdp = NULL;
2200
2201         mac_control = &nic->mac_control;
2202         config = &nic->config;
2203         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2204             atomic_read(&nic->rx_bufs_left[ring_no]);
2205
2206         while (alloc_tab < alloc_cnt) {
2207                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2208                     block_index;
2209                 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.
2210                     block_index;
2211                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2212                 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2213
2214                 rxdp = mac_control->rings[ring_no].
2215                                 rx_blocks[block_no].rxds[off].virt_addr;
2216
2217                 if ((block_no == block_no1) && (off == off1) &&
2218                                         (rxdp->Host_Control)) {
2219                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2220                                   dev->name);
2221                         DBG_PRINT(INTR_DBG, " info equated\n");
2222                         goto end;
2223                 }
2224                 if (off && (off == rxd_count[nic->rxd_mode])) {
2225                         mac_control->rings[ring_no].rx_curr_put_info.
2226                             block_index++;
2227                         if (mac_control->rings[ring_no].rx_curr_put_info.
2228                             block_index == mac_control->rings[ring_no].
2229                                         block_count)
2230                                 mac_control->rings[ring_no].rx_curr_put_info.
2231                                         block_index = 0;
2232                         block_no = mac_control->rings[ring_no].
2233                                         rx_curr_put_info.block_index;
2234                         if (off == rxd_count[nic->rxd_mode])
2235                                 off = 0;
2236                         mac_control->rings[ring_no].rx_curr_put_info.
2237                                 offset = off;
2238                         rxdp = mac_control->rings[ring_no].
2239                                 rx_blocks[block_no].block_virt_addr;
2240                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2241                                   dev->name, rxdp);
2242                 }
2243 #ifndef CONFIG_S2IO_NAPI
2244                 spin_lock_irqsave(&nic->put_lock, flags);
2245                 mac_control->rings[ring_no].put_pos =
2246                     (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2247                 spin_unlock_irqrestore(&nic->put_lock, flags);
2248 #endif
2249                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2250                         ((nic->rxd_mode >= RXD_MODE_3A) &&
2251                                 (rxdp->Control_2 & BIT(0)))) {
2252                         mac_control->rings[ring_no].rx_curr_put_info.
2253                                         offset = off;
2254                         goto end;
2255                 }
2256                 /* calculate size of skb based on ring mode */
2257                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2258                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2259                 if (nic->rxd_mode == RXD_MODE_1)
2260                         size += NET_IP_ALIGN;
2261                 else if (nic->rxd_mode == RXD_MODE_3B)
2262                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2263                 else
2264                         size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
2265
2266                 /* allocate skb */
2267                 skb = dev_alloc_skb(size);
2268                 if(!skb) {
2269                         DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2270                         DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
2271                         if (first_rxdp) {
2272                                 wmb();
2273                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2274                         }
2275                         return -ENOMEM ;
2276                 }
2277                 if (nic->rxd_mode == RXD_MODE_1) {
2278                         /* 1 buffer mode - normal operation mode */
2279                         memset(rxdp, 0, sizeof(RxD1_t));
2280                         skb_reserve(skb, NET_IP_ALIGN);
2281                         ((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single
2282                             (nic->pdev, skb->data, size, PCI_DMA_FROMDEVICE);
2283                         rxdp->Control_2 &= (~MASK_BUFFER0_SIZE_1);
2284                         rxdp->Control_2 |= SET_BUFFER0_SIZE_1(size);
2285
2286                 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2287                         /*
2288                          * 2 or 3 buffer mode -
2289                          * Both 2 buffer mode and 3 buffer mode provides 128
2290                          * byte aligned receive buffers.
2291                          *
2292                          * 3 buffer mode provides header separation where in
2293                          * skb->data will have L3/L4 headers where as
2294                          * skb_shinfo(skb)->frag_list will have the L4 data
2295                          * payload
2296                          */
2297
2298                         memset(rxdp, 0, sizeof(RxD3_t));
2299                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2300                         skb_reserve(skb, BUF0_LEN);
2301                         tmp = (u64)(unsigned long) skb->data;
2302                         tmp += ALIGN_SIZE;
2303                         tmp &= ~ALIGN_SIZE;
2304                         skb->data = (void *) (unsigned long)tmp;
2305                         skb->tail = (void *) (unsigned long)tmp;
2306
2307                         ((RxD3_t*)rxdp)->Buffer0_ptr =
2308                             pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2309                                            PCI_DMA_FROMDEVICE);
2310                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2311                         if (nic->rxd_mode == RXD_MODE_3B) {
2312                                 /* Two buffer mode */
2313
2314                                 /*
2315                                  * Buffer2 will have L3/L4 header plus
2316                                  * L4 payload
2317                                  */
2318                                 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single
2319                                 (nic->pdev, skb->data, dev->mtu + 4,
2320                                                 PCI_DMA_FROMDEVICE);
2321
2322                                 /* Buffer-1 will be dummy buffer not used */
2323                                 ((RxD3_t*)rxdp)->Buffer1_ptr =
2324                                 pci_map_single(nic->pdev, ba->ba_1, BUF1_LEN,
2325                                         PCI_DMA_FROMDEVICE);
2326                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2327                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2328                                                                 (dev->mtu + 4);
2329                         } else {
2330                                 /* 3 buffer mode */
2331                                 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2332                                         dev_kfree_skb_irq(skb);
2333                                         if (first_rxdp) {
2334                                                 wmb();
2335                                                 first_rxdp->Control_1 |=
2336                                                         RXD_OWN_XENA;
2337                                         }
2338                                         return -ENOMEM ;
2339                                 }
2340                         }
2341                         rxdp->Control_2 |= BIT(0);
2342                 }
2343                 rxdp->Host_Control = (unsigned long) (skb);
2344                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2345                         rxdp->Control_1 |= RXD_OWN_XENA;
2346                 off++;
2347                 if (off == (rxd_count[nic->rxd_mode] + 1))
2348                         off = 0;
2349                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2350
2351                 rxdp->Control_2 |= SET_RXD_MARKER;
2352                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2353                         if (first_rxdp) {
2354                                 wmb();
2355                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2356                         }
2357                         first_rxdp = rxdp;
2358                 }
2359                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2360                 alloc_tab++;
2361         }
2362
2363       end:
2364         /* Transfer ownership of first descriptor to adapter just before
2365          * exiting. Before that, use memory barrier so that ownership
2366          * and other fields are seen by adapter correctly.
2367          */
2368         if (first_rxdp) {
2369                 wmb();
2370                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2371         }
2372
2373         return SUCCESS;
2374 }
2375
2376 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2377 {
2378         struct net_device *dev = sp->dev;
2379         int j;
2380         struct sk_buff *skb;
2381         RxD_t *rxdp;
2382         mac_info_t *mac_control;
2383         buffAdd_t *ba;
2384
2385         mac_control = &sp->mac_control;
2386         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2387                 rxdp = mac_control->rings[ring_no].
2388                                 rx_blocks[blk].rxds[j].virt_addr;
2389                 skb = (struct sk_buff *)
2390                         ((unsigned long) rxdp->Host_Control);
2391                 if (!skb) {
2392                         continue;
2393                 }
2394                 if (sp->rxd_mode == RXD_MODE_1) {
2395                         pci_unmap_single(sp->pdev, (dma_addr_t)
2396                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2397                                  dev->mtu +
2398                                  HEADER_ETHERNET_II_802_3_SIZE
2399                                  + HEADER_802_2_SIZE +
2400                                  HEADER_SNAP_SIZE,
2401                                  PCI_DMA_FROMDEVICE);
2402                         memset(rxdp, 0, sizeof(RxD1_t));
2403                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2404                         ba = &mac_control->rings[ring_no].
2405                                 ba[blk][j];
2406                         pci_unmap_single(sp->pdev, (dma_addr_t)
2407                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2408                                  BUF0_LEN,
2409                                  PCI_DMA_FROMDEVICE);
2410                         pci_unmap_single(sp->pdev, (dma_addr_t)
2411                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2412                                  BUF1_LEN,
2413                                  PCI_DMA_FROMDEVICE);
2414                         pci_unmap_single(sp->pdev, (dma_addr_t)
2415                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2416                                  dev->mtu + 4,
2417                                  PCI_DMA_FROMDEVICE);
2418                         memset(rxdp, 0, sizeof(RxD3_t));
2419                 } else {
2420                         pci_unmap_single(sp->pdev, (dma_addr_t)
2421                                 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2422                                 PCI_DMA_FROMDEVICE);
2423                         pci_unmap_single(sp->pdev, (dma_addr_t)
2424                                 ((RxD3_t*)rxdp)->Buffer1_ptr,
2425                                 l3l4hdr_size + 4,
2426                                 PCI_DMA_FROMDEVICE);
2427                         pci_unmap_single(sp->pdev, (dma_addr_t)
2428                                 ((RxD3_t*)rxdp)->Buffer2_ptr, dev->mtu,
2429                                 PCI_DMA_FROMDEVICE);
2430                         memset(rxdp, 0, sizeof(RxD3_t));
2431                 }
2432                 dev_kfree_skb(skb);
2433                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2434         }
2435 }
2436
2437 /**
2438  *  free_rx_buffers - Frees all Rx buffers
2439  *  @sp: device private variable.
2440  *  Description:
2441  *  This function will free all Rx buffers allocated by host.
2442  *  Return Value:
2443  *  NONE.
2444  */
2445
2446 static void free_rx_buffers(struct s2io_nic *sp)
2447 {
2448         struct net_device *dev = sp->dev;
2449         int i, blk = 0, buf_cnt = 0;
2450         mac_info_t *mac_control;
2451         struct config_param *config;
2452
2453         mac_control = &sp->mac_control;
2454         config = &sp->config;
2455
2456         for (i = 0; i < config->rx_ring_num; i++) {
2457                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2458                         free_rxd_blk(sp,i,blk);
2459
2460                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2461                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2462                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2463                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2464                 atomic_set(&sp->rx_bufs_left[i], 0);
2465                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2466                           dev->name, buf_cnt, i);
2467         }
2468 }
2469
2470 /**
2471  * s2io_poll - Rx interrupt handler for NAPI support
2472  * @dev : pointer to the device structure.
2473  * @budget : The number of packets that were budgeted to be processed
2474  * during  one pass through the 'Poll" function.
2475  * Description:
2476  * Comes into picture only if NAPI support has been incorporated. It does
2477  * the same thing that rx_intr_handler does, but not in a interrupt context
2478  * also It will process only a given number of packets.
2479  * Return value:
2480  * 0 on success and 1 if there are No Rx packets to be processed.
2481  */
2482
2483 #if defined(CONFIG_S2IO_NAPI)
2484 static int s2io_poll(struct net_device *dev, int *budget)
2485 {
2486         nic_t *nic = dev->priv;
2487         int pkt_cnt = 0, org_pkts_to_process;
2488         mac_info_t *mac_control;
2489         struct config_param *config;
2490         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2491         u64 val64;
2492         int i;
2493
2494         atomic_inc(&nic->isr_cnt);
2495         mac_control = &nic->mac_control;
2496         config = &nic->config;
2497
2498         nic->pkts_to_process = *budget;
2499         if (nic->pkts_to_process > dev->quota)
2500                 nic->pkts_to_process = dev->quota;
2501         org_pkts_to_process = nic->pkts_to_process;
2502
2503         val64 = readq(&bar0->rx_traffic_int);
2504         writeq(val64, &bar0->rx_traffic_int);
2505
2506         for (i = 0; i < config->rx_ring_num; i++) {
2507                 rx_intr_handler(&mac_control->rings[i]);
2508                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2509                 if (!nic->pkts_to_process) {
2510                         /* Quota for the current iteration has been met */
2511                         goto no_rx;
2512                 }
2513         }
2514         if (!pkt_cnt)
2515                 pkt_cnt = 1;
2516
2517         dev->quota -= pkt_cnt;
2518         *budget -= pkt_cnt;
2519         netif_rx_complete(dev);
2520
2521         for (i = 0; i < config->rx_ring_num; i++) {
2522                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2523                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2524                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2525                         break;
2526                 }
2527         }
2528         /* Re enable the Rx interrupts. */
2529         en_dis_able_nic_intrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS);
2530         atomic_dec(&nic->isr_cnt);
2531         return 0;
2532
2533 no_rx:
2534         dev->quota -= pkt_cnt;
2535         *budget -= pkt_cnt;
2536
2537         for (i = 0; i < config->rx_ring_num; i++) {
2538                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2539                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2540                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2541                         break;
2542                 }
2543         }
2544         atomic_dec(&nic->isr_cnt);
2545         return 1;
2546 }
2547 #endif
2548
2549 /**
2550  *  rx_intr_handler - Rx interrupt handler
2551  *  @nic: device private variable.
2552  *  Description:
2553  *  If the interrupt is because of a received frame or if the
2554  *  receive ring contains fresh as yet un-processed frames,this function is
2555  *  called. It picks out the RxD at which place the last Rx processing had
2556  *  stopped and sends the skb to the OSM's Rx handler and then increments
2557  *  the offset.
2558  *  Return Value:
2559  *  NONE.
2560  */
2561 static void rx_intr_handler(ring_info_t *ring_data)
2562 {
2563         nic_t *nic = ring_data->nic;
2564         struct net_device *dev = (struct net_device *) nic->dev;
2565         int get_block, put_block, put_offset;
2566         rx_curr_get_info_t get_info, put_info;
2567         RxD_t *rxdp;
2568         struct sk_buff *skb;
2569 #ifndef CONFIG_S2IO_NAPI
2570         int pkt_cnt = 0;
2571 #endif
2572         spin_lock(&nic->rx_lock);
2573         if (atomic_read(&nic->card_state) == CARD_DOWN) {
2574                 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2575                           __FUNCTION__, dev->name);
2576                 spin_unlock(&nic->rx_lock);
2577                 return;
2578         }
2579
2580         get_info = ring_data->rx_curr_get_info;
2581         get_block = get_info.block_index;
2582         put_info = ring_data->rx_curr_put_info;
2583         put_block = put_info.block_index;
2584         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2585 #ifndef CONFIG_S2IO_NAPI
2586         spin_lock(&nic->put_lock);
2587         put_offset = ring_data->put_pos;
2588         spin_unlock(&nic->put_lock);
2589 #else
2590         put_offset = (put_block * (rxd_count[nic->rxd_mode] + 1)) +
2591                 put_info.offset;
2592 #endif
2593         while (RXD_IS_UP2DT(rxdp)) {
2594                 /* If your are next to put index then it's FIFO full condition */
2595                 if ((get_block == put_block) &&
2596                     (get_info.offset + 1) == put_info.offset) {
2597                         DBG_PRINT(ERR_DBG, "%s: Ring Full\n",dev->name);
2598                         break;
2599                 }
2600                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2601                 if (skb == NULL) {
2602                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2603                                   dev->name);
2604                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2605                         spin_unlock(&nic->rx_lock);
2606                         return;
2607                 }
2608                 if (nic->rxd_mode == RXD_MODE_1) {
2609                         pci_unmap_single(nic->pdev, (dma_addr_t)
2610                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2611                                  dev->mtu +
2612                                  HEADER_ETHERNET_II_802_3_SIZE +
2613                                  HEADER_802_2_SIZE +
2614                                  HEADER_SNAP_SIZE,
2615                                  PCI_DMA_FROMDEVICE);
2616                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2617                         pci_unmap_single(nic->pdev, (dma_addr_t)
2618                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2619                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
2620                         pci_unmap_single(nic->pdev, (dma_addr_t)
2621                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2622                                  BUF1_LEN, PCI_DMA_FROMDEVICE);
2623                         pci_unmap_single(nic->pdev, (dma_addr_t)
2624                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2625                                  dev->mtu + 4,
2626                                  PCI_DMA_FROMDEVICE);
2627                 } else {
2628                         pci_unmap_single(nic->pdev, (dma_addr_t)
2629                                          ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2630                                          PCI_DMA_FROMDEVICE);
2631                         pci_unmap_single(nic->pdev, (dma_addr_t)
2632                                          ((RxD3_t*)rxdp)->Buffer1_ptr,
2633                                          l3l4hdr_size + 4,
2634                                          PCI_DMA_FROMDEVICE);
2635                         pci_unmap_single(nic->pdev, (dma_addr_t)
2636                                          ((RxD3_t*)rxdp)->Buffer2_ptr,
2637                                          dev->mtu, PCI_DMA_FROMDEVICE);
2638                 }
2639                 rx_osm_handler(ring_data, rxdp);
2640                 get_info.offset++;
2641                 ring_data->rx_curr_get_info.offset = get_info.offset;
2642                 rxdp = ring_data->rx_blocks[get_block].
2643                                 rxds[get_info.offset].virt_addr;
2644                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2645                         get_info.offset = 0;
2646                         ring_data->rx_curr_get_info.offset = get_info.offset;
2647                         get_block++;
2648                         if (get_block == ring_data->block_count)
2649                                 get_block = 0;
2650                         ring_data->rx_curr_get_info.block_index = get_block;
2651                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2652                 }
2653
2654 #ifdef CONFIG_S2IO_NAPI
2655                 nic->pkts_to_process -= 1;
2656                 if (!nic->pkts_to_process)
2657                         break;
2658 #else
2659                 pkt_cnt++;
2660                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2661                         break;
2662 #endif
2663         }
2664         spin_unlock(&nic->rx_lock);
2665 }
2666
2667 /**
2668  *  tx_intr_handler - Transmit interrupt handler
2669  *  @nic : device private variable
2670  *  Description:
2671  *  If an interrupt was raised to indicate DMA complete of the
2672  *  Tx packet, this function is called. It identifies the last TxD
2673  *  whose buffer was freed and frees all skbs whose data have already
2674  *  DMA'ed into the NICs internal memory.
2675  *  Return Value:
2676  *  NONE
2677  */
2678
2679 static void tx_intr_handler(fifo_info_t *fifo_data)
2680 {
2681         nic_t *nic = fifo_data->nic;
2682         struct net_device *dev = (struct net_device *) nic->dev;
2683         tx_curr_get_info_t get_info, put_info;
2684         struct sk_buff *skb;
2685         TxD_t *txdlp;
2686
2687         get_info = fifo_data->tx_curr_get_info;
2688         put_info = fifo_data->tx_curr_put_info;
2689         txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2690             list_virt_addr;
2691         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2692                (get_info.offset != put_info.offset) &&
2693                (txdlp->Host_Control)) {
2694                 /* Check for TxD errors */
2695                 if (txdlp->Control_1 & TXD_T_CODE) {
2696                         unsigned long long err;
2697                         err = txdlp->Control_1 & TXD_T_CODE;
2698                         if ((err >> 48) == 0xA) {
2699                                 DBG_PRINT(TX_DBG, "TxD returned due \
2700 to loss of link\n");
2701                         }
2702                         else {
2703                                 DBG_PRINT(ERR_DBG, "***TxD error \
2704 %llx\n", err);
2705                         }
2706                 }
2707
2708                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2709                 if (skb == NULL) {
2710                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
2711                         __FUNCTION__);
2712                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2713                         return;
2714                 }
2715
2716                 /* Updating the statistics block */
2717                 nic->stats.tx_bytes += skb->len;
2718                 dev_kfree_skb_irq(skb);
2719
2720                 get_info.offset++;
2721                 get_info.offset %= get_info.fifo_len + 1;
2722                 txdlp = (TxD_t *) fifo_data->list_info
2723                     [get_info.offset].list_virt_addr;
2724                 fifo_data->tx_curr_get_info.offset =
2725                     get_info.offset;
2726         }
2727
2728         spin_lock(&nic->tx_lock);
2729         if (netif_queue_stopped(dev))
2730                 netif_wake_queue(dev);
2731         spin_unlock(&nic->tx_lock);
2732 }
2733
2734 /**
2735  *  alarm_intr_handler - Alarm Interrrupt handler
2736  *  @nic: device private variable
2737  *  Description: If the interrupt was neither because of Rx packet or Tx
2738  *  complete, this function is called. If the interrupt was to indicate
2739  *  a loss of link, the OSM link status handler is invoked for any other
2740  *  alarm interrupt the block that raised the interrupt is displayed
2741  *  and a H/W reset is issued.
2742  *  Return Value:
2743  *  NONE
2744 */
2745
2746 static void alarm_intr_handler(struct s2io_nic *nic)
2747 {
2748         struct net_device *dev = (struct net_device *) nic->dev;
2749         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2750         register u64 val64 = 0, err_reg = 0;
2751
2752         /* Handling link status change error Intr */
2753         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2754                 err_reg = readq(&bar0->mac_rmac_err_reg);
2755                 writeq(err_reg, &bar0->mac_rmac_err_reg);
2756                 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
2757                         schedule_work(&nic->set_link_task);
2758                 }
2759         }
2760
2761         /* Handling Ecc errors */
2762         val64 = readq(&bar0->mc_err_reg);
2763         writeq(val64, &bar0->mc_err_reg);
2764         if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
2765                 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
2766                         nic->mac_control.stats_info->sw_stat.
2767                                 double_ecc_errs++;
2768                         DBG_PRINT(INIT_DBG, "%s: Device indicates ",
2769                                   dev->name);
2770                         DBG_PRINT(INIT_DBG, "double ECC error!!\n");
2771                         if (nic->device_type != XFRAME_II_DEVICE) {
2772                                 /* Reset XframeI only if critical error */
2773                                 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
2774                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
2775                                         netif_stop_queue(dev);
2776                                         schedule_work(&nic->rst_timer_task);
2777                                 }
2778                         }
2779                 } else {
2780                         nic->mac_control.stats_info->sw_stat.
2781                                 single_ecc_errs++;
2782                 }
2783         }
2784
2785         /* In case of a serious error, the device will be Reset. */
2786         val64 = readq(&bar0->serr_source);
2787         if (val64 & SERR_SOURCE_ANY) {
2788                 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
2789                 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
2790                           (unsigned long long)val64);
2791                 netif_stop_queue(dev);
2792                 schedule_work(&nic->rst_timer_task);
2793         }
2794
2795         /*
2796          * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
2797          * Error occurs, the adapter will be recycled by disabling the
2798          * adapter enable bit and enabling it again after the device
2799          * becomes Quiescent.
2800          */
2801         val64 = readq(&bar0->pcc_err_reg);
2802         writeq(val64, &bar0->pcc_err_reg);
2803         if (val64 & PCC_FB_ECC_DB_ERR) {
2804                 u64 ac = readq(&bar0->adapter_control);
2805                 ac &= ~(ADAPTER_CNTL_EN);
2806                 writeq(ac, &bar0->adapter_control);
2807                 ac = readq(&bar0->adapter_control);
2808                 schedule_work(&nic->set_link_task);
2809         }
2810
2811         /* Other type of interrupts are not being handled now,  TODO */
2812 }
2813
2814 /**
2815  *  wait_for_cmd_complete - waits for a command to complete.
2816  *  @sp : private member of the device structure, which is a pointer to the
2817  *  s2io_nic structure.
2818  *  Description: Function that waits for a command to Write into RMAC
2819  *  ADDR DATA registers to be completed and returns either success or
2820  *  error depending on whether the command was complete or not.
2821  *  Return value:
2822  *   SUCCESS on success and FAILURE on failure.
2823  */
2824
2825 static int wait_for_cmd_complete(nic_t * sp)
2826 {
2827         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2828         int ret = FAILURE, cnt = 0;
2829         u64 val64;
2830
2831         while (TRUE) {
2832                 val64 = readq(&bar0->rmac_addr_cmd_mem);
2833                 if (!(val64 & RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
2834                         ret = SUCCESS;
2835                         break;
2836                 }
2837                 msleep(50);
2838                 if (cnt++ > 10)
2839                         break;
2840         }
2841
2842         return ret;
2843 }
2844
2845 /**
2846  *  s2io_reset - Resets the card.
2847  *  @sp : private member of the device structure.
2848  *  Description: Function to Reset the card. This function then also
2849  *  restores the previously saved PCI configuration space registers as
2850  *  the card reset also resets the configuration space.
2851  *  Return value:
2852  *  void.
2853  */
2854
2855 void s2io_reset(nic_t * sp)
2856 {
2857         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2858         u64 val64;
2859         u16 subid, pci_cmd;
2860
2861         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
2862         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
2863
2864         val64 = SW_RESET_ALL;
2865         writeq(val64, &bar0->sw_reset);
2866
2867         /*
2868          * At this stage, if the PCI write is indeed completed, the
2869          * card is reset and so is the PCI Config space of the device.
2870          * So a read cannot be issued at this stage on any of the
2871          * registers to ensure the write into "sw_reset" register
2872          * has gone through.
2873          * Question: Is there any system call that will explicitly force
2874          * all the write commands still pending on the bus to be pushed
2875          * through?
2876          * As of now I'am just giving a 250ms delay and hoping that the
2877          * PCI write to sw_reset register is done by this time.
2878          */
2879         msleep(250);
2880
2881         /* Restore the PCI state saved during initialization. */
2882         pci_restore_state(sp->pdev);
2883         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
2884                                      pci_cmd);
2885         s2io_init_pci(sp);
2886
2887         msleep(250);
2888
2889         /* Set swapper to enable I/O register access */
2890         s2io_set_swapper(sp);
2891
2892         /* Restore the MSIX table entries from local variables */
2893         restore_xmsi_data(sp);
2894
2895         /* Clear certain PCI/PCI-X fields after reset */
2896         if (sp->device_type == XFRAME_II_DEVICE) {
2897                 /* Clear parity err detect bit */
2898                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
2899
2900                 /* Clearing PCIX Ecc status register */
2901                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
2902
2903                 /* Clearing PCI_STATUS error reflected here */
2904                 writeq(BIT(62), &bar0->txpic_int_reg);
2905         }
2906
2907         /* Reset device statistics maintained by OS */
2908         memset(&sp->stats, 0, sizeof (struct net_device_stats));
2909
2910         /* SXE-002: Configure link and activity LED to turn it off */
2911         subid = sp->pdev->subsystem_device;
2912         if (((subid & 0xFF) >= 0x07) &&
2913             (sp->device_type == XFRAME_I_DEVICE)) {
2914                 val64 = readq(&bar0->gpio_control);
2915                 val64 |= 0x0000800000000000ULL;
2916                 writeq(val64, &bar0->gpio_control);
2917                 val64 = 0x0411040400000000ULL;
2918                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2919         }
2920
2921         /*
2922          * Clear spurious ECC interrupts that would have occured on
2923          * XFRAME II cards after reset.
2924          */
2925         if (sp->device_type == XFRAME_II_DEVICE) {
2926                 val64 = readq(&bar0->pcc_err_reg);
2927                 writeq(val64, &bar0->pcc_err_reg);
2928         }
2929
2930         sp->device_enabled_once = FALSE;
2931 }
2932
2933 /**
2934  *  s2io_set_swapper - to set the swapper controle on the card
2935  *  @sp : private member of the device structure,
2936  *  pointer to the s2io_nic structure.
2937  *  Description: Function to set the swapper control on the card
2938  *  correctly depending on the 'endianness' of the system.
2939  *  Return value:
2940  *  SUCCESS on success and FAILURE on failure.
2941  */
2942
2943 int s2io_set_swapper(nic_t * sp)
2944 {
2945         struct net_device *dev = sp->dev;
2946         XENA_dev_config_t __iomem *bar0 = sp->bar0;
2947         u64 val64, valt, valr;
2948
2949         /*
2950          * Set proper endian settings and verify the same by reading
2951          * the PIF Feed-back register.
2952          */
2953
2954         val64 = readq(&bar0->pif_rd_swapper_fb);
2955         if (val64 != 0x0123456789ABCDEFULL) {
2956                 int i = 0;
2957                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
2958                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
2959                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
2960                                 0};                     /* FE=0, SE=0 */
2961
2962                 while(i<4) {
2963                         writeq(value[i], &bar0->swapper_ctrl);
2964                         val64 = readq(&bar0->pif_rd_swapper_fb);
2965                         if (val64 == 0x0123456789ABCDEFULL)
2966                                 break;
2967                         i++;
2968                 }
2969                 if (i == 4) {
2970                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
2971                                 dev->name);
2972                         DBG_PRINT(ERR_DBG, "feedback read %llx\n",
2973                                 (unsigned long long) val64);
2974                         return FAILURE;
2975                 }
2976                 valr = value[i];
2977         } else {
2978                 valr = readq(&bar0->swapper_ctrl);
2979         }
2980
2981         valt = 0x0123456789ABCDEFULL;
2982         writeq(valt, &bar0->xmsi_address);
2983         val64 = readq(&bar0->xmsi_address);
2984
2985         if(val64 != valt) {
2986                 int i = 0;
2987                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
2988                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
2989                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
2990                                 0};                     /* FE=0, SE=0 */
2991
2992                 while(i<4) {
2993                         writeq((value[i] | valr), &bar0->swapper_ctrl);
2994                         writeq(valt, &bar0->xmsi_address);
2995                         val64 = readq(&bar0->xmsi_address);
2996                         if(val64 == valt)
2997                                 break;
2998                         i++;
2999                 }
3000                 if(i == 4) {
3001                         unsigned long long x = val64;
3002                         DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3003                         DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3004                         return FAILURE;
3005                 }
3006         }
3007         val64 = readq(&bar0->swapper_ctrl);
3008         val64 &= 0xFFFF000000000000ULL;
3009
3010 #ifdef  __BIG_ENDIAN
3011         /*
3012          * The device by default set to a big endian format, so a
3013          * big endian driver need not set anything.
3014          */
3015         val64 |= (SWAPPER_CTRL_TXP_FE |
3016                  SWAPPER_CTRL_TXP_SE |
3017                  SWAPPER_CTRL_TXD_R_FE |
3018                  SWAPPER_CTRL_TXD_W_FE |
3019                  SWAPPER_CTRL_TXF_R_FE |
3020                  SWAPPER_CTRL_RXD_R_FE |
3021                  SWAPPER_CTRL_RXD_W_FE |
3022                  SWAPPER_CTRL_RXF_W_FE |
3023                  SWAPPER_CTRL_XMSI_FE |
3024                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3025         if (sp->intr_type == INTA)
3026                 val64 |= SWAPPER_CTRL_XMSI_SE;
3027         writeq(val64, &bar0->swapper_ctrl);
3028 #else
3029         /*
3030          * Initially we enable all bits to make it accessible by the
3031          * driver, then we selectively enable only those bits that
3032          * we want to set.
3033          */
3034         val64 |= (SWAPPER_CTRL_TXP_FE |
3035                  SWAPPER_CTRL_TXP_SE |
3036                  SWAPPER_CTRL_TXD_R_FE |
3037                  SWAPPER_CTRL_TXD_R_SE |
3038                  SWAPPER_CTRL_TXD_W_FE |
3039                  SWAPPER_CTRL_TXD_W_SE |
3040                  SWAPPER_CTRL_TXF_R_FE |
3041                  SWAPPER_CTRL_RXD_R_FE |
3042                  SWAPPER_CTRL_RXD_R_SE |
3043                  SWAPPER_CTRL_RXD_W_FE |
3044                  SWAPPER_CTRL_RXD_W_SE |
3045                  SWAPPER_CTRL_RXF_W_FE |
3046                  SWAPPER_CTRL_XMSI_FE |
3047                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3048         if (sp->intr_type == INTA)
3049                 val64 |= SWAPPER_CTRL_XMSI_SE;
3050         writeq(val64, &bar0->swapper_ctrl);
3051 #endif
3052         val64 = readq(&bar0->swapper_ctrl);
3053
3054         /*
3055          * Verifying if endian settings are accurate by reading a
3056          * feedback register.
3057          */
3058         val64 = readq(&bar0->pif_rd_swapper_fb);
3059         if (val64 != 0x0123456789ABCDEFULL) {
3060                 /* Endian settings are incorrect, calls for another dekko. */
3061                 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3062                           dev->name);
3063                 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3064                           (unsigned long long) val64);
3065                 return FAILURE;
3066         }
3067
3068         return SUCCESS;
3069 }
3070
3071 static int wait_for_msix_trans(nic_t *nic, int i)
3072 {
3073         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3074         u64 val64;
3075         int ret = 0, cnt = 0;
3076
3077         do {
3078                 val64 = readq(&bar0->xmsi_access);
3079                 if (!(val64 & BIT(15)))
3080                         break;
3081                 mdelay(1);
3082                 cnt++;
3083         } while(cnt < 5);
3084         if (cnt == 5) {
3085                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3086                 ret = 1;
3087         }
3088
3089         return ret;
3090 }
3091
3092 void restore_xmsi_data(nic_t *nic)
3093 {
3094         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3095         u64 val64;
3096         int i;
3097
3098         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3099                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3100                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3101                 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3102                 writeq(val64, &bar0->xmsi_access);
3103                 if (wait_for_msix_trans(nic, i)) {
3104                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3105                         continue;
3106                 }
3107         }
3108 }
3109
3110 static void store_xmsi_data(nic_t *nic)
3111 {
3112         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3113         u64 val64, addr, data;
3114         int i;
3115
3116         /* Store and display */
3117         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3118                 val64 = (BIT(15) | vBIT(i, 26, 6));
3119                 writeq(val64, &bar0->xmsi_access);
3120                 if (wait_for_msix_trans(nic, i)) {
3121                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3122                         continue;
3123                 }
3124                 addr = readq(&bar0->xmsi_address);
3125                 data = readq(&bar0->xmsi_data);
3126                 if (addr && data) {
3127                         nic->msix_info[i].addr = addr;
3128                         nic->msix_info[i].data = data;
3129                 }
3130         }
3131 }
3132
3133 int s2io_enable_msi(nic_t *nic)
3134 {
3135         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3136         u16 msi_ctrl, msg_val;
3137         struct config_param *config = &nic->config;
3138         struct net_device *dev = nic->dev;
3139         u64 val64, tx_mat, rx_mat;
3140         int i, err;
3141
3142         val64 = readq(&bar0->pic_control);
3143         val64 &= ~BIT(1);
3144         writeq(val64, &bar0->pic_control);
3145
3146         err = pci_enable_msi(nic->pdev);
3147         if (err) {
3148                 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3149                           nic->dev->name);
3150                 return err;
3151         }
3152
3153         /*
3154          * Enable MSI and use MSI-1 in stead of the standard MSI-0
3155          * for interrupt handling.
3156          */
3157         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3158         msg_val ^= 0x1;
3159         pci_write_config_word(nic->pdev, 0x4c, msg_val);
3160         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3161
3162         pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3163         msi_ctrl |= 0x10;
3164         pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3165
3166         /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3167         tx_mat = readq(&bar0->tx_mat0_n[0]);
3168         for (i=0; i<config->tx_fifo_num; i++) {
3169                 tx_mat |= TX_MAT_SET(i, 1);
3170         }
3171         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3172
3173         rx_mat = readq(&bar0->rx_mat);
3174         for (i=0; i<config->rx_ring_num; i++) {
3175                 rx_mat |= RX_MAT_SET(i, 1);
3176         }
3177         writeq(rx_mat, &bar0->rx_mat);
3178
3179         dev->irq = nic->pdev->irq;
3180         return 0;
3181 }
3182
3183 int s2io_enable_msi_x(nic_t *nic)
3184 {
3185         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3186         u64 tx_mat, rx_mat;
3187         u16 msi_control; /* Temp variable */
3188         int ret, i, j, msix_indx = 1;
3189
3190         nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3191                                GFP_KERNEL);
3192         if (nic->entries == NULL) {
3193                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3194                 return -ENOMEM;
3195         }
3196         memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3197
3198         nic->s2io_entries =
3199                 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3200                                    GFP_KERNEL);
3201         if (nic->s2io_entries == NULL) {
3202                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3203                 kfree(nic->entries);
3204                 return -ENOMEM;
3205         }
3206         memset(nic->s2io_entries, 0,
3207                MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3208
3209         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3210                 nic->entries[i].entry = i;
3211                 nic->s2io_entries[i].entry = i;
3212                 nic->s2io_entries[i].arg = NULL;
3213                 nic->s2io_entries[i].in_use = 0;
3214         }
3215
3216         tx_mat = readq(&bar0->tx_mat0_n[0]);
3217         for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3218                 tx_mat |= TX_MAT_SET(i, msix_indx);
3219                 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3220                 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3221                 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3222         }
3223         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3224
3225         if (!nic->config.bimodal) {
3226                 rx_mat = readq(&bar0->rx_mat);
3227                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3228                         rx_mat |= RX_MAT_SET(j, msix_indx);
3229                         nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3230                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3231                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3232                 }
3233                 writeq(rx_mat, &bar0->rx_mat);
3234         } else {
3235                 tx_mat = readq(&bar0->tx_mat0_n[7]);
3236                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3237                         tx_mat |= TX_MAT_SET(i, msix_indx);
3238                         nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3239                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3240                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3241                 }
3242                 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3243         }
3244
3245         ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3246         if (ret) {
3247                 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3248                 kfree(nic->entries);
3249                 kfree(nic->s2io_entries);
3250                 nic->entries = NULL;
3251                 nic->s2io_entries = NULL;
3252                 return -ENOMEM;
3253         }
3254
3255         /*
3256          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3257          * in the herc NIC. (Temp change, needs to be removed later)
3258          */
3259         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3260         msi_control |= 0x1; /* Enable MSI */
3261         pci_write_config_word(nic->pdev, 0x42, msi_control);
3262
3263         return 0;
3264 }
3265
3266 /* ********************************************************* *
3267  * Functions defined below concern the OS part of the driver *
3268  * ********************************************************* */
3269
3270 /**
3271  *  s2io_open - open entry point of the driver
3272  *  @dev : pointer to the device structure.
3273  *  Description:
3274  *  This function is the open entry point of the driver. It mainly calls a
3275  *  function to allocate Rx buffers and inserts them into the buffer
3276  *  descriptors and then enables the Rx part of the NIC.
3277  *  Return value:
3278  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3279  *   file on failure.
3280  */
3281
3282 static int s2io_open(struct net_device *dev)
3283 {
3284         nic_t *sp = dev->priv;
3285         int err = 0;
3286         int i;
3287         u16 msi_control; /* Temp variable */
3288
3289         /*
3290          * Make sure you have link off by default every time
3291          * Nic is initialized
3292          */
3293         netif_carrier_off(dev);
3294         sp->last_link_state = 0;
3295
3296         /* Initialize H/W and enable interrupts */
3297         if (s2io_card_up(sp)) {
3298                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3299                           dev->name);
3300                 err = -ENODEV;
3301                 goto hw_init_failed;
3302         }
3303
3304         /* Store the values of the MSIX table in the nic_t structure */
3305         store_xmsi_data(sp);
3306
3307         /* After proper initialization of H/W, register ISR */
3308         if (sp->intr_type == MSI) {
3309                 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
3310                         SA_SHIRQ, sp->name, dev);
3311                 if (err) {
3312                         DBG_PRINT(ERR_DBG, "%s: MSI registration \
3313 failed\n", dev->name);
3314                         goto isr_registration_failed;
3315                 }
3316         }
3317         if (sp->intr_type == MSI_X) {
3318                 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
3319                         if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
3320                                 sprintf(sp->desc1, "%s:MSI-X-%d-TX",
3321                                         dev->name, i);
3322                                 err = request_irq(sp->entries[i].vector,
3323                                           s2io_msix_fifo_handle, 0, sp->desc1,
3324                                           sp->s2io_entries[i].arg);
3325                                 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc1,
3326                                     (unsigned long long)sp->msix_info[i].addr);
3327                         } else {
3328                                 sprintf(sp->desc2, "%s:MSI-X-%d-RX",
3329                                         dev->name, i);
3330                                 err = request_irq(sp->entries[i].vector,
3331                                           s2io_msix_ring_handle, 0, sp->desc2,
3332                                           sp->s2io_entries[i].arg);
3333                                 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc2,
3334                                      (unsigned long long)sp->msix_info[i].addr);
3335                         }
3336                         if (err) {
3337                                 DBG_PRINT(ERR_DBG, "%s: MSI-X-%d registration \
3338 failed\n", dev->name, i);
3339                                 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
3340                                 goto isr_registration_failed;
3341                         }
3342                         sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
3343                 }
3344         }
3345         if (sp->intr_type == INTA) {
3346                 err = request_irq((int) sp->pdev->irq, s2io_isr, SA_SHIRQ,
3347                                 sp->name, dev);
3348                 if (err) {
3349                         DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
3350                                   dev->name);
3351                         goto isr_registration_failed;
3352                 }
3353         }
3354
3355         if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3356                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3357                 err = -ENODEV;
3358                 goto setting_mac_address_failed;
3359         }
3360
3361         netif_start_queue(dev);
3362         return 0;
3363
3364 setting_mac_address_failed:
3365         if (sp->intr_type != MSI_X)
3366                 free_irq(sp->pdev->irq, dev);
3367 isr_registration_failed:
3368         del_timer_sync(&sp->alarm_timer);
3369         if (sp->intr_type == MSI_X) {
3370                 if (sp->device_type == XFRAME_II_DEVICE) {
3371                         for (i=1; (sp->s2io_entries[i].in_use ==
3372                                 MSIX_REGISTERED_SUCCESS); i++) {
3373                                 int vector = sp->entries[i].vector;
3374                                 void *arg = sp->s2io_entries[i].arg;
3375
3376                                 free_irq(vector, arg);
3377                         }
3378                         pci_disable_msix(sp->pdev);
3379
3380                         /* Temp */
3381                         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3382                         msi_control &= 0xFFFE; /* Disable MSI */
3383                         pci_write_config_word(sp->pdev, 0x42, msi_control);
3384                 }
3385         }
3386         else if (sp->intr_type == MSI)
3387                 pci_disable_msi(sp->pdev);
3388         s2io_reset(sp);
3389 hw_init_failed:
3390         if (sp->intr_type == MSI_X) {
3391                 if (sp->entries)
3392                         kfree(sp->entries);
3393                 if (sp->s2io_entries)
3394                         kfree(sp->s2io_entries);
3395         }
3396         return err;
3397 }
3398
3399 /**
3400  *  s2io_close -close entry point of the driver
3401  *  @dev : device pointer.
3402  *  Description:
3403  *  This is the stop entry point of the driver. It needs to undo exactly
3404  *  whatever was done by the open entry point,thus it's usually referred to
3405  *  as the close function.Among other things this function mainly stops the
3406  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3407  *  Return value:
3408  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3409  *  file on failure.
3410  */
3411
3412 static int s2io_close(struct net_device *dev)
3413 {
3414         nic_t *sp = dev->priv;
3415         int i;
3416         u16 msi_control;
3417
3418         flush_scheduled_work();
3419         netif_stop_queue(dev);
3420         /* Reset card, kill tasklet and free Tx and Rx buffers. */
3421         s2io_card_down(sp);
3422
3423         if (sp->intr_type == MSI_X) {
3424                 if (sp->device_type == XFRAME_II_DEVICE) {
3425                         for (i=1; (sp->s2io_entries[i].in_use ==
3426                                         MSIX_REGISTERED_SUCCESS); i++) {
3427                                 int vector = sp->entries[i].vector;
3428                                 void *arg = sp->s2io_entries[i].arg;
3429
3430                                 free_irq(vector, arg);
3431                         }
3432                         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3433                         msi_control &= 0xFFFE; /* Disable MSI */
3434                         pci_write_config_word(sp->pdev, 0x42, msi_control);
3435
3436                         pci_disable_msix(sp->pdev);
3437                 }
3438         }
3439         else {
3440                 free_irq(sp->pdev->irq, dev);
3441                 if (sp->intr_type == MSI)
3442                         pci_disable_msi(sp->pdev);
3443         }
3444         sp->device_close_flag = TRUE;   /* Device is shut down. */
3445         return 0;
3446 }
3447
3448 /**
3449  *  s2io_xmit - Tx entry point of te driver
3450  *  @skb : the socket buffer containing the Tx data.
3451  *  @dev : device pointer.
3452  *  Description :
3453  *  This function is the Tx entry point of the driver. S2IO NIC supports
3454  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
3455  *  NOTE: when device cant queue the pkt,just the trans_start variable will
3456  *  not be upadted.
3457  *  Return value:
3458  *  0 on success & 1 on failure.
3459  */
3460
3461 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3462 {
3463         nic_t *sp = dev->priv;
3464         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3465         register u64 val64;
3466         TxD_t *txdp;
3467         TxFIFO_element_t __iomem *tx_fifo;
3468         unsigned long flags;
3469 #ifdef NETIF_F_TSO
3470         int mss;
3471 #endif
3472         u16 vlan_tag = 0;
3473         int vlan_priority = 0;
3474         mac_info_t *mac_control;
3475         struct config_param *config;
3476
3477         mac_control = &sp->mac_control;
3478         config = &sp->config;
3479
3480         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
3481         spin_lock_irqsave(&sp->tx_lock, flags);
3482         if (atomic_read(&sp->card_state) == CARD_DOWN) {
3483                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
3484                           dev->name);
3485                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3486                 dev_kfree_skb(skb);
3487                 return 0;
3488         }
3489
3490         queue = 0;
3491
3492         /* Get Fifo number to Transmit based on vlan priority */
3493         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3494                 vlan_tag = vlan_tx_tag_get(skb);
3495                 vlan_priority = vlan_tag >> 13;
3496                 queue = config->fifo_mapping[vlan_priority];
3497         }
3498
3499         put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3500         get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
3501         txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off].
3502                 list_virt_addr;
3503
3504         queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
3505         /* Avoid "put" pointer going beyond "get" pointer */
3506         if (txdp->Host_Control || (((put_off + 1) % queue_len) == get_off)) {
3507                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3508                 netif_stop_queue(dev);
3509                 dev_kfree_skb(skb);
3510                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3511                 return 0;
3512         }
3513
3514         /* A buffer with no data will be dropped */
3515         if (!skb->len) {
3516                 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3517                 dev_kfree_skb(skb);
3518                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3519                 return 0;
3520         }
3521
3522         txdp->Control_1 = 0;
3523         txdp->Control_2 = 0;
3524 #ifdef NETIF_F_TSO
3525         mss = skb_shinfo(skb)->tso_size;
3526         if (mss) {
3527                 txdp->Control_1 |= TXD_TCP_LSO_EN;
3528                 txdp->Control_1 |= TXD_TCP_LSO_MSS(mss);
3529         }
3530 #endif
3531         if (skb->ip_summed == CHECKSUM_HW) {
3532                 txdp->Control_2 |=
3533                     (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3534                      TXD_TX_CKO_UDP_EN);
3535         }
3536         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
3537         txdp->Control_1 |= TXD_LIST_OWN_XENA;
3538         txdp->Control_2 |= config->tx_intr_type;
3539
3540         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3541                 txdp->Control_2 |= TXD_VLAN_ENABLE;
3542                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3543         }
3544
3545         frg_len = skb->len - skb->data_len;
3546         if (skb_shinfo(skb)->ufo_size) {
3547                 int ufo_size;
3548
3549                 ufo_size = skb_shinfo(skb)->ufo_size;
3550                 ufo_size &= ~7;
3551                 txdp->Control_1 |= TXD_UFO_EN;
3552                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
3553                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
3554 #ifdef __BIG_ENDIAN
3555                 sp->ufo_in_band_v[put_off] =
3556                                 (u64)skb_shinfo(skb)->ip6_frag_id;
3557 #else
3558                 sp->ufo_in_band_v[put_off] =
3559                                 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
3560 #endif
3561                 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
3562                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
3563                                         sp->ufo_in_band_v,
3564                                         sizeof(u64), PCI_DMA_TODEVICE);
3565                 txdp++;
3566                 txdp->Control_1 = 0;
3567                 txdp->Control_2 = 0;
3568         }
3569
3570         txdp->Buffer_Pointer = pci_map_single
3571             (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
3572         txdp->Host_Control = (unsigned long) skb;
3573         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
3574
3575         if (skb_shinfo(skb)->ufo_size)
3576                 txdp->Control_1 |= TXD_UFO_EN;
3577
3578         frg_cnt = skb_shinfo(skb)->nr_frags;
3579         /* For fragmented SKB. */
3580         for (i = 0; i < frg_cnt; i++) {
3581                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3582                 /* A '0' length fragment will be ignored */
3583                 if (!frag->size)
3584                         continue;
3585                 txdp++;
3586                 txdp->Buffer_Pointer = (u64) pci_map_page
3587                     (sp->pdev, frag->page, frag->page_offset,
3588                      frag->size, PCI_DMA_TODEVICE);
3589                 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
3590                 if (skb_shinfo(skb)->ufo_size)
3591                         txdp->Control_1 |= TXD_UFO_EN;
3592         }
3593         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
3594
3595         if (skb_shinfo(skb)->ufo_size)
3596                 frg_cnt++; /* as Txd0 was used for inband header */
3597
3598         tx_fifo = mac_control->tx_FIFO_start[queue];
3599         val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
3600         writeq(val64, &tx_fifo->TxDL_Pointer);
3601
3602         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
3603                  TX_FIFO_LAST_LIST);
3604
3605 #ifdef NETIF_F_TSO
3606         if (mss)
3607                 val64 |= TX_FIFO_SPECIAL_FUNC;
3608 #endif
3609         if (skb_shinfo(skb)->ufo_size)
3610                 val64 |= TX_FIFO_SPECIAL_FUNC;
3611         writeq(val64, &tx_fifo->List_Control);
3612
3613         mmiowb();
3614
3615         put_off++;
3616         put_off %= mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
3617         mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
3618
3619         /* Avoid "put" pointer going beyond "get" pointer */
3620         if (((put_off + 1) % queue_len) == get_off) {
3621                 DBG_PRINT(TX_DBG,
3622                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
3623                           put_off, get_off);
3624                 netif_stop_queue(dev);
3625         }
3626
3627         dev->trans_start = jiffies;
3628         spin_unlock_irqrestore(&sp->tx_lock, flags);
3629
3630         return 0;
3631 }
3632
3633 static void
3634 s2io_alarm_handle(unsigned long data)
3635 {
3636         nic_t *sp = (nic_t *)data;
3637
3638         alarm_intr_handler(sp);
3639         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
3640 }
3641
3642 static irqreturn_t
3643 s2io_msi_handle(int irq, void *dev_id, struct pt_regs *regs)
3644 {
3645         struct net_device *dev = (struct net_device *) dev_id;
3646         nic_t *sp = dev->priv;
3647         int i;
3648         int ret;
3649         mac_info_t *mac_control;
3650         struct config_param *config;
3651
3652         atomic_inc(&sp->isr_cnt);
3653         mac_control = &sp->mac_control;
3654         config = &sp->config;
3655         DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
3656
3657         /* If Intr is because of Rx Traffic */
3658         for (i = 0; i < config->rx_ring_num; i++)
3659                 rx_intr_handler(&mac_control->rings[i]);
3660
3661         /* If Intr is because of Tx Traffic */
3662         for (i = 0; i < config->tx_fifo_num; i++)
3663                 tx_intr_handler(&mac_control->fifos[i]);
3664
3665         /*
3666          * If the Rx buffer count is below the panic threshold then
3667          * reallocate the buffers from the interrupt handler itself,
3668          * else schedule a tasklet to reallocate the buffers.
3669          */
3670         for (i = 0; i < config->rx_ring_num; i++) {
3671                 int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
3672                 int level = rx_buffer_level(sp, rxb_size, i);
3673
3674                 if ((level == PANIC) && (!TASKLET_IN_USE)) {
3675                         DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", dev->name);
3676                         DBG_PRINT(INTR_DBG, "PANIC levels\n");
3677                         if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
3678                                 DBG_PRINT(ERR_DBG, "%s:Out of memory",
3679                                           dev->name);
3680                                 DBG_PRINT(ERR_DBG, " in ISR!!\n");
3681                                 clear_bit(0, (&sp->tasklet_status));
3682                                 atomic_dec(&sp->isr_cnt);
3683                                 return IRQ_HANDLED;
3684                         }
3685                         clear_bit(0, (&sp->tasklet_status));
3686                 } else if (level == LOW) {
3687                         tasklet_schedule(&sp->task);
3688                 }
3689         }
3690
3691         atomic_dec(&sp->isr_cnt);
3692         return IRQ_HANDLED;
3693 }
3694
3695 static irqreturn_t
3696 s2io_msix_ring_handle(int irq, void *dev_id, struct pt_regs *regs)
3697 {
3698         ring_info_t *ring = (ring_info_t *)dev_id;
3699         nic_t *sp = ring->nic;
3700         int rxb_size, level, rng_n;
3701
3702         atomic_inc(&sp->isr_cnt);
3703         rx_intr_handler(ring);
3704
3705         rng_n = ring->ring_no;
3706         rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
3707         level = rx_buffer_level(sp, rxb_size, rng_n);
3708
3709         if ((level == PANIC) && (!TASKLET_IN_USE)) {
3710                 int ret;
3711                 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
3712                 DBG_PRINT(INTR_DBG, "PANIC levels\n");
3713                 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
3714                         DBG_PRINT(ERR_DBG, "Out of memory in %s",
3715                                   __FUNCTION__);
3716                         clear_bit(0, (&sp->tasklet_status));
3717                         return IRQ_HANDLED;
3718                 }
3719                 clear_bit(0, (&sp->tasklet_status));
3720         } else if (level == LOW) {
3721                 tasklet_schedule(&sp->task);
3722         }
3723         atomic_dec(&sp->isr_cnt);
3724
3725         return IRQ_HANDLED;
3726 }
3727
3728 static irqreturn_t
3729 s2io_msix_fifo_handle(int irq, void *dev_id, struct pt_regs *regs)
3730 {
3731         fifo_info_t *fifo = (fifo_info_t *)dev_id;
3732         nic_t *sp = fifo->nic;
3733
3734         atomic_inc(&sp->isr_cnt);
3735         tx_intr_handler(fifo);
3736         atomic_dec(&sp->isr_cnt);
3737         return IRQ_HANDLED;
3738 }
3739
3740 static void s2io_txpic_intr_handle(nic_t *sp)
3741 {
3742         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3743         u64 val64;
3744
3745         val64 = readq(&bar0->pic_int_status);
3746         if (val64 & PIC_INT_GPIO) {
3747                 val64 = readq(&bar0->gpio_int_reg);
3748                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
3749                     (val64 & GPIO_INT_REG_LINK_UP)) {
3750                         val64 |=  GPIO_INT_REG_LINK_DOWN;
3751                         val64 |= GPIO_INT_REG_LINK_UP;
3752                         writeq(val64, &bar0->gpio_int_reg);
3753                         goto masking;
3754                 }
3755
3756                 if (((sp->last_link_state == LINK_UP) &&
3757                         (val64 & GPIO_INT_REG_LINK_DOWN)) ||
3758                 ((sp->last_link_state == LINK_DOWN) &&
3759                 (val64 & GPIO_INT_REG_LINK_UP))) {
3760                         val64 = readq(&bar0->gpio_int_mask);
3761                         val64 |=  GPIO_INT_MASK_LINK_DOWN;
3762                         val64 |= GPIO_INT_MASK_LINK_UP;
3763                         writeq(val64, &bar0->gpio_int_mask);
3764                         s2io_set_link((unsigned long)sp);
3765                 }
3766 masking:
3767                 if (sp->last_link_state == LINK_UP) {
3768                         /*enable down interrupt */
3769                         val64 = readq(&bar0->gpio_int_mask);
3770                         /* unmasks link down intr */
3771                         val64 &=  ~GPIO_INT_MASK_LINK_DOWN;
3772                         /* masks link up intr */
3773                         val64 |= GPIO_INT_MASK_LINK_UP;
3774                         writeq(val64, &bar0->gpio_int_mask);
3775                 } else {
3776                         /*enable UP Interrupt */
3777                         val64 = readq(&bar0->gpio_int_mask);
3778                         /* unmasks link up interrupt */
3779                         val64 &= ~GPIO_INT_MASK_LINK_UP;
3780                         /* masks link down interrupt */
3781                         val64 |=  GPIO_INT_MASK_LINK_DOWN;
3782                         writeq(val64, &bar0->gpio_int_mask);
3783                 }
3784         }
3785 }
3786
3787 /**
3788  *  s2io_isr - ISR handler of the device .
3789  *  @irq: the irq of the device.
3790  *  @dev_id: a void pointer to the dev structure of the NIC.
3791  *  @pt_regs: pointer to the registers pushed on the stack.
3792  *  Description:  This function is the ISR handler of the device. It
3793  *  identifies the reason for the interrupt and calls the relevant
3794  *  service routines. As a contongency measure, this ISR allocates the
3795  *  recv buffers, if their numbers are below the panic value which is
3796  *  presently set to 25% of the original number of rcv buffers allocated.
3797  *  Return value:
3798  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
3799  *   IRQ_NONE: will be returned if interrupt is not from our device
3800  */
3801 static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
3802 {
3803         struct net_device *dev = (struct net_device *) dev_id;
3804         nic_t *sp = dev->priv;
3805         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3806         int i;
3807         u64 reason = 0, val64;
3808         mac_info_t *mac_control;
3809         struct config_param *config;
3810
3811         atomic_inc(&sp->isr_cnt);
3812         mac_control = &sp->mac_control;
3813         config = &sp->config;
3814
3815         /*
3816          * Identify the cause for interrupt and call the appropriate
3817          * interrupt handler. Causes for the interrupt could be;
3818          * 1. Rx of packet.
3819          * 2. Tx complete.
3820          * 3. Link down.
3821          * 4. Error in any functional blocks of the NIC.
3822          */
3823         reason = readq(&bar0->general_int_status);
3824
3825         if (!reason) {
3826                 /* The interrupt was not raised by Xena. */
3827                 atomic_dec(&sp->isr_cnt);
3828                 return IRQ_NONE;
3829         }
3830
3831 #ifdef CONFIG_S2IO_NAPI
3832         if (reason & GEN_INTR_RXTRAFFIC) {
3833                 if (netif_rx_schedule_prep(dev)) {
3834                         en_dis_able_nic_intrs(sp, RX_TRAFFIC_INTR,
3835                                               DISABLE_INTRS);
3836                         __netif_rx_schedule(dev);
3837                 }
3838         }
3839 #else
3840         /* If Intr is because of Rx Traffic */
3841         if (reason & GEN_INTR_RXTRAFFIC) {
3842                 /*
3843                  * rx_traffic_int reg is an R1 register, writing all 1's
3844                  * will ensure that the actual interrupt causing bit get's
3845                  * cleared and hence a read can be avoided.
3846                  */
3847                 val64 = 0xFFFFFFFFFFFFFFFFULL;
3848                 writeq(val64, &bar0->rx_traffic_int);
3849                 for (i = 0; i < config->rx_ring_num; i++) {
3850                         rx_intr_handler(&mac_control->rings[i]);
3851                 }
3852         }
3853 #endif
3854
3855         /* If Intr is because of Tx Traffic */
3856         if (reason & GEN_INTR_TXTRAFFIC) {
3857                 /*
3858                  * tx_traffic_int reg is an R1 register, writing all 1's
3859                  * will ensure that the actual interrupt causing bit get's
3860                  * cleared and hence a read can be avoided.
3861                  */
3862                 val64 = 0xFFFFFFFFFFFFFFFFULL;
3863                 writeq(val64, &bar0->tx_traffic_int);
3864
3865                 for (i = 0; i < config->tx_fifo_num; i++)
3866                         tx_intr_handler(&mac_control->fifos[i]);
3867         }
3868
3869         if (reason & GEN_INTR_TXPIC)
3870                 s2io_txpic_intr_handle(sp);
3871         /*
3872          * If the Rx buffer count is below the panic threshold then
3873          * reallocate the buffers from the interrupt handler itself,
3874          * else schedule a tasklet to reallocate the buffers.
3875          */
3876 #ifndef CONFIG_S2IO_NAPI
3877         for (i = 0; i < config->rx_ring_num; i++) {
3878                 int ret;
3879                 int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
3880                 int level = rx_buffer_level(sp, rxb_size, i);
3881
3882                 if ((level == PANIC) && (!TASKLET_IN_USE)) {
3883                         DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", dev->name);
3884                         DBG_PRINT(INTR_DBG, "PANIC levels\n");
3885                         if ((ret = fill_rx_buffers(sp, i)) == -ENOMEM) {
3886                                 DBG_PRINT(ERR_DBG, "%s:Out of memory",
3887                                           dev->name);
3888                                 DBG_PRINT(ERR_DBG, " in ISR!!\n");
3889                                 clear_bit(0, (&sp->tasklet_status));
3890                                 atomic_dec(&sp->isr_cnt);
3891                                 return IRQ_HANDLED;
3892                         }
3893                         clear_bit(0, (&sp->tasklet_status));
3894                 } else if (level == LOW) {
3895                         tasklet_schedule(&sp->task);
3896                 }
3897         }
3898 #endif
3899
3900         atomic_dec(&sp->isr_cnt);
3901         return IRQ_HANDLED;
3902 }
3903
3904 /**
3905  * s2io_updt_stats -
3906  */
3907 static void s2io_updt_stats(nic_t *sp)
3908 {
3909         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3910         u64 val64;
3911         int cnt = 0;
3912
3913         if (atomic_read(&sp->card_state) == CARD_UP) {
3914                 /* Apprx 30us on a 133 MHz bus */
3915                 val64 = SET_UPDT_CLICKS(10) |
3916                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
3917                 writeq(val64, &bar0->stat_cfg);
3918                 do {
3919                         udelay(100);
3920                         val64 = readq(&bar0->stat_cfg);
3921                         if (!(val64 & BIT(0)))
3922                                 break;
3923                         cnt++;
3924                         if (cnt == 5)
3925                                 break; /* Updt failed */
3926                 } while(1);
3927         }
3928 }
3929
3930 /**
3931  *  s2io_get_stats - Updates the device statistics structure.
3932  *  @dev : pointer to the device structure.
3933  *  Description:
3934  *  This function updates the device statistics structure in the s2io_nic
3935  *  structure and returns a pointer to the same.
3936  *  Return value:
3937  *  pointer to the updated net_device_stats structure.
3938  */
3939
3940 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
3941 {
3942         nic_t *sp = dev->priv;
3943         mac_info_t *mac_control;
3944         struct config_param *config;
3945
3946
3947         mac_control = &sp->mac_control;
3948         config = &sp->config;
3949
3950         /* Configure Stats for immediate updt */
3951         s2io_updt_stats(sp);
3952
3953         sp->stats.tx_packets =
3954                 le32_to_cpu(mac_control->stats_info->tmac_frms);
3955         sp->stats.tx_errors =
3956                 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
3957         sp->stats.rx_errors =
3958                 le32_to_cpu(mac_control->stats_info->rmac_drop_frms);
3959         sp->stats.multicast =
3960                 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
3961         sp->stats.rx_length_errors =
3962                 le32_to_cpu(mac_control->stats_info->rmac_long_frms);
3963
3964         return (&sp->stats);
3965 }
3966
3967 /**
3968  *  s2io_set_multicast - entry point for multicast address enable/disable.
3969  *  @dev : pointer to the device structure
3970  *  Description:
3971  *  This function is a driver entry point which gets called by the kernel
3972  *  whenever multicast addresses must be enabled/disabled. This also gets
3973  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
3974  *  determine, if multicast address must be enabled or if promiscuous mode
3975  *  is to be disabled etc.
3976  *  Return value:
3977  *  void.
3978  */
3979
3980 static void s2io_set_multicast(struct net_device *dev)
3981 {
3982         int i, j, prev_cnt;
3983         struct dev_mc_list *mclist;
3984         nic_t *sp = dev->priv;
3985         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3986         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
3987             0xfeffffffffffULL;
3988         u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
3989         void __iomem *add;
3990
3991         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
3992                 /*  Enable all Multicast addresses */
3993                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
3994                        &bar0->rmac_addr_data0_mem);
3995                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
3996                        &bar0->rmac_addr_data1_mem);
3997                 val64 = RMAC_ADDR_CMD_MEM_WE |
3998                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
3999                     RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4000                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4001                 /* Wait till command completes */
4002                 wait_for_cmd_complete(sp);
4003
4004                 sp->m_cast_flg = 1;
4005                 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4006         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4007                 /*  Disable all Multicast addresses */
4008                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4009                        &bar0->rmac_addr_data0_mem);
4010                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4011                        &bar0->rmac_addr_data1_mem);
4012                 val64 = RMAC_ADDR_CMD_MEM_WE |
4013                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4014                     RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4015                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4016                 /* Wait till command completes */
4017                 wait_for_cmd_complete(sp);
4018
4019                 sp->m_cast_flg = 0;
4020                 sp->all_multi_pos = 0;
4021         }
4022
4023         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4024                 /*  Put the NIC into promiscuous mode */
4025                 add = &bar0->mac_cfg;
4026                 val64 = readq(&bar0->mac_cfg);
4027                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4028
4029                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4030                 writel((u32) val64, add);
4031                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4032                 writel((u32) (val64 >> 32), (add + 4));
4033
4034                 val64 = readq(&bar0->mac_cfg);
4035                 sp->promisc_flg = 1;
4036                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4037                           dev->name);
4038         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4039                 /*  Remove the NIC from promiscuous mode */
4040                 add = &bar0->mac_cfg;
4041                 val64 = readq(&bar0->mac_cfg);
4042                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4043
4044                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4045                 writel((u32) val64, add);
4046                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4047                 writel((u32) (val64 >> 32), (add + 4));
4048
4049                 val64 = readq(&bar0->mac_cfg);
4050                 sp->promisc_flg = 0;
4051                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
4052                           dev->name);
4053         }
4054
4055         /*  Update individual M_CAST address list */
4056         if ((!sp->m_cast_flg) && dev->mc_count) {
4057                 if (dev->mc_count >
4058                     (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4059                         DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4060                                   dev->name);
4061                         DBG_PRINT(ERR_DBG, "can be added, please enable ");
4062                         DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4063                         return;
4064                 }
4065
4066                 prev_cnt = sp->mc_addr_count;
4067                 sp->mc_addr_count = dev->mc_count;
4068
4069                 /* Clear out the previous list of Mc in the H/W. */
4070                 for (i = 0; i < prev_cnt; i++) {
4071                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4072                                &bar0->rmac_addr_data0_mem);
4073                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4074                                 &bar0->rmac_addr_data1_mem);
4075                         val64 = RMAC_ADDR_CMD_MEM_WE |
4076                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4077                             RMAC_ADDR_CMD_MEM_OFFSET
4078                             (MAC_MC_ADDR_START_OFFSET + i);
4079                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4080
4081                         /* Wait for command completes */
4082                         if (wait_for_cmd_complete(sp)) {
4083                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4084                                           dev->name);
4085                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4086                                 return;
4087                         }
4088                 }
4089
4090                 /* Create the new Rx filter list and update the same in H/W. */
4091                 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4092                      i++, mclist = mclist->next) {
4093                         memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4094                                ETH_ALEN);
4095                         mac_addr = 0;
4096                         for (j = 0; j < ETH_ALEN; j++) {
4097                                 mac_addr |= mclist->dmi_addr[j];
4098                                 mac_addr <<= 8;
4099                         }
4100                         mac_addr >>= 8;
4101                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4102                                &bar0->rmac_addr_data0_mem);
4103                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4104                                 &bar0->rmac_addr_data1_mem);
4105                         val64 = RMAC_ADDR_CMD_MEM_WE |
4106                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4107                             RMAC_ADDR_CMD_MEM_OFFSET
4108                             (i + MAC_MC_ADDR_START_OFFSET);
4109                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4110
4111                         /* Wait for command completes */
4112                         if (wait_for_cmd_complete(sp)) {
4113                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4114                                           dev->name);
4115                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4116                                 return;
4117                         }
4118                 }
4119         }
4120 }
4121
4122 /**
4123  *  s2io_set_mac_addr - Programs the Xframe mac address
4124  *  @dev : pointer to the device structure.
4125  *  @addr: a uchar pointer to the new mac address which is to be set.
4126  *  Description : This procedure will program the Xframe to receive
4127  *  frames with new Mac Address
4128  *  Return value: SUCCESS on success and an appropriate (-)ve integer
4129  *  as defined in errno.h file on failure.
4130  */
4131
4132 int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4133 {
4134         nic_t *sp = dev->priv;
4135         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4136         register u64 val64, mac_addr = 0;
4137         int i;
4138
4139         /*
4140          * Set the new MAC address as the new unicast filter and reflect this
4141          * change on the device address registered with the OS. It will be
4142          * at offset 0.
4143          */
4144         for (i = 0; i < ETH_ALEN; i++) {
4145                 mac_addr <<= 8;
4146                 mac_addr |= addr[i];
4147         }
4148
4149         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4150                &bar0->rmac_addr_data0_mem);
4151
4152         val64 =
4153             RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4154             RMAC_ADDR_CMD_MEM_OFFSET(0);
4155         writeq(val64, &bar0->rmac_addr_cmd_mem);
4156         /* Wait till command completes */
4157         if (wait_for_cmd_complete(sp)) {
4158                 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4159                 return FAILURE;
4160         }
4161
4162         return SUCCESS;
4163 }
4164
4165 /**
4166  * s2io_ethtool_sset - Sets different link parameters.
4167  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
4168  * @info: pointer to the structure with parameters given by ethtool to set
4169  * link information.
4170  * Description:
4171  * The function sets different link parameters provided by the user onto
4172  * the NIC.
4173  * Return value:
4174  * 0 on success.
4175 */
4176
4177 static int s2io_ethtool_sset(struct net_device *dev,
4178                              struct ethtool_cmd *info)
4179 {
4180         nic_t *sp = dev->priv;
4181         if ((info->autoneg == AUTONEG_ENABLE) ||
4182             (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4183                 return -EINVAL;
4184         else {
4185                 s2io_close(sp->dev);
4186                 s2io_open(sp->dev);
4187         }
4188
4189         return 0;
4190 }
4191
4192 /**
4193  * s2io_ethtol_gset - Return link specific information.
4194  * @sp : private member of the device structure, pointer to the
4195  *      s2io_nic structure.
4196  * @info : pointer to the structure with parameters given by ethtool
4197  * to return link information.
4198  * Description:
4199  * Returns link specific information like speed, duplex etc.. to ethtool.
4200  * Return value :
4201  * return 0 on success.
4202  */
4203
4204 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4205 {
4206         nic_t *sp = dev->priv;
4207         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4208         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4209         info->port = PORT_FIBRE;
4210         /* info->transceiver?? TODO */
4211
4212         if (netif_carrier_ok(sp->dev)) {
4213                 info->speed = 10000;
4214                 info->duplex = DUPLEX_FULL;
4215         } else {
4216                 info->speed = -1;
4217                 info->duplex = -1;
4218         }
4219
4220         info->autoneg = AUTONEG_DISABLE;
4221         return 0;
4222 }
4223
4224 /**
4225  * s2io_ethtool_gdrvinfo - Returns driver specific information.
4226  * @sp : private member of the device structure, which is a pointer to the
4227  * s2io_nic structure.
4228  * @info : pointer to the structure with parameters given by ethtool to
4229  * return driver information.
4230  * Description:
4231  * Returns driver specefic information like name, version etc.. to ethtool.
4232  * Return value:
4233  *  void
4234  */
4235
4236 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4237                                   struct ethtool_drvinfo *info)
4238 {
4239         nic_t *sp = dev->priv;
4240
4241         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4242         strncpy(info->version, s2io_driver_version, sizeof(info->version));
4243         strncpy(info->fw_version, "", sizeof(info->fw_version));
4244         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
4245         info->regdump_len = XENA_REG_SPACE;
4246         info->eedump_len = XENA_EEPROM_SPACE;
4247         info->testinfo_len = S2IO_TEST_LEN;
4248         info->n_stats = S2IO_STAT_LEN;
4249 }
4250
4251 /**
4252  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
4253  *  @sp: private member of the device structure, which is a pointer to the
4254  *  s2io_nic structure.
4255  *  @regs : pointer to the structure with parameters given by ethtool for
4256  *  dumping the registers.
4257  *  @reg_space: The input argumnet into which all the registers are dumped.
4258  *  Description:
4259  *  Dumps the entire register space of xFrame NIC into the user given
4260  *  buffer area.
4261  * Return value :
4262  * void .
4263 */
4264
4265 static void s2io_ethtool_gregs(struct net_device *dev,
4266                                struct ethtool_regs *regs, void *space)
4267 {
4268         int i;
4269         u64 reg;
4270         u8 *reg_space = (u8 *) space;
4271         nic_t *sp = dev->priv;
4272
4273         regs->len = XENA_REG_SPACE;
4274         regs->version = sp->pdev->subsystem_device;
4275
4276         for (i = 0; i < regs->len; i += 8) {
4277                 reg = readq(sp->bar0 + i);
4278                 memcpy((reg_space + i), &reg, 8);
4279         }
4280 }
4281
4282 /**
4283  *  s2io_phy_id  - timer function that alternates adapter LED.
4284  *  @data : address of the private member of the device structure, which
4285  *  is a pointer to the s2io_nic structure, provided as an u32.
4286  * Description: This is actually the timer function that alternates the
4287  * adapter LED bit of the adapter control bit to set/reset every time on
4288  * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
4289  *  once every second.
4290 */
4291 static void s2io_phy_id(unsigned long data)
4292 {
4293         nic_t *sp = (nic_t *) data;
4294         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4295         u64 val64 = 0;
4296         u16 subid;
4297
4298         subid = sp->pdev->subsystem_device;
4299         if ((sp->device_type == XFRAME_II_DEVICE) ||
4300                    ((subid & 0xFF) >= 0x07)) {
4301                 val64 = readq(&bar0->gpio_control);
4302                 val64 ^= GPIO_CTRL_GPIO_0;
4303                 writeq(val64, &bar0->gpio_control);
4304         } else {
4305                 val64 = readq(&bar0->adapter_control);
4306                 val64 ^= ADAPTER_LED_ON;
4307                 writeq(val64, &bar0->adapter_control);
4308         }
4309
4310         mod_timer(&sp->id_timer, jiffies + HZ / 2);
4311 }
4312
4313 /**
4314  * s2io_ethtool_idnic - To physically identify the nic on the system.
4315  * @sp : private member of the device structure, which is a pointer to the
4316  * s2io_nic structure.
4317  * @id : pointer to the structure with identification parameters given by
4318  * ethtool.
4319  * Description: Used to physically identify the NIC on the system.
4320  * The Link LED will blink for a time specified by the user for
4321  * identification.
4322  * NOTE: The Link has to be Up to be able to blink the LED. Hence
4323  * identification is possible only if it's link is up.
4324  * Return value:
4325  * int , returns 0 on success
4326  */
4327
4328 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4329 {
4330         u64 val64 = 0, last_gpio_ctrl_val;
4331         nic_t *sp = dev->priv;
4332         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4333         u16 subid;
4334
4335         subid = sp->pdev->subsystem_device;
4336         last_gpio_ctrl_val = readq(&bar0->gpio_control);
4337         if ((sp->device_type == XFRAME_I_DEVICE) &&
4338                 ((subid & 0xFF) < 0x07)) {
4339                 val64 = readq(&bar0->adapter_control);
4340                 if (!(val64 & ADAPTER_CNTL_EN)) {
4341                         printk(KERN_ERR
4342                                "Adapter Link down, cannot blink LED\n");
4343                         return -EFAULT;
4344                 }
4345         }
4346         if (sp->id_timer.function == NULL) {
4347                 init_timer(&sp->id_timer);
4348                 sp->id_timer.function = s2io_phy_id;
4349                 sp->id_timer.data = (unsigned long) sp;
4350         }
4351         mod_timer(&sp->id_timer, jiffies);
4352         if (data)
4353                 msleep_interruptible(data * HZ);
4354         else
4355                 msleep_interruptible(MAX_FLICKER_TIME);
4356         del_timer_sync(&sp->id_timer);
4357
4358         if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
4359                 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4360                 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4361         }
4362
4363         return 0;
4364 }
4365
4366 /**
4367  * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
4368  * @sp : private member of the device structure, which is a pointer to the
4369  *      s2io_nic structure.
4370  * @ep : pointer to the structure with pause parameters given by ethtool.
4371  * Description:
4372  * Returns the Pause frame generation and reception capability of the NIC.
4373  * Return value:
4374  *  void
4375  */
4376 static void s2io_ethtool_getpause_data(struct net_device *dev,
4377                                        struct ethtool_pauseparam *ep)
4378 {
4379         u64 val64;
4380         nic_t *sp = dev->priv;
4381         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4382
4383         val64 = readq(&bar0->rmac_pause_cfg);
4384         if (val64 & RMAC_PAUSE_GEN_ENABLE)
4385                 ep->tx_pause = TRUE;
4386         if (val64 & RMAC_PAUSE_RX_ENABLE)
4387                 ep->rx_pause = TRUE;
4388         ep->autoneg = FALSE;
4389 }
4390
4391 /**
4392  * s2io_ethtool_setpause_data -  set/reset pause frame generation.
4393  * @sp : private member of the device structure, which is a pointer to the
4394  *      s2io_nic structure.
4395  * @ep : pointer to the structure with pause parameters given by ethtool.
4396  * Description:
4397  * It can be used to set or reset Pause frame generation or reception
4398  * support of the NIC.
4399  * Return value:
4400  * int, returns 0 on Success
4401  */
4402
4403 static int s2io_ethtool_setpause_data(struct net_device *dev,
4404                                struct ethtool_pauseparam *ep)
4405 {
4406         u64 val64;
4407         nic_t *sp = dev->priv;
4408         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4409
4410         val64 = readq(&bar0->rmac_pause_cfg);
4411         if (ep->tx_pause)
4412                 val64 |= RMAC_PAUSE_GEN_ENABLE;
4413         else
4414                 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4415         if (ep->rx_pause)
4416                 val64 |= RMAC_PAUSE_RX_ENABLE;
4417         else
4418                 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4419         writeq(val64, &bar0->rmac_pause_cfg);
4420         return 0;
4421 }
4422
4423 /**
4424  * read_eeprom - reads 4 bytes of data from user given offset.
4425  * @sp : private member of the device structure, which is a pointer to the
4426  *      s2io_nic structure.
4427  * @off : offset at which the data must be written
4428  * @data : Its an output parameter where the data read at the given
4429  *      offset is stored.
4430  * Description:
4431  * Will read 4 bytes of data from the user given offset and return the
4432  * read data.
4433  * NOTE: Will allow to read only part of the EEPROM visible through the
4434  *   I2C bus.
4435  * Return value:
4436  *  -1 on failure and 0 on success.
4437  */
4438
4439 #define S2IO_DEV_ID             5
4440 static int read_eeprom(nic_t * sp, int off, u64 * data)
4441 {
4442         int ret = -1;
4443         u32 exit_cnt = 0;
4444         u64 val64;
4445         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4446
4447         if (sp->device_type == XFRAME_I_DEVICE) {
4448                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4449                     I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4450                     I2C_CONTROL_CNTL_START;
4451                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4452
4453                 while (exit_cnt < 5) {
4454                         val64 = readq(&bar0->i2c_control);
4455                         if (I2C_CONTROL_CNTL_END(val64)) {
4456                                 *data = I2C_CONTROL_GET_DATA(val64);
4457                                 ret = 0;
4458                                 break;
4459                         }
4460                         msleep(50);
4461                         exit_cnt++;
4462                 }
4463         }
4464
4465         if (sp->device_type == XFRAME_II_DEVICE) {
4466                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4467                         SPI_CONTROL_BYTECNT(0x3) |
4468                         SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4469                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4470                 val64 |= SPI_CONTROL_REQ;
4471                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4472                 while (exit_cnt < 5) {
4473                         val64 = readq(&bar0->spi_control);
4474                         if (val64 & SPI_CONTROL_NACK) {
4475                                 ret = 1;
4476                                 break;
4477                         } else if (val64 & SPI_CONTROL_DONE) {
4478                                 *data = readq(&bar0->spi_data);
4479                                 *data &= 0xffffff;
4480                                 ret = 0;
4481                                 break;
4482                         }
4483                         msleep(50);
4484                         exit_cnt++;
4485                 }
4486         }
4487         return ret;
4488 }
4489
4490 /**
4491  *  write_eeprom - actually writes the relevant part of the data value.
4492  *  @sp : private member of the device structure, which is a pointer to the
4493  *       s2io_nic structure.
4494  *  @off : offset at which the data must be written
4495  *  @data : The data that is to be written
4496  *  @cnt : Number of bytes of the data that are actually to be written into
4497  *  the Eeprom. (max of 3)
4498  * Description:
4499  *  Actually writes the relevant part of the data value into the Eeprom
4500  *  through the I2C bus.
4501  * Return value:
4502  *  0 on success, -1 on failure.
4503  */
4504
4505 static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
4506 {
4507         int exit_cnt = 0, ret = -1;
4508         u64 val64;
4509         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4510
4511         if (sp->device_type == XFRAME_I_DEVICE) {
4512                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4513                     I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
4514                     I2C_CONTROL_CNTL_START;
4515                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4516
4517                 while (exit_cnt < 5) {
4518                         val64 = readq(&bar0->i2c_control);
4519                         if (I2C_CONTROL_CNTL_END(val64)) {
4520                                 if (!(val64 & I2C_CONTROL_NACK))
4521                                         ret = 0;
4522                                 break;
4523                         }
4524                         msleep(50);
4525                         exit_cnt++;
4526                 }
4527         }
4528
4529         if (sp->device_type == XFRAME_II_DEVICE) {
4530                 int write_cnt = (cnt == 8) ? 0 : cnt;
4531                 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
4532
4533                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4534                         SPI_CONTROL_BYTECNT(write_cnt) |
4535                         SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
4536                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4537                 val64 |= SPI_CONTROL_REQ;
4538                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4539                 while (exit_cnt < 5) {
4540                         val64 = readq(&bar0->spi_control);
4541                         if (val64 & SPI_CONTROL_NACK) {
4542                                 ret = 1;
4543                                 break;
4544                         } else if (val64 & SPI_CONTROL_DONE) {
4545                                 ret = 0;
4546                                 break;
4547                         }
4548                         msleep(50);
4549                         exit_cnt++;
4550                 }
4551         }
4552         return ret;
4553 }
4554
4555 /**
4556  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
4557  *  @sp : private member of the device structure, which is a pointer to the *       s2io_nic structure.
4558  *  @eeprom : pointer to the user level structure provided by ethtool,
4559  *  containing all relevant information.
4560  *  @data_buf : user defined value to be written into Eeprom.
4561  *  Description: Reads the values stored in the Eeprom at given offset
4562  *  for a given length. Stores these values int the input argument data
4563  *  buffer 'data_buf' and returns these to the caller (ethtool.)
4564  *  Return value:
4565  *  int  0 on success
4566  */
4567
4568 static int s2io_ethtool_geeprom(struct net_device *dev,
4569                          struct ethtool_eeprom *eeprom, u8 * data_buf)
4570 {
4571         u32 i, valid;
4572         u64 data;
4573         nic_t *sp = dev->priv;
4574
4575         eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
4576
4577         if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
4578                 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
4579
4580         for (i = 0; i < eeprom->len; i += 4) {
4581                 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
4582                         DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
4583                         return -EFAULT;
4584                 }
4585                 valid = INV(data);
4586                 memcpy((data_buf + i), &valid, 4);
4587         }
4588         return 0;
4589 }
4590
4591 /**
4592  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
4593  *  @sp : private member of the device structure, which is a pointer to the
4594  *  s2io_nic structure.
4595  *  @eeprom : pointer to the user level structure provided by ethtool,
4596  *  containing all relevant information.
4597  *  @data_buf ; user defined value to be written into Eeprom.
4598  *  Description:
4599  *  Tries to write the user provided value in the Eeprom, at the offset
4600  *  given by the user.
4601  *  Return value:
4602  *  0 on success, -EFAULT on failure.
4603  */
4604
4605 static int s2io_ethtool_seeprom(struct net_device *dev,
4606                                 struct ethtool_eeprom *eeprom,
4607                                 u8 * data_buf)
4608 {
4609         int len = eeprom->len, cnt = 0;
4610         u64 valid = 0, data;
4611         nic_t *sp = dev->priv;
4612
4613         if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
4614                 DBG_PRINT(ERR_DBG,
4615                           "ETHTOOL_WRITE_EEPROM Err: Magic value ");
4616                 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
4617                           eeprom->magic);
4618                 return -EFAULT;
4619         }
4620
4621         while (len) {
4622                 data = (u32) data_buf[cnt] & 0x000000FF;
4623                 if (data) {
4624                         valid = (u32) (data << 24);
4625                 } else
4626                         valid = data;
4627
4628                 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
4629                         DBG_PRINT(ERR_DBG,
4630                                   "ETHTOOL_WRITE_EEPROM Err: Cannot ");
4631                         DBG_PRINT(ERR_DBG,
4632                                   "write into the specified offset\n");
4633                         return -EFAULT;
4634                 }
4635                 cnt++;
4636                 len--;
4637         }
4638
4639         return 0;
4640 }
4641
4642 /**
4643  * s2io_register_test - reads and writes into all clock domains.
4644  * @sp : private member of the device structure, which is a pointer to the
4645  * s2io_nic structure.
4646  * @data : variable that returns the result of each of the test conducted b
4647  * by the driver.
4648  * Description:
4649  * Read and write into all clock domains. The NIC has 3 clock domains,
4650  * see that registers in all the three regions are accessible.
4651  * Return value:
4652  * 0 on success.
4653  */
4654
4655 static int s2io_register_test(nic_t * sp, uint64_t * data)
4656 {
4657         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4658         u64 val64 = 0, exp_val;
4659         int fail = 0;
4660
4661         val64 = readq(&bar0->pif_rd_swapper_fb);
4662         if (val64 != 0x123456789abcdefULL) {
4663                 fail = 1;
4664                 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
4665         }
4666
4667         val64 = readq(&bar0->rmac_pause_cfg);
4668         if (val64 != 0xc000ffff00000000ULL) {
4669                 fail = 1;
4670                 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
4671         }
4672
4673         val64 = readq(&bar0->rx_queue_cfg);
4674         if (sp->device_type == XFRAME_II_DEVICE)
4675                 exp_val = 0x0404040404040404ULL;
4676         else
4677                 exp_val = 0x0808080808080808ULL;
4678         if (val64 != exp_val) {
4679                 fail = 1;
4680                 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
4681         }
4682
4683         val64 = readq(&bar0->xgxs_efifo_cfg);
4684         if (val64 != 0x000000001923141EULL) {
4685                 fail = 1;
4686                 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
4687         }
4688
4689         val64 = 0x5A5A5A5A5A5A5A5AULL;
4690         writeq(val64, &bar0->xmsi_data);
4691         val64 = readq(&bar0->xmsi_data);
4692         if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
4693                 fail = 1;
4694                 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
4695         }
4696
4697         val64 = 0xA5A5A5A5A5A5A5A5ULL;
4698         writeq(val64, &bar0->xmsi_data);
4699         val64 = readq(&bar0->xmsi_data);
4700         if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
4701                 fail = 1;
4702                 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
4703         }
4704
4705         *data = fail;
4706         return fail;
4707 }
4708
4709 /**
4710  * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
4711  * @sp : private member of the device structure, which is a pointer to the
4712  * s2io_nic structure.
4713  * @data:variable that returns the result of each of the test conducted by
4714  * the driver.
4715  * Description:
4716  * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
4717  * register.
4718  * Return value:
4719  * 0 on success.
4720  */
4721
4722 static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
4723 {
4724         int fail = 0;
4725         u64 ret_data, org_4F0, org_7F0;
4726         u8 saved_4F0 = 0, saved_7F0 = 0;
4727         struct net_device *dev = sp->dev;
4728
4729         /* Test Write Error at offset 0 */
4730         /* Note that SPI interface allows write access to all areas
4731          * of EEPROM. Hence doing all negative testing only for Xframe I.
4732          */
4733         if (sp->device_type == XFRAME_I_DEVICE)
4734                 if (!write_eeprom(sp, 0, 0, 3))
4735                         fail = 1;
4736
4737         /* Save current values at offsets 0x4F0 and 0x7F0 */
4738         if (!read_eeprom(sp, 0x4F0, &org_4F0))
4739                 saved_4F0 = 1;
4740         if (!read_eeprom(sp, 0x7F0, &org_7F0))
4741                 saved_7F0 = 1;
4742
4743         /* Test Write at offset 4f0 */
4744         if (write_eeprom(sp, 0x4F0, 0x012345, 3))
4745                 fail = 1;
4746         if (read_eeprom(sp, 0x4F0, &ret_data))
4747                 fail = 1;
4748
4749         if (ret_data != 0x012345) {
4750                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
4751                         "Data written %llx Data read %llx\n",
4752                         dev->name, (unsigned long long)0x12345,
4753                         (unsigned long long)ret_data);
4754                 fail = 1;
4755         }
4756
4757         /* Reset the EEPROM data go FFFF */
4758         write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
4759
4760         /* Test Write Request Error at offset 0x7c */
4761         if (sp->device_type == XFRAME_I_DEVICE)
4762                 if (!write_eeprom(sp, 0x07C, 0, 3))
4763                         fail = 1;
4764
4765         /* Test Write Request at offset 0x7f0 */
4766         if (write_eeprom(sp, 0x7F0, 0x012345, 3))
4767                 fail = 1;
4768         if (read_eeprom(sp, 0x7F0, &ret_data))
4769                 fail = 1;
4770
4771         if (ret_data != 0x012345) {
4772                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
4773                         "Data written %llx Data read %llx\n",
4774                         dev->name, (unsigned long long)0x12345,
4775                         (unsigned long long)ret_data);
4776                 fail = 1;
4777         }
4778
4779         /* Reset the EEPROM data go FFFF */
4780         write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
4781
4782         if (sp->device_type == XFRAME_I_DEVICE) {
4783                 /* Test Write Error at offset 0x80 */
4784                 if (!write_eeprom(sp, 0x080, 0, 3))
4785                         fail = 1;
4786
4787                 /* Test Write Error at offset 0xfc */
4788                 if (!write_eeprom(sp, 0x0FC, 0, 3))
4789                         fail = 1;
4790
4791                 /* Test Write Error at offset 0x100 */
4792                 if (!write_eeprom(sp, 0x100, 0, 3))
4793                         fail = 1;
4794
4795                 /* Test Write Error at offset 4ec */
4796                 if (!write_eeprom(sp, 0x4EC, 0, 3))
4797                         fail = 1;
4798         }
4799
4800         /* Restore values at offsets 0x4F0 and 0x7F0 */
4801         if (saved_4F0)
4802                 write_eeprom(sp, 0x4F0, org_4F0, 3);
4803         if (saved_7F0)
4804                 write_eeprom(sp, 0x7F0, org_7F0, 3);
4805
4806         *data = fail;
4807         return fail;
4808 }
4809
4810 /**
4811  * s2io_bist_test - invokes the MemBist test of the card .
4812  * @sp : private member of the device structure, which is a pointer to the
4813  * s2io_nic structure.
4814  * @data:variable that returns the result of each of the test conducted by
4815  * the driver.
4816  * Description:
4817  * This invokes the MemBist test of the card. We give around
4818  * 2 secs time for the Test to complete. If it's still not complete
4819  * within this peiod, we consider that the test failed.
4820  * Return value:
4821  * 0 on success and -1 on failure.
4822  */
4823
4824 static int s2io_bist_test(nic_t * sp, uint64_t * data)
4825 {
4826         u8 bist = 0;
4827         int cnt = 0, ret = -1;
4828
4829         pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
4830         bist |= PCI_BIST_START;
4831         pci_write_config_word(sp->pdev, PCI_BIST, bist);
4832
4833         while (cnt < 20) {
4834                 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
4835                 if (!(bist & PCI_BIST_START)) {
4836                         *data = (bist & PCI_BIST_CODE_MASK);
4837                         ret = 0;
4838                         break;
4839                 }
4840                 msleep(100);
4841                 cnt++;
4842         }
4843
4844         return ret;
4845 }
4846
4847 /**
4848  * s2io-link_test - verifies the link state of the nic
4849  * @sp ; private member of the device structure, which is a pointer to the
4850  * s2io_nic structure.
4851  * @data: variable that returns the result of each of the test conducted by
4852  * the driver.
4853  * Description:
4854  * The function verifies the link state of the NIC and updates the input
4855  * argument 'data' appropriately.
4856  * Return value:
4857  * 0 on success.
4858  */
4859
4860 static int s2io_link_test(nic_t * sp, uint64_t * data)
4861 {
4862         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4863         u64 val64;
4864
4865         val64 = readq(&bar0->adapter_status);
4866         if (val64 & ADAPTER_STATUS_RMAC_LOCAL_FAULT)
4867                 *data = 1;
4868
4869         return 0;
4870 }
4871
4872 /**
4873  * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
4874  * @sp - private member of the device structure, which is a pointer to the
4875  * s2io_nic structure.
4876  * @data - variable that returns the result of each of the test
4877  * conducted by the driver.
4878  * Description:
4879  *  This is one of the offline test that tests the read and write
4880  *  access to the RldRam chip on the NIC.
4881  * Return value:
4882  *  0 on success.
4883  */
4884
4885 static int s2io_rldram_test(nic_t * sp, uint64_t * data)
4886 {
4887         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4888         u64 val64;
4889         int cnt, iteration = 0, test_fail = 0;
4890
4891         val64 = readq(&bar0->adapter_control);
4892         val64 &= ~ADAPTER_ECC_EN;
4893         writeq(val64, &bar0->adapter_control);
4894
4895         val64 = readq(&bar0->mc_rldram_test_ctrl);
4896         val64 |= MC_RLDRAM_TEST_MODE;
4897         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
4898
4899         val64 = readq(&bar0->mc_rldram_mrs);
4900         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
4901         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
4902
4903         val64 |= MC_RLDRAM_MRS_ENABLE;
4904         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
4905
4906         while (iteration < 2) {
4907                 val64 = 0x55555555aaaa0000ULL;
4908                 if (iteration == 1) {
4909                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
4910                 }
4911                 writeq(val64, &bar0->mc_rldram_test_d0);
4912
4913                 val64 = 0xaaaa5a5555550000ULL;
4914                 if (iteration == 1) {
4915                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
4916                 }
4917                 writeq(val64, &bar0->mc_rldram_test_d1);
4918
4919                 val64 = 0x55aaaaaaaa5a0000ULL;
4920                 if (iteration == 1) {
4921                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
4922                 }
4923                 writeq(val64, &bar0->mc_rldram_test_d2);
4924
4925                 val64 = (u64) (0x0000003ffffe0100ULL);
4926                 writeq(val64, &bar0->mc_rldram_test_add);
4927
4928                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
4929                         MC_RLDRAM_TEST_GO;
4930                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
4931
4932                 for (cnt = 0; cnt < 5; cnt++) {
4933                         val64 = readq(&bar0->mc_rldram_test_ctrl);
4934                         if (val64 & MC_RLDRAM_TEST_DONE)
4935                                 break;
4936                         msleep(200);
4937                 }
4938
4939                 if (cnt == 5)
4940                         break;
4941
4942                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
4943                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
4944
4945                 for (cnt = 0; cnt < 5; cnt++) {
4946                         val64 = readq(&bar0->mc_rldram_test_ctrl);
4947                         if (val64 & MC_RLDRAM_TEST_DONE)
4948                                 break;
4949                         msleep(500);
4950                 }
4951
4952                 if (cnt == 5)
4953                         break;
4954
4955                 val64 = readq(&bar0->mc_rldram_test_ctrl);
4956                 if (!(val64 & MC_RLDRAM_TEST_PASS))
4957                         test_fail = 1;
4958
4959                 iteration++;
4960         }
4961
4962         *data = test_fail;
4963
4964         /* Bring the adapter out of test mode */
4965         SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
4966
4967         return test_fail;
4968 }
4969
4970 /**
4971  *  s2io_ethtool_test - conducts 6 tsets to determine the health of card.
4972  *  @sp : private member of the device structure, which is a pointer to the
4973  *  s2io_nic structure.
4974  *  @ethtest : pointer to a ethtool command specific structure that will be
4975  *  returned to the user.
4976  *  @data : variable that returns the result of each of the test
4977  * conducted by the driver.
4978  * Description:
4979  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
4980  *  the health of the card.
4981  * Return value:
4982  *  void
4983  */
4984
4985 static void s2io_ethtool_test(struct net_device *dev,
4986                               struct ethtool_test *ethtest,
4987                               uint64_t * data)
4988 {
4989         nic_t *sp = dev->priv;
4990         int orig_state = netif_running(sp->dev);
4991
4992         if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
4993                 /* Offline Tests. */
4994                 if (orig_state)
4995                         s2io_close(sp->dev);
4996
4997                 if (s2io_register_test(sp, &data[0]))
4998                         ethtest->flags |= ETH_TEST_FL_FAILED;
4999
5000                 s2io_reset(sp);
5001
5002                 if (s2io_rldram_test(sp, &data[3]))
5003                         ethtest->flags |= ETH_TEST_FL_FAILED;
5004
5005                 s2io_reset(sp);
5006
5007                 if (s2io_eeprom_test(sp, &data[1]))
5008                         ethtest->flags |= ETH_TEST_FL_FAILED;
5009
5010                 if (s2io_bist_test(sp, &data[4]))
5011                         ethtest->flags |= ETH_TEST_FL_FAILED;
5012
5013                 if (orig_state)
5014                         s2io_open(sp->dev);
5015
5016                 data[2] = 0;
5017         } else {
5018                 /* Online Tests. */
5019                 if (!orig_state) {
5020                         DBG_PRINT(ERR_DBG,
5021                                   "%s: is not up, cannot run test\n",
5022                                   dev->name);
5023                         data[0] = -1;
5024                         data[1] = -1;
5025                         data[2] = -1;
5026                         data[3] = -1;
5027                         data[4] = -1;
5028                 }
5029
5030                 if (s2io_link_test(sp, &data[2]))
5031                         ethtest->flags |= ETH_TEST_FL_FAILED;
5032
5033                 data[0] = 0;
5034                 data[1] = 0;
5035                 data[3] = 0;
5036                 data[4] = 0;
5037         }
5038 }
5039
5040 static void s2io_get_ethtool_stats(struct net_device *dev,
5041                                    struct ethtool_stats *estats,
5042                                    u64 * tmp_stats)
5043 {
5044         int i = 0;
5045         nic_t *sp = dev->priv;
5046         StatInfo_t *stat_info = sp->mac_control.stats_info;
5047
5048         s2io_updt_stats(sp);
5049         tmp_stats[i++] =
5050                 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32  |
5051                 le32_to_cpu(stat_info->tmac_frms);
5052         tmp_stats[i++] =
5053                 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5054                 le32_to_cpu(stat_info->tmac_data_octets);
5055         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
5056         tmp_stats[i++] =
5057                 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5058                 le32_to_cpu(stat_info->tmac_mcst_frms);
5059         tmp_stats[i++] =
5060                 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5061                 le32_to_cpu(stat_info->tmac_bcst_frms);
5062         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
5063         tmp_stats[i++] =
5064                 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5065                 le32_to_cpu(stat_info->tmac_any_err_frms);
5066         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
5067         tmp_stats[i++] =
5068                 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5069                 le32_to_cpu(stat_info->tmac_vld_ip);
5070         tmp_stats[i++] =
5071                 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5072                 le32_to_cpu(stat_info->tmac_drop_ip);
5073         tmp_stats[i++] =
5074                 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5075                 le32_to_cpu(stat_info->tmac_icmp);
5076         tmp_stats[i++] =
5077                 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5078                 le32_to_cpu(stat_info->tmac_rst_tcp);
5079         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
5080         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5081                 le32_to_cpu(stat_info->tmac_udp);
5082         tmp_stats[i++] =
5083                 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5084                 le32_to_cpu(stat_info->rmac_vld_frms);
5085         tmp_stats[i++] =
5086                 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5087                 le32_to_cpu(stat_info->rmac_data_octets);
5088         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5089         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
5090         tmp_stats[i++] =
5091                 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5092                 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5093         tmp_stats[i++] =
5094                 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5095                 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
5096         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
5097         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5098         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
5099         tmp_stats[i++] =
5100                 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5101                 le32_to_cpu(stat_info->rmac_discarded_frms);
5102         tmp_stats[i++] =
5103                 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5104                 le32_to_cpu(stat_info->rmac_usized_frms);
5105         tmp_stats[i++] =
5106                 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5107                 le32_to_cpu(stat_info->rmac_osized_frms);
5108         tmp_stats[i++] =
5109                 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5110                 le32_to_cpu(stat_info->rmac_frag_frms);
5111         tmp_stats[i++] =
5112                 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5113                 le32_to_cpu(stat_info->rmac_jabber_frms);
5114         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
5115                 le32_to_cpu(stat_info->rmac_ip);
5116         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5117         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
5118         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
5119                 le32_to_cpu(stat_info->rmac_drop_ip);
5120         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
5121                 le32_to_cpu(stat_info->rmac_icmp);
5122         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
5123         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
5124                 le32_to_cpu(stat_info->rmac_udp);
5125         tmp_stats[i++] =
5126                 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5127                 le32_to_cpu(stat_info->rmac_err_drp_udp);
5128         tmp_stats[i++] =
5129                 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5130                 le32_to_cpu(stat_info->rmac_pause_cnt);
5131         tmp_stats[i++] =
5132                 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5133                 le32_to_cpu(stat_info->rmac_accepted_ip);
5134         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
5135         tmp_stats[i++] = 0;
5136         tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5137         tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
5138 }
5139
5140 static int s2io_ethtool_get_regs_len(struct net_device *dev)
5141 {
5142         return (XENA_REG_SPACE);
5143 }
5144
5145
5146 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
5147 {
5148         nic_t *sp = dev->priv;
5149
5150         return (sp->rx_csum);
5151 }
5152
5153 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
5154 {
5155         nic_t *sp = dev->priv;
5156
5157         if (data)
5158                 sp->rx_csum = 1;
5159         else
5160                 sp->rx_csum = 0;
5161
5162         return 0;
5163 }
5164
5165 static int s2io_get_eeprom_len(struct net_device *dev)
5166 {
5167         return (XENA_EEPROM_SPACE);
5168 }
5169
5170 static int s2io_ethtool_self_test_count(struct net_device *dev)
5171 {
5172         return (S2IO_TEST_LEN);
5173 }
5174
5175 static void s2io_ethtool_get_strings(struct net_device *dev,
5176                                      u32 stringset, u8 * data)
5177 {
5178         switch (stringset) {
5179         case ETH_SS_TEST:
5180                 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5181                 break;
5182         case ETH_SS_STATS:
5183                 memcpy(data, &ethtool_stats_keys,
5184                        sizeof(ethtool_stats_keys));
5185         }
5186 }
5187 static int s2io_ethtool_get_stats_count(struct net_device *dev)
5188 {
5189         return (S2IO_STAT_LEN);
5190 }
5191
5192 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
5193 {
5194         if (data)
5195                 dev->features |= NETIF_F_IP_CSUM;
5196         else
5197                 dev->features &= ~NETIF_F_IP_CSUM;
5198
5199         return 0;
5200 }
5201
5202
5203 static struct ethtool_ops netdev_ethtool_ops = {
5204         .get_settings = s2io_ethtool_gset,
5205         .set_settings = s2io_ethtool_sset,
5206         .get_drvinfo = s2io_ethtool_gdrvinfo,
5207         .get_regs_len = s2io_ethtool_get_regs_len,
5208         .get_regs = s2io_ethtool_gregs,
5209         .get_link = ethtool_op_get_link,
5210         .get_eeprom_len = s2io_get_eeprom_len,
5211         .get_eeprom = s2io_ethtool_geeprom,
5212         .set_eeprom = s2io_ethtool_seeprom,
5213         .get_pauseparam = s2io_ethtool_getpause_data,
5214         .set_pauseparam = s2io_ethtool_setpause_data,
5215         .get_rx_csum = s2io_ethtool_get_rx_csum,
5216         .set_rx_csum = s2io_ethtool_set_rx_csum,
5217         .get_tx_csum = ethtool_op_get_tx_csum,
5218         .set_tx_csum = s2io_ethtool_op_set_tx_csum,
5219         .get_sg = ethtool_op_get_sg,
5220         .set_sg = ethtool_op_set_sg,
5221 #ifdef NETIF_F_TSO
5222         .get_tso = ethtool_op_get_tso,
5223         .set_tso = ethtool_op_set_tso,
5224 #endif
5225         .get_ufo = ethtool_op_get_ufo,
5226         .set_ufo = ethtool_op_set_ufo,
5227         .self_test_count = s2io_ethtool_self_test_count,
5228         .self_test = s2io_ethtool_test,
5229         .get_strings = s2io_ethtool_get_strings,
5230         .phys_id = s2io_ethtool_idnic,
5231         .get_stats_count = s2io_ethtool_get_stats_count,
5232         .get_ethtool_stats = s2io_get_ethtool_stats
5233 };
5234
5235 /**
5236  *  s2io_ioctl - Entry point for the Ioctl
5237  *  @dev :  Device pointer.
5238  *  @ifr :  An IOCTL specefic structure, that can contain a pointer to
5239  *  a proprietary structure used to pass information to the driver.
5240  *  @cmd :  This is used to distinguish between the different commands that
5241  *  can be passed to the IOCTL functions.
5242  *  Description:
5243  *  Currently there are no special functionality supported in IOCTL, hence
5244  *  function always return EOPNOTSUPPORTED
5245  */
5246
5247 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5248 {
5249         return -EOPNOTSUPP;
5250 }
5251
5252 /**
5253  *  s2io_change_mtu - entry point to change MTU size for the device.
5254  *   @dev : device pointer.
5255  *   @new_mtu : the new MTU size for the device.
5256  *   Description: A driver entry point to change MTU size for the device.
5257  *   Before changing the MTU the device must be stopped.
5258  *  Return value:
5259  *   0 on success and an appropriate (-)ve integer as defined in errno.h
5260  *   file on failure.
5261  */
5262
5263 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
5264 {
5265         nic_t *sp = dev->priv;
5266
5267         if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
5268                 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
5269                           dev->name);
5270                 return -EPERM;
5271         }
5272
5273         dev->mtu = new_mtu;
5274         if (netif_running(dev)) {
5275                 s2io_card_down(sp);
5276                 netif_stop_queue(dev);
5277                 if (s2io_card_up(sp)) {
5278                         DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5279                                   __FUNCTION__);
5280                 }
5281                 if (netif_queue_stopped(dev))
5282                         netif_wake_queue(dev);
5283         } else { /* Device is down */
5284                 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5285                 u64 val64 = new_mtu;
5286
5287                 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
5288         }
5289
5290         return 0;
5291 }
5292
5293 /**
5294  *  s2io_tasklet - Bottom half of the ISR.
5295  *  @dev_adr : address of the device structure in dma_addr_t format.
5296  *  Description:
5297  *  This is the tasklet or the bottom half of the ISR. This is
5298  *  an extension of the ISR which is scheduled by the scheduler to be run
5299  *  when the load on the CPU is low. All low priority tasks of the ISR can
5300  *  be pushed into the tasklet. For now the tasklet is used only to
5301  *  replenish the Rx buffers in the Rx buffer descriptors.
5302  *  Return value:
5303  *  void.
5304  */
5305
5306 static void s2io_tasklet(unsigned long dev_addr)
5307 {
5308         struct net_device *dev = (struct net_device *) dev_addr;
5309         nic_t *sp = dev->priv;
5310         int i, ret;
5311         mac_info_t *mac_control;
5312         struct config_param *config;
5313
5314         mac_control = &sp->mac_control;
5315         config = &sp->config;
5316
5317         if (!TASKLET_IN_USE) {
5318                 for (i = 0; i < config->rx_ring_num; i++) {
5319                         ret = fill_rx_buffers(sp, i);
5320                         if (ret == -ENOMEM) {
5321                                 DBG_PRINT(ERR_DBG, "%s: Out of ",
5322                                           dev->name);
5323                                 DBG_PRINT(ERR_DBG, "memory in tasklet\n");
5324                                 break;
5325                         } else if (ret == -EFILL) {
5326                                 DBG_PRINT(ERR_DBG,
5327                                           "%s: Rx Ring %d is full\n",
5328                                           dev->name, i);
5329                                 break;
5330                         }
5331                 }
5332                 clear_bit(0, (&sp->tasklet_status));
5333         }
5334 }
5335
5336 /**
5337  * s2io_set_link - Set the LInk status
5338  * @data: long pointer to device private structue
5339  * Description: Sets the link status for the adapter
5340  */
5341
5342 static void s2io_set_link(unsigned long data)
5343 {
5344         nic_t *nic = (nic_t *) data;
5345         struct net_device *dev = nic->dev;
5346         XENA_dev_config_t __iomem *bar0 = nic->bar0;
5347         register u64 val64;
5348         u16 subid;
5349
5350         if (test_and_set_bit(0, &(nic->link_state))) {
5351                 /* The card is being reset, no point doing anything */
5352                 return;
5353         }
5354
5355         subid = nic->pdev->subsystem_device;
5356         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
5357                 /*
5358                  * Allow a small delay for the NICs self initiated
5359                  * cleanup to complete.
5360                  */
5361                 msleep(100);
5362         }
5363
5364         val64 = readq(&bar0->adapter_status);
5365         if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
5366                 if (LINK_IS_UP(val64)) {
5367                         val64 = readq(&bar0->adapter_control);
5368                         val64 |= ADAPTER_CNTL_EN;
5369                         writeq(val64, &bar0->adapter_control);
5370                         if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5371                                                              subid)) {
5372                                 val64 = readq(&bar0->gpio_control);
5373                                 val64 |= GPIO_CTRL_GPIO_0;
5374                                 writeq(val64, &bar0->gpio_control);
5375                                 val64 = readq(&bar0->gpio_control);
5376                         } else {
5377                                 val64 |= ADAPTER_LED_ON;
5378                                 writeq(val64, &bar0->adapter_control);
5379                         }
5380                         if (s2io_link_fault_indication(nic) ==
5381                                                 MAC_RMAC_ERR_TIMER) {
5382                                 val64 = readq(&bar0->adapter_status);
5383                                 if (!LINK_IS_UP(val64)) {
5384                                         DBG_PRINT(ERR_DBG, "%s:", dev->name);
5385                                         DBG_PRINT(ERR_DBG, " Link down");
5386                                         DBG_PRINT(ERR_DBG, "after ");
5387                                         DBG_PRINT(ERR_DBG, "enabling ");
5388                                         DBG_PRINT(ERR_DBG, "device \n");
5389                                 }
5390                         }
5391                         if (nic->device_enabled_once == FALSE) {
5392                                 nic->device_enabled_once = TRUE;
5393                         }
5394                         s2io_link(nic, LINK_UP);
5395                 } else {
5396                         if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5397                                                               subid)) {
5398                                 val64 = readq(&bar0->gpio_control);
5399                                 val64 &= ~GPIO_CTRL_GPIO_0;
5400                                 writeq(val64, &bar0->gpio_control);
5401                                 val64 = readq(&bar0->gpio_control);
5402                         }
5403                         s2io_link(nic, LINK_DOWN);
5404                 }
5405         } else {                /* NIC is not Quiescent. */
5406                 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
5407                 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
5408                 netif_stop_queue(dev);
5409         }
5410         clear_bit(0, &(nic->link_state));
5411 }
5412
5413 static void s2io_card_down(nic_t * sp)
5414 {
5415         int cnt = 0;
5416         XENA_dev_config_t __iomem *bar0 = sp->bar0;
5417         unsigned long flags;
5418         register u64 val64 = 0;
5419
5420         del_timer_sync(&sp->alarm_timer);
5421         /* If s2io_set_link task is executing, wait till it completes. */
5422         while (test_and_set_bit(0, &(sp->link_state))) {
5423                 msleep(50);
5424         }
5425         atomic_set(&sp->card_state, CARD_DOWN);
5426
5427         /* disable Tx and Rx traffic on the NIC */
5428         stop_nic(sp);
5429
5430         /* Kill tasklet. */
5431         tasklet_kill(&sp->task);
5432
5433         /* Check if the device is Quiescent and then Reset the NIC */
5434         do {
5435                 val64 = readq(&bar0->adapter_status);
5436                 if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) {
5437                         break;
5438                 }
5439
5440                 msleep(50);
5441                 cnt++;
5442                 if (cnt == 10) {
5443                         DBG_PRINT(ERR_DBG,
5444                                   "s2io_close:Device not Quiescent ");
5445                         DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
5446                                   (unsigned long long) val64);
5447                         break;
5448                 }
5449         } while (1);
5450         s2io_reset(sp);
5451
5452         /* Waiting till all Interrupt handlers are complete */
5453         cnt = 0;
5454         do {
5455                 msleep(10);
5456                 if (!atomic_read(&sp->isr_cnt))
5457                         break;
5458                 cnt++;
5459         } while(cnt < 5);
5460
5461         spin_lock_irqsave(&sp->tx_lock, flags);
5462         /* Free all Tx buffers */
5463         free_tx_buffers(sp);
5464         spin_unlock_irqrestore(&sp->tx_lock, flags);
5465
5466         /* Free all Rx buffers */
5467         spin_lock_irqsave(&sp->rx_lock, flags);
5468         free_rx_buffers(sp);
5469         spin_unlock_irqrestore(&sp->rx_lock, flags);
5470
5471         clear_bit(0, &(sp->link_state));
5472 }
5473
5474 static int s2io_card_up(nic_t * sp)
5475 {
5476         int i, ret = 0;
5477         mac_info_t *mac_control;
5478         struct config_param *config;
5479         struct net_device *dev = (struct net_device *) sp->dev;
5480
5481         /* Initialize the H/W I/O registers */
5482         if (init_nic(sp) != 0) {
5483                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
5484                           dev->name);
5485                 return -ENODEV;
5486         }
5487
5488         if (sp->intr_type == MSI)
5489                 ret = s2io_enable_msi(sp);
5490         else if (sp->intr_type == MSI_X)
5491                 ret = s2io_enable_msi_x(sp);
5492         if (ret) {
5493                 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
5494                 sp->intr_type = INTA;
5495         }
5496
5497         /*
5498          * Initializing the Rx buffers. For now we are considering only 1
5499          * Rx ring and initializing buffers into 30 Rx blocks
5500          */
5501         mac_control = &sp->mac_control;
5502         config = &sp->config;
5503
5504         for (i = 0; i < config->rx_ring_num; i++) {
5505                 if ((ret = fill_rx_buffers(sp, i))) {
5506                         DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
5507                                   dev->name);
5508                         s2io_reset(sp);
5509                         free_rx_buffers(sp);
5510                         return -ENOMEM;
5511                 }
5512                 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
5513                           atomic_read(&sp->rx_bufs_left[i]));
5514         }
5515
5516         /* Setting its receive mode */
5517         s2io_set_multicast(dev);
5518
5519         /* Enable tasklet for the device */
5520         tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
5521
5522         /* Enable Rx Traffic and interrupts on the NIC */
5523         if (start_nic(sp)) {
5524                 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
5525                 tasklet_kill(&sp->task);
5526                 s2io_reset(sp);
5527                 free_irq(dev->irq, dev);
5528                 free_rx_buffers(sp);
5529                 return -ENODEV;
5530         }
5531
5532         S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
5533
5534         atomic_set(&sp->card_state, CARD_UP);
5535         return 0;
5536 }
5537
5538 /**
5539  * s2io_restart_nic - Resets the NIC.
5540  * @data : long pointer to the device private structure
5541  * Description:
5542  * This function is scheduled to be run by the s2io_tx_watchdog
5543  * function after 0.5 secs to reset the NIC. The idea is to reduce
5544  * the run time of the watch dog routine which is run holding a
5545  * spin lock.
5546  */
5547
5548 static void s2io_restart_nic(unsigned long data)
5549 {
5550         struct net_device *dev = (struct net_device *) data;
5551         nic_t *sp = dev->priv;
5552
5553         s2io_card_down(sp);
5554         if (s2io_card_up(sp)) {
5555                 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5556                           dev->name);
5557         }
5558         netif_wake_queue(dev);
5559         DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
5560                   dev->name);
5561
5562 }
5563
5564 /**
5565  *  s2io_tx_watchdog - Watchdog for transmit side.
5566  *  @dev : Pointer to net device structure
5567  *  Description:
5568  *  This function is triggered if the Tx Queue is stopped
5569  *  for a pre-defined amount of time when the Interface is still up.
5570  *  If the Interface is jammed in such a situation, the hardware is
5571  *  reset (by s2io_close) and restarted again (by s2io_open) to
5572  *  overcome any problem that might have been caused in the hardware.
5573  *  Return value:
5574  *  void
5575  */
5576
5577 static void s2io_tx_watchdog(struct net_device *dev)
5578 {
5579         nic_t *sp = dev->priv;
5580
5581         if (netif_carrier_ok(dev)) {
5582                 schedule_work(&sp->rst_timer_task);
5583         }
5584 }
5585
5586 /**
5587  *   rx_osm_handler - To perform some OS related operations on SKB.
5588  *   @sp: private member of the device structure,pointer to s2io_nic structure.
5589  *   @skb : the socket buffer pointer.
5590  *   @len : length of the packet
5591  *   @cksum : FCS checksum of the frame.
5592  *   @ring_no : the ring from which this RxD was extracted.
5593  *   Description:
5594  *   This function is called by the Tx interrupt serivce routine to perform
5595  *   some OS related operations on the SKB before passing it to the upper
5596  *   layers. It mainly checks if the checksum is OK, if so adds it to the
5597  *   SKBs cksum variable, increments the Rx packet count and passes the SKB
5598  *   to the upper layer. If the checksum is wrong, it increments the Rx
5599  *   packet error count, frees the SKB and returns error.
5600  *   Return value:
5601  *   SUCCESS on success and -1 on failure.
5602  */
5603 static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
5604 {
5605         nic_t *sp = ring_data->nic;
5606         struct net_device *dev = (struct net_device *) sp->dev;
5607         struct sk_buff *skb = (struct sk_buff *)
5608                 ((unsigned long) rxdp->Host_Control);
5609         int ring_no = ring_data->ring_no;
5610         u16 l3_csum, l4_csum;
5611
5612         skb->dev = dev;
5613         if (rxdp->Control_1 & RXD_T_CODE) {
5614                 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
5615                 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
5616                           dev->name, err);
5617                 dev_kfree_skb(skb);
5618                 sp->stats.rx_crc_errors++;
5619                 atomic_dec(&sp->rx_bufs_left[ring_no]);
5620                 rxdp->Host_Control = 0;
5621                 return 0;
5622         }
5623
5624         /* Updating statistics */
5625         rxdp->Host_Control = 0;
5626         sp->rx_pkt_count++;
5627         sp->stats.rx_packets++;
5628         if (sp->rxd_mode == RXD_MODE_1) {
5629                 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
5630
5631                 sp->stats.rx_bytes += len;
5632                 skb_put(skb, len);
5633
5634         } else if (sp->rxd_mode >= RXD_MODE_3A) {
5635                 int get_block = ring_data->rx_curr_get_info.block_index;
5636                 int get_off = ring_data->rx_curr_get_info.offset;
5637                 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
5638                 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
5639                 unsigned char *buff = skb_push(skb, buf0_len);
5640
5641                 buffAdd_t *ba = &ring_data->ba[get_block][get_off];
5642                 sp->stats.rx_bytes += buf0_len + buf2_len;
5643                 memcpy(buff, ba->ba_0, buf0_len);
5644
5645                 if (sp->rxd_mode == RXD_MODE_3A) {
5646                         int buf1_len = RXD_GET_BUFFER1_SIZE_3(rxdp->Control_2);
5647
5648                         skb_put(skb, buf1_len);
5649                         skb->len += buf2_len;
5650                         skb->data_len += buf2_len;
5651                         skb->truesize += buf2_len;
5652                         skb_put(skb_shinfo(skb)->frag_list, buf2_len);
5653                         sp->stats.rx_bytes += buf1_len;
5654
5655                 } else
5656                         skb_put(skb, buf2_len);
5657         }
5658
5659         if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
5660             (sp->rx_csum)) {
5661                 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
5662                 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
5663                 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
5664                         /*
5665                          * NIC verifies if the Checksum of the received
5666                          * frame is Ok or not and accordingly returns
5667                          * a flag in the RxD.
5668                          */
5669                         skb->ip_summed = CHECKSUM_UNNECESSARY;
5670                 } else {
5671                         /*
5672                          * Packet with erroneous checksum, let the
5673                          * upper layers deal with it.
5674                          */
5675                         skb->ip_summed = CHECKSUM_NONE;
5676                 }
5677         } else {
5678                 skb->ip_summed = CHECKSUM_NONE;
5679         }
5680
5681         skb->protocol = eth_type_trans(skb, dev);
5682 #ifdef CONFIG_S2IO_NAPI
5683         if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
5684                 /* Queueing the vlan frame to the upper layer */
5685                 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
5686                         RXD_GET_VLAN_TAG(rxdp->Control_2));
5687         } else {
5688                 netif_receive_skb(skb);
5689         }
5690 #else
5691         if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
5692                 /* Queueing the vlan frame to the upper layer */
5693                 vlan_hwaccel_rx(skb, sp->vlgrp,
5694                         RXD_GET_VLAN_TAG(rxdp->Control_2));
5695         } else {
5696                 netif_rx(skb);
5697         }
5698 #endif
5699         dev->last_rx = jiffies;
5700         atomic_dec(&sp->rx_bufs_left[ring_no]);
5701         return SUCCESS;
5702 }
5703
5704 /**
5705  *  s2io_link - stops/starts the Tx queue.
5706  *  @sp : private member of the device structure, which is a pointer to the
5707  *  s2io_nic structure.
5708  *  @link : inidicates whether link is UP/DOWN.
5709  *  Description:
5710  *  This function stops/starts the Tx queue depending on whether the link
5711  *  status of the NIC is is down or up. This is called by the Alarm
5712  *  interrupt handler whenever a link change interrupt comes up.
5713  *  Return value:
5714  *  void.
5715  */
5716
5717 void s2io_link(nic_t * sp, int link)
5718 {
5719         struct net_device *dev = (struct net_device *) sp->dev;
5720
5721         if (link != sp->last_link_state) {
5722                 if (link == LINK_DOWN) {
5723                         DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
5724                         netif_carrier_off(dev);
5725                 } else {
5726                         DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
5727                         netif_carrier_on(dev);
5728                 }
5729         }
5730         sp->last_link_state = link;
5731 }
5732
5733 /**
5734  *  get_xena_rev_id - to identify revision ID of xena.
5735  *  @pdev : PCI Dev structure
5736  *  Description:
5737  *  Function to identify the Revision ID of xena.
5738  *  Return value:
5739  *  returns the revision ID of the device.
5740  */
5741
5742 int get_xena_rev_id(struct pci_dev *pdev)
5743 {
5744         u8 id = 0;
5745         int ret;
5746         ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
5747         return id;
5748 }
5749
5750 /**
5751  *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
5752  *  @sp : private member of the device structure, which is a pointer to the
5753  *  s2io_nic structure.
5754  *  Description:
5755  *  This function initializes a few of the PCI and PCI-X configuration registers
5756  *  with recommended values.
5757  *  Return value:
5758  *  void
5759  */
5760
5761 static void s2io_init_pci(nic_t * sp)
5762 {
5763         u16 pci_cmd = 0, pcix_cmd = 0;
5764
5765         /* Enable Data Parity Error Recovery in PCI-X command register. */
5766         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5767                              &(pcix_cmd));
5768         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5769                               (pcix_cmd | 1));
5770         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5771                              &(pcix_cmd));
5772
5773         /* Set the PErr Response bit in PCI command register. */
5774         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
5775         pci_write_config_word(sp->pdev, PCI_COMMAND,
5776                               (pci_cmd | PCI_COMMAND_PARITY));
5777         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
5778
5779         /* Forcibly disabling relaxed ordering capability of the card. */
5780         pcix_cmd &= 0xfffd;
5781         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5782                               pcix_cmd);
5783         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
5784                              &(pcix_cmd));
5785 }
5786
5787 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
5788 MODULE_LICENSE("GPL");
5789 MODULE_VERSION(DRV_VERSION);
5790
5791 module_param(tx_fifo_num, int, 0);
5792 module_param(rx_ring_num, int, 0);
5793 module_param(rx_ring_mode, int, 0);
5794 module_param_array(tx_fifo_len, uint, NULL, 0);
5795 module_param_array(rx_ring_sz, uint, NULL, 0);
5796 module_param_array(rts_frm_len, uint, NULL, 0);
5797 module_param(use_continuous_tx_intrs, int, 1);
5798 module_param(rmac_pause_time, int, 0);
5799 module_param(mc_pause_threshold_q0q3, int, 0);
5800 module_param(mc_pause_threshold_q4q7, int, 0);
5801 module_param(shared_splits, int, 0);
5802 module_param(tmac_util_period, int, 0);
5803 module_param(rmac_util_period, int, 0);
5804 module_param(bimodal, bool, 0);
5805 module_param(l3l4hdr_size, int , 0);
5806 #ifndef CONFIG_S2IO_NAPI
5807 module_param(indicate_max_pkts, int, 0);
5808 #endif
5809 module_param(rxsync_frequency, int, 0);
5810 module_param(intr_type, int, 0);
5811
5812 /**
5813  *  s2io_init_nic - Initialization of the adapter .
5814  *  @pdev : structure containing the PCI related information of the device.
5815  *  @pre: List of PCI devices supported by the driver listed in s2io_tbl.
5816  *  Description:
5817  *  The function initializes an adapter identified by the pci_dec structure.
5818  *  All OS related initialization including memory and device structure and
5819  *  initlaization of the device private variable is done. Also the swapper
5820  *  control register is initialized to enable read and write into the I/O
5821  *  registers of the device.
5822  *  Return value:
5823  *  returns 0 on success and negative on failure.
5824  */
5825
5826 static int __devinit
5827 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
5828 {
5829         nic_t *sp;
5830         struct net_device *dev;
5831         int i, j, ret;
5832         int dma_flag = FALSE;
5833         u32 mac_up, mac_down;
5834         u64 val64 = 0, tmp64 = 0;
5835         XENA_dev_config_t __iomem *bar0 = NULL;
5836         u16 subid;
5837         mac_info_t *mac_control;
5838         struct config_param *config;
5839         int mode;
5840         u8 dev_intr_type = intr_type;
5841
5842 #ifdef CONFIG_S2IO_NAPI
5843         if (dev_intr_type != INTA) {
5844                 DBG_PRINT(ERR_DBG, "NAPI cannot be enabled when MSI/MSI-X \
5845 is enabled. Defaulting to INTA\n");
5846                 dev_intr_type = INTA;
5847         }
5848         else
5849                 DBG_PRINT(ERR_DBG, "NAPI support has been enabled\n");
5850 #endif
5851
5852         if ((ret = pci_enable_device(pdev))) {
5853                 DBG_PRINT(ERR_DBG,
5854                           "s2io_init_nic: pci_enable_device failed\n");
5855                 return ret;
5856         }
5857
5858         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
5859                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
5860                 dma_flag = TRUE;
5861                 if (pci_set_consistent_dma_mask
5862                     (pdev, DMA_64BIT_MASK)) {
5863                         DBG_PRINT(ERR_DBG,
5864                                   "Unable to obtain 64bit DMA for \
5865                                         consistent allocations\n");
5866                         pci_disable_device(pdev);
5867                         return -ENOMEM;
5868                 }
5869         } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
5870                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
5871         } else {
5872                 pci_disable_device(pdev);
5873                 return -ENOMEM;
5874         }
5875
5876         if ((dev_intr_type == MSI_X) &&
5877                         ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
5878                         (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
5879                 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. \
5880 Defaulting to INTA\n");
5881                 dev_intr_type = INTA;
5882         }
5883         if (dev_intr_type != MSI_X) {
5884                 if (pci_request_regions(pdev, s2io_driver_name)) {
5885                         DBG_PRINT(ERR_DBG, "Request Regions failed\n"),
5886                             pci_disable_device(pdev);
5887                         return -ENODEV;
5888                 }
5889         }
5890         else {
5891                 if (!(request_mem_region(pci_resource_start(pdev, 0),
5892                          pci_resource_len(pdev, 0), s2io_driver_name))) {
5893                         DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
5894                         pci_disable_device(pdev);
5895                         return -ENODEV;
5896                 }
5897                 if (!(request_mem_region(pci_resource_start(pdev, 2),
5898                          pci_resource_len(pdev, 2), s2io_driver_name))) {
5899                         DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
5900                         release_mem_region(pci_resource_start(pdev, 0),
5901                                    pci_resource_len(pdev, 0));
5902                         pci_disable_device(pdev);
5903                         return -ENODEV;
5904                 }
5905         }
5906
5907         dev = alloc_etherdev(sizeof(nic_t));
5908         if (dev == NULL) {
5909                 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
5910                 pci_disable_device(pdev);
5911                 pci_release_regions(pdev);
5912                 return -ENODEV;
5913         }
5914
5915         pci_set_master(pdev);
5916         pci_set_drvdata(pdev, dev);
5917         SET_MODULE_OWNER(dev);
5918         SET_NETDEV_DEV(dev, &pdev->dev);
5919
5920         /*  Private member variable initialized to s2io NIC structure */
5921         sp = dev->priv;
5922         memset(sp, 0, sizeof(nic_t));
5923         sp->dev = dev;
5924         sp->pdev = pdev;
5925         sp->high_dma_flag = dma_flag;
5926         sp->device_enabled_once = FALSE;
5927         if (rx_ring_mode == 1)
5928                 sp->rxd_mode = RXD_MODE_1;
5929         if (rx_ring_mode == 2)
5930                 sp->rxd_mode = RXD_MODE_3B;
5931         if (rx_ring_mode == 3)
5932                 sp->rxd_mode = RXD_MODE_3A;
5933
5934         sp->intr_type = dev_intr_type;
5935
5936         if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
5937                 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
5938                 sp->device_type = XFRAME_II_DEVICE;
5939         else
5940                 sp->device_type = XFRAME_I_DEVICE;
5941
5942
5943         /* Initialize some PCI/PCI-X fields of the NIC. */
5944         s2io_init_pci(sp);
5945
5946         /*
5947          * Setting the device configuration parameters.
5948          * Most of these parameters can be specified by the user during
5949          * module insertion as they are module loadable parameters. If
5950          * these parameters are not not specified during load time, they
5951          * are initialized with default values.
5952          */
5953         mac_control = &sp->mac_control;
5954         config = &sp->config;
5955
5956         /* Tx side parameters. */
5957         if (tx_fifo_len[0] == 0)
5958                 tx_fifo_len[0] = DEFAULT_FIFO_LEN; /* Default value. */
5959         config->tx_fifo_num = tx_fifo_num;
5960         for (i = 0; i < MAX_TX_FIFOS; i++) {
5961                 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
5962                 config->tx_cfg[i].fifo_priority = i;
5963         }
5964
5965         /* mapping the QoS priority to the configured fifos */
5966         for (i = 0; i < MAX_TX_FIFOS; i++)
5967                 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
5968
5969         config->tx_intr_type = TXD_INT_TYPE_UTILZ;
5970         for (i = 0; i < config->tx_fifo_num; i++) {
5971                 config->tx_cfg[i].f_no_snoop =
5972                     (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
5973                 if (config->tx_cfg[i].fifo_len < 65) {
5974                         config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
5975                         break;
5976                 }
5977         }
5978         /* + 2 because one Txd for skb->data and one Txd for UFO */
5979         config->max_txds = MAX_SKB_FRAGS + 2;
5980
5981         /* Rx side parameters. */
5982         if (rx_ring_sz[0] == 0)
5983                 rx_ring_sz[0] = SMALL_BLK_CNT; /* Default value. */
5984         config->rx_ring_num = rx_ring_num;
5985         for (i = 0; i < MAX_RX_RINGS; i++) {
5986                 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
5987                     (rxd_count[sp->rxd_mode] + 1);
5988                 config->rx_cfg[i].ring_priority = i;
5989         }
5990
5991         for (i = 0; i < rx_ring_num; i++) {
5992                 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
5993                 config->rx_cfg[i].f_no_snoop =
5994                     (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
5995         }
5996
5997         /*  Setting Mac Control parameters */
5998         mac_control->rmac_pause_time = rmac_pause_time;
5999         mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
6000         mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
6001
6002
6003         /* Initialize Ring buffer parameters. */
6004         for (i = 0; i < config->rx_ring_num; i++)
6005                 atomic_set(&sp->rx_bufs_left[i], 0);
6006
6007         /* Initialize the number of ISRs currently running */
6008         atomic_set(&sp->isr_cnt, 0);
6009
6010         /*  initialize the shared memory used by the NIC and the host */
6011         if (init_shared_mem(sp)) {
6012                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
6013                           __FUNCTION__);
6014                 ret = -ENOMEM;
6015                 goto mem_alloc_failed;
6016         }
6017
6018         sp->bar0 = ioremap(pci_resource_start(pdev, 0),
6019                                      pci_resource_len(pdev, 0));
6020         if (!sp->bar0) {
6021                 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n",
6022                           dev->name);
6023                 ret = -ENOMEM;
6024                 goto bar0_remap_failed;
6025         }
6026
6027         sp->bar1 = ioremap(pci_resource_start(pdev, 2),
6028                                      pci_resource_len(pdev, 2));
6029         if (!sp->bar1) {
6030                 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n",
6031                           dev->name);
6032                 ret = -ENOMEM;
6033                 goto bar1_remap_failed;
6034         }
6035
6036         dev->irq = pdev->irq;
6037         dev->base_addr = (unsigned long) sp->bar0;
6038
6039         /* Initializing the BAR1 address as the start of the FIFO pointer. */
6040         for (j = 0; j < MAX_TX_FIFOS; j++) {
6041                 mac_control->tx_FIFO_start[j] = (TxFIFO_element_t __iomem *)
6042                     (sp->bar1 + (j * 0x00020000));
6043         }
6044
6045         /*  Driver entry points */
6046         dev->open = &s2io_open;
6047         dev->stop = &s2io_close;
6048         dev->hard_start_xmit = &s2io_xmit;
6049         dev->get_stats = &s2io_get_stats;
6050         dev->set_multicast_list = &s2io_set_multicast;
6051         dev->do_ioctl = &s2io_ioctl;
6052         dev->change_mtu = &s2io_change_mtu;
6053         SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
6054         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6055         dev->vlan_rx_register = s2io_vlan_rx_register;
6056         dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
6057
6058         /*
6059          * will use eth_mac_addr() for  dev->set_mac_address
6060          * mac address will be set every time dev->open() is called
6061          */
6062 #if defined(CONFIG_S2IO_NAPI)
6063         dev->poll = s2io_poll;
6064         dev->weight = 32;
6065 #endif
6066
6067         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
6068         if (sp->high_dma_flag == TRUE)
6069                 dev->features |= NETIF_F_HIGHDMA;
6070 #ifdef NETIF_F_TSO
6071         dev->features |= NETIF_F_TSO;
6072 #endif
6073         if (sp->device_type & XFRAME_II_DEVICE) {
6074                 dev->features |= NETIF_F_UFO;
6075                 dev->features |= NETIF_F_HW_CSUM;
6076         }
6077
6078         dev->tx_timeout = &s2io_tx_watchdog;
6079         dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
6080         INIT_WORK(&sp->rst_timer_task,
6081                   (void (*)(void *)) s2io_restart_nic, dev);
6082         INIT_WORK(&sp->set_link_task,
6083                   (void (*)(void *)) s2io_set_link, sp);
6084
6085         pci_save_state(sp->pdev);
6086
6087         /* Setting swapper control on the NIC, for proper reset operation */
6088         if (s2io_set_swapper(sp)) {
6089                 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
6090                           dev->name);
6091                 ret = -EAGAIN;
6092                 goto set_swap_failed;
6093         }
6094
6095         /* Verify if the Herc works on the slot its placed into */
6096         if (sp->device_type & XFRAME_II_DEVICE) {
6097                 mode = s2io_verify_pci_mode(sp);
6098                 if (mode < 0) {
6099                         DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
6100                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
6101                         ret = -EBADSLT;
6102                         goto set_swap_failed;
6103                 }
6104         }
6105
6106         /* Not needed for Herc */
6107         if (sp->device_type & XFRAME_I_DEVICE) {
6108                 /*
6109                  * Fix for all "FFs" MAC address problems observed on
6110                  * Alpha platforms
6111                  */
6112                 fix_mac_address(sp);
6113                 s2io_reset(sp);
6114         }
6115
6116         /*
6117          * MAC address initialization.
6118          * For now only one mac address will be read and used.
6119          */
6120         bar0 = sp->bar0;
6121         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
6122             RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
6123         writeq(val64, &bar0->rmac_addr_cmd_mem);
6124         wait_for_cmd_complete(sp);
6125
6126         tmp64 = readq(&bar0->rmac_addr_data0_mem);
6127         mac_down = (u32) tmp64;
6128         mac_up = (u32) (tmp64 >> 32);
6129
6130         memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
6131
6132         sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
6133         sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
6134         sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
6135         sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
6136         sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
6137         sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
6138
6139         /*  Set the factory defined MAC address initially   */
6140         dev->addr_len = ETH_ALEN;
6141         memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
6142
6143         /*
6144          * Initialize the tasklet status and link state flags
6145          * and the card state parameter
6146          */
6147         atomic_set(&(sp->card_state), 0);
6148         sp->tasklet_status = 0;
6149         sp->link_state = 0;
6150
6151         /* Initialize spinlocks */
6152         spin_lock_init(&sp->tx_lock);
6153 #ifndef CONFIG_S2IO_NAPI
6154         spin_lock_init(&sp->put_lock);
6155 #endif
6156         spin_lock_init(&sp->rx_lock);
6157
6158         /*
6159          * SXE-002: Configure link and activity LED to init state
6160          * on driver load.
6161          */
6162         subid = sp->pdev->subsystem_device;
6163         if ((subid & 0xFF) >= 0x07) {
6164                 val64 = readq(&bar0->gpio_control);
6165                 val64 |= 0x0000800000000000ULL;
6166                 writeq(val64, &bar0->gpio_control);
6167                 val64 = 0x0411040400000000ULL;
6168                 writeq(val64, (void __iomem *) bar0 + 0x2700);
6169                 val64 = readq(&bar0->gpio_control);
6170         }
6171
6172         sp->rx_csum = 1;        /* Rx chksum verify enabled by default */
6173
6174         if (register_netdev(dev)) {
6175                 DBG_PRINT(ERR_DBG, "Device registration failed\n");
6176                 ret = -ENODEV;
6177                 goto register_failed;
6178         }
6179
6180         if (sp->device_type & XFRAME_II_DEVICE) {
6181                 DBG_PRINT(ERR_DBG, "%s: Neterion Xframe II 10GbE adapter ",
6182                           dev->name);
6183                 DBG_PRINT(ERR_DBG, "(rev %d), Version %s",
6184                                 get_xena_rev_id(sp->pdev),
6185                                 s2io_driver_version);
6186                 switch(sp->intr_type) {
6187                         case INTA:
6188                                 DBG_PRINT(ERR_DBG, ", Intr type INTA");
6189                                 break;
6190                         case MSI:
6191                                 DBG_PRINT(ERR_DBG, ", Intr type MSI");
6192                                 break;
6193                         case MSI_X:
6194                                 DBG_PRINT(ERR_DBG, ", Intr type MSI-X");
6195                                 break;
6196                 }
6197
6198                 DBG_PRINT(ERR_DBG, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
6199                 DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
6200                           sp->def_mac_addr[0].mac_addr[0],
6201                           sp->def_mac_addr[0].mac_addr[1],
6202                           sp->def_mac_addr[0].mac_addr[2],
6203                           sp->def_mac_addr[0].mac_addr[3],
6204                           sp->def_mac_addr[0].mac_addr[4],
6205                           sp->def_mac_addr[0].mac_addr[5]);
6206                 mode = s2io_print_pci_mode(sp);
6207                 if (mode < 0) {
6208                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode ");
6209                         ret = -EBADSLT;
6210                         goto set_swap_failed;
6211                 }
6212         } else {
6213                 DBG_PRINT(ERR_DBG, "%s: Neterion Xframe I 10GbE adapter ",
6214                           dev->name);
6215                 DBG_PRINT(ERR_DBG, "(rev %d), Version %s",
6216                                         get_xena_rev_id(sp->pdev),
6217                                         s2io_driver_version);
6218                 switch(sp->intr_type) {
6219                         case INTA:
6220                                 DBG_PRINT(ERR_DBG, ", Intr type INTA");
6221                                 break;
6222                         case MSI:
6223                                 DBG_PRINT(ERR_DBG, ", Intr type MSI");
6224                                 break;
6225                         case MSI_X:
6226                                 DBG_PRINT(ERR_DBG, ", Intr type MSI-X");
6227                                 break;
6228                 }
6229                 DBG_PRINT(ERR_DBG, "\nCopyright(c) 2002-2005 Neterion Inc.\n");
6230                 DBG_PRINT(ERR_DBG, "MAC ADDR: %02x:%02x:%02x:%02x:%02x:%02x\n",
6231                           sp->def_mac_addr[0].mac_addr[0],
6232                           sp->def_mac_addr[0].mac_addr[1],
6233                           sp->def_mac_addr[0].mac_addr[2],
6234                           sp->def_mac_addr[0].mac_addr[3],
6235                           sp->def_mac_addr[0].mac_addr[4],
6236                           sp->def_mac_addr[0].mac_addr[5]);
6237         }
6238         if (sp->rxd_mode == RXD_MODE_3B)
6239                 DBG_PRINT(ERR_DBG, "%s: 2-Buffer mode support has been "
6240                           "enabled\n",dev->name);
6241         if (sp->rxd_mode == RXD_MODE_3A)
6242                 DBG_PRINT(ERR_DBG, "%s: 3-Buffer mode support has been "
6243                           "enabled\n",dev->name);
6244
6245         /* Initialize device name */
6246         strcpy(sp->name, dev->name);
6247         if (sp->device_type & XFRAME_II_DEVICE)
6248                 strcat(sp->name, ": Neterion Xframe II 10GbE adapter");
6249         else
6250                 strcat(sp->name, ": Neterion Xframe I 10GbE adapter");
6251
6252         /* Initialize bimodal Interrupts */
6253         sp->config.bimodal = bimodal;
6254         if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
6255                 sp->config.bimodal = 0;
6256                 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
6257                         dev->name);
6258         }
6259
6260         /*
6261          * Make Link state as off at this point, when the Link change
6262          * interrupt comes the state will be automatically changed to
6263          * the right state.
6264          */
6265         netif_carrier_off(dev);
6266
6267         return 0;
6268
6269       register_failed:
6270       set_swap_failed:
6271         iounmap(sp->bar1);
6272       bar1_remap_failed:
6273         iounmap(sp->bar0);
6274       bar0_remap_failed:
6275       mem_alloc_failed:
6276         free_shared_mem(sp);
6277         pci_disable_device(pdev);
6278         if (dev_intr_type != MSI_X)
6279                 pci_release_regions(pdev);
6280         else {
6281                 release_mem_region(pci_resource_start(pdev, 0),
6282                         pci_resource_len(pdev, 0));
6283                 release_mem_region(pci_resource_start(pdev, 2),
6284                         pci_resource_len(pdev, 2));
6285         }
6286         pci_set_drvdata(pdev, NULL);
6287         free_netdev(dev);
6288
6289         return ret;
6290 }
6291
6292 /**
6293  * s2io_rem_nic - Free the PCI device
6294  * @pdev: structure containing the PCI related information of the device.
6295  * Description: This function is called by the Pci subsystem to release a
6296  * PCI device and free up all resource held up by the device. This could
6297  * be in response to a Hot plug event or when the driver is to be removed
6298  * from memory.
6299  */
6300
6301 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
6302 {
6303         struct net_device *dev =
6304             (struct net_device *) pci_get_drvdata(pdev);
6305         nic_t *sp;
6306
6307         if (dev == NULL) {
6308                 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
6309                 return;
6310         }
6311
6312         sp = dev->priv;
6313         unregister_netdev(dev);
6314
6315         free_shared_mem(sp);
6316         iounmap(sp->bar0);
6317         iounmap(sp->bar1);
6318         pci_disable_device(pdev);
6319         if (sp->intr_type != MSI_X)
6320                 pci_release_regions(pdev);
6321         else {
6322                 release_mem_region(pci_resource_start(pdev, 0),
6323                         pci_resource_len(pdev, 0));
6324                 release_mem_region(pci_resource_start(pdev, 2),
6325                         pci_resource_len(pdev, 2));
6326         }
6327         pci_set_drvdata(pdev, NULL);
6328         free_netdev(dev);
6329 }
6330
6331 /**
6332  * s2io_starter - Entry point for the driver
6333  * Description: This function is the entry point for the driver. It verifies
6334  * the module loadable parameters and initializes PCI configuration space.
6335  */
6336
6337 int __init s2io_starter(void)
6338 {
6339         return pci_module_init(&s2io_driver);
6340 }
6341
6342 /**
6343  * s2io_closer - Cleanup routine for the driver
6344  * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
6345  */
6346
6347 void s2io_closer(void)
6348 {
6349         pci_unregister_driver(&s2io_driver);
6350         DBG_PRINT(INIT_DBG, "cleanup done\n");
6351 }
6352
6353 module_init(s2io_starter);
6354 module_exit(s2io_closer);