1 /************************************************************************
2 * s2io.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
3 * Copyright 2002 Raghavendra Koushik (raghavendra.koushik@s2io.com)
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
17 #define BIT(loc) (0x8000000000000000ULL >> (loc))
18 #define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
33 /* Maximum outstanding splits to be configured into xena. */
34 typedef enum xena_max_outstanding_splits {
35 XENA_ONE_SPLIT_TRANSACTION = 0,
36 XENA_TWO_SPLIT_TRANSACTION = 1,
37 XENA_THREE_SPLIT_TRANSACTION = 2,
38 XENA_FOUR_SPLIT_TRANSACTION = 3,
39 XENA_EIGHT_SPLIT_TRANSACTION = 4,
40 XENA_TWELVE_SPLIT_TRANSACTION = 5,
41 XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
42 XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
43 } xena_max_outstanding_splits;
44 #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
46 /* OS concerned variables and constants */
47 #define WATCH_DOG_TIMEOUT 5*HZ
49 #define ALIGN_SIZE 127
50 #define PCIX_COMMAND_REGISTER 0x62
53 * Debug related variables.
57 /* different debug levels. */
64 /* Global variable that defines the present debug level of the driver. */
65 int debug_level = ERR_DBG; /* Default level. */
67 /* DEBUG message print. */
68 #define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
70 /* Protocol assist features of the NIC */
71 #define L3_CKSUM_OK 0xFFFF
72 #define L4_CKSUM_OK 0xFFFF
73 #define S2IO_JUMBO_SIZE 9600
75 /* The statistics block of Xena */
76 typedef struct stat_block {
78 /* Tx MAC statistics counters. */
84 u64 tmac_pause_ctrl_frms;
88 u32 tmac_any_err_frms;
89 u64 tmac_ttl_less_fb_octets;
90 u64 tmac_vld_ip_octets;
99 /* Rx MAC Statistics counters. */
101 u32 rmac_data_octets;
102 u64 rmac_fcs_err_frms;
104 u32 rmac_vld_mcst_frms;
105 u32 rmac_vld_bcst_frms;
106 u32 rmac_in_rng_len_err_frms;
107 u32 rmac_out_rng_len_err_frms;
109 u64 rmac_pause_ctrl_frms;
110 u64 rmac_unsup_ctrl_frms;
112 u32 rmac_accepted_ucst_frms;
113 u32 rmac_accepted_nucst_frms;
114 u32 rmac_discarded_frms;
115 u32 rmac_drop_events;
117 u64 rmac_ttl_less_fb_octets;
121 u32 rmac_usized_frms;
122 u32 rmac_osized_frms;
124 u32 rmac_jabber_frms;
126 u64 rmac_ttl_64_frms;
127 u64 rmac_ttl_65_127_frms;
129 u64 rmac_ttl_128_255_frms;
130 u64 rmac_ttl_256_511_frms;
132 u64 rmac_ttl_512_1023_frms;
133 u64 rmac_ttl_1024_1518_frms;
143 u32 rmac_err_drp_udp;
144 u64 rmac_xgmii_err_sym;
163 u64 rmac_xgmii_data_err_cnt;
164 u64 rmac_xgmii_ctrl_err_cnt;
165 u32 rmac_accepted_ip;
168 /* PCI/PCI-X Read transaction statistics. */
171 u32 new_rd_req_rtry_cnt;
173 u32 wr_rtry_rd_ack_cnt;
175 /* PCI/PCI-X write transaction statistics. */
178 u32 new_wr_req_rtry_cnt;
181 u32 rd_rtry_wr_ack_cnt;
183 /* DMA Transaction statistics. */
192 /* Tx MAC statistics counters. */
193 u32 tmac_data_octets;
198 u64 tmac_pause_ctrl_frms;
201 u32 tmac_any_err_frms;
203 u64 tmac_ttl_less_fb_octets;
204 u64 tmac_vld_ip_octets;
213 /* Rx MAC Statistics counters. */
214 u32 rmac_data_octets;
216 u64 rmac_fcs_err_frms;
218 u32 rmac_vld_bcst_frms;
219 u32 rmac_vld_mcst_frms;
220 u32 rmac_out_rng_len_err_frms;
221 u32 rmac_in_rng_len_err_frms;
223 u64 rmac_pause_ctrl_frms;
224 u64 rmac_unsup_ctrl_frms;
225 u32 rmac_accepted_ucst_frms;
227 u32 rmac_discarded_frms;
228 u32 rmac_accepted_nucst_frms;
230 u32 rmac_drop_events;
231 u64 rmac_ttl_less_fb_octets;
234 u32 rmac_usized_frms;
237 u32 rmac_osized_frms;
239 u32 rmac_jabber_frms;
240 u64 rmac_ttl_64_frms;
241 u64 rmac_ttl_65_127_frms;
243 u64 rmac_ttl_128_255_frms;
244 u64 rmac_ttl_256_511_frms;
246 u64 rmac_ttl_512_1023_frms;
247 u64 rmac_ttl_1024_1518_frms;
256 u32 rmac_err_drp_udp;
258 u64 rmac_xgmii_err_sym;
277 u64 rmac_xgmii_data_err_cnt;
278 u64 rmac_xgmii_ctrl_err_cnt;
280 u32 rmac_accepted_ip;
282 /* PCI/PCI-X Read transaction statistics. */
286 u32 new_rd_req_rtry_cnt;
288 /* PCI/PCI-X Write/Read transaction statistics. */
290 u32 wr_rtry_rd_ack_cnt;
291 u32 new_wr_req_rtry_cnt;
296 /* PCI/PCI-X Write / DMA Transaction statistics. */
298 u32 rd_rtry_wr_ack_cnt;
308 /* Structures representing different init time configuration
309 * parameters of the NIC.
312 /* Maintains Per FIFO related information. */
313 typedef struct tx_fifo_config {
314 #define MAX_AVAILABLE_TXDS 8192
315 u32 FifoLen; /* specifies len of FIFO upto 8192, ie no of TxDLs */
316 /* Priority definition */
317 #define TX_FIFO_PRI_0 0 /*Highest */
318 #define TX_FIFO_PRI_1 1
319 #define TX_FIFO_PRI_2 2
320 #define TX_FIFO_PRI_3 3
321 #define TX_FIFO_PRI_4 4
322 #define TX_FIFO_PRI_5 5
323 #define TX_FIFO_PRI_6 6
324 #define TX_FIFO_PRI_7 7 /*lowest */
325 u8 FifoPriority; /* specifies pointer level for FIFO */
326 /* user should not set twos fifos with same pri */
328 #define NO_SNOOP_TXD 0x01
329 #define NO_SNOOP_TXD_BUFFER 0x02
333 /* Maintains per Ring related information */
334 typedef struct rx_ring_config {
335 u32 NumRxd; /*No of RxDs per Rx Ring */
336 #define RX_RING_PRI_0 0 /* highest */
337 #define RX_RING_PRI_1 1
338 #define RX_RING_PRI_2 2
339 #define RX_RING_PRI_3 3
340 #define RX_RING_PRI_4 4
341 #define RX_RING_PRI_5 5
342 #define RX_RING_PRI_6 6
343 #define RX_RING_PRI_7 7 /* lowest */
345 u8 RingPriority; /*Specifies service priority of ring */
346 /* OSM should not set any two rings with same priority */
347 u8 RingOrg; /*Organization of ring */
348 #define RING_ORG_BUFF1 0x01
349 #define RX_RING_ORG_BUFF3 0x03
350 #define RX_RING_ORG_BUFF5 0x05
352 /* In case of 3 buffer recv. mode, size of three buffers is expected as.. */
353 #define BUFF_SZ_1 22 /* ethernet header */
354 #define BUFF_SZ_2 (64+64) /* max. IP+TCP header size */
355 #define BUFF_SZ_3 (1500-20-20) /* TCP payload */
356 #define BUFF_SZ_3_JUMBO (9600-20-20) /* Jumbo TCP payload */
358 u32 RxdThresh; /*No of used Rxds NIC can store before transfer to host */
359 #define DEFAULT_RXD_THRESHOLD 0x1 /* TODO */
361 #define NO_SNOOP_RXD 0x01
362 #define NO_SNOOP_RXD_BUFFER 0x02
363 u32 RxD_BackOff_Interval;
364 #define RXD_BACKOFF_INTERVAL_DEF 0x0
365 #define RXD_BACKOFF_INTERVAL_MIN 0x0
366 #define RXD_BACKOFF_INTERVAL_MAX 0x0
369 /* This structure provides contains values of the tunable parameters
372 struct config_param {
375 u32 TxFIFONum; /*Number of Tx FIFOs */
376 #define MAX_TX_FIFOS 8
378 tx_fifo_config_t TxCfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
379 u32 MaxTxDs; /*Max no. of Tx buffer descriptor per TxDL */
380 BOOL TxVLANEnable; /*TRUE: Insert VLAN ID, FALSE: Don't insert */
381 #define TX_REQ_TIMEOUT_DEFAULT 0x0
382 #define TX_REQ_TIMEOUT_MIN 0x0
383 #define TX_REQ_TIMEOUT_MAX 0x0
385 BOOL TxFlow; /*Tx flow control enable */
387 BOOL OverrideTxServiceState; /* TRUE: Overide, FALSE: Do not override
388 Use the new priority information
389 of service state. It is not recommended
390 to change but OSM can opt to do so */
391 #define MAX_SERVICE_STATES 36
392 u8 TxServiceState[MAX_SERVICE_STATES];
393 /* Array element represent 'priority'
394 * and array index represents
395 * 'Service state' e.g.
396 * TxServiceState[3]=7; it means
397 * Service state 3 is associated
398 * with priority 7 of a Tx FIFO */
399 u64 TxIntrType; /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
402 u32 RxRingNum; /*Number of receive rings */
403 #define MAX_RX_RINGS 8
404 #define MAX_RX_BLOCKS_PER_RING 150
406 rx_ring_config_t RxCfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
407 BOOL RxVLANEnable; /*TRUE: Strip off VLAN tag from the frame,
408 FALSE: Don't strip off VLAN tag */
410 #define HEADER_ETHERNET_II_802_3_SIZE 14
411 #define HEADER_802_2_SIZE 3
412 #define HEADER_SNAP_SIZE 5
413 #define HEADER_VLAN_SIZE 4
414 #define HEADER_ALIGN_LAYER_3 2
417 #define MAX_PYLD 1500
418 #define MAX_MTU (MAX_PYLD+18)
419 #define MAX_MTU_VLAN (MAX_PYLD+22)
420 #define MAX_PYLD_JUMBO 9600
421 #define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
422 #define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
423 u32 MTU; /*Maximum Payload */
424 BOOL JumboEnable; /*Enable Jumbo frames recv/send */
425 BOOL OverrideRxServiceState; /* TRUE: Overide, FALSE: Do not override
426 Use the new priority information
427 of service state. It is not recommended
428 to change but OSM can opt to do so */
429 #define MAX_SERVICE_STATES 36
430 u8 RxServiceState[MAX_SERVICE_STATES];
431 /* Array element represent 'priority'
432 * and array index represents
433 * 'Service state'e.g.
434 * RxServiceState[3]=7; it means
435 * Service state 3 is associated
436 * with priority 7 of a Rx FIFO */
437 BOOL StatAutoRefresh; /* When true, StatRefreshTime have valid value */
438 u32 StatRefreshTime; /*Time for refreshing statistics */
439 #define STAT_TRSF_PER_1_SECOND 0x208D5
442 /* Structure representing MAC Addrs */
443 typedef struct mac_addr {
444 u8 mac_addr[ETH_ALEN];
447 /* Structure that represent every FIFO element in the BAR1
450 typedef struct _TxFIFO_element {
454 #define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
455 #define TX_FIFO_FIRST_LIST BIT(14)
456 #define TX_FIFO_LAST_LIST BIT(15)
457 #define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
458 #define TX_FIFO_SPECIAL_FUNC BIT(23)
459 #define TX_FIFO_DS_NO_SNOOP BIT(31)
460 #define TX_FIFO_BUFF_NO_SNOOP BIT(30)
463 /* Tx descriptor structure */
464 typedef struct _TxD {
467 #define TXD_LIST_OWN_XENA BIT(7)
468 #define TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
469 #define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
470 #define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
471 #define TXD_GATHER_CODE (BIT(22) | BIT(23))
472 #define TXD_GATHER_CODE_FIRST BIT(22)
473 #define TXD_GATHER_CODE_LAST BIT(23)
474 #define TXD_TCP_LSO_EN BIT(30)
475 #define TXD_UDP_COF_EN BIT(31)
476 #define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
477 #define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
480 #define TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7))
481 #define TXD_TX_CKO_IPV4_EN BIT(5)
482 #define TXD_TX_CKO_TCP_EN BIT(6)
483 #define TXD_TX_CKO_UDP_EN BIT(7)
484 #define TXD_VLAN_ENABLE BIT(15)
485 #define TXD_VLAN_TAG(val) vBIT(val,16,16)
486 #define TXD_INT_NUMBER(val) vBIT(val,34,6)
487 #define TXD_INT_TYPE_PER_LIST BIT(47)
488 #define TXD_INT_TYPE_UTILZ BIT(46)
489 #define TXD_SET_MARKER vBIT(0x6,0,4)
492 u64 Host_Control; /* reserved for host */
495 /* Rx descriptor structure */
496 typedef struct _RxD_t {
497 u64 Host_Control; /* reserved for host */
499 #define RXD_OWN_XENA BIT(7)
500 #define RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
501 #define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
502 #define RXD_FRAME_PROTO_IPV4 BIT(27)
503 #define RXD_FRAME_PROTO_IPV6 BIT(28)
504 #define RXD_FRAME_PROTO_TCP BIT(30)
505 #define RXD_FRAME_PROTO_UDP BIT(31)
506 #define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
507 #define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
508 #define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
511 #define MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16)
512 #define SET_BUFFER0_SIZE(val) vBIT(val,0,16)
513 #define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
514 #define SET_VLAN_TAG(val) vBIT(val,48,16)
515 #define SET_NUM_TAG(val) vBIT(val,16,32)
517 #define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0xFFFF,0,16)))
519 #define TXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) >> (63-31))
520 #define TXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) >> (63-47))
526 /* Structure that represents the Rx descriptor block which contains
527 * 128 Rx descriptors.
529 typedef struct _RxD_block {
530 #define MAX_RXDS_PER_BLOCK 127
531 RxD_t rxd[MAX_RXDS_PER_BLOCK];
534 #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
535 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd in this blk */
536 u64 reserved_2_pNext_RxD_block; /*@ Logical ptr to next */
537 u64 pNext_RxD_Blk_physical; /* Buff0_ptr.
538 In a 32 bit arch the upper 32 bits
542 /* Structure which stores all the MAC control parameters */
544 /* This structure stores the offset of the RxD in the ring
545 * from which the Rx Interrupt processor can start picking
546 * up the RxDs for processing.
548 typedef struct _rx_curr_get_info_t {
552 } rx_curr_get_info_t;
554 typedef rx_curr_get_info_t rx_curr_put_info_t;
556 /* This structure stores the offset of the TxDl in the FIFO
557 * from which the Tx Interrupt processor can start picking
558 * up the TxDLs for send complete interrupt processing.
563 } tx_curr_get_info_t;
565 typedef tx_curr_get_info_t tx_curr_put_info_t;
567 /* Infomation related to the Tx and Rx FIFOs and Rings of Xena
568 * is maintained in this structure.
570 typedef struct mac_info {
573 RxD_t *RxRing[MAX_RX_RINGS]; /* Logical Rx ring pointers */
574 dma_addr_t RxRing_Phy[MAX_RX_RINGS];
576 /* Put pointer info which indictes which RxD has to be replenished
579 rx_curr_put_info_t rx_curr_put_info[MAX_RX_RINGS];
581 /* Get pointer info which indictes which is the last RxD that was
582 * processed by the driver.
584 rx_curr_get_info_t rx_curr_get_info[MAX_RX_RINGS];
588 /* this will be used in receive function, this decides which ring would
589 be processed first. eg: ring with priority value 0 (highest) should
591 first 3 LSB bits represent ring number which should be processed
592 first, similarly next 3 bits represent next ring to be processed.
593 eg: value of _rx_ring_pri_map = 0x0000 003A means
594 ring #2 would be processed first and #7 would be processed next
596 u32 _rx_ring_pri_map;
599 void *txd_list_mem; /* orignal pointer to allocated mem */
600 dma_addr_t txd_list_mem_phy;
603 /* logical pointer of start of each Tx FIFO */
604 TxFIFO_element_t *tx_FIFO_start[MAX_TX_FIFOS];
606 /* logical pointer of start of TxDL which corresponds to each Tx FIFO */
607 TxD_t *txdl_start[MAX_TX_FIFOS];
609 /* Same as txdl_start but phy addr */
610 dma_addr_t txdl_start_phy[MAX_TX_FIFOS];
612 /* Current offset within tx_FIFO_start, where driver would write new Tx frame*/
613 tx_curr_put_info_t tx_curr_put_info[MAX_TX_FIFOS];
614 tx_curr_get_info_t tx_curr_get_info[MAX_TX_FIFOS];
616 u16 txdl_len; /* length of a TxDL, same for all */
618 void *stats_mem; /* orignal pointer to allocated mem */
619 dma_addr_t stats_mem_phy; /* Physical address of the stat block */
621 StatInfo_t *StatsInfo; /* Logical address of the stat block */
624 /* structure representing the user defined MAC addresses */
630 /* Structure that holds the Phy and virt addresses of the Blocks */
631 typedef struct rx_block_info {
632 RxD_t *block_virt_addr;
633 dma_addr_t block_dma_addr;
636 /* Structure representing one instance of the NIC */
637 typedef struct s2io_nic {
638 #define MAX_MAC_SUPPORTED 16
639 #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
641 macaddr_t defMacAddr[MAX_MAC_SUPPORTED];
642 macaddr_t preMacAddr[MAX_MAC_SUPPORTED];
644 struct net_device_stats stats;
647 struct config_param config;
648 mac_info_t mac_control;
650 int device_close_flag;
651 int device_enabled_once;
654 struct tasklet_struct task;
655 atomic_t tasklet_status;
656 struct timer_list timer;
657 struct net_device *dev;
658 struct pci_dev *pdev;
671 u32 config_space[256 / sizeof(u32)];
673 atomic_t rx_bufs_left[MAX_RX_RINGS];
681 #define MAX_ADDRS_SUPPORTED 64
684 usr_addr_t usr_addrs[MAX_ADDRS_SUPPORTED];
704 /* Place holders for the virtual and physical addresses of
708 rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING];
709 int block_count[MAX_RX_RINGS];
710 int pkt_cnt[MAX_RX_RINGS];
712 /* Id timer, used to blink NIC to physically identify NIC. */
713 struct timer_list id_timer;
715 /* Restart timer, used to restart NIC if the device is stuck and
716 * a schedule task that will set the correct Link state once the
717 * NIC's PHY has stabilized after a state change.
720 struct tq_struct rst_timer_task;
721 struct tq_struct set_link_task;
723 struct work_struct rst_timer_task;
724 struct work_struct set_link_task;
727 /* Flag that can be used to turn on or turn off the Rx checksum
732 /* after blink, the adapter must be restored with original
737 /* Last known link state. */
743 #define RESET_ERROR 1;
746 /* Default Tunable parameters of the NIC. */
747 #define DEFAULT_FIFO_LEN 4096
748 #define SMALL_RXD_CNT 40 * (MAX_RXDS_PER_BLOCK+1)
749 #define LARGE_RXD_CNT 100 * (MAX_RXDS_PER_BLOCK+1)
751 /* OS related system calls */
753 static inline u64 readq(void *addr)
756 ret = readl(addr + 4);
765 static inline void writeq(u64 val, void *addr)
767 writel((u32) (val), addr);
768 writel((u32) (val >> 32), (addr + 4));
772 /* Interrupt related values of Xena */
774 #define ENABLE_INTRS 1
775 #define DISABLE_INTRS 2
777 /* Highest level interrupt blocks */
778 #define TX_PIC_INTR (0x0001<<0)
779 #define TX_DMA_INTR (0x0001<<1)
780 #define TX_MAC_INTR (0x0001<<2)
781 #define TX_XGXS_INTR (0x0001<<3)
782 #define TX_TRAFFIC_INTR (0x0001<<4)
783 #define RX_PIC_INTR (0x0001<<5)
784 #define RX_DMA_INTR (0x0001<<6)
785 #define RX_MAC_INTR (0x0001<<7)
786 #define RX_XGXS_INTR (0x0001<<8)
787 #define RX_TRAFFIC_INTR (0x0001<<9)
788 #define MC_INTR (0x0001<<10)
789 #define ENA_ALL_INTRS ( TX_PIC_INTR | \
801 /* Interrupt masks for the general interrupt mask register */
802 #define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
804 #define TXPIC_INT_M BIT(0)
805 #define TXDMA_INT_M BIT(1)
806 #define TXMAC_INT_M BIT(2)
807 #define TXXGXS_INT_M BIT(3)
808 #define TXTRAFFIC_INT_M BIT(8)
809 #define PIC_RX_INT_M BIT(32)
810 #define RXDMA_INT_M BIT(33)
811 #define RXMAC_INT_M BIT(34)
812 #define MC_INT_M BIT(35)
813 #define RXXGXS_INT_M BIT(36)
814 #define RXTRAFFIC_INT_M BIT(40)
816 /* PIC level Interrupts TODO*/
818 /* DMA level Inressupts */
819 #define TXDMA_PFC_INT_M BIT(0)
820 /* PFC block interrupts */
821 #define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */
824 * Prototype declaration.
826 static int __devinit s2io_init_nic(struct pci_dev *pdev,
827 const struct pci_device_id *pre);
828 static void __devexit s2io_rem_nic(struct pci_dev *pdev);
829 static int initSharedMem(struct s2io_nic *sp);
830 static void freeSharedMem(struct s2io_nic *sp);
831 static int initNic(struct s2io_nic *nic);
832 #ifndef CONFIG_S2IO_NAPI
833 static void rxIntrHandler(struct s2io_nic *sp);
835 static void txIntrHandler(struct s2io_nic *sp);
836 static void alarmIntrHandler(struct s2io_nic *sp);
838 static int s2io_starter(void);
839 void s2io_closer(void);
840 static void s2io_tx_watchdog(struct net_device *dev);
841 static void s2io_tasklet(unsigned long dev_addr);
842 static void s2io_set_multicast(struct net_device *dev);
843 static int rxOsmHandler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no);
844 void s2io_link(nic_t * sp, int link);
845 void s2io_reset(nic_t * sp);
846 #ifdef CONFIG_S2IO_NAPI
847 static int s2io_poll(struct net_device *dev, int *budget);
849 static void s2io_init_pci(nic_t * sp);
850 int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
851 static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs);
852 static int verify_xena_quiescence(u64 val64, int flag);
853 static struct ethtool_ops netdev_ethtool_ops;