1 /************************************************************************
2 * s2io.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
3 * Copyright 2002 Raghavendra Koushik (raghavendra.koushik@s2io.com)
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
17 #define BIT(loc) (0x8000000000000000ULL >> (loc))
18 #define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
19 #define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
34 /* Maximum outstanding splits to be configured into xena. */
35 typedef enum xena_max_outstanding_splits {
36 XENA_ONE_SPLIT_TRANSACTION = 0,
37 XENA_TWO_SPLIT_TRANSACTION = 1,
38 XENA_THREE_SPLIT_TRANSACTION = 2,
39 XENA_FOUR_SPLIT_TRANSACTION = 3,
40 XENA_EIGHT_SPLIT_TRANSACTION = 4,
41 XENA_TWELVE_SPLIT_TRANSACTION = 5,
42 XENA_SIXTEEN_SPLIT_TRANSACTION = 6,
43 XENA_THIRTYTWO_SPLIT_TRANSACTION = 7
44 } xena_max_outstanding_splits;
45 #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
47 /* OS concerned variables and constants */
48 #define WATCH_DOG_TIMEOUT 5*HZ
50 #define ALIGN_SIZE 127
51 #define PCIX_COMMAND_REGISTER 0x62
54 * Debug related variables.
56 /* different debug levels. */
63 /* Global variable that defines the present debug level of the driver. */
64 static int debug_level = ERR_DBG; /* Default level. */
66 /* DEBUG message print. */
67 #define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
69 /* Protocol assist features of the NIC */
70 #define L3_CKSUM_OK 0xFFFF
71 #define L4_CKSUM_OK 0xFFFF
72 #define S2IO_JUMBO_SIZE 9600
74 /* The statistics block of Xena */
75 typedef struct stat_block {
77 /* Tx MAC statistics counters. */
83 u64 tmac_pause_ctrl_frms;
87 u32 tmac_any_err_frms;
88 u64 tmac_ttl_less_fb_octets;
89 u64 tmac_vld_ip_octets;
98 /* Rx MAC Statistics counters. */
100 u32 rmac_data_octets;
101 u64 rmac_fcs_err_frms;
103 u32 rmac_vld_mcst_frms;
104 u32 rmac_vld_bcst_frms;
105 u32 rmac_in_rng_len_err_frms;
106 u32 rmac_out_rng_len_err_frms;
108 u64 rmac_pause_ctrl_frms;
109 u64 rmac_unsup_ctrl_frms;
111 u32 rmac_accepted_ucst_frms;
112 u32 rmac_accepted_nucst_frms;
113 u32 rmac_discarded_frms;
114 u32 rmac_drop_events;
116 u64 rmac_ttl_less_fb_octets;
120 u32 rmac_usized_frms;
121 u32 rmac_osized_frms;
123 u32 rmac_jabber_frms;
125 u64 rmac_ttl_64_frms;
126 u64 rmac_ttl_65_127_frms;
128 u64 rmac_ttl_128_255_frms;
129 u64 rmac_ttl_256_511_frms;
131 u64 rmac_ttl_512_1023_frms;
132 u64 rmac_ttl_1024_1518_frms;
142 u32 rmac_err_drp_udp;
143 u64 rmac_xgmii_err_sym;
162 u64 rmac_xgmii_data_err_cnt;
163 u64 rmac_xgmii_ctrl_err_cnt;
164 u32 rmac_accepted_ip;
167 /* PCI/PCI-X Read transaction statistics. */
170 u32 new_rd_req_rtry_cnt;
172 u32 wr_rtry_rd_ack_cnt;
174 /* PCI/PCI-X write transaction statistics. */
177 u32 new_wr_req_rtry_cnt;
180 u32 rd_rtry_wr_ack_cnt;
182 /* DMA Transaction statistics. */
191 /* Tx MAC statistics counters. */
192 u32 tmac_data_octets;
197 u64 tmac_pause_ctrl_frms;
200 u32 tmac_any_err_frms;
202 u64 tmac_ttl_less_fb_octets;
203 u64 tmac_vld_ip_octets;
212 /* Rx MAC Statistics counters. */
213 u32 rmac_data_octets;
215 u64 rmac_fcs_err_frms;
217 u32 rmac_vld_bcst_frms;
218 u32 rmac_vld_mcst_frms;
219 u32 rmac_out_rng_len_err_frms;
220 u32 rmac_in_rng_len_err_frms;
222 u64 rmac_pause_ctrl_frms;
223 u64 rmac_unsup_ctrl_frms;
224 u32 rmac_accepted_ucst_frms;
226 u32 rmac_discarded_frms;
227 u32 rmac_accepted_nucst_frms;
229 u32 rmac_drop_events;
230 u64 rmac_ttl_less_fb_octets;
233 u32 rmac_usized_frms;
236 u32 rmac_osized_frms;
238 u32 rmac_jabber_frms;
239 u64 rmac_ttl_64_frms;
240 u64 rmac_ttl_65_127_frms;
242 u64 rmac_ttl_128_255_frms;
243 u64 rmac_ttl_256_511_frms;
245 u64 rmac_ttl_512_1023_frms;
246 u64 rmac_ttl_1024_1518_frms;
255 u32 rmac_err_drp_udp;
257 u64 rmac_xgmii_err_sym;
276 u64 rmac_xgmii_data_err_cnt;
277 u64 rmac_xgmii_ctrl_err_cnt;
279 u32 rmac_accepted_ip;
281 /* PCI/PCI-X Read transaction statistics. */
285 u32 new_rd_req_rtry_cnt;
287 /* PCI/PCI-X Write/Read transaction statistics. */
289 u32 wr_rtry_rd_ack_cnt;
290 u32 new_wr_req_rtry_cnt;
295 /* PCI/PCI-X Write / DMA Transaction statistics. */
297 u32 rd_rtry_wr_ack_cnt;
307 /* Structures representing different init time configuration
308 * parameters of the NIC.
311 /* Maintains Per FIFO related information. */
312 typedef struct tx_fifo_config {
313 #define MAX_AVAILABLE_TXDS 8192
314 u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
315 /* Priority definition */
316 #define TX_FIFO_PRI_0 0 /*Highest */
317 #define TX_FIFO_PRI_1 1
318 #define TX_FIFO_PRI_2 2
319 #define TX_FIFO_PRI_3 3
320 #define TX_FIFO_PRI_4 4
321 #define TX_FIFO_PRI_5 5
322 #define TX_FIFO_PRI_6 6
323 #define TX_FIFO_PRI_7 7 /*lowest */
324 u8 fifo_priority; /* specifies pointer level for FIFO */
325 /* user should not set twos fifos with same pri */
327 #define NO_SNOOP_TXD 0x01
328 #define NO_SNOOP_TXD_BUFFER 0x02
332 /* Maintains per Ring related information */
333 typedef struct rx_ring_config {
334 u32 num_rxd; /*No of RxDs per Rx Ring */
335 #define RX_RING_PRI_0 0 /* highest */
336 #define RX_RING_PRI_1 1
337 #define RX_RING_PRI_2 2
338 #define RX_RING_PRI_3 3
339 #define RX_RING_PRI_4 4
340 #define RX_RING_PRI_5 5
341 #define RX_RING_PRI_6 6
342 #define RX_RING_PRI_7 7 /* lowest */
344 u8 ring_priority; /*Specifies service priority of ring */
345 /* OSM should not set any two rings with same priority */
346 u8 ring_org; /*Organization of ring */
347 #define RING_ORG_BUFF1 0x01
348 #define RX_RING_ORG_BUFF3 0x03
349 #define RX_RING_ORG_BUFF5 0x05
352 #define NO_SNOOP_RXD 0x01
353 #define NO_SNOOP_RXD_BUFFER 0x02
356 /* This structure provides contains values of the tunable parameters
359 struct config_param {
361 u32 tx_fifo_num; /*Number of Tx FIFOs */
362 #define MAX_TX_FIFOS 8
364 tx_fifo_config_t tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
365 u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
367 /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
370 u32 rx_ring_num; /*Number of receive rings */
371 #define MAX_RX_RINGS 8
372 #define MAX_RX_BLOCKS_PER_RING 150
374 rx_ring_config_t rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
376 #define HEADER_ETHERNET_II_802_3_SIZE 14
377 #define HEADER_802_2_SIZE 3
378 #define HEADER_SNAP_SIZE 5
379 #define HEADER_VLAN_SIZE 4
382 #define MAX_PYLD 1500
383 #define MAX_MTU (MAX_PYLD+18)
384 #define MAX_MTU_VLAN (MAX_PYLD+22)
385 #define MAX_PYLD_JUMBO 9600
386 #define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
387 #define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
390 /* Structure representing MAC Addrs */
391 typedef struct mac_addr {
392 u8 mac_addr[ETH_ALEN];
395 /* Structure that represent every FIFO element in the BAR1
398 typedef struct _TxFIFO_element {
402 #define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
403 #define TX_FIFO_FIRST_LIST BIT(14)
404 #define TX_FIFO_LAST_LIST BIT(15)
405 #define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
406 #define TX_FIFO_SPECIAL_FUNC BIT(23)
407 #define TX_FIFO_DS_NO_SNOOP BIT(31)
408 #define TX_FIFO_BUFF_NO_SNOOP BIT(30)
411 /* Tx descriptor structure */
412 typedef struct _TxD {
415 #define TXD_LIST_OWN_XENA BIT(7)
416 #define TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
417 #define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
418 #define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
419 #define TXD_GATHER_CODE (BIT(22) | BIT(23))
420 #define TXD_GATHER_CODE_FIRST BIT(22)
421 #define TXD_GATHER_CODE_LAST BIT(23)
422 #define TXD_TCP_LSO_EN BIT(30)
423 #define TXD_UDP_COF_EN BIT(31)
424 #define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
425 #define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
428 #define TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7))
429 #define TXD_TX_CKO_IPV4_EN BIT(5)
430 #define TXD_TX_CKO_TCP_EN BIT(6)
431 #define TXD_TX_CKO_UDP_EN BIT(7)
432 #define TXD_VLAN_ENABLE BIT(15)
433 #define TXD_VLAN_TAG(val) vBIT(val,16,16)
434 #define TXD_INT_NUMBER(val) vBIT(val,34,6)
435 #define TXD_INT_TYPE_PER_LIST BIT(47)
436 #define TXD_INT_TYPE_UTILZ BIT(46)
437 #define TXD_SET_MARKER vBIT(0x6,0,4)
440 u64 Host_Control; /* reserved for host */
443 /* Structure to hold the phy and virt addr of every TxDL. */
444 typedef struct list_info_hold {
445 dma_addr_t list_phy_addr;
446 void *list_virt_addr;
449 /* Rx descriptor structure */
450 typedef struct _RxD_t {
451 u64 Host_Control; /* reserved for host */
453 #define RXD_OWN_XENA BIT(7)
454 #define RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
455 #define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
456 #define RXD_FRAME_PROTO_IPV4 BIT(27)
457 #define RXD_FRAME_PROTO_IPV6 BIT(28)
458 #define RXD_FRAME_PROTO_TCP BIT(30)
459 #define RXD_FRAME_PROTO_UDP BIT(31)
460 #define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
461 #define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
462 #define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
465 #ifndef CONFIG_2BUFF_MODE
466 #define MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16)
467 #define SET_BUFFER0_SIZE(val) vBIT(val,0,16)
469 #define MASK_BUFFER0_SIZE vBIT(0xFF,0,16)
470 #define MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16)
471 #define MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16)
472 #define SET_BUFFER0_SIZE(val) vBIT(val,8,8)
473 #define SET_BUFFER1_SIZE(val) vBIT(val,16,16)
474 #define SET_BUFFER2_SIZE(val) vBIT(val,32,16)
477 #define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
478 #define SET_VLAN_TAG(val) vBIT(val,48,16)
479 #define SET_NUM_TAG(val) vBIT(val,16,32)
481 #ifndef CONFIG_2BUFF_MODE
482 #define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0xFFFF,0,16)))
484 #define RXD_GET_BUFFER0_SIZE(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE) \
486 #define RXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) \
488 #define RXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) \
495 #ifdef CONFIG_2BUFF_MODE
501 /* Structure that represents the Rx descriptor block which contains
502 * 128 Rx descriptors.
504 #ifndef CONFIG_2BUFF_MODE
505 typedef struct _RxD_block {
506 #define MAX_RXDS_PER_BLOCK 127
507 RxD_t rxd[MAX_RXDS_PER_BLOCK];
510 #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
511 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
513 u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
514 u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
515 * the upper 32 bits should
519 typedef struct _RxD_block {
520 #define MAX_RXDS_PER_BLOCK 85
521 RxD_t rxd[MAX_RXDS_PER_BLOCK];
523 #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
524 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd
526 u64 pNext_RxD_Blk_physical; /* Phy ponter to next blk. */
528 #define SIZE_OF_BLOCK 4096
530 /* Structure to hold virtual addresses of Buf0 and Buf1 in
532 typedef struct bufAdd {
540 /* Structure which stores all the MAC control parameters */
542 /* This structure stores the offset of the RxD in the ring
543 * from which the Rx Interrupt processor can start picking
544 * up the RxDs for processing.
546 typedef struct _rx_curr_get_info_t {
550 } rx_curr_get_info_t;
552 typedef rx_curr_get_info_t rx_curr_put_info_t;
554 /* This structure stores the offset of the TxDl in the FIFO
555 * from which the Tx Interrupt processor can start picking
556 * up the TxDLs for send complete interrupt processing.
561 } tx_curr_get_info_t;
563 typedef tx_curr_get_info_t tx_curr_put_info_t;
565 /* Infomation related to the Tx and Rx FIFOs and Rings of Xena
566 * is maintained in this structure.
568 typedef struct mac_info {
570 /* Put pointer info which indictes which RxD has to be replenished
573 rx_curr_put_info_t rx_curr_put_info[MAX_RX_RINGS];
575 /* Get pointer info which indictes which is the last RxD that was
576 * processed by the driver.
578 rx_curr_get_info_t rx_curr_get_info[MAX_RX_RINGS];
581 u16 mc_pause_threshold_q0q3;
582 u16 mc_pause_threshold_q4q7;
585 /* logical pointer of start of each Tx FIFO */
586 TxFIFO_element_t __iomem *tx_FIFO_start[MAX_TX_FIFOS];
588 /* Current offset within tx_FIFO_start, where driver would write new Tx frame*/
589 tx_curr_put_info_t tx_curr_put_info[MAX_TX_FIFOS];
590 tx_curr_get_info_t tx_curr_get_info[MAX_TX_FIFOS];
592 void *stats_mem; /* orignal pointer to allocated mem */
593 dma_addr_t stats_mem_phy; /* Physical address of the stat block */
595 StatInfo_t *stats_info; /* Logical address of the stat block */
598 /* structure representing the user defined MAC addresses */
604 /* Structure that holds the Phy and virt addresses of the Blocks */
605 typedef struct rx_block_info {
606 RxD_t *block_virt_addr;
607 dma_addr_t block_dma_addr;
610 /* Default Tunable parameters of the NIC. */
611 #define DEFAULT_FIFO_LEN 4096
612 #define SMALL_RXD_CNT 30 * (MAX_RXDS_PER_BLOCK+1)
613 #define LARGE_RXD_CNT 100 * (MAX_RXDS_PER_BLOCK+1)
614 #define SMALL_BLK_CNT 30
615 #define LARGE_BLK_CNT 100
617 /* Structure representing one instance of the NIC */
618 typedef struct s2io_nic {
619 #define MAX_MAC_SUPPORTED 16
620 #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
622 macaddr_t def_mac_addr[MAX_MAC_SUPPORTED];
623 macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED];
625 struct net_device_stats stats;
628 struct config_param config;
629 mac_info_t mac_control;
631 int device_close_flag;
632 int device_enabled_once;
635 struct tasklet_struct task;
636 volatile unsigned long tasklet_status;
637 struct timer_list timer;
638 struct net_device *dev;
639 struct pci_dev *pdev;
653 atomic_t rx_bufs_left[MAX_RX_RINGS];
656 #ifndef CONFIG_S2IO_NAPI
663 #define MAX_ADDRS_SUPPORTED 64
666 usr_addr_t usr_addrs[MAX_ADDRS_SUPPORTED];
677 #ifndef CONFIG_S2IO_NAPI
678 /* Index to the absolute position of the put pointer of Rx ring. */
679 int put_pos[MAX_RX_RINGS];
683 * Place holders for the virtual and physical addresses of
686 rx_block_info_t rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING];
687 int block_count[MAX_RX_RINGS];
688 int pkt_cnt[MAX_RX_RINGS];
690 /* Place holder of all the TX List's Phy and Virt addresses. */
691 list_info_hold_t *list_info[MAX_TX_FIFOS];
693 /* Id timer, used to blink NIC to physically identify NIC. */
694 struct timer_list id_timer;
696 /* Restart timer, used to restart NIC if the device is stuck and
697 * a schedule task that will set the correct Link state once the
698 * NIC's PHY has stabilized after a state change.
701 struct tq_struct rst_timer_task;
702 struct tq_struct set_link_task;
704 struct work_struct rst_timer_task;
705 struct work_struct set_link_task;
708 /* Flag that can be used to turn on or turn off the Rx checksum
713 /* after blink, the adapter must be restored with original
718 /* Last known link state. */
723 #ifdef CONFIG_2BUFF_MODE
724 /* Buffer Address store. */
725 buffAdd_t **ba[MAX_RX_RINGS];
731 volatile unsigned long link_state;
734 #define RESET_ERROR 1;
737 /* OS related system calls */
739 static inline u64 readq(void __iomem *addr)
741 u64 ret = readl(addr + 4);
750 static inline void writeq(u64 val, void __iomem *addr)
752 writel((u32) (val), addr);
753 writel((u32) (val >> 32), (addr + 4));
756 /* In 32 bit modes, some registers have to be written in a
757 * particular order to expect correct hardware operation. The
758 * macro SPECIAL_REG_WRITE is used to perform such ordered
759 * writes. Defines UF (Upper First) and LF (Lower First) will
760 * be used to specify the required write order.
764 static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
767 writel((u32) (val), addr);
768 writel((u32) (val >> 32), (addr + 4));
770 writel((u32) (val >> 32), (addr + 4));
771 writel((u32) (val), addr);
775 #define SPECIAL_REG_WRITE(val, addr, dummy) writeq(val, addr)
778 /* Interrupt related values of Xena */
780 #define ENABLE_INTRS 1
781 #define DISABLE_INTRS 2
783 /* Highest level interrupt blocks */
784 #define TX_PIC_INTR (0x0001<<0)
785 #define TX_DMA_INTR (0x0001<<1)
786 #define TX_MAC_INTR (0x0001<<2)
787 #define TX_XGXS_INTR (0x0001<<3)
788 #define TX_TRAFFIC_INTR (0x0001<<4)
789 #define RX_PIC_INTR (0x0001<<5)
790 #define RX_DMA_INTR (0x0001<<6)
791 #define RX_MAC_INTR (0x0001<<7)
792 #define RX_XGXS_INTR (0x0001<<8)
793 #define RX_TRAFFIC_INTR (0x0001<<9)
794 #define MC_INTR (0x0001<<10)
795 #define ENA_ALL_INTRS ( TX_PIC_INTR | \
807 /* Interrupt masks for the general interrupt mask register */
808 #define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
810 #define TXPIC_INT_M BIT(0)
811 #define TXDMA_INT_M BIT(1)
812 #define TXMAC_INT_M BIT(2)
813 #define TXXGXS_INT_M BIT(3)
814 #define TXTRAFFIC_INT_M BIT(8)
815 #define PIC_RX_INT_M BIT(32)
816 #define RXDMA_INT_M BIT(33)
817 #define RXMAC_INT_M BIT(34)
818 #define MC_INT_M BIT(35)
819 #define RXXGXS_INT_M BIT(36)
820 #define RXTRAFFIC_INT_M BIT(40)
822 /* PIC level Interrupts TODO*/
824 /* DMA level Inressupts */
825 #define TXDMA_PFC_INT_M BIT(0)
826 #define TXDMA_PCC_INT_M BIT(2)
828 /* PFC block interrupts */
829 #define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */
831 /* PCC block interrupts. */
832 #define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
836 * Prototype declaration.
838 static int __devinit s2io_init_nic(struct pci_dev *pdev,
839 const struct pci_device_id *pre);
840 static void __devexit s2io_rem_nic(struct pci_dev *pdev);
841 static int init_shared_mem(struct s2io_nic *sp);
842 static void free_shared_mem(struct s2io_nic *sp);
843 static int init_nic(struct s2io_nic *nic);
844 #ifndef CONFIG_S2IO_NAPI
845 static void rx_intr_handler(struct s2io_nic *sp);
847 static void tx_intr_handler(struct s2io_nic *sp);
848 static void alarm_intr_handler(struct s2io_nic *sp);
850 static int s2io_starter(void);
851 void s2io_closer(void);
852 static void s2io_tx_watchdog(struct net_device *dev);
853 static void s2io_tasklet(unsigned long dev_addr);
854 static void s2io_set_multicast(struct net_device *dev);
855 #ifndef CONFIG_2BUFF_MODE
856 static int rx_osm_handler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no);
858 static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no,
861 void s2io_link(nic_t * sp, int link);
862 void s2io_reset(nic_t * sp);
863 #ifdef CONFIG_S2IO_NAPI
864 static int s2io_poll(struct net_device *dev, int *budget);
866 static void s2io_init_pci(nic_t * sp);
867 int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
868 static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs);
869 static int verify_xena_quiescence(u64 val64, int flag);
870 static struct ethtool_ops netdev_ethtool_ops;
871 static void s2io_set_link(unsigned long data);
872 static void s2io_card_down(nic_t * nic);
873 static int s2io_card_up(nic_t * nic);