1 /******************************************************************************
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
6 * See the file "skfddi.c" for further information.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * The information in this file is provided "AS IS" without warranty.
15 ******************************************************************************/
18 * FORMAC+ Driver for tag mode
24 #include "h/supern_2.h"
28 static const char ID_sccs[] = "@(#)fplustm.c 1.32 99/02/23 (C) SK " ;
33 #define UNUSED(x) (x) = (x)
39 #define FM_ADDRX (FM_ADDET|FM_EXGPA0|FM_EXGPA1)
40 #define MS2BCLK(x) ((x)*12500L)
41 #define US2BCLK(x) ((x)*1250L)
44 * prototypes for static function
46 static void build_claim_beacon() ;
47 static int init_mac() ;
48 static void rtm_init() ;
49 static void smt_split_up_fifo() ;
51 #if (!defined(NO_SMT_PANIC) || defined(DEBUG))
52 static char write_mdr_warning [] = "E350 write_mdr() FM_SNPPND is set\n";
53 static char cam_warning [] = "E_SMT_004: CAM still busy\n";
56 #define DUMMY_READ() smc->hw.mc_dummy = (u_short) inp(ADDR(B0_RAP))
58 #define CHECK_NPP() { unsigned k = 10000 ;\
59 while ((inpw(FM_A(FM_STMCHN)) & FM_SNPPND) && k) k--;\
61 SMT_PANIC(smc,SMT_E0130, SMT_E0130_MSG) ; \
65 #define CHECK_CAM() { unsigned k = 10 ;\
66 while (!(inpw(FM_A(FM_AFSTAT)) & FM_DONE) && k) k--;\
68 SMT_PANIC(smc,SMT_E0131, SMT_E0131_MSG) ; \
72 const struct fddi_addr fddi_broadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};
73 static const struct fddi_addr null_addr = {{0,0,0,0,0,0}};
74 static const struct fddi_addr dbeacon_multi = {{0x01,0x80,0xc2,0x00,0x01,0x00}};
76 static const u_short my_said = 0xffff ; /* short address (n.u.) */
77 static const u_short my_sagp = 0xffff ; /* short group address (n.u.) */
83 #define MA smc->hw.fddi_canon_addr
85 #define MA smc->hw.fddi_home_addr
90 * useful interrupt bits
92 static int mac_imsk1u = FM_STXABRS | FM_STXABRA0 | FM_SXMTABT ;
93 static int mac_imsk1l = FM_SQLCKS | FM_SQLCKA0 | FM_SPCEPDS | FM_SPCEPDA0|
94 FM_STBURS | FM_STBURA0 ;
96 /* delete FM_SRBFL after tests */
97 static int mac_imsk2u = FM_SERRSF | FM_SNFSLD | FM_SRCVOVR | FM_SRBFL |
99 static int mac_imsk2l = FM_STRTEXR | FM_SDUPCLM | FM_SFRMCTR |
100 FM_SERRCTR | FM_SLSTCTR |
101 FM_STRTEXP | FM_SMULTDA | FM_SRNGOP ;
103 static int mac_imsk3u = FM_SRCVOVR2 | FM_SRBFL2 ;
104 static int mac_imsk3l = FM_SRPERRQ2 | FM_SRPERRQ1 ;
106 static int mac_beacon_imsk2u = FM_SOTRBEC | FM_SMYBEC | FM_SBEC |
107 FM_SLOCLM | FM_SHICLM | FM_SMYCLM | FM_SCLM ;
110 static u_long mac_get_tneg(smc)
115 tneg = (u_long)((long)inpw(FM_A(FM_TNEG))<<5) ;
116 return((u_long)((tneg + ((inpw(FM_A(FM_TMRS))>>10)&0x1f)) |
120 void mac_update_counter(smc)
123 smc->mib.m[MAC0].fddiMACFrame_Ct =
124 (smc->mib.m[MAC0].fddiMACFrame_Ct & 0xffff0000L)
125 + (u_short) inpw(FM_A(FM_FCNTR)) ;
126 smc->mib.m[MAC0].fddiMACLost_Ct =
127 (smc->mib.m[MAC0].fddiMACLost_Ct & 0xffff0000L)
128 + (u_short) inpw(FM_A(FM_LCNTR)) ;
129 smc->mib.m[MAC0].fddiMACError_Ct =
130 (smc->mib.m[MAC0].fddiMACError_Ct & 0xffff0000L)
131 + (u_short) inpw(FM_A(FM_ECNTR)) ;
132 smc->mib.m[MAC0].fddiMACT_Neg = mac_get_tneg(smc) ;
133 #ifdef SMT_REAL_TOKEN_CT
135 * If the token counter is emulated it is updated in smt_event.
139 smt_emulate_token_ct( smc, MAC0 );
144 * write long value into buffer memory over memory data register (MDR),
146 void write_mdr(smc,val)
155 * read long value from buffer memory over memory data register (MDR),
157 u_long read_mdr(smc,addr)
164 outpw(FM_A(FM_CMDREG1),FM_IRMEMWO) ;
165 CHECK_NPP() ; /* needed for PCI to prevent from timeing violations */
166 /* p = MDRR() ; */ /* bad read values if the workaround */
167 /* smc->hw.mc_dummy = *((short volatile far *)(addr)))*/
169 p = (u_long)inpw(FM_A(FM_MDRU))<<16 ;
170 p += (u_long)inpw(FM_A(FM_MDRL)) ;
174 * clear buffer memory
176 static void init_ram(smc)
181 smc->hw.fp.fifo.rbc_ram_start = 0 ;
182 smc->hw.fp.fifo.rbc_ram_end =
183 smc->hw.fp.fifo.rbc_ram_start + RBC_MEM_SIZE ;
185 MARW(smc->hw.fp.fifo.rbc_ram_start) ;
186 for (i = smc->hw.fp.fifo.rbc_ram_start;
187 i < (u_short) (smc->hw.fp.fifo.rbc_ram_end-1); i++)
189 /* Erase the last byte too */
194 * set receive FIFO pointer
196 static void set_recvptr(smc)
200 * initialize the pointer for receive queue 1
202 outpw(FM_A(FM_RPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* RPR1 */
203 outpw(FM_A(FM_SWPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* SWPR1 */
204 outpw(FM_A(FM_WPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* WPR1 */
205 outpw(FM_A(FM_EARV1),smc->hw.fp.fifo.tx_s_start-1) ; /* EARV1 */
208 * initialize the pointer for receive queue 2
210 if (smc->hw.fp.fifo.rx2_fifo_size) {
211 outpw(FM_A(FM_RPR2),smc->hw.fp.fifo.rx2_fifo_start) ;
212 outpw(FM_A(FM_SWPR2),smc->hw.fp.fifo.rx2_fifo_start) ;
213 outpw(FM_A(FM_WPR2),smc->hw.fp.fifo.rx2_fifo_start) ;
214 outpw(FM_A(FM_EARV2),smc->hw.fp.fifo.rbc_ram_end-1) ;
217 outpw(FM_A(FM_RPR2),smc->hw.fp.fifo.rbc_ram_end-1) ;
218 outpw(FM_A(FM_SWPR2),smc->hw.fp.fifo.rbc_ram_end-1) ;
219 outpw(FM_A(FM_WPR2),smc->hw.fp.fifo.rbc_ram_end-1) ;
220 outpw(FM_A(FM_EARV2),smc->hw.fp.fifo.rbc_ram_end-1) ;
225 * set transmit FIFO pointer
227 static void set_txptr(smc)
230 outpw(FM_A(FM_CMDREG2),FM_IRSTQ) ; /* reset transmit queues */
233 * initialize the pointer for asynchronous transmit queue
235 outpw(FM_A(FM_RPXA0),smc->hw.fp.fifo.tx_a0_start) ; /* RPXA0 */
236 outpw(FM_A(FM_SWPXA0),smc->hw.fp.fifo.tx_a0_start) ; /* SWPXA0 */
237 outpw(FM_A(FM_WPXA0),smc->hw.fp.fifo.tx_a0_start) ; /* WPXA0 */
238 outpw(FM_A(FM_EAA0),smc->hw.fp.fifo.rx2_fifo_start-1) ; /* EAA0 */
241 * initialize the pointer for synchronous transmit queue
243 if (smc->hw.fp.fifo.tx_s_size) {
244 outpw(FM_A(FM_RPXS),smc->hw.fp.fifo.tx_s_start) ;
245 outpw(FM_A(FM_SWPXS),smc->hw.fp.fifo.tx_s_start) ;
246 outpw(FM_A(FM_WPXS),smc->hw.fp.fifo.tx_s_start) ;
247 outpw(FM_A(FM_EAS),smc->hw.fp.fifo.tx_a0_start-1) ;
250 outpw(FM_A(FM_RPXS),smc->hw.fp.fifo.tx_a0_start-1) ;
251 outpw(FM_A(FM_SWPXS),smc->hw.fp.fifo.tx_a0_start-1) ;
252 outpw(FM_A(FM_WPXS),smc->hw.fp.fifo.tx_a0_start-1) ;
253 outpw(FM_A(FM_EAS),smc->hw.fp.fifo.tx_a0_start-1) ;
258 * init memory buffer management registers
260 static void init_rbc(smc)
263 u_short rbc_ram_addr ;
266 * set unused pointers or permanent pointers
268 rbc_ram_addr = smc->hw.fp.fifo.rx2_fifo_start - 1 ;
270 outpw(FM_A(FM_RPXA1),rbc_ram_addr) ; /* a1-send pointer */
271 outpw(FM_A(FM_WPXA1),rbc_ram_addr) ;
272 outpw(FM_A(FM_SWPXA1),rbc_ram_addr) ;
273 outpw(FM_A(FM_EAA1),rbc_ram_addr) ;
282 static void init_rx(smc)
285 struct s_smt_rx_queue *queue ;
288 * init all tx data structures for receive queue 1
290 smc->hw.fp.rx[QUEUE_R1] = queue = &smc->hw.fp.rx_q[QUEUE_R1] ;
291 queue->rx_bmu_ctl = (HW_PTR) ADDR(B0_R1_CSR) ;
292 queue->rx_bmu_dsc = (HW_PTR) ADDR(B4_R1_DA) ;
295 * init all tx data structures for receive queue 2
297 smc->hw.fp.rx[QUEUE_R2] = queue = &smc->hw.fp.rx_q[QUEUE_R2] ;
298 queue->rx_bmu_ctl = (HW_PTR) ADDR(B0_R2_CSR) ;
299 queue->rx_bmu_dsc = (HW_PTR) ADDR(B4_R2_DA) ;
303 * set the TSYNC register of the FORMAC to regulate synchronous transmission
305 void set_formac_tsync(smc,sync_bw)
309 outpw(FM_A(FM_TSYNC),(unsigned int) (((-sync_bw) >> 5) & 0xffff) ) ;
313 * init all tx data structures
315 static void init_tx(smc)
318 struct s_smt_tx_queue *queue ;
321 * init all tx data structures for the synchronous queue
323 smc->hw.fp.tx[QUEUE_S] = queue = &smc->hw.fp.tx_q[QUEUE_S] ;
324 queue->tx_bmu_ctl = (HW_PTR) ADDR(B0_XS_CSR) ;
325 queue->tx_bmu_dsc = (HW_PTR) ADDR(B5_XS_DA) ;
328 set_formac_tsync(smc,smc->ess.sync_bw) ;
332 * init all tx data structures for the asynchronous queue 0
334 smc->hw.fp.tx[QUEUE_A0] = queue = &smc->hw.fp.tx_q[QUEUE_A0] ;
335 queue->tx_bmu_ctl = (HW_PTR) ADDR(B0_XA_CSR) ;
336 queue->tx_bmu_dsc = (HW_PTR) ADDR(B5_XA_DA) ;
339 llc_recover_tx(smc) ;
342 static void mac_counter_init(smc)
349 * clear FORMAC+ frame-, lost- and error counter
351 outpw(FM_A(FM_FCNTR),0) ;
352 outpw(FM_A(FM_LCNTR),0) ;
353 outpw(FM_A(FM_ECNTR),0) ;
355 * clear internal error counter stucture
357 ec = (u_long *)&smc->hw.fp.err_stats ;
358 for (i = (sizeof(struct err_st)/sizeof(long)) ; i ; i--)
360 smc->mib.m[MAC0].fddiMACRingOp_Ct = 0 ;
364 * set FORMAC address, and t_request
366 static void set_formac_addr(smc)
369 long t_requ = smc->mib.m[MAC0].fddiMACT_Req ;
371 outpw(FM_A(FM_SAID),my_said) ; /* set short address */
372 outpw(FM_A(FM_LAIL),(unsigned)((smc->hw.fddi_home_addr.a[4]<<8) +
373 smc->hw.fddi_home_addr.a[5])) ;
374 outpw(FM_A(FM_LAIC),(unsigned)((smc->hw.fddi_home_addr.a[2]<<8) +
375 smc->hw.fddi_home_addr.a[3])) ;
376 outpw(FM_A(FM_LAIM),(unsigned)((smc->hw.fddi_home_addr.a[0]<<8) +
377 smc->hw.fddi_home_addr.a[1])) ;
379 outpw(FM_A(FM_SAGP),my_sagp) ; /* set short group address */
381 outpw(FM_A(FM_LAGL),(unsigned)((smc->hw.fp.group_addr.a[4]<<8) +
382 smc->hw.fp.group_addr.a[5])) ;
383 outpw(FM_A(FM_LAGC),(unsigned)((smc->hw.fp.group_addr.a[2]<<8) +
384 smc->hw.fp.group_addr.a[3])) ;
385 outpw(FM_A(FM_LAGM),(unsigned)((smc->hw.fp.group_addr.a[0]<<8) +
386 smc->hw.fp.group_addr.a[1])) ;
388 /* set r_request regs. (MSW & LSW of TRT ) */
389 outpw(FM_A(FM_TREQ1),(unsigned)(t_requ>>16)) ;
390 outpw(FM_A(FM_TREQ0),(unsigned)t_requ) ;
393 static void set_int(p,l)
397 p[0] = (char)(l >> 24) ;
398 p[1] = (char)(l >> 16) ;
399 p[2] = (char)(l >> 8) ;
400 p[3] = (char)(l >> 0) ;
404 * copy TX descriptor to buffer mem
405 * append FC field and MAC frame
406 * if more bit is set in descr
407 * append pointer to descriptor (endless loop)
409 * append 'end of chain' pointer
411 static void copy_tx_mac(smc,td,mac,off,len)
413 u_long td; /* transmit descriptor */
414 struct fddi_mac *mac; /* mac frame pointer */
415 unsigned off; /* start address within buffer memory */
416 int len ; /* lenght of the frame including the FC */
422 MARW(off) ; /* set memory address reg for writes */
425 for (i = (len + 3)/4 ; i ; i--) {
427 /* last word, set the tag bit */
428 outpw(FM_A(FM_CMDREG2),FM_ISTTB) ;
430 write_mdr(smc,MDR_REVERSE(*p)) ;
434 outpw(FM_A(FM_CMDREG2),FM_ISTTB) ; /* set the tag bit */
435 write_mdr(smc,td) ; /* write over memory data reg to buffer */
439 BEGIN_MANUAL_ENTRY(module;tests;3)
440 How to test directed beacon frames
441 ----------------------------------------------------------------
443 o Insert a break point in the function build_claim_beacon()
444 before calling copy_tx_mac() for building the claim frame.
445 o Modify the RM3_DETECT case so that the RM6_DETECT state
446 will always entered from the RM3_DETECT state (function rmt_fsm(),
448 o Compile the driver.
449 o Set the parameter TREQ in the protocol.ini or net.cfg to a
450 small value to make sure your station will win the claim
453 o When you reach the break point, modify the SA and DA address
454 of the claim frame (e.g. SA = DA = 10005affffff).
455 o When you see RM3_DETECT and RM6_DETECT, observe the direct
456 beacon frames on the UPPSLANA.
460 static void directed_beacon(smc)
463 SK_LOC_DECL(u_int,a[2]) ;
467 * enable FORMAC to send endless queue of directed beacon
468 * important: the UNA starts at byte 1 (not at byte 0)
470 * (char *) a = (char) ((long)DBEACON_INFO<<24L) ;
472 memcpy((char *)a+1,(char *) &smc->mib.m[MAC0].fddiMACUpstreamNbr,6) ;
475 /* set memory address reg for writes */
476 MARW(smc->hw.fp.fifo.rbc_ram_start+DBEACON_FRAME_OFF+4) ;
477 write_mdr(smc,MDR_REVERSE(a[0])) ;
478 outpw(FM_A(FM_CMDREG2),FM_ISTTB) ; /* set the tag bit */
479 write_mdr(smc,MDR_REVERSE(a[1])) ;
481 outpw(FM_A(FM_SABC),smc->hw.fp.fifo.rbc_ram_start + DBEACON_FRAME_OFF) ;
485 setup claim & beacon pointer
487 special frame packets end with a pointer to their own
488 descriptor, and the MORE bit is set in the descriptor
490 static void build_claim_beacon(smc,t_request)
496 struct fddi_mac_sf *mac ;
502 td = TX_DESCRIPTOR | ((((u_int)len-1)&3)<<27) ;
503 mac = &smc->hw.fp.mac_sfb ;
504 mac->mac_fc = FC_CLAIM ;
505 /* DA == SA in claim frame */
506 mac->mac_source = mac->mac_dest = MA ;
508 set_int((char *)mac->mac_info,(int)t_request) ;
510 copy_tx_mac(smc,td,(struct fddi_mac *)mac,
511 smc->hw.fp.fifo.rbc_ram_start + CLAIM_FRAME_OFF,len) ;
512 /* set CLAIM start pointer */
513 outpw(FM_A(FM_SACL),smc->hw.fp.fifo.rbc_ram_start + CLAIM_FRAME_OFF) ;
516 * build beacon packet
519 td = TX_DESCRIPTOR | ((((u_int)len-1)&3)<<27) ;
520 mac->mac_fc = FC_BEACON ;
521 mac->mac_source = MA ;
522 mac->mac_dest = null_addr ; /* DA == 0 in beacon frame */
523 set_int((char *) mac->mac_info,((int)BEACON_INFO<<24) + 0 ) ;
525 copy_tx_mac(smc,td,(struct fddi_mac *)mac,
526 smc->hw.fp.fifo.rbc_ram_start + BEACON_FRAME_OFF,len) ;
527 /* set beacon start pointer */
528 outpw(FM_A(FM_SABC),smc->hw.fp.fifo.rbc_ram_start + BEACON_FRAME_OFF) ;
531 * build directed beacon packet
532 * contains optional UNA
535 td = TX_DESCRIPTOR | ((((u_int)len-1)&3)<<27) ;
536 mac->mac_fc = FC_BEACON ;
537 mac->mac_source = MA ;
538 mac->mac_dest = dbeacon_multi ; /* multicast */
539 set_int((char *) mac->mac_info,((int)DBEACON_INFO<<24) + 0 ) ;
540 set_int((char *) mac->mac_info+4,0) ;
541 set_int((char *) mac->mac_info+8,0) ;
543 copy_tx_mac(smc,td,(struct fddi_mac *)mac,
544 smc->hw.fp.fifo.rbc_ram_start + DBEACON_FRAME_OFF,len) ;
546 /* end of claim/beacon queue */
547 outpw(FM_A(FM_EACB),smc->hw.fp.fifo.rx1_fifo_start-1) ;
549 outpw(FM_A(FM_WPXSF),0) ;
550 outpw(FM_A(FM_RPXSF),0) ;
553 void formac_rcv_restart(smc)
556 /* enable receive function */
557 SETMASK(FM_A(FM_MDREG1),smc->hw.fp.rx_mode,FM_ADDRX) ;
559 outpw(FM_A(FM_CMDREG1),FM_ICLLR) ; /* clear receive lock */
562 void formac_tx_restart(smc)
565 outpw(FM_A(FM_CMDREG1),FM_ICLLS) ; /* clear s-frame lock */
566 outpw(FM_A(FM_CMDREG1),FM_ICLLA0) ; /* clear a-frame lock */
569 static void enable_formac(smc)
572 /* set formac IMSK : 0 enables irq */
573 outpw(FM_A(FM_IMSK1U),~mac_imsk1u) ;
574 outpw(FM_A(FM_IMSK1L),~mac_imsk1l) ;
575 outpw(FM_A(FM_IMSK2U),~mac_imsk2u) ;
576 outpw(FM_A(FM_IMSK2L),~mac_imsk2l) ;
577 outpw(FM_A(FM_IMSK3U),~mac_imsk3u) ;
578 outpw(FM_A(FM_IMSK3L),~mac_imsk3l) ;
581 #if 0 /* Removed because the driver should use the ASICs TX complete IRQ. */
582 /* The FORMACs tx complete IRQ should be used any longer */
585 BEGIN_MANUAL_ENTRY(if,func;others;4)
587 void enable_tx_irq(smc, queue)
591 Function DOWNCALL (SMT, fplustm.c)
592 enable_tx_irq() enables the FORMACs transmit complete
593 interrupt of the queue.
595 Para queue = QUEUE_S: synchronous queue
596 = QUEUE_A0: asynchronous queue
598 Note After any ring operational change the transmit complete
599 interrupts are disabled.
600 The operating system dependent module must enable
601 the transmit complete interrupt of a queue,
602 - when it queues the first frame,
603 because of no transmit resources are beeing
605 - when it escapes from the function llc_restart_tx
606 while some frames are still queued.
610 void enable_tx_irq(smc, queue)
612 u_short queue ; /* 0 = synchronous queue, 1 = asynchronous queue 0 */
616 imask = ~(inpw(FM_A(FM_IMSK1U))) ;
619 outpw(FM_A(FM_IMSK1U),~(imask|FM_STEFRMS)) ;
622 outpw(FM_A(FM_IMSK1U),~(imask|FM_STEFRMA0)) ;
627 BEGIN_MANUAL_ENTRY(if,func;others;4)
629 void disable_tx_irq(smc, queue)
633 Function DOWNCALL (SMT, fplustm.c)
634 disable_tx_irq disables the FORMACs transmit complete
635 interrupt of the queue
637 Para queue = QUEUE_S: synchronous queue
638 = QUEUE_A0: asynchronous queue
640 Note The operating system dependent module should disable
641 the transmit complete interrupts if it escapes from the
642 function llc_restart_tx and no frames are queued.
646 void disable_tx_irq(smc, queue)
648 u_short queue ; /* 0 = synchronous queue, 1 = asynchronous queue 0 */
652 imask = ~(inpw(FM_A(FM_IMSK1U))) ;
655 outpw(FM_A(FM_IMSK1U),~(imask&~FM_STEFRMS)) ;
658 outpw(FM_A(FM_IMSK1U),~(imask&~FM_STEFRMA0)) ;
663 static void disable_formac(smc)
666 /* clear formac IMSK : 1 disables irq */
667 outpw(FM_A(FM_IMSK1U),MW) ;
668 outpw(FM_A(FM_IMSK1L),MW) ;
669 outpw(FM_A(FM_IMSK2U),MW) ;
670 outpw(FM_A(FM_IMSK2L),MW) ;
671 outpw(FM_A(FM_IMSK3U),MW) ;
672 outpw(FM_A(FM_IMSK3L),MW) ;
676 static void mac_ring_up(smc,up)
681 formac_rcv_restart(smc) ; /* enable receive function */
682 smc->hw.mac_ring_is_up = TRUE ;
683 llc_restart_tx(smc) ; /* TX queue */
686 /* disable receive function */
687 SETMASK(FM_A(FM_MDREG1),FM_MDISRCV,FM_ADDET) ;
689 /* abort current transmit activity */
690 outpw(FM_A(FM_CMDREG2),FM_IACTR) ;
692 smc->hw.mac_ring_is_up = FALSE ;
696 /*--------------------------- ISR handling ----------------------------------*/
698 * mac1_irq is in drvfbi.c
702 * mac2_irq: status bits for the receive queue 1, and ring status
703 * ring status indication bits
705 void mac2_irq(smc,code_s2u,code_s2l)
714 * Restart 2_DMax Timer after end of claiming or beaconing
716 if (code_s2u & (FM_SCLM|FM_SHICLM|FM_SBEC|FM_SOTRBEC)) {
717 queue_event(smc,EVENT_RMT,RM_TX_STATE_CHANGE) ;
719 else if (code_s2l & (FM_STKISS)) {
720 queue_event(smc,EVENT_RMT,RM_TX_STATE_CHANGE) ;
724 * XOR current st bits with the last to avoid useless RMT event queuing
726 change_s2l = smc->hw.fp.s2l ^ code_s2l ;
727 change_s2u = smc->hw.fp.s2u ^ code_s2u ;
729 if ((change_s2l & FM_SRNGOP) ||
730 (!smc->hw.mac_ring_is_up && ((code_s2l & FM_SRNGOP)))) {
731 if (code_s2l & FM_SRNGOP) {
733 queue_event(smc,EVENT_RMT,RM_RING_OP) ;
734 smc->mib.m[MAC0].fddiMACRingOp_Ct++ ;
738 queue_event(smc,EVENT_RMT,RM_RING_NON_OP) ;
742 if (code_s2l & FM_SMISFRM) { /* missed frame */
743 smc->mib.m[MAC0].fddiMACNotCopied_Ct++ ;
745 if (code_s2u & (FM_SRCVOVR | /* recv. FIFO overflow */
746 FM_SRBFL)) { /* recv. buffer full */
747 smc->hw.mac_ct.mac_r_restart_counter++ ;
748 /* formac_rcv_restart(smc) ; */
749 smt_stat_counter(smc,1) ;
750 /* goto mac2_end ; */
752 if (code_s2u & FM_SOTRBEC)
753 queue_event(smc,EVENT_RMT,RM_OTHER_BEACON) ;
754 if (code_s2u & FM_SMYBEC)
755 queue_event(smc,EVENT_RMT,RM_MY_BEACON) ;
756 if (change_s2u & code_s2u & FM_SLOCLM) {
757 DB_RMTN(2,"RMT : lower claim received\n",0,0) ;
759 if ((code_s2u & FM_SMYCLM) && !(code_s2l & FM_SDUPCLM)) {
761 * This is my claim and that claim is not detected as a
764 queue_event(smc,EVENT_RMT,RM_MY_CLAIM) ;
766 if (code_s2l & FM_SDUPCLM) {
768 * If a duplicate claim frame (same SA but T_Bid != T_Req)
769 * this flag will be set.
770 * In the RMT state machine we need a RM_VALID_CLAIM event
771 * to do the appropriate state change.
774 queue_event(smc,EVENT_RMT,RM_VALID_CLAIM) ;
776 if (change_s2u & code_s2u & FM_SHICLM) {
777 DB_RMTN(2,"RMT : higher claim received\n",0,0) ;
779 if ( (code_s2l & FM_STRTEXP) ||
780 (code_s2l & FM_STRTEXR) )
781 queue_event(smc,EVENT_RMT,RM_TRT_EXP) ;
782 if (code_s2l & FM_SMULTDA) {
784 * The MAC has found a 2. MAC with the same address.
785 * Signal dup_addr_test = failed to RMT state machine.
788 smc->r.dup_addr_test = DA_FAILED ;
789 queue_event(smc,EVENT_RMT,RM_DUP_ADDR) ;
791 if (code_s2u & FM_SBEC)
792 smc->hw.fp.err_stats.err_bec_stat++ ;
793 if (code_s2u & FM_SCLM)
794 smc->hw.fp.err_stats.err_clm_stat++ ;
795 if (code_s2l & FM_STVXEXP)
796 smc->mib.m[MAC0].fddiMACTvxExpired_Ct++ ;
797 if ((code_s2u & (FM_SBEC|FM_SCLM))) {
798 if (!(change_s2l & FM_SRNGOP) && (smc->hw.fp.s2l & FM_SRNGOP)) {
800 queue_event(smc,EVENT_RMT,RM_RING_NON_OP) ;
803 queue_event(smc,EVENT_RMT,RM_RING_OP) ;
804 smc->mib.m[MAC0].fddiMACRingOp_Ct++ ;
807 if (code_s2l & FM_SPHINV)
808 smc->hw.fp.err_stats.err_phinv++ ;
809 if (code_s2l & FM_SSIFG)
810 smc->hw.fp.err_stats.err_sifg_det++ ;
811 if (code_s2l & FM_STKISS)
812 smc->hw.fp.err_stats.err_tkiss++ ;
813 if (code_s2l & FM_STKERR)
814 smc->hw.fp.err_stats.err_tkerr++ ;
815 if (code_s2l & FM_SFRMCTR)
816 smc->mib.m[MAC0].fddiMACFrame_Ct += 0x10000L ;
817 if (code_s2l & FM_SERRCTR)
818 smc->mib.m[MAC0].fddiMACError_Ct += 0x10000L ;
819 if (code_s2l & FM_SLSTCTR)
820 smc->mib.m[MAC0].fddiMACLost_Ct += 0x10000L ;
821 if (code_s2u & FM_SERRSF) {
822 SMT_PANIC(smc,SMT_E0114, SMT_E0114_MSG) ;
825 /* notice old status */
826 smc->hw.fp.s2l = code_s2l ;
827 smc->hw.fp.s2u = code_s2u ;
828 outpw(FM_A(FM_IMSK2U),~mac_imsk2u) ;
832 * mac3_irq: receive queue 2 bits and address detection bits
834 void mac3_irq(smc,code_s3u,code_s3l)
841 if (code_s3u & (FM_SRCVOVR2 | /* recv. FIFO overflow */
842 FM_SRBFL2)) { /* recv. buffer full */
843 smc->hw.mac_ct.mac_r_restart_counter++ ;
844 smt_stat_counter(smc,1);
848 if (code_s3u & FM_SRPERRQ2) { /* parity error receive queue 2 */
849 SMT_PANIC(smc,SMT_E0115, SMT_E0115_MSG) ;
851 if (code_s3u & FM_SRPERRQ1) { /* parity error receive queue 2 */
852 SMT_PANIC(smc,SMT_E0116, SMT_E0116_MSG) ;
858 * take formac offline
860 static void formac_offline(smc)
863 outpw(FM_A(FM_CMDREG2),FM_IACTR) ;/* abort current transmit activity */
865 /* disable receive function */
866 SETMASK(FM_A(FM_MDREG1),FM_MDISRCV,FM_ADDET) ;
868 /* FORMAC+ 'Initialize Mode' */
869 SETMASK(FM_A(FM_MDREG1),FM_MINIT,FM_MMODE) ;
871 disable_formac(smc) ;
872 smc->hw.mac_ring_is_up = FALSE ;
873 smc->hw.hw_state = STOPPED ;
877 * bring formac online
879 static void formac_online(smc)
883 SETMASK(FM_A(FM_MDREG1),FM_MONLINE | FM_SELRA | MDR1INIT |
884 smc->hw.fp.rx_mode, FM_MMODE | FM_SELRA | FM_ADDRX) ;
888 * FORMAC+ full init. (tx, rx, timer, counter, claim & beacon)
893 smc->hw.fp.nsa_mode = FM_MRNNSAFNMA ;
894 smc->hw.fp.rx_mode = FM_MDAMA ;
895 smc->hw.fp.group_addr = fddi_broadcast ;
896 smc->hw.fp.func_addr = 0 ;
897 smc->hw.fp.frselreg_init = 0 ;
899 init_driver_fplus(smc) ;
900 if (smc->s.sas == SMT_DAS)
901 smc->hw.fp.mdr3init |= FM_MENDAS ;
903 smc->hw.mac_ct.mac_nobuf_counter = 0 ;
904 smc->hw.mac_ct.mac_r_restart_counter = 0 ;
906 smc->hw.fp.fm_st1u = (HW_PTR) ADDR(B0_ST1U) ;
907 smc->hw.fp.fm_st1l = (HW_PTR) ADDR(B0_ST1L) ;
908 smc->hw.fp.fm_st2u = (HW_PTR) ADDR(B0_ST2U) ;
909 smc->hw.fp.fm_st2l = (HW_PTR) ADDR(B0_ST2L) ;
910 smc->hw.fp.fm_st3u = (HW_PTR) ADDR(B0_ST3U) ;
911 smc->hw.fp.fm_st3l = (HW_PTR) ADDR(B0_ST3L) ;
913 smc->hw.fp.s2l = smc->hw.fp.s2u = 0 ;
914 smc->hw.mac_ring_is_up = 0 ;
916 mac_counter_init(smc) ;
918 /* convert BCKL units to symbol time */
919 smc->hw.mac_pa.t_neg = (u_long)0 ;
920 smc->hw.mac_pa.t_pri = (u_long)0 ;
922 /* make sure all PCI settings are correct */
923 mac_do_pci_fix(smc) ;
925 return(init_mac(smc,1)) ;
926 /* enable_formac(smc) ; */
929 static int init_mac(smc,all)
939 outpw(FM_A(FM_MDREG1),FM_MINIT) ; /* FORMAC+ init mode */
940 set_formac_addr(smc) ;
941 outpw(FM_A(FM_MDREG1),FM_MMEMACT) ; /* FORMAC+ memory activ mode */
942 /* Note: Mode register 2 is set here, incase parity is enabled. */
943 outpw(FM_A(FM_MDREG2),smc->hw.fp.mdr2init) ;
950 * reset the HPI, the Master and the BMUs
952 outp(ADDR(B0_CTRL), CTRL_HPI_SET) ;
953 time = hwt_quick_read(smc) ;
957 * set all pointers, frames etc
959 smt_split_up_fifo(smc) ;
965 build_claim_beacon(smc,smc->mib.m[MAC0].fddiMACT_Req) ;
967 /* set RX threshold */
968 /* see Errata #SN2 Phantom receive overflow */
969 outpw(FM_A(FM_FRMTHR),14<<12) ; /* switch on */
971 /* set formac work mode */
972 outpw(FM_A(FM_MDREG1),MDR1INIT | FM_SELRA | smc->hw.fp.rx_mode) ;
973 outpw(FM_A(FM_MDREG2),smc->hw.fp.mdr2init) ;
974 outpw(FM_A(FM_MDREG3),smc->hw.fp.mdr3init) ;
975 outpw(FM_A(FM_FRSELREG),smc->hw.fp.frselreg_init) ;
980 * T_MAX must not be FFFE
981 * or one of FFDF, FFB8, FF91 (-0x27 etc..)
983 t_max = (u_short)(smc->mib.m[MAC0].fddiMACT_Max/32) ;
986 if ((t_max == 0xfffe) || (t_max - x == 0x16))
988 outpw(FM_A(FM_TMAX),(u_short)t_max) ;
990 /* BugFix for report #10204 */
991 if (smc->mib.m[MAC0].fddiMACTvxValue < (u_long) (- US2BCLK(52))) {
992 outpw(FM_A(FM_TVX), (u_short) (- US2BCLK(52))/255 & MB) ;
995 (u_short)((smc->mib.m[MAC0].fddiMACTvxValue/255) & MB)) ;
998 outpw(FM_A(FM_CMDREG1),FM_ICLLS) ; /* clear s-frame lock */
999 outpw(FM_A(FM_CMDREG1),FM_ICLLA0) ; /* clear a-frame lock */
1000 outpw(FM_A(FM_CMDREG1),FM_ICLLR); /* clear receive lock */
1002 /* Auto unlock receice threshold for receive queue 1 and 2 */
1003 outpw(FM_A(FM_UNLCKDLY),(0xff|(0xff<<8))) ;
1005 rtm_init(smc) ; /* RT-Monitor */
1009 * after 10ms, reset the BMUs and repair the rings
1011 hwt_wait_time(smc,time,MS2BCLK(10)) ;
1012 outpd(ADDR(B0_R1_CSR),CSR_SET_RESET) ;
1013 outpd(ADDR(B0_XA_CSR),CSR_SET_RESET) ;
1014 outpd(ADDR(B0_XS_CSR),CSR_SET_RESET) ;
1015 outp(ADDR(B0_CTRL), CTRL_HPI_CLR) ;
1016 outpd(ADDR(B0_R1_CSR),CSR_CLR_RESET) ;
1017 outpd(ADDR(B0_XA_CSR),CSR_CLR_RESET) ;
1018 outpd(ADDR(B0_XS_CSR),CSR_CLR_RESET) ;
1019 if (!smc->hw.hw_is_64bit) {
1020 outpd(ADDR(B4_R1_F), RX_WATERMARK) ;
1021 outpd(ADDR(B5_XA_F), TX_WATERMARK) ;
1022 outpd(ADDR(B5_XS_F), TX_WATERMARK) ;
1024 smc->hw.hw_state = STOPPED ;
1025 mac_drv_repair_descr(smc) ;
1027 smc->hw.hw_state = STARTED ;
1036 void config_mux(smc,mux)
1040 plc_config_mux(smc,mux) ;
1042 SETMASK(FM_A(FM_MDREG1),FM_SELRA,FM_SELRA) ;
1047 * enable CLAIM/BEACON interrupts
1048 * (only called if these events are of interest, e.g. in DETECT state
1049 * the interrupt must not be permanently enabled
1050 * RMT calls this function periodically (timer driven polling)
1052 void sm_mac_check_beacon_claim(smc)
1055 /* set formac IMSK : 0 enables irq */
1056 outpw(FM_A(FM_IMSK2U),~(mac_imsk2u | mac_beacon_imsk2u)) ;
1057 /* the driver must receive the directed beacons */
1058 formac_rcv_restart(smc) ;
1059 process_receive(smc) ;
1062 /*-------------------------- interface functions ----------------------------*/
1064 * control ODL output
1066 void sm_pm_control(smc,mode)
1073 * if PCM logic has set LS_REQUEST = Transmit QUIET Line State
1074 * /FOTOFF signal turn activ -> ODL disable
1077 case PM_TRANSMIT_DISABLE :
1079 case PM_TRANSMIT_ENABLE :
1085 * control MAC layer (called by RMT)
1087 void sm_ma_control(smc,mode)
1093 /* Add to make the MAC offline in RM0_ISOLATED state */
1094 formac_offline(smc) ;
1097 (void)init_mac(smc,0) ;
1100 formac_online(smc) ;
1103 directed_beacon(smc) ;
1107 * no actions necessary, TREQ is already set
1113 int sm_mac_get_tx_state(smc)
1116 return((inpw(FM_A(FM_STMCHN))>>4)&7) ;
1120 * multicast functions
1123 static struct s_fpmc *mac_get_mc_table(smc,user,own,del,can)
1125 struct fddi_addr *user ;
1126 struct fddi_addr *own ;
1131 struct s_fpmc *slot ;
1136 * set own = can(user)
1141 for (i = 0 ; i < 6 ; i++, p++)
1142 *p = canonical[*p] ;
1145 for (i = 0, tb = smc->hw.fp.mc.table ; i < FPMAX_MULTICAST ; i++, tb++){
1146 if (!tb->n) { /* not used */
1147 if (!del && !slot) /* if !del save first free */
1151 if (memcmp((char *)&tb->a,(char *)own,6))
1155 return(slot) ; /* return first free or NULL */
1159 BEGIN_MANUAL_ENTRY(if,func;others;2)
1161 void mac_clear_multicast(smc)
1164 Function DOWNCALL (SMT, fplustm.c)
1165 Clear all multicast entries
1169 void mac_clear_multicast(smc)
1175 smc->hw.fp.os_slots_used = 0 ; /* note the SMT addresses */
1176 /* will not be deleted */
1177 for (i = 0, tb = smc->hw.fp.mc.table ; i < FPMAX_MULTICAST ; i++, tb++){
1185 BEGIN_MANUAL_ENTRY(if,func;others;2)
1187 int mac_set_func_addr(smc,f_addr)
1191 Function DOWNCALL (SMT, fplustm.c)
1192 Set a Token-Ring functional address, the address will
1193 be activated after calling mac_update_multicast()
1195 Para f_addr functional bits in non-canonical format
1197 Returns 0: always success
1201 int mac_set_func_addr(smc,f_addr)
1205 smc->hw.fp.func_addr = f_addr ;
1211 BEGIN_MANUAL_ENTRY(if,func;others;2)
1213 int mac_add_multicast(smc,addr,can)
1215 struct fddi_addr *addr ;
1218 Function DOWNCALL (SMC, fplustm.c)
1219 Add an entry to the multicast table
1221 Para addr pointer to a multicast address
1222 can = 0: the multicast address has the physical format
1223 = 1: the multicast address has the canonical format
1227 1: address table full
1229 Note After a 'driver reset' or a 'station set address' all
1230 entries of the multicast table are cleared.
1231 In this case the driver has to fill the multicast table again.
1232 After the operating system dependent module filled
1233 the multicast table it must call mac_update_multicast
1234 to activate the new multicast addresses!
1238 int mac_add_multicast(smc,addr,can)
1240 struct fddi_addr *addr ;
1243 SK_LOC_DECL(struct fddi_addr,own) ;
1247 * check if there are free table entries
1250 if (smc->hw.fp.smt_slots_used >= SMT_MAX_MULTI) {
1255 if (smc->hw.fp.os_slots_used >= FPMAX_MULTICAST-SMT_MAX_MULTI) {
1263 if (!(tb = mac_get_mc_table(smc,addr,&own,0,can & ~0x80)))
1267 tb->perm = (can & 0x80) ? 1 : 0 ;
1270 smc->hw.fp.smt_slots_used++ ;
1272 smc->hw.fp.os_slots_used++ ;
1278 BEGIN_MANUAL_ENTRY(if,func;others;2)
1280 void mac_del_multicast(smc,addr,can)
1282 struct fddi_addr *addr ;
1285 Function DOWNCALL (SMT, fplustm.c)
1286 Delete an entry from the multicast table
1288 Para addr pointer to a multicast address
1289 can = 0: the multicast address has the physical format
1290 = 1: the multicast address has the canonical format
1295 void mac_del_multicast(smc,addr,can)
1297 struct fddi_addr *addr ;
1300 SK_LOC_DECL(struct fddi_addr,own) ;
1303 if (!(tb = mac_get_mc_table(smc,addr,&own,1,can & ~0x80)))
1306 * permanent addresses must be deleted with perm bit
1309 if (( tb->perm && (can & 0x80)) ||
1310 (!tb->perm && !(can & 0x80))) {
1317 smc->hw.fp.smt_slots_used-- ;
1320 smc->hw.fp.os_slots_used-- ;
1330 #define RX_MODE_PROM 0x1
1331 #define RX_MODE_ALL_MULTI 0x2
1334 BEGIN_MANUAL_ENTRY(if,func;others;2)
1336 void mac_update_multicast(smc)
1339 Function DOWNCALL (SMT, fplustm.c)
1340 Update FORMAC multicast registers
1344 void mac_update_multicast(smc)
1352 * invalidate the CAM
1354 outpw(FM_A(FM_AFCMD),FM_IINV_CAM) ;
1357 * set the functional address
1359 if (smc->hw.fp.func_addr) {
1360 fu = (u_char *) &smc->hw.fp.func_addr ;
1361 outpw(FM_A(FM_AFMASK2),0xffff) ;
1362 outpw(FM_A(FM_AFMASK1),(u_short) ~((fu[0] << 8) + fu[1])) ;
1363 outpw(FM_A(FM_AFMASK0),(u_short) ~((fu[2] << 8) + fu[3])) ;
1364 outpw(FM_A(FM_AFPERS),FM_VALID|FM_DA) ;
1365 outpw(FM_A(FM_AFCOMP2), 0xc000) ;
1366 outpw(FM_A(FM_AFCOMP1), 0x0000) ;
1367 outpw(FM_A(FM_AFCOMP0), 0x0000) ;
1368 outpw(FM_A(FM_AFCMD),FM_IWRITE_CAM) ;
1372 * set the mask and the personality register(s)
1374 outpw(FM_A(FM_AFMASK0),0xffff) ;
1375 outpw(FM_A(FM_AFMASK1),0xffff) ;
1376 outpw(FM_A(FM_AFMASK2),0xffff) ;
1377 outpw(FM_A(FM_AFPERS),FM_VALID|FM_DA) ;
1379 for (i = 0, tb = smc->hw.fp.mc.table; i < FPMAX_MULTICAST; i++, tb++) {
1384 * write the multicast address into the CAM
1386 outpw(FM_A(FM_AFCOMP2),
1387 (u_short)((tb->a.a[0]<<8)+tb->a.a[1])) ;
1388 outpw(FM_A(FM_AFCOMP1),
1389 (u_short)((tb->a.a[2]<<8)+tb->a.a[3])) ;
1390 outpw(FM_A(FM_AFCOMP0),
1391 (u_short)((tb->a.a[4]<<8)+tb->a.a[5])) ;
1392 outpw(FM_A(FM_AFCMD),FM_IWRITE_CAM) ;
1398 BEGIN_MANUAL_ENTRY(if,func;others;3)
1400 void mac_set_rx_mode(smc,mode)
1404 Function DOWNCALL/INTERN (SMT, fplustm.c)
1405 This function enables / disables the selected receive.
1406 Don't call this function if the hardware module is
1407 used -- use mac_drv_rx_mode() instead of.
1409 Para mode = 1 RX_ENABLE_ALLMULTI enable all multicasts
1410 2 RX_DISABLE_ALLMULTI disable "enable all multicasts"
1411 3 RX_ENABLE_PROMISC enable promiscous
1412 4 RX_DISABLE_PROMISC disable promiscous
1413 5 RX_ENABLE_NSA enable reception of NSA frames
1414 6 RX_DISABLE_NSA disable reception of NSA frames
1416 Note The selected receive modes will be lost after 'driver reset'
1417 or 'set station address'
1421 void mac_set_rx_mode(smc,mode)
1426 case RX_ENABLE_ALLMULTI :
1427 smc->hw.fp.rx_prom |= RX_MODE_ALL_MULTI ;
1429 case RX_DISABLE_ALLMULTI :
1430 smc->hw.fp.rx_prom &= ~RX_MODE_ALL_MULTI ;
1432 case RX_ENABLE_PROMISC :
1433 smc->hw.fp.rx_prom |= RX_MODE_PROM ;
1435 case RX_DISABLE_PROMISC :
1436 smc->hw.fp.rx_prom &= ~RX_MODE_PROM ;
1438 case RX_ENABLE_NSA :
1439 smc->hw.fp.nsa_mode = FM_MDAMA ;
1440 smc->hw.fp.rx_mode = (smc->hw.fp.rx_mode & ~FM_ADDET) |
1441 smc->hw.fp.nsa_mode ;
1443 case RX_DISABLE_NSA :
1444 smc->hw.fp.nsa_mode = FM_MRNNSAFNMA ;
1445 smc->hw.fp.rx_mode = (smc->hw.fp.rx_mode & ~FM_ADDET) |
1446 smc->hw.fp.nsa_mode ;
1449 if (smc->hw.fp.rx_prom & RX_MODE_PROM) {
1450 smc->hw.fp.rx_mode = FM_MLIMPROM ;
1452 else if (smc->hw.fp.rx_prom & RX_MODE_ALL_MULTI) {
1453 smc->hw.fp.rx_mode = smc->hw.fp.nsa_mode | FM_EXGPA0 ;
1456 smc->hw.fp.rx_mode = smc->hw.fp.nsa_mode ;
1457 SETMASK(FM_A(FM_MDREG1),smc->hw.fp.rx_mode,FM_ADDRX) ;
1458 mac_update_multicast(smc) ;
1462 BEGIN_MANUAL_ENTRY(module;tests;3)
1463 How to test the Restricted Token Monitor
1464 ----------------------------------------------------------------
1466 o Insert a break point in the function rtm_irq()
1467 o Remove all stations with a restricted token monitor from the
1469 o Connect a UPPS ISA or EISA station to the network.
1470 o Give the FORMAC of UPPS station the command to send
1471 restricted tokens until the ring becomes instable.
1472 o Now connect your test test client.
1473 o The restricted token monitor should detect the restricted token,
1474 and your break point will be reached.
1475 o You can ovserve how the station will clean the ring.
1482 outpw(ADDR(B2_RTM_CRTL),TIM_CL_IRQ) ; /* clear IRQ */
1483 if (inpw(ADDR(B2_RTM_CRTL)) & TIM_RES_TOK) {
1484 outpw(FM_A(FM_CMDREG1),FM_ICL) ; /* force claim */
1485 DB_RMT("RMT: fddiPATHT_Rmode expired\n",0,0) ;
1486 AIX_EVENT(smc, (u_long) FDDI_RING_STATUS,
1487 (u_long) FDDI_SMT_EVENT,
1488 (u_long) FDDI_RTT, smt_get_event_word(smc));
1490 outpw(ADDR(B2_RTM_CRTL),TIM_START) ; /* enable RTM monitoring */
1493 static void rtm_init(smc)
1496 outpd(ADDR(B2_RTM_INI),0) ; /* timer = 0 */
1497 outpw(ADDR(B2_RTM_CRTL),TIM_START) ; /* enable IRQ */
1500 void rtm_set_timer(smc)
1504 * MIB timer and hardware timer have the same resolution of 80nS
1506 DB_RMT("RMT: setting new fddiPATHT_Rmode, t = %d ns \n",
1507 (int) smc->mib.a[PATH0].fddiPATHT_Rmode,0) ;
1508 outpd(ADDR(B2_RTM_INI),smc->mib.a[PATH0].fddiPATHT_Rmode) ;
1511 static void smt_split_up_fifo(smc)
1516 BEGIN_MANUAL_ENTRY(module;mem;1)
1517 -------------------------------------------------------------
1518 RECEIVE BUFFER MEMORY DIVERSION
1519 -------------------------------------------------------------
1521 R1_RxD == SMT_R1_RXD_COUNT
1522 R2_RxD == SMT_R2_RXD_COUNT
1524 SMT_R1_RXD_COUNT must be unequal zero
1526 | R1_RxD R2_RxD |R1_RxD R2_RxD | R1_RxD R2_RxD
1527 | x 0 | x 1-3 | x < 3
1528 ----------------------------------------------------------------------
1529 | 63,75 kB | 54,75 | R1_RxD
1530 rx queue 1 | RX_FIFO_SPACE | RX_LARGE_FIFO| ------------- * 63,75 kB
1532 ----------------------------------------------------------------------
1534 rx queue 2 | 0 kB | RX_SMALL_FIFO| ------------- * 63,75 kB
1535 | (not used) | | R1_RxD+R2_RxD
1540 if (SMT_R1_RXD_COUNT == 0) {
1541 SMT_PANIC(smc,SMT_E0117, SMT_E0117_MSG) ;
1544 switch(SMT_R2_RXD_COUNT) {
1546 smc->hw.fp.fifo.rx1_fifo_size = RX_FIFO_SPACE ;
1547 smc->hw.fp.fifo.rx2_fifo_size = 0 ;
1552 smc->hw.fp.fifo.rx1_fifo_size = RX_LARGE_FIFO ;
1553 smc->hw.fp.fifo.rx2_fifo_size = RX_SMALL_FIFO ;
1555 default: /* this is not the real defaule */
1556 smc->hw.fp.fifo.rx1_fifo_size = RX_FIFO_SPACE *
1557 SMT_R1_RXD_COUNT/(SMT_R1_RXD_COUNT+SMT_R2_RXD_COUNT) ;
1558 smc->hw.fp.fifo.rx2_fifo_size = RX_FIFO_SPACE *
1559 SMT_R2_RXD_COUNT/(SMT_R1_RXD_COUNT+SMT_R2_RXD_COUNT) ;
1564 BEGIN_MANUAL_ENTRY(module;mem;1)
1565 -------------------------------------------------------------
1566 TRANSMIT BUFFER MEMORY DIVERSION
1567 -------------------------------------------------------------
1570 | no sync bw | sync bw available and | sync bw available and
1571 | available | SynchTxMode = SPLIT | SynchTxMode = ALL
1572 -----------------------------------------------------------------------
1573 sync tx | 0 kB | 32 kB | 55 kB
1574 queue | | TX_MEDIUM_FIFO | TX_LARGE_FIFO
1575 -----------------------------------------------------------------------
1576 async tx | 64 kB | 32 kB | 9 k
1577 queue | TX_FIFO_SPACE| TX_MEDIUM_FIFO | TX_SMALL_FIFO
1583 * set the tx mode bits
1585 if (smc->mib.a[PATH0].fddiPATHSbaPayload) {
1587 smc->hw.fp.fifo.fifo_config_mode |=
1588 smc->mib.fddiESSSynchTxMode | SYNC_TRAFFIC_ON ;
1592 smc->hw.fp.fifo.fifo_config_mode &=
1593 ~(SEND_ASYNC_AS_SYNC|SYNC_TRAFFIC_ON) ;
1599 if (smc->hw.fp.fifo.fifo_config_mode & SYNC_TRAFFIC_ON) {
1600 if (smc->hw.fp.fifo.fifo_config_mode & SEND_ASYNC_AS_SYNC) {
1601 smc->hw.fp.fifo.tx_s_size = TX_LARGE_FIFO ;
1602 smc->hw.fp.fifo.tx_a0_size = TX_SMALL_FIFO ;
1605 smc->hw.fp.fifo.tx_s_size = TX_MEDIUM_FIFO ;
1606 smc->hw.fp.fifo.tx_a0_size = TX_MEDIUM_FIFO ;
1610 smc->hw.fp.fifo.tx_s_size = 0 ;
1611 smc->hw.fp.fifo.tx_a0_size = TX_FIFO_SPACE ;
1614 smc->hw.fp.fifo.rx1_fifo_start = smc->hw.fp.fifo.rbc_ram_start +
1616 smc->hw.fp.fifo.tx_s_start = smc->hw.fp.fifo.rx1_fifo_start +
1617 smc->hw.fp.fifo.rx1_fifo_size ;
1618 smc->hw.fp.fifo.tx_a0_start = smc->hw.fp.fifo.tx_s_start +
1619 smc->hw.fp.fifo.tx_s_size ;
1620 smc->hw.fp.fifo.rx2_fifo_start = smc->hw.fp.fifo.tx_a0_start +
1621 smc->hw.fp.fifo.tx_a0_size ;
1623 DB_SMT("FIFO split: mode = %x\n",smc->hw.fp.fifo.fifo_config_mode,0) ;
1624 DB_SMT("rbc_ram_start = %x rbc_ram_end = %x\n",
1625 smc->hw.fp.fifo.rbc_ram_start, smc->hw.fp.fifo.rbc_ram_end) ;
1626 DB_SMT("rx1_fifo_start = %x tx_s_start = %x\n",
1627 smc->hw.fp.fifo.rx1_fifo_start, smc->hw.fp.fifo.tx_s_start) ;
1628 DB_SMT("tx_a0_start = %x rx2_fifo_start = %x\n",
1629 smc->hw.fp.fifo.tx_a0_start, smc->hw.fp.fifo.rx2_fifo_start) ;
1632 void formac_reinit_tx(smc)
1636 * Split up the FIFO and reinitialize the MAC if synchronous
1637 * bandwidth becomes available but no synchronous queue is
1640 if (!smc->hw.fp.fifo.tx_s_size && smc->mib.a[PATH0].fddiPATHSbaPayload){
1641 (void)init_mac(smc,0) ;