1 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
6 * Support for Apple GMAC and assorted PHYs by
7 * Benjamin Herrenscmidt (benh@kernel.crashing.org)
10 * - Get rid of all those nasty mdelay's and replace them
11 * with schedule_timeout.
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/fcntl.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
22 #include <linux/slab.h>
23 #include <linux/string.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/errno.h>
27 #include <linux/pci.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/skbuff.h>
31 #include <linux/mii.h>
32 #include <linux/ethtool.h>
33 #include <linux/crc32.h>
34 #include <linux/random.h>
35 #include <linux/workqueue.h>
37 #include <asm/system.h>
38 #include <asm/bitops.h>
40 #include <asm/byteorder.h>
41 #include <asm/uaccess.h>
45 #include <asm/idprom.h>
46 #include <asm/openprom.h>
47 #include <asm/oplib.h>
51 #ifdef CONFIG_PPC_PMAC
52 #include <asm/pci-bridge.h>
54 #include <asm/machdep.h>
55 #include <asm/pmac_feature.h>
58 #include "sungem_phy.h"
61 /* Stripping FCS is causing problems, disabled for now */
64 #define DEFAULT_MSG (NETIF_MSG_DRV | \
68 #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
69 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
70 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
72 #define DRV_NAME "sungem"
73 #define DRV_VERSION "0.98"
74 #define DRV_RELDATE "8/24/03"
75 #define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
77 static char version[] __devinitdata =
78 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
80 MODULE_AUTHOR(DRV_AUTHOR);
81 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
82 MODULE_LICENSE("GPL");
84 #define GEM_MODULE_NAME "gem"
85 #define PFX GEM_MODULE_NAME ": "
87 static struct pci_device_id gem_pci_tbl[] = {
88 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
89 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
91 /* These models only differ from the original GEM in
92 * that their tx/rx fifos are of a different size and
93 * they only support 10/100 speeds. -DaveM
95 * Apple's GMAC does support gigabit on machines with
96 * the BCM54xx PHYs. -BenH
98 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
99 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
100 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
102 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
103 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
104 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
106 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
111 MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
113 static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
120 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
121 cmd |= (reg << 18) & MIF_FRAME_REGAD;
122 cmd |= (MIF_FRAME_TAMSB);
123 writel(cmd, gp->regs + MIF_FRAME);
126 cmd = readl(gp->regs + MIF_FRAME);
127 if (cmd & MIF_FRAME_TALSB)
136 return cmd & MIF_FRAME_DATA;
139 static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
141 struct gem *gp = dev->priv;
142 return __phy_read(gp, mii_id, reg);
145 static inline u16 phy_read(struct gem *gp, int reg)
147 return __phy_read(gp, gp->mii_phy_addr, reg);
150 static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
157 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
158 cmd |= (reg << 18) & MIF_FRAME_REGAD;
159 cmd |= (MIF_FRAME_TAMSB);
160 cmd |= (val & MIF_FRAME_DATA);
161 writel(cmd, gp->regs + MIF_FRAME);
164 cmd = readl(gp->regs + MIF_FRAME);
165 if (cmd & MIF_FRAME_TALSB)
172 static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
174 struct gem *gp = dev->priv;
175 __phy_write(gp, mii_id, reg, val & 0xffff);
178 static inline void phy_write(struct gem *gp, int reg, u16 val)
180 __phy_write(gp, gp->mii_phy_addr, reg, val);
183 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
185 if (netif_msg_intr(gp))
186 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
189 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
191 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
194 if (netif_msg_intr(gp))
195 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
196 gp->dev->name, pcs_istat);
198 if (!(pcs_istat & PCS_ISTAT_LSC)) {
199 printk(KERN_ERR "%s: PCS irq but no link status change???\n",
204 /* The link status bit latches on zero, so you must
205 * read it twice in such a case to see a transition
206 * to the link being up.
208 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
209 if (!(pcs_miistat & PCS_MIISTAT_LS))
211 (readl(gp->regs + PCS_MIISTAT) &
214 if (pcs_miistat & PCS_MIISTAT_ANC) {
215 /* The remote-fault indication is only valid
216 * when autoneg has completed.
218 if (pcs_miistat & PCS_MIISTAT_RF)
219 printk(KERN_INFO "%s: PCS AutoNEG complete, "
220 "RemoteFault\n", dev->name);
222 printk(KERN_INFO "%s: PCS AutoNEG complete.\n",
226 if (pcs_miistat & PCS_MIISTAT_LS) {
227 printk(KERN_INFO "%s: PCS link is now up.\n",
229 netif_carrier_on(gp->dev);
231 printk(KERN_INFO "%s: PCS link is now down.\n",
233 netif_carrier_off(gp->dev);
234 /* If this happens and the link timer is not running,
235 * reset so we re-negotiate.
237 if (!timer_pending(&gp->link_timer))
244 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
246 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
248 if (netif_msg_intr(gp))
249 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
250 gp->dev->name, txmac_stat);
252 /* Defer timer expiration is quite normal,
253 * don't even log the event.
255 if ((txmac_stat & MAC_TXSTAT_DTE) &&
256 !(txmac_stat & ~MAC_TXSTAT_DTE))
259 if (txmac_stat & MAC_TXSTAT_URUN) {
260 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
262 gp->net_stats.tx_fifo_errors++;
265 if (txmac_stat & MAC_TXSTAT_MPE) {
266 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
268 gp->net_stats.tx_errors++;
271 /* The rest are all cases of one of the 16-bit TX
274 if (txmac_stat & MAC_TXSTAT_NCE)
275 gp->net_stats.collisions += 0x10000;
277 if (txmac_stat & MAC_TXSTAT_ECE) {
278 gp->net_stats.tx_aborted_errors += 0x10000;
279 gp->net_stats.collisions += 0x10000;
282 if (txmac_stat & MAC_TXSTAT_LCE) {
283 gp->net_stats.tx_aborted_errors += 0x10000;
284 gp->net_stats.collisions += 0x10000;
287 /* We do not keep track of MAC_TXSTAT_FCE and
288 * MAC_TXSTAT_PCE events.
293 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
294 * so we do the following.
296 * If any part of the reset goes wrong, we return 1 and that causes the
297 * whole chip to be reset.
299 static int gem_rxmac_reset(struct gem *gp)
301 struct net_device *dev = gp->dev;
306 /* First, reset MAC RX. */
307 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
308 gp->regs + MAC_RXCFG);
309 for (limit = 0; limit < 5000; limit++) {
310 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
315 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
316 "chip.\n", dev->name);
320 /* Second, disable RX DMA. */
321 writel(0, gp->regs + RXDMA_CFG);
322 for (limit = 0; limit < 5000; limit++) {
323 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
328 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
329 "chip.\n", dev->name);
335 /* Execute RX reset command. */
336 writel(gp->swrst_base | GREG_SWRST_RXRST,
337 gp->regs + GREG_SWRST);
338 for (limit = 0; limit < 5000; limit++) {
339 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
344 printk(KERN_ERR "%s: RX reset command will not execute, resetting "
345 "whole chip.\n", dev->name);
349 /* Refresh the RX ring. */
350 for (i = 0; i < RX_RING_SIZE; i++) {
351 struct gem_rxd *rxd = &gp->init_block->rxd[i];
353 if (gp->rx_skbs[i] == NULL) {
354 printk(KERN_ERR "%s: Parts of RX ring empty, resetting "
355 "whole chip.\n", dev->name);
359 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
361 gp->rx_new = gp->rx_old = 0;
363 /* Now we must reprogram the rest of RX unit. */
364 desc_dma = (u64) gp->gblock_dvma;
365 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
366 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
367 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
368 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
369 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
370 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
371 writel(val, gp->regs + RXDMA_CFG);
372 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
373 writel(((5 & RXDMA_BLANK_IPKTS) |
374 ((8 << 12) & RXDMA_BLANK_ITIME)),
375 gp->regs + RXDMA_BLANK);
377 writel(((5 & RXDMA_BLANK_IPKTS) |
378 ((4 << 12) & RXDMA_BLANK_ITIME)),
379 gp->regs + RXDMA_BLANK);
380 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
381 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
382 writel(val, gp->regs + RXDMA_PTHRESH);
383 val = readl(gp->regs + RXDMA_CFG);
384 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
385 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
386 val = readl(gp->regs + MAC_RXCFG);
387 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
392 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
394 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
397 if (netif_msg_intr(gp))
398 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
399 gp->dev->name, rxmac_stat);
401 if (rxmac_stat & MAC_RXSTAT_OFLW) {
402 u32 smac = readl(gp->regs + MAC_SMACHINE);
404 printk(KERN_ERR "%s: RX MAC fifo overflow smac[%08x].\n",
406 gp->net_stats.rx_over_errors++;
407 gp->net_stats.rx_fifo_errors++;
409 ret = gem_rxmac_reset(gp);
412 if (rxmac_stat & MAC_RXSTAT_ACE)
413 gp->net_stats.rx_frame_errors += 0x10000;
415 if (rxmac_stat & MAC_RXSTAT_CCE)
416 gp->net_stats.rx_crc_errors += 0x10000;
418 if (rxmac_stat & MAC_RXSTAT_LCE)
419 gp->net_stats.rx_length_errors += 0x10000;
421 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
427 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
429 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
431 if (netif_msg_intr(gp))
432 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
433 gp->dev->name, mac_cstat);
435 /* This interrupt is just for pause frame and pause
436 * tracking. It is useful for diagnostics and debug
437 * but probably by default we will mask these events.
439 if (mac_cstat & MAC_CSTAT_PS)
442 if (mac_cstat & MAC_CSTAT_PRCV)
443 gp->pause_last_time_recvd = (mac_cstat >> 16);
448 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
450 u32 mif_status = readl(gp->regs + MIF_STATUS);
451 u32 reg_val, changed_bits;
453 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
454 changed_bits = (mif_status & MIF_STATUS_STAT);
456 gem_handle_mif_event(gp, reg_val, changed_bits);
461 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
463 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
465 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
466 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
467 printk(KERN_ERR "%s: PCI error [%04x] ",
468 dev->name, pci_estat);
470 if (pci_estat & GREG_PCIESTAT_BADACK)
471 printk("<No ACK64# during ABS64 cycle> ");
472 if (pci_estat & GREG_PCIESTAT_DTRTO)
473 printk("<Delayed transaction timeout> ");
474 if (pci_estat & GREG_PCIESTAT_OTHER)
478 pci_estat |= GREG_PCIESTAT_OTHER;
479 printk(KERN_ERR "%s: PCI error\n", dev->name);
482 if (pci_estat & GREG_PCIESTAT_OTHER) {
485 /* Interrogate PCI config space for the
488 pci_read_config_word(gp->pdev, PCI_STATUS,
490 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
491 dev->name, pci_cfg_stat);
492 if (pci_cfg_stat & PCI_STATUS_PARITY)
493 printk(KERN_ERR "%s: PCI parity error detected.\n",
495 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
496 printk(KERN_ERR "%s: PCI target abort.\n",
498 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
499 printk(KERN_ERR "%s: PCI master acks target abort.\n",
501 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
502 printk(KERN_ERR "%s: PCI master abort.\n",
504 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
505 printk(KERN_ERR "%s: PCI system error SERR#.\n",
507 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
508 printk(KERN_ERR "%s: PCI parity error.\n",
511 /* Write the error bits back to clear them. */
512 pci_cfg_stat &= (PCI_STATUS_PARITY |
513 PCI_STATUS_SIG_TARGET_ABORT |
514 PCI_STATUS_REC_TARGET_ABORT |
515 PCI_STATUS_REC_MASTER_ABORT |
516 PCI_STATUS_SIG_SYSTEM_ERROR |
517 PCI_STATUS_DETECTED_PARITY);
518 pci_write_config_word(gp->pdev,
519 PCI_STATUS, pci_cfg_stat);
522 /* For all PCI errors, we should reset the chip. */
526 /* All non-normal interrupt conditions get serviced here.
527 * Returns non-zero if we should just exit the interrupt
528 * handler right now (ie. if we reset the card which invalidates
529 * all of the other original irq status bits).
531 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
533 if (gem_status & GREG_STAT_RXNOBUF) {
534 /* Frame arrived, no free RX buffers available. */
535 if (netif_msg_rx_err(gp))
536 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
538 gp->net_stats.rx_dropped++;
541 if (gem_status & GREG_STAT_RXTAGERR) {
542 /* corrupt RX tag framing */
543 if (netif_msg_rx_err(gp))
544 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
546 gp->net_stats.rx_errors++;
551 if (gem_status & GREG_STAT_PCS) {
552 if (gem_pcs_interrupt(dev, gp, gem_status))
556 if (gem_status & GREG_STAT_TXMAC) {
557 if (gem_txmac_interrupt(dev, gp, gem_status))
561 if (gem_status & GREG_STAT_RXMAC) {
562 if (gem_rxmac_interrupt(dev, gp, gem_status))
566 if (gem_status & GREG_STAT_MAC) {
567 if (gem_mac_interrupt(dev, gp, gem_status))
571 if (gem_status & GREG_STAT_MIF) {
572 if (gem_mif_interrupt(dev, gp, gem_status))
576 if (gem_status & GREG_STAT_PCIERR) {
577 if (gem_pci_interrupt(dev, gp, gem_status))
584 gp->reset_task_pending = 2;
585 schedule_work(&gp->reset_task);
590 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
594 if (netif_msg_intr(gp))
595 printk(KERN_DEBUG "%s: tx interrupt, gem_status: 0x%x\n",
596 gp->dev->name, gem_status);
599 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
600 while (entry != limit) {
607 if (netif_msg_tx_done(gp))
608 printk(KERN_DEBUG "%s: tx done, slot %d\n",
609 gp->dev->name, entry);
610 skb = gp->tx_skbs[entry];
611 if (skb_shinfo(skb)->nr_frags) {
612 int last = entry + skb_shinfo(skb)->nr_frags;
616 last &= (TX_RING_SIZE - 1);
618 walk = NEXT_TX(walk);
627 gp->tx_skbs[entry] = NULL;
628 gp->net_stats.tx_bytes += skb->len;
630 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
631 txd = &gp->init_block->txd[entry];
633 dma_addr = le64_to_cpu(txd->buffer);
634 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
636 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
637 entry = NEXT_TX(entry);
640 gp->net_stats.tx_packets++;
641 dev_kfree_skb_irq(skb);
645 if (netif_queue_stopped(dev) &&
646 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
647 netif_wake_queue(dev);
650 static __inline__ void gem_post_rxds(struct gem *gp, int limit)
652 int cluster_start, curr, count, kick;
654 cluster_start = curr = (gp->rx_new & ~(4 - 1));
658 while (curr != limit) {
659 curr = NEXT_RX(curr);
661 struct gem_rxd *rxd =
662 &gp->init_block->rxd[cluster_start];
664 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
666 cluster_start = NEXT_RX(cluster_start);
667 if (cluster_start == curr)
676 writel(kick, gp->regs + RXDMA_KICK);
680 static void gem_rx(struct gem *gp)
685 if (netif_msg_intr(gp))
686 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
687 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
691 done = readl(gp->regs + RXDMA_DONE);
693 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
695 u64 status = cpu_to_le64(rxd->status_word);
699 if ((status & RXDCTRL_OWN) != 0)
702 /* When writing back RX descriptor, GEM writes status
703 * then buffer address, possibly in seperate transactions.
704 * If we don't wait for the chip to write both, we could
705 * post a new buffer to this descriptor then have GEM spam
706 * on the buffer address. We sync on the RX completion
707 * register to prevent this from happening.
710 done = readl(gp->regs + RXDMA_DONE);
715 skb = gp->rx_skbs[entry];
717 len = (status & RXDCTRL_BUFSZ) >> 16;
718 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
719 gp->net_stats.rx_errors++;
721 gp->net_stats.rx_length_errors++;
722 if (len & RXDCTRL_BAD)
723 gp->net_stats.rx_crc_errors++;
725 /* We'll just return it to GEM. */
727 gp->net_stats.rx_dropped++;
731 dma_addr = cpu_to_le64(rxd->buffer);
732 if (len > RX_COPY_THRESHOLD) {
733 struct sk_buff *new_skb;
735 new_skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
736 if (new_skb == NULL) {
740 pci_unmap_page(gp->pdev, dma_addr,
741 RX_BUF_ALLOC_SIZE(gp),
743 gp->rx_skbs[entry] = new_skb;
744 new_skb->dev = gp->dev;
745 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET));
746 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
747 virt_to_page(new_skb->data),
748 offset_in_page(new_skb->data),
749 RX_BUF_ALLOC_SIZE(gp),
750 PCI_DMA_FROMDEVICE));
751 skb_reserve(new_skb, RX_OFFSET);
753 /* Trim the original skb for the netif. */
756 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
758 if (copy_skb == NULL) {
763 copy_skb->dev = gp->dev;
764 skb_reserve(copy_skb, 2);
765 skb_put(copy_skb, len);
766 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
767 memcpy(copy_skb->data, skb->data, len);
768 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
770 /* We'll reuse the original ring buffer. */
774 skb->csum = ntohs((status & RXDCTRL_TCPCSUM) ^ 0xffff);
775 skb->ip_summed = CHECKSUM_HW;
776 skb->protocol = eth_type_trans(skb, gp->dev);
779 gp->net_stats.rx_packets++;
780 gp->net_stats.rx_bytes += len;
781 gp->dev->last_rx = jiffies;
784 entry = NEXT_RX(entry);
787 gem_post_rxds(gp, entry);
792 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
796 static irqreturn_t gem_interrupt(int irq, void *dev_id, struct pt_regs *regs)
798 struct net_device *dev = dev_id;
799 struct gem *gp = dev->priv;
800 u32 gem_status = readl(gp->regs + GREG_STAT);
802 /* Swallow interrupts when shutting the chip down */
803 if (gp->hw_running == 0)
806 spin_lock(&gp->lock);
808 if (gem_status & GREG_STAT_ABNORMAL) {
809 if (gem_abnormal_irq(dev, gp, gem_status))
812 if (gem_status & (GREG_STAT_TXALL | GREG_STAT_TXINTME))
813 gem_tx(dev, gp, gem_status);
814 if (gem_status & GREG_STAT_RXDONE)
818 spin_unlock(&gp->lock);
823 static void gem_tx_timeout(struct net_device *dev)
825 struct gem *gp = dev->priv;
827 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
828 if (!gp->hw_running) {
829 printk("%s: hrm.. hw not running !\n", dev->name);
832 printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x]\n",
834 readl(gp->regs + TXDMA_CFG),
835 readl(gp->regs + MAC_TXSTAT),
836 readl(gp->regs + MAC_TXCFG));
837 printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
839 readl(gp->regs + RXDMA_CFG),
840 readl(gp->regs + MAC_RXSTAT),
841 readl(gp->regs + MAC_RXCFG));
843 spin_lock_irq(&gp->lock);
845 gp->reset_task_pending = 2;
846 schedule_work(&gp->reset_task);
848 spin_unlock_irq(&gp->lock);
851 static __inline__ int gem_intme(int entry)
853 /* Algorithm: IRQ every 1/2 of descriptors. */
854 if (!(entry & ((TX_RING_SIZE>>1)-1)))
860 static int gem_start_xmit(struct sk_buff *skb, struct net_device *dev)
862 struct gem *gp = dev->priv;
867 if (skb->ip_summed == CHECKSUM_HW) {
868 u64 csum_start_off, csum_stuff_off;
870 csum_start_off = (u64) (skb->h.raw - skb->data);
871 csum_stuff_off = (u64) ((skb->h.raw + skb->csum) - skb->data);
873 ctrl = (TXDCTRL_CENAB |
874 (csum_start_off << 15) |
875 (csum_stuff_off << 21));
878 spin_lock_irq(&gp->lock);
880 /* This is a hard error, log it. */
881 if (TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1)) {
882 netif_stop_queue(dev);
883 spin_unlock_irq(&gp->lock);
884 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
890 gp->tx_skbs[entry] = skb;
892 if (skb_shinfo(skb)->nr_frags == 0) {
893 struct gem_txd *txd = &gp->init_block->txd[entry];
898 mapping = pci_map_page(gp->pdev,
899 virt_to_page(skb->data),
900 offset_in_page(skb->data),
901 len, PCI_DMA_TODEVICE);
902 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
903 if (gem_intme(entry))
904 ctrl |= TXDCTRL_INTME;
905 txd->buffer = cpu_to_le64(mapping);
907 txd->control_word = cpu_to_le64(ctrl);
908 entry = NEXT_TX(entry);
913 dma_addr_t first_mapping;
914 int frag, first_entry = entry;
917 if (gem_intme(entry))
918 intme |= TXDCTRL_INTME;
920 /* We must give this initial chunk to the device last.
921 * Otherwise we could race with the device.
923 first_len = skb_headlen(skb);
924 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
925 offset_in_page(skb->data),
926 first_len, PCI_DMA_TODEVICE);
927 entry = NEXT_TX(entry);
929 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
930 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
935 len = this_frag->size;
936 mapping = pci_map_page(gp->pdev,
938 this_frag->page_offset,
939 len, PCI_DMA_TODEVICE);
941 if (frag == skb_shinfo(skb)->nr_frags - 1)
942 this_ctrl |= TXDCTRL_EOF;
944 txd = &gp->init_block->txd[entry];
945 txd->buffer = cpu_to_le64(mapping);
947 txd->control_word = cpu_to_le64(this_ctrl | len);
949 if (gem_intme(entry))
950 intme |= TXDCTRL_INTME;
952 entry = NEXT_TX(entry);
954 txd = &gp->init_block->txd[first_entry];
955 txd->buffer = cpu_to_le64(first_mapping);
958 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
962 if (TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))
963 netif_stop_queue(dev);
965 if (netif_msg_tx_queued(gp))
966 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
967 dev->name, entry, skb->len);
969 writel(gp->tx_new, gp->regs + TXDMA_KICK);
970 spin_unlock_irq(&gp->lock);
972 dev->trans_start = jiffies;
977 /* Jumbo-grams don't seem to work :-( */
978 #define GEM_MIN_MTU 68
980 #define GEM_MAX_MTU 1500
982 #define GEM_MAX_MTU 9000
985 static int gem_change_mtu(struct net_device *dev, int new_mtu)
987 struct gem *gp = dev->priv;
989 if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
992 if (!netif_running(dev) || !netif_device_present(dev)) {
993 /* We'll just catch it later when the
994 * device is up'd or resumed.
1000 spin_lock_irq(&gp->lock);
1002 gp->reset_task_pending = 1;
1003 schedule_work(&gp->reset_task);
1004 spin_unlock_irq(&gp->lock);
1006 flush_scheduled_work();
1011 #define STOP_TRIES 32
1013 /* Must be invoked under gp->lock. */
1014 static void gem_stop(struct gem *gp)
1019 /* Make sure we won't get any more interrupts */
1020 writel(0xffffffff, gp->regs + GREG_IMASK);
1022 /* Reset the chip */
1023 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1024 gp->regs + GREG_SWRST);
1030 val = readl(gp->regs + GREG_SWRST);
1033 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1036 printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name);
1039 /* Must be invoked under gp->lock. */
1040 static void gem_start_dma(struct gem *gp)
1044 /* We are ready to rock, turn everything on. */
1045 val = readl(gp->regs + TXDMA_CFG);
1046 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1047 val = readl(gp->regs + RXDMA_CFG);
1048 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1049 val = readl(gp->regs + MAC_TXCFG);
1050 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1051 val = readl(gp->regs + MAC_RXCFG);
1052 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1054 (void) readl(gp->regs + MAC_RXCFG);
1057 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
1059 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1064 /* Must be invoked under gp->lock. */
1065 // XXX dbl check what that function should do when called on PCS PHY
1066 static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
1068 u32 advertise, features;
1073 if (gp->phy_type != phy_mii_mdio0 &&
1074 gp->phy_type != phy_mii_mdio1)
1077 /* Setup advertise */
1078 if (found_mii_phy(gp))
1079 features = gp->phy_mii.def->features;
1083 advertise = features & ADVERTISE_MASK;
1084 if (gp->phy_mii.advertising != 0)
1085 advertise &= gp->phy_mii.advertising;
1087 autoneg = gp->want_autoneg;
1088 speed = gp->phy_mii.speed;
1089 duplex = gp->phy_mii.duplex;
1091 /* Setup link parameters */
1094 if (ep->autoneg == AUTONEG_ENABLE) {
1095 advertise = ep->advertising;
1100 duplex = ep->duplex;
1104 /* Sanitize settings based on PHY capabilities */
1105 if ((features & SUPPORTED_Autoneg) == 0)
1107 if (speed == SPEED_1000 &&
1108 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1110 if (speed == SPEED_100 &&
1111 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1113 if (duplex == DUPLEX_FULL &&
1114 !(features & (SUPPORTED_1000baseT_Full |
1115 SUPPORTED_100baseT_Full |
1116 SUPPORTED_10baseT_Full)))
1117 duplex = DUPLEX_HALF;
1121 /* If HW is down, we don't try to actually setup the PHY, we
1122 * just store the settings
1124 if (!gp->hw_running) {
1125 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1126 gp->phy_mii.speed = speed;
1127 gp->phy_mii.duplex = duplex;
1131 /* Configure PHY & start aneg */
1132 gp->want_autoneg = autoneg;
1134 if (found_mii_phy(gp))
1135 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1136 gp->lstate = link_aneg;
1138 if (found_mii_phy(gp))
1139 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1140 gp->lstate = link_force_ok;
1144 gp->timer_ticks = 0;
1145 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1148 /* A link-up condition has occurred, initialize and enable the
1151 * Must be invoked under gp->lock.
1153 static int gem_set_link_modes(struct gem *gp)
1156 int full_duplex, speed, pause;
1162 if (found_mii_phy(gp)) {
1163 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1165 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1166 speed = gp->phy_mii.speed;
1167 pause = gp->phy_mii.pause;
1168 } else if (gp->phy_type == phy_serialink ||
1169 gp->phy_type == phy_serdes) {
1170 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1172 if (pcs_lpa & PCS_MIIADV_FD)
1177 if (netif_msg_link(gp))
1178 printk(KERN_INFO "%s: Link is up at %d Mbps, %s-duplex.\n",
1179 gp->dev->name, speed, (full_duplex ? "full" : "half"));
1181 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1183 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1185 /* MAC_TXCFG_NBO must be zero. */
1187 writel(val, gp->regs + MAC_TXCFG);
1189 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1191 (gp->phy_type == phy_mii_mdio0 ||
1192 gp->phy_type == phy_mii_mdio1)) {
1193 val |= MAC_XIFCFG_DISE;
1194 } else if (full_duplex) {
1195 val |= MAC_XIFCFG_FLED;
1198 if (speed == SPEED_1000)
1199 val |= (MAC_XIFCFG_GMII);
1201 writel(val, gp->regs + MAC_XIFCFG);
1203 /* If gigabit and half-duplex, enable carrier extension
1204 * mode. Else, disable it.
1206 if (speed == SPEED_1000 && !full_duplex) {
1207 val = readl(gp->regs + MAC_TXCFG);
1208 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1210 val = readl(gp->regs + MAC_RXCFG);
1211 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1213 val = readl(gp->regs + MAC_TXCFG);
1214 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1216 val = readl(gp->regs + MAC_RXCFG);
1217 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1220 if (gp->phy_type == phy_serialink ||
1221 gp->phy_type == phy_serdes) {
1222 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1224 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1228 if (netif_msg_link(gp)) {
1230 printk(KERN_INFO "%s: Pause is enabled "
1231 "(rxfifo: %d off: %d on: %d)\n",
1237 printk(KERN_INFO "%s: Pause is disabled\n",
1243 writel(512, gp->regs + MAC_STIME);
1245 writel(64, gp->regs + MAC_STIME);
1246 val = readl(gp->regs + MAC_MCCFG);
1248 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1250 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1251 writel(val, gp->regs + MAC_MCCFG);
1258 /* Must be invoked under gp->lock. */
1259 static int gem_mdio_link_not_up(struct gem *gp)
1261 switch (gp->lstate) {
1262 case link_force_ret:
1263 if (netif_msg_link(gp))
1264 printk(KERN_INFO "%s: Autoneg failed again, keeping"
1265 " forced mode\n", gp->dev->name);
1266 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1267 gp->last_forced_speed, DUPLEX_HALF);
1268 gp->timer_ticks = 5;
1269 gp->lstate = link_force_ok;
1272 /* We try forced modes after a failed aneg only on PHYs that don't
1273 * have "magic_aneg" bit set, which means they internally do the
1274 * while forced-mode thingy. On these, we just restart aneg
1276 if (gp->phy_mii.def->magic_aneg)
1278 if (netif_msg_link(gp))
1279 printk(KERN_INFO "%s: switching to forced 100bt\n",
1281 /* Try forced modes. */
1282 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1284 gp->timer_ticks = 5;
1285 gp->lstate = link_force_try;
1287 case link_force_try:
1288 /* Downgrade from 100 to 10 Mbps if necessary.
1289 * If already at 10Mbps, warn user about the
1290 * situation every 10 ticks.
1292 if (gp->phy_mii.speed == SPEED_100) {
1293 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1295 gp->timer_ticks = 5;
1296 if (netif_msg_link(gp))
1297 printk(KERN_INFO "%s: switching to forced 10bt\n",
1307 static void gem_init_rings(struct gem *);
1308 static void gem_init_hw(struct gem *, int);
1310 static void gem_reset_task(void *data)
1312 struct gem *gp = (struct gem *) data;
1314 /* The link went down, we reset the ring, but keep
1315 * DMA stopped. Todo: Use this function for reset
1319 spin_lock_irq(&gp->lock);
1321 if (gp->hw_running && gp->opened) {
1322 /* Make sure we don't get interrupts or tx packets */
1323 netif_stop_queue(gp->dev);
1325 writel(0xffffffff, gp->regs + GREG_IMASK);
1327 /* Reset the chip & rings */
1332 (gp->reset_task_pending == 2));
1334 netif_wake_queue(gp->dev);
1336 gp->reset_task_pending = 0;
1338 spin_unlock_irq(&gp->lock);
1341 static void gem_link_timer(unsigned long data)
1343 struct gem *gp = (struct gem *) data;
1344 int restart_aneg = 0;
1346 if (!gp->hw_running)
1349 spin_lock_irq(&gp->lock);
1351 /* If the link of task is still pending, we just
1352 * reschedule the link timer
1354 if (gp->reset_task_pending)
1357 if (gp->phy_type == phy_serialink ||
1358 gp->phy_type == phy_serdes) {
1359 u32 val = readl(gp->regs + PCS_MIISTAT);
1361 if (!(val & PCS_MIISTAT_LS))
1362 val = readl(gp->regs + PCS_MIISTAT);
1364 if ((val & PCS_MIISTAT_LS) != 0) {
1365 gp->lstate = link_up;
1366 netif_carrier_on(gp->dev);
1368 (void)gem_set_link_modes(gp);
1372 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1373 /* Ok, here we got a link. If we had it due to a forced
1374 * fallback, and we were configured for autoneg, we do
1375 * retry a short autoneg pass. If you know your hub is
1376 * broken, use ethtool ;)
1378 if (gp->lstate == link_force_try && gp->want_autoneg) {
1379 gp->lstate = link_force_ret;
1380 gp->last_forced_speed = gp->phy_mii.speed;
1381 gp->timer_ticks = 5;
1382 if (netif_msg_link(gp))
1383 printk(KERN_INFO "%s: Got link after fallback, retrying"
1384 " autoneg once...\n", gp->dev->name);
1385 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1386 } else if (gp->lstate != link_up) {
1387 gp->lstate = link_up;
1388 netif_carrier_on(gp->dev);
1389 if (gp->opened && gem_set_link_modes(gp))
1393 /* If the link was previously up, we restart the
1396 if (gp->lstate == link_up) {
1397 gp->lstate = link_down;
1398 if (netif_msg_link(gp))
1399 printk(KERN_INFO "%s: Link down\n",
1401 netif_carrier_off(gp->dev);
1402 gp->reset_task_pending = 2;
1403 schedule_work(&gp->reset_task);
1405 } else if (++gp->timer_ticks > 10) {
1406 if (found_mii_phy(gp))
1407 restart_aneg = gem_mdio_link_not_up(gp);
1413 gem_begin_auto_negotiation(gp, NULL);
1417 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1419 spin_unlock_irq(&gp->lock);
1422 /* Must be invoked under gp->lock. */
1423 static void gem_clean_rings(struct gem *gp)
1425 struct gem_init_block *gb = gp->init_block;
1426 struct sk_buff *skb;
1428 dma_addr_t dma_addr;
1430 for (i = 0; i < RX_RING_SIZE; i++) {
1431 struct gem_rxd *rxd;
1434 if (gp->rx_skbs[i] != NULL) {
1435 skb = gp->rx_skbs[i];
1436 dma_addr = le64_to_cpu(rxd->buffer);
1437 pci_unmap_page(gp->pdev, dma_addr,
1438 RX_BUF_ALLOC_SIZE(gp),
1439 PCI_DMA_FROMDEVICE);
1440 dev_kfree_skb_any(skb);
1441 gp->rx_skbs[i] = NULL;
1443 rxd->status_word = 0;
1448 for (i = 0; i < TX_RING_SIZE; i++) {
1449 if (gp->tx_skbs[i] != NULL) {
1450 struct gem_txd *txd;
1453 skb = gp->tx_skbs[i];
1454 gp->tx_skbs[i] = NULL;
1456 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1457 int ent = i & (TX_RING_SIZE - 1);
1459 txd = &gb->txd[ent];
1460 dma_addr = le64_to_cpu(txd->buffer);
1461 pci_unmap_page(gp->pdev, dma_addr,
1462 le64_to_cpu(txd->control_word) &
1463 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1465 if (frag != skb_shinfo(skb)->nr_frags)
1468 dev_kfree_skb_any(skb);
1473 /* Must be invoked under gp->lock. */
1474 static void gem_init_rings(struct gem *gp)
1476 struct gem_init_block *gb = gp->init_block;
1477 struct net_device *dev = gp->dev;
1479 dma_addr_t dma_addr;
1481 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1483 gem_clean_rings(gp);
1485 for (i = 0; i < RX_RING_SIZE; i++) {
1486 struct sk_buff *skb;
1487 struct gem_rxd *rxd = &gb->rxd[i];
1489 skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
1492 rxd->status_word = 0;
1496 gp->rx_skbs[i] = skb;
1498 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET));
1499 dma_addr = pci_map_page(gp->pdev,
1500 virt_to_page(skb->data),
1501 offset_in_page(skb->data),
1502 RX_BUF_ALLOC_SIZE(gp),
1503 PCI_DMA_FROMDEVICE);
1504 rxd->buffer = cpu_to_le64(dma_addr);
1506 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1507 skb_reserve(skb, RX_OFFSET);
1510 for (i = 0; i < TX_RING_SIZE; i++) {
1511 struct gem_txd *txd = &gb->txd[i];
1513 txd->control_word = 0;
1520 /* Must be invoked under gp->lock. */
1521 static void gem_init_phy(struct gem *gp)
1525 /* Revert MIF CFG setting done on stop_phy */
1526 mifcfg = readl(gp->regs + MIF_CFG);
1527 mifcfg &= ~MIF_CFG_BBMODE;
1528 writel(mifcfg, gp->regs + MIF_CFG);
1530 #ifdef CONFIG_PPC_PMAC
1531 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1534 /* Those delay sucks, the HW seem to love them though, I'll
1535 * serisouly consider breaking some locks here to be able
1536 * to schedule instead
1538 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1539 for (j = 0; j < 3; j++) {
1540 /* Some PHYs used by apple have problem getting back to us,
1541 * we _know_ it's actually at addr 0 or 1, that's a hack, but
1542 * it helps to do that reset now. I suspect some motherboards
1543 * don't wire the PHY reset line properly, thus the PHY doesn't
1544 * come back with the above pmac_call_feature.
1546 gp->mii_phy_addr = 0;
1547 phy_write(gp, MII_BMCR, BMCR_RESET);
1548 gp->mii_phy_addr = 1;
1549 phy_write(gp, MII_BMCR, BMCR_RESET);
1550 /* We should probably break some locks here and schedule... */
1553 /* On K2, we only probe the internal PHY at address 1, other
1554 * addresses tend to return garbage.
1556 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
1559 for (i = 0; i < 32; i++) {
1560 gp->mii_phy_addr = i;
1561 if (phy_read(gp, MII_BMCR) != 0xffff)
1565 printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
1567 gp->mii_phy_addr = 0;
1572 #endif /* CONFIG_PPC_PMAC */
1574 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1575 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1578 /* Init datapath mode register. */
1579 if (gp->phy_type == phy_mii_mdio0 ||
1580 gp->phy_type == phy_mii_mdio1) {
1581 val = PCS_DMODE_MGM;
1582 } else if (gp->phy_type == phy_serialink) {
1583 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1585 val = PCS_DMODE_ESM;
1588 writel(val, gp->regs + PCS_DMODE);
1591 if (gp->phy_type == phy_mii_mdio0 ||
1592 gp->phy_type == phy_mii_mdio1) {
1593 // XXX check for errors
1594 mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1597 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1598 gp->phy_mii.def->ops->init(&gp->phy_mii);
1603 /* Reset PCS unit. */
1604 val = readl(gp->regs + PCS_MIICTRL);
1605 val |= PCS_MIICTRL_RST;
1606 writeb(val, gp->regs + PCS_MIICTRL);
1609 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1615 printk(KERN_WARNING "%s: PCS reset bit would not clear.\n",
1618 /* Make sure PCS is disabled while changing advertisement
1621 val = readl(gp->regs + PCS_CFG);
1622 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1623 writel(val, gp->regs + PCS_CFG);
1625 /* Advertise all capabilities except assymetric
1628 val = readl(gp->regs + PCS_MIIADV);
1629 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1630 PCS_MIIADV_SP | PCS_MIIADV_AP);
1631 writel(val, gp->regs + PCS_MIIADV);
1633 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1634 * and re-enable PCS.
1636 val = readl(gp->regs + PCS_MIICTRL);
1637 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1638 val &= ~PCS_MIICTRL_WB;
1639 writel(val, gp->regs + PCS_MIICTRL);
1641 val = readl(gp->regs + PCS_CFG);
1642 val |= PCS_CFG_ENABLE;
1643 writel(val, gp->regs + PCS_CFG);
1645 /* Make sure serialink loopback is off. The meaning
1646 * of this bit is logically inverted based upon whether
1647 * you are in Serialink or SERDES mode.
1649 val = readl(gp->regs + PCS_SCTRL);
1650 if (gp->phy_type == phy_serialink)
1651 val &= ~PCS_SCTRL_LOOP;
1653 val |= PCS_SCTRL_LOOP;
1654 writel(val, gp->regs + PCS_SCTRL);
1658 /* Must be invoked under gp->lock. */
1659 static void gem_init_dma(struct gem *gp)
1661 u64 desc_dma = (u64) gp->gblock_dvma;
1664 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1665 writel(val, gp->regs + TXDMA_CFG);
1667 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1668 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1669 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1671 writel(0, gp->regs + TXDMA_KICK);
1673 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1674 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1675 writel(val, gp->regs + RXDMA_CFG);
1677 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1678 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1680 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1682 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1683 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1684 writel(val, gp->regs + RXDMA_PTHRESH);
1686 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1687 writel(((5 & RXDMA_BLANK_IPKTS) |
1688 ((8 << 12) & RXDMA_BLANK_ITIME)),
1689 gp->regs + RXDMA_BLANK);
1691 writel(((5 & RXDMA_BLANK_IPKTS) |
1692 ((4 << 12) & RXDMA_BLANK_ITIME)),
1693 gp->regs + RXDMA_BLANK);
1696 /* Must be invoked under gp->lock. */
1698 gem_setup_multicast(struct gem *gp)
1703 if ((gp->dev->flags & IFF_ALLMULTI) ||
1704 (gp->dev->mc_count > 256)) {
1705 for (i=0; i<16; i++)
1706 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1707 rxcfg |= MAC_RXCFG_HFE;
1708 } else if (gp->dev->flags & IFF_PROMISC) {
1709 rxcfg |= MAC_RXCFG_PROM;
1713 struct dev_mc_list *dmi = gp->dev->mc_list;
1716 for (i = 0; i < 16; i++)
1719 for (i = 0; i < gp->dev->mc_count; i++) {
1720 char *addrs = dmi->dmi_addr;
1727 crc = ether_crc_le(6, addrs);
1729 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1731 for (i=0; i<16; i++)
1732 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1733 rxcfg |= MAC_RXCFG_HFE;
1739 /* Must be invoked under gp->lock. */
1740 static void gem_init_mac(struct gem *gp)
1742 unsigned char *e = &gp->dev->dev_addr[0];
1744 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1746 writel(0x00, gp->regs + MAC_IPG0);
1747 writel(0x08, gp->regs + MAC_IPG1);
1748 writel(0x04, gp->regs + MAC_IPG2);
1749 writel(0x40, gp->regs + MAC_STIME);
1750 writel(0x40, gp->regs + MAC_MINFSZ);
1752 /* Ethernet payload + header + FCS + optional VLAN tag. */
1753 writel(0x20000000 | (gp->dev->mtu + ETH_HLEN + 4 + 4), gp->regs + MAC_MAXFSZ);
1755 writel(0x07, gp->regs + MAC_PASIZE);
1756 writel(0x04, gp->regs + MAC_JAMSIZE);
1757 writel(0x10, gp->regs + MAC_ATTLIM);
1758 writel(0x8808, gp->regs + MAC_MCTYPE);
1760 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1762 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1763 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1764 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1766 writel(0, gp->regs + MAC_ADDR3);
1767 writel(0, gp->regs + MAC_ADDR4);
1768 writel(0, gp->regs + MAC_ADDR5);
1770 writel(0x0001, gp->regs + MAC_ADDR6);
1771 writel(0xc200, gp->regs + MAC_ADDR7);
1772 writel(0x0180, gp->regs + MAC_ADDR8);
1774 writel(0, gp->regs + MAC_AFILT0);
1775 writel(0, gp->regs + MAC_AFILT1);
1776 writel(0, gp->regs + MAC_AFILT2);
1777 writel(0, gp->regs + MAC_AF21MSK);
1778 writel(0, gp->regs + MAC_AF0MSK);
1780 gp->mac_rx_cfg = gem_setup_multicast(gp);
1782 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1784 writel(0, gp->regs + MAC_NCOLL);
1785 writel(0, gp->regs + MAC_FASUCC);
1786 writel(0, gp->regs + MAC_ECOLL);
1787 writel(0, gp->regs + MAC_LCOLL);
1788 writel(0, gp->regs + MAC_DTIMER);
1789 writel(0, gp->regs + MAC_PATMPS);
1790 writel(0, gp->regs + MAC_RFCTR);
1791 writel(0, gp->regs + MAC_LERR);
1792 writel(0, gp->regs + MAC_AERR);
1793 writel(0, gp->regs + MAC_FCSERR);
1794 writel(0, gp->regs + MAC_RXCVERR);
1796 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1797 * them once a link is established.
1799 writel(0, gp->regs + MAC_TXCFG);
1800 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1801 writel(0, gp->regs + MAC_MCCFG);
1802 writel(0, gp->regs + MAC_XIFCFG);
1804 /* Setup MAC interrupts. We want to get all of the interesting
1805 * counter expiration events, but we do not want to hear about
1806 * normal rx/tx as the DMA engine tells us that.
1808 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1809 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1811 /* Don't enable even the PAUSE interrupts for now, we
1812 * make no use of those events other than to record them.
1814 writel(0xffffffff, gp->regs + MAC_MCMASK);
1817 /* Must be invoked under gp->lock. */
1818 static void gem_init_pause_thresholds(struct gem *gp)
1822 /* Calculate pause thresholds. Setting the OFF threshold to the
1823 * full RX fifo size effectively disables PAUSE generation which
1824 * is what we do for 10/100 only GEMs which have FIFOs too small
1825 * to make real gains from PAUSE.
1827 if (gp->rx_fifo_sz <= (2 * 1024)) {
1828 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1830 int max_frame = (gp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63;
1831 int off = (gp->rx_fifo_sz - (max_frame * 2));
1832 int on = off - max_frame;
1834 gp->rx_pause_off = off;
1835 gp->rx_pause_on = on;
1839 /* Configure the chip "burst" DMA mode & enable some
1840 * HW bug fixes on Apple version
1843 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1844 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1845 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1846 cfg |= GREG_CFG_IBURST;
1848 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1849 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1850 writel(cfg, gp->regs + GREG_CFG);
1852 /* If Infinite Burst didn't stick, then use different
1853 * thresholds (and Apple bug fixes don't exist)
1855 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1856 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1857 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1858 writel(cfg, gp->regs + GREG_CFG);
1862 static int gem_check_invariants(struct gem *gp)
1864 struct pci_dev *pdev = gp->pdev;
1867 /* On Apple's sungem, we can't rely on registers as the chip
1868 * was been powered down by the firmware. The PHY is looked
1871 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1872 gp->phy_type = phy_mii_mdio0;
1873 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1874 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1879 mif_cfg = readl(gp->regs + MIF_CFG);
1881 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
1882 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
1883 /* One of the MII PHYs _must_ be present
1884 * as this chip has no gigabit PHY.
1886 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
1887 printk(KERN_ERR PFX "RIO GEM lacks MII phy, mif_cfg[%08x]\n",
1893 /* Determine initial PHY interface type guess. MDIO1 is the
1894 * external PHY and thus takes precedence over MDIO0.
1897 if (mif_cfg & MIF_CFG_MDI1) {
1898 gp->phy_type = phy_mii_mdio1;
1899 mif_cfg |= MIF_CFG_PSELECT;
1900 writel(mif_cfg, gp->regs + MIF_CFG);
1901 } else if (mif_cfg & MIF_CFG_MDI0) {
1902 gp->phy_type = phy_mii_mdio0;
1903 mif_cfg &= ~MIF_CFG_PSELECT;
1904 writel(mif_cfg, gp->regs + MIF_CFG);
1906 gp->phy_type = phy_serialink;
1908 if (gp->phy_type == phy_mii_mdio1 ||
1909 gp->phy_type == phy_mii_mdio0) {
1912 for (i = 0; i < 32; i++) {
1913 gp->mii_phy_addr = i;
1914 if (phy_read(gp, MII_BMCR) != 0xffff)
1918 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
1919 printk(KERN_ERR PFX "RIO MII phy will not respond.\n");
1922 gp->phy_type = phy_serdes;
1926 /* Fetch the FIFO configurations now too. */
1927 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1928 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1930 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
1931 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1932 if (gp->tx_fifo_sz != (9 * 1024) ||
1933 gp->rx_fifo_sz != (20 * 1024)) {
1934 printk(KERN_ERR PFX "GEM has bogus fifo sizes tx(%d) rx(%d)\n",
1935 gp->tx_fifo_sz, gp->rx_fifo_sz);
1940 if (gp->tx_fifo_sz != (2 * 1024) ||
1941 gp->rx_fifo_sz != (2 * 1024)) {
1942 printk(KERN_ERR PFX "RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
1943 gp->tx_fifo_sz, gp->rx_fifo_sz);
1946 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
1953 /* Must be invoked under gp->lock. */
1954 static void gem_init_hw(struct gem *gp, int restart_link)
1956 /* On Apple's gmac, I initialize the PHY only after
1957 * setting up the chip. It appears the gigabit PHYs
1958 * don't quite like beeing talked to on the GII when
1959 * the chip is not running, I suspect it might not
1960 * be clocked at that point. --BenH
1964 gem_init_pause_thresholds(gp);
1969 /* Default aneg parameters */
1970 gp->timer_ticks = 0;
1971 gp->lstate = link_down;
1972 netif_carrier_off(gp->dev);
1974 /* Can I advertise gigabit here ? I'd need BCM PHY docs... */
1975 gem_begin_auto_negotiation(gp, NULL);
1977 if (gp->lstate == link_up) {
1978 netif_carrier_on(gp->dev);
1979 gem_set_link_modes(gp);
1984 #ifdef CONFIG_PPC_PMAC
1985 /* Enable the chip's clock and make sure it's config space is
1986 * setup properly. There appear to be no need to restore the
1989 static void gem_apple_powerup(struct gem *gp)
1994 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
1998 mif_cfg = readl(gp->regs + MIF_CFG);
1999 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
2000 mif_cfg |= MIF_CFG_MDI0;
2001 writel(mif_cfg, gp->regs + MIF_CFG);
2002 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
2003 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
2006 /* Turn off the chip's clock */
2007 static void gem_apple_powerdown(struct gem *gp)
2009 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
2012 #endif /* CONFIG_PPC_PMAC */
2014 /* Must be invoked with no lock held. */
2015 static void gem_stop_phy(struct gem *gp)
2018 unsigned long flags;
2020 /* Let the chip settle down a bit, it seems that helps
2021 * for sleep mode on some models
2023 set_current_state(TASK_UNINTERRUPTIBLE);
2024 schedule_timeout(HZ/100);
2026 /* Make sure we aren't polling PHY status change. We
2027 * don't currently use that feature though
2029 mifcfg = readl(gp->regs + MIF_CFG);
2030 mifcfg &= ~MIF_CFG_POLL;
2031 writel(mifcfg, gp->regs + MIF_CFG);
2033 if (gp->wake_on_lan) {
2034 /* Setup wake-on-lan */
2036 writel(0, gp->regs + MAC_RXCFG);
2037 (void)readl(gp->regs + MAC_RXCFG);
2038 /* Machine sleep will die in strange ways if we
2039 * dont wait a bit here, looks like the chip takes
2040 * some time to really shut down
2042 set_current_state(TASK_UNINTERRUPTIBLE);
2043 schedule_timeout(HZ/100);
2046 writel(0, gp->regs + MAC_TXCFG);
2047 writel(0, gp->regs + MAC_XIFCFG);
2048 writel(0, gp->regs + TXDMA_CFG);
2049 writel(0, gp->regs + RXDMA_CFG);
2051 if (!gp->wake_on_lan) {
2052 spin_lock_irqsave(&gp->lock, flags);
2054 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2055 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2056 spin_unlock_irqrestore(&gp->lock, flags);
2059 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2060 gp->phy_mii.def->ops->suspend(&gp->phy_mii, 0 /* wake on lan options */);
2062 if (!gp->wake_on_lan) {
2063 /* According to Apple, we must set the MDIO pins to this begnign
2064 * state or we may 1) eat more current, 2) damage some PHYs
2066 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2067 writel(0, gp->regs + MIF_BBCLK);
2068 writel(0, gp->regs + MIF_BBDATA);
2069 writel(0, gp->regs + MIF_BBOENAB);
2070 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2071 (void) readl(gp->regs + MAC_XIFCFG);
2075 /* Shut down the chip, must be called with pm_sem held. */
2076 static void gem_shutdown(struct gem *gp)
2078 /* Make us not-running to avoid timers respawning
2084 /* Stop the link timer */
2085 del_timer_sync(&gp->link_timer);
2087 /* Stop the reset task */
2088 while (gp->reset_task_pending)
2091 /* Actually stop the chip */
2092 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
2095 #ifdef CONFIG_PPC_PMAC
2096 /* Power down the chip */
2097 gem_apple_powerdown(gp);
2098 #endif /* CONFIG_PPC_PMAC */
2100 unsigned long flags;
2102 spin_lock_irqsave(&gp->lock, flags);
2104 spin_unlock_irqrestore(&gp->lock, flags);
2108 static void gem_pm_task(void *data)
2110 struct gem *gp = (struct gem *) data;
2112 /* We assume if we can't lock the pm_sem, then open() was
2113 * called again (or suspend()), and we can safely ignore
2116 if (down_trylock(&gp->pm_sem))
2119 /* Driver was re-opened or already shut down */
2120 if (gp->opened || !gp->hw_running) {
2130 static void gem_pm_timer(unsigned long data)
2132 struct gem *gp = (struct gem *) data;
2134 schedule_work(&gp->pm_task);
2137 static int gem_open(struct net_device *dev)
2139 struct gem *gp = dev->priv;
2144 hw_was_up = gp->hw_running;
2146 /* Stop the PM timer/task */
2147 del_timer(&gp->pm_timer);
2148 flush_scheduled_work();
2150 /* The power-management semaphore protects the hw_running
2151 * etc. state so it is safe to do this bit without gp->lock
2153 if (!gp->hw_running) {
2154 #ifdef CONFIG_PPC_PMAC
2155 /* First, we need to bring up the chip */
2156 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
2157 gem_apple_powerup(gp);
2158 gem_check_invariants(gp);
2160 #endif /* CONFIG_PPC_PMAC */
2162 /* Reset the chip */
2163 spin_lock_irq(&gp->lock);
2165 spin_unlock_irq(&gp->lock);
2170 /* We can now request the interrupt as we know it's masked
2173 if (request_irq(gp->pdev->irq, gem_interrupt,
2174 SA_SHIRQ, dev->name, (void *)dev)) {
2175 printk(KERN_ERR "%s: failed to request irq !\n", gp->dev->name);
2177 spin_lock_irq(&gp->lock);
2178 #ifdef CONFIG_PPC_PMAC
2179 if (!hw_was_up && gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
2180 gem_apple_powerdown(gp);
2181 #endif /* CONFIG_PPC_PMAC */
2182 /* Fire the PM timer that will shut us down in about 10 seconds */
2183 gp->pm_timer.expires = jiffies + 10*HZ;
2184 add_timer(&gp->pm_timer);
2186 spin_unlock_irq(&gp->lock);
2191 spin_lock_irq(&gp->lock);
2193 /* Allocate & setup ring buffers */
2196 /* Init & setup chip hardware */
2197 gem_init_hw(gp, !hw_was_up);
2201 spin_unlock_irq(&gp->lock);
2208 static int gem_close(struct net_device *dev)
2210 struct gem *gp = dev->priv;
2212 /* Make sure we don't get distracted by suspend/resume */
2215 /* Stop traffic, mark us closed */
2216 spin_lock_irq(&gp->lock);
2219 writel(0xffffffff, gp->regs + GREG_IMASK);
2220 netif_stop_queue(dev);
2225 /* Get rid of rings */
2226 gem_clean_rings(gp);
2228 /* Bye, the pm timer will finish the job */
2229 free_irq(gp->pdev->irq, (void *) dev);
2231 spin_unlock_irq(&gp->lock);
2233 /* Fire the PM timer that will shut us down in about 10 seconds */
2234 gp->pm_timer.expires = jiffies + 10*HZ;
2235 add_timer(&gp->pm_timer);
2243 static int gem_suspend(struct pci_dev *pdev, u32 state)
2245 struct net_device *dev = pci_get_drvdata(pdev);
2246 struct gem *gp = dev->priv;
2248 /* We hold the PM semaphore during entire driver
2253 printk(KERN_INFO "%s: suspending, WakeOnLan %s\n",
2254 dev->name, gp->wake_on_lan ? "enabled" : "disabled");
2256 /* If the driver is opened, we stop the DMA */
2258 spin_lock_irq(&gp->lock);
2260 /* Stop traffic, mark us closed */
2261 netif_device_detach(dev);
2263 writel(0xffffffff, gp->regs + GREG_IMASK);
2268 /* Get rid of ring buffers */
2269 gem_clean_rings(gp);
2271 spin_unlock_irq(&gp->lock);
2273 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
2274 disable_irq(gp->pdev->irq);
2277 if (gp->hw_running) {
2278 /* Kill PM timer if any */
2279 del_timer_sync(&gp->pm_timer);
2280 flush_scheduled_work();
2288 static int gem_resume(struct pci_dev *pdev)
2290 struct net_device *dev = pci_get_drvdata(pdev);
2291 struct gem *gp = dev->priv;
2293 printk(KERN_INFO "%s: resuming\n", dev->name);
2296 #ifdef CONFIG_PPC_PMAC
2297 /* First, we need to bring up the chip */
2298 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
2299 gem_apple_powerup(gp);
2300 gem_check_invariants(gp);
2302 #endif /* CONFIG_PPC_PMAC */
2303 spin_lock_irq(&gp->lock);
2310 spin_unlock_irq(&gp->lock);
2312 netif_device_attach(dev);
2313 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
2314 enable_irq(gp->pdev->irq);
2320 #endif /* CONFIG_PM */
2322 static struct net_device_stats *gem_get_stats(struct net_device *dev)
2324 struct gem *gp = dev->priv;
2325 struct net_device_stats *stats = &gp->net_stats;
2327 spin_lock_irq(&gp->lock);
2329 if (gp->hw_running) {
2330 stats->rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2331 writel(0, gp->regs + MAC_FCSERR);
2333 stats->rx_frame_errors += readl(gp->regs + MAC_AERR);
2334 writel(0, gp->regs + MAC_AERR);
2336 stats->rx_length_errors += readl(gp->regs + MAC_LERR);
2337 writel(0, gp->regs + MAC_LERR);
2339 stats->tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2340 stats->collisions +=
2341 (readl(gp->regs + MAC_ECOLL) +
2342 readl(gp->regs + MAC_LCOLL));
2343 writel(0, gp->regs + MAC_ECOLL);
2344 writel(0, gp->regs + MAC_LCOLL);
2347 spin_unlock_irq(&gp->lock);
2349 return &gp->net_stats;
2352 static void gem_set_multicast(struct net_device *dev)
2354 struct gem *gp = dev->priv;
2355 u32 rxcfg, rxcfg_new;
2358 if (!gp->hw_running)
2361 spin_lock_irq(&gp->lock);
2363 netif_stop_queue(dev);
2365 rxcfg = readl(gp->regs + MAC_RXCFG);
2366 rxcfg_new = gem_setup_multicast(gp);
2368 rxcfg_new |= MAC_RXCFG_SFCS;
2370 gp->mac_rx_cfg = rxcfg_new;
2372 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2373 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2379 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2382 writel(rxcfg, gp->regs + MAC_RXCFG);
2384 netif_wake_queue(dev);
2386 spin_unlock_irq(&gp->lock);
2389 static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2391 struct gem *gp = dev->priv;
2393 strcpy(info->driver, DRV_NAME);
2394 strcpy(info->version, DRV_VERSION);
2395 strcpy(info->bus_info, pci_name(gp->pdev));
2398 static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2400 struct gem *gp = dev->priv;
2402 if (gp->phy_type == phy_mii_mdio0 ||
2403 gp->phy_type == phy_mii_mdio1) {
2404 if (gp->phy_mii.def)
2405 cmd->supported = gp->phy_mii.def->features;
2407 cmd->supported = (SUPPORTED_10baseT_Half |
2408 SUPPORTED_10baseT_Full);
2410 /* XXX hardcoded stuff for now */
2411 cmd->port = PORT_MII;
2412 cmd->transceiver = XCVR_EXTERNAL;
2413 cmd->phy_address = 0; /* XXX fixed PHYAD */
2415 /* Return current PHY settings */
2416 spin_lock_irq(&gp->lock);
2417 cmd->autoneg = gp->want_autoneg;
2418 cmd->speed = gp->phy_mii.speed;
2419 cmd->duplex = gp->phy_mii.duplex;
2420 cmd->advertising = gp->phy_mii.advertising;
2422 /* If we started with a forced mode, we don't have a default
2423 * advertise set, we need to return something sensible so
2424 * userland can re-enable autoneg properly.
2426 if (cmd->advertising == 0)
2427 cmd->advertising = cmd->supported;
2428 spin_unlock_irq(&gp->lock);
2429 } else { // XXX PCS ?
2431 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2432 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2434 cmd->advertising = cmd->supported;
2436 cmd->duplex = cmd->port = cmd->phy_address =
2437 cmd->transceiver = cmd->autoneg = 0;
2439 cmd->maxtxpkt = cmd->maxrxpkt = 0;
2444 static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2446 struct gem *gp = dev->priv;
2448 /* Verify the settings we care about. */
2449 if (cmd->autoneg != AUTONEG_ENABLE &&
2450 cmd->autoneg != AUTONEG_DISABLE)
2453 if (cmd->autoneg == AUTONEG_ENABLE &&
2454 cmd->advertising == 0)
2457 if (cmd->autoneg == AUTONEG_DISABLE &&
2458 ((cmd->speed != SPEED_1000 &&
2459 cmd->speed != SPEED_100 &&
2460 cmd->speed != SPEED_10) ||
2461 (cmd->duplex != DUPLEX_HALF &&
2462 cmd->duplex != DUPLEX_FULL)))
2465 /* Apply settings and restart link process. */
2466 spin_lock_irq(&gp->lock);
2467 gem_begin_auto_negotiation(gp, cmd);
2468 spin_unlock_irq(&gp->lock);
2473 static int gem_nway_reset(struct net_device *dev)
2475 struct gem *gp = dev->priv;
2477 if (!gp->want_autoneg)
2480 /* Restart link process. */
2481 spin_lock_irq(&gp->lock);
2482 gem_begin_auto_negotiation(gp, NULL);
2483 spin_unlock_irq(&gp->lock);
2488 static u32 gem_get_msglevel(struct net_device *dev)
2490 struct gem *gp = dev->priv;
2491 return gp->msg_enable;
2494 static void gem_set_msglevel(struct net_device *dev, u32 value)
2496 struct gem *gp = dev->priv;
2497 gp->msg_enable = value;
2500 static struct ethtool_ops gem_ethtool_ops = {
2501 .get_drvinfo = gem_get_drvinfo,
2502 .get_link = ethtool_op_get_link,
2503 .get_settings = gem_get_settings,
2504 .set_settings = gem_set_settings,
2505 .nway_reset = gem_nway_reset,
2506 .get_msglevel = gem_get_msglevel,
2507 .set_msglevel = gem_set_msglevel,
2510 static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2512 struct gem *gp = dev->priv;
2513 struct mii_ioctl_data *data = if_mii(ifr);
2514 int rc = -EOPNOTSUPP;
2516 /* Hold the PM semaphore while doing ioctl's or we may collide
2517 * with open/close and power management and oops.
2522 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2523 data->phy_id = gp->mii_phy_addr;
2524 /* Fallthrough... */
2526 case SIOCGMIIREG: /* Read MII PHY register. */
2527 if (!gp->hw_running)
2530 data->val_out = __phy_read(gp, data->phy_id & 0x1f, data->reg_num & 0x1f);
2535 case SIOCSMIIREG: /* Write MII PHY register. */
2536 if (!capable(CAP_NET_ADMIN))
2538 else if (!gp->hw_running)
2541 __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
2552 #if (!defined(__sparc__) && !defined(CONFIG_PPC))
2553 /* Fetch MAC address from vital product data of PCI ROM. */
2554 static void find_eth_addr_in_vpd(void *rom_base, int len, unsigned char *dev_addr)
2558 for (this_offset = 0x20; this_offset < len; this_offset++) {
2559 void *p = rom_base + this_offset;
2562 if (readb(p + 0) != 0x90 ||
2563 readb(p + 1) != 0x00 ||
2564 readb(p + 2) != 0x09 ||
2565 readb(p + 3) != 0x4e ||
2566 readb(p + 4) != 0x41 ||
2567 readb(p + 5) != 0x06)
2573 for (i = 0; i < 6; i++)
2574 dev_addr[i] = readb(p + i);
2579 static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2584 if (pdev->resource[PCI_ROM_RESOURCE].parent == NULL) {
2585 if (pci_assign_resource(pdev, PCI_ROM_RESOURCE) < 0)
2589 pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_reg_orig);
2590 pci_write_config_dword(pdev, pdev->rom_base_reg,
2591 rom_reg_orig | PCI_ROM_ADDRESS_ENABLE);
2593 p = ioremap(pci_resource_start(pdev, PCI_ROM_RESOURCE), (64 * 1024));
2594 if (p != NULL && readb(p) == 0x55 && readb(p + 1) == 0xaa)
2595 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2600 pci_write_config_dword(pdev, pdev->rom_base_reg, rom_reg_orig);
2604 /* Sun MAC prefix then 3 random bytes. */
2608 get_random_bytes(dev_addr + 3, 3);
2611 #endif /* not Sparc and not PPC */
2613 static int __devinit gem_get_device_address(struct gem *gp)
2615 #if defined(__sparc__) || defined(CONFIG_PPC_PMAC)
2616 struct net_device *dev = gp->dev;
2619 #if defined(__sparc__)
2620 struct pci_dev *pdev = gp->pdev;
2621 struct pcidev_cookie *pcp = pdev->sysdata;
2625 node = pcp->prom_node;
2626 if (prom_getproplen(node, "local-mac-address") == 6)
2627 prom_getproperty(node, "local-mac-address",
2633 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2634 #elif defined(CONFIG_PPC_PMAC)
2635 unsigned char *addr;
2637 addr = get_property(gp->of_node, "local-mac-address", NULL);
2640 printk(KERN_ERR "%s: can't get mac-address\n", dev->name);
2643 memcpy(dev->dev_addr, addr, 6);
2645 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2650 static int __devinit gem_init_one(struct pci_dev *pdev,
2651 const struct pci_device_id *ent)
2653 static int gem_version_printed = 0;
2654 unsigned long gemreg_base, gemreg_len;
2655 struct net_device *dev;
2657 int i, err, pci_using_dac;
2659 if (gem_version_printed++ == 0)
2660 printk(KERN_INFO "%s", version);
2662 /* Apple gmac note: during probe, the chip is powered up by
2663 * the arch code to allow the code below to work (and to let
2664 * the chip be probed on the config space. It won't stay powered
2665 * up until the interface is brought up however, so we can't rely
2666 * on register configuration done at this point.
2668 err = pci_enable_device(pdev);
2670 printk(KERN_ERR PFX "Cannot enable MMIO operation, "
2674 pci_set_master(pdev);
2676 /* Configure DMA attributes. */
2678 /* All of the GEM documentation states that 64-bit DMA addressing
2679 * is fully supported and should work just fine. However the
2680 * front end for RIO based GEMs is different and only supports
2681 * 32-bit addressing.
2683 * For now we assume the various PPC GEMs are 32-bit only as well.
2685 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2686 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
2687 !pci_set_dma_mask(pdev, (u64) 0xffffffffffffffffULL)) {
2690 err = pci_set_dma_mask(pdev, (u64) 0xffffffff);
2692 printk(KERN_ERR PFX "No usable DMA configuration, "
2694 goto err_disable_device;
2699 gemreg_base = pci_resource_start(pdev, 0);
2700 gemreg_len = pci_resource_len(pdev, 0);
2702 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
2703 printk(KERN_ERR PFX "Cannot find proper PCI device "
2704 "base address, aborting.\n");
2706 goto err_disable_device;
2709 dev = alloc_etherdev(sizeof(*gp));
2711 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
2713 goto err_disable_device;
2715 SET_MODULE_OWNER(dev);
2716 SET_NETDEV_DEV(dev, &pdev->dev);
2720 err = pci_request_regions(pdev, dev->name);
2722 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
2724 goto err_out_free_netdev;
2728 dev->base_addr = (long) pdev;
2731 gp->msg_enable = DEFAULT_MSG;
2733 spin_lock_init(&gp->lock);
2734 init_MUTEX(&gp->pm_sem);
2736 init_timer(&gp->link_timer);
2737 gp->link_timer.function = gem_link_timer;
2738 gp->link_timer.data = (unsigned long) gp;
2740 init_timer(&gp->pm_timer);
2741 gp->pm_timer.function = gem_pm_timer;
2742 gp->pm_timer.data = (unsigned long) gp;
2744 INIT_WORK(&gp->pm_task, gem_pm_task, gp);
2745 INIT_WORK(&gp->reset_task, gem_reset_task, gp);
2747 gp->lstate = link_down;
2748 gp->timer_ticks = 0;
2749 netif_carrier_off(dev);
2751 gp->regs = (unsigned long) ioremap(gemreg_base, gemreg_len);
2752 if (gp->regs == 0UL) {
2753 printk(KERN_ERR PFX "Cannot map device registers, "
2756 goto err_out_free_res;
2759 /* On Apple, we power the chip up now in order for check
2760 * invariants to work, but also because the firmware might
2761 * not have properly shut down the PHY.
2763 #ifdef CONFIG_PPC_PMAC
2764 gp->of_node = pci_device_to_OF_node(pdev);
2765 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
2766 gem_apple_powerup(gp);
2768 spin_lock_irq(&gp->lock);
2770 spin_unlock_irq(&gp->lock);
2772 /* Fill up the mii_phy structure (even if we won't use it) */
2773 gp->phy_mii.dev = dev;
2774 gp->phy_mii.mdio_read = _phy_read;
2775 gp->phy_mii.mdio_write = _phy_write;
2777 /* By default, we start with autoneg */
2778 gp->want_autoneg = 1;
2780 if (gem_check_invariants(gp)) {
2782 goto err_out_iounmap;
2785 /* It is guaranteed that the returned buffer will be at least
2786 * PAGE_SIZE aligned.
2788 gp->init_block = (struct gem_init_block *)
2789 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
2791 if (!gp->init_block) {
2792 printk(KERN_ERR PFX "Cannot allocate init block, "
2795 goto err_out_iounmap;
2798 if (gem_get_device_address(gp))
2799 goto err_out_free_consistent;
2801 dev->open = gem_open;
2802 dev->stop = gem_close;
2803 dev->hard_start_xmit = gem_start_xmit;
2804 dev->get_stats = gem_get_stats;
2805 dev->set_multicast_list = gem_set_multicast;
2806 dev->do_ioctl = gem_ioctl;
2807 dev->ethtool_ops = &gem_ethtool_ops;
2808 dev->tx_timeout = gem_tx_timeout;
2809 dev->watchdog_timeo = 5 * HZ;
2810 dev->change_mtu = gem_change_mtu;
2811 dev->irq = pdev->irq;
2814 if (register_netdev(dev)) {
2815 printk(KERN_ERR PFX "Cannot register net device, "
2818 goto err_out_free_consistent;
2821 printk(KERN_INFO "%s: Sun GEM (PCI) 10/100/1000BaseT Ethernet ",
2823 for (i = 0; i < 6; i++)
2824 printk("%2.2x%c", dev->dev_addr[i],
2825 i == 5 ? ' ' : ':');
2828 /* Detect & init PHY, start autoneg */
2829 spin_lock_irq(&gp->lock);
2832 gem_begin_auto_negotiation(gp, NULL);
2833 spin_unlock_irq(&gp->lock);
2835 if (gp->phy_type == phy_mii_mdio0 ||
2836 gp->phy_type == phy_mii_mdio1)
2837 printk(KERN_INFO "%s: Found %s PHY\n", dev->name,
2838 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
2840 pci_set_drvdata(pdev, dev);
2842 /* GEM can do it all... */
2843 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
2845 dev->features |= NETIF_F_HIGHDMA;
2847 /* Fire the PM timer that will shut us down in about 10 seconds */
2848 gp->pm_timer.expires = jiffies + 10*HZ;
2849 add_timer(&gp->pm_timer);
2853 err_out_free_consistent:
2854 pci_free_consistent(pdev,
2855 sizeof(struct gem_init_block),
2861 /* Stop the PM timer & task */
2862 del_timer_sync(&gp->pm_timer);
2863 flush_scheduled_work();
2868 iounmap((void *) gp->regs);
2871 pci_release_regions(pdev);
2873 err_out_free_netdev:
2876 pci_disable_device(pdev);
2881 static void __devexit gem_remove_one(struct pci_dev *pdev)
2883 struct net_device *dev = pci_get_drvdata(pdev);
2886 struct gem *gp = dev->priv;
2888 unregister_netdev(dev);
2891 /* Stop the PM timer & task */
2892 del_timer_sync(&gp->pm_timer);
2893 flush_scheduled_work();
2898 pci_free_consistent(pdev,
2899 sizeof(struct gem_init_block),
2902 iounmap((void *) gp->regs);
2903 pci_release_regions(pdev);
2906 pci_set_drvdata(pdev, NULL);
2910 static struct pci_driver gem_driver = {
2911 .name = GEM_MODULE_NAME,
2912 .id_table = gem_pci_tbl,
2913 .probe = gem_init_one,
2914 .remove = __devexit_p(gem_remove_one),
2916 .suspend = gem_suspend,
2917 .resume = gem_resume,
2918 #endif /* CONFIG_PM */
2921 static int __init gem_init(void)
2923 return pci_module_init(&gem_driver);
2926 static void __exit gem_cleanup(void)
2928 pci_unregister_driver(&gem_driver);
2931 module_init(gem_init);
2932 module_exit(gem_cleanup);