1 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
11 #define TG3_64BIT_REG_HIGH 0x00UL
12 #define TG3_64BIT_REG_LOW 0x04UL
14 /* Descriptor block info. */
15 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
16 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
17 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
18 #define BDINFO_FLAGS_DISABLED 0x00000002
19 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
20 #define BDINFO_FLAGS_MAXLEN_SHIFT 16
21 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
22 #define TG3_BDINFO_SIZE 0x10UL
24 #define RX_COPY_THRESHOLD 256
26 #define RX_STD_MAX_SIZE 1536
27 #define RX_STD_MAX_SIZE_5705 512
28 #define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */
30 /* First 256 bytes are a mirror of PCI config space. */
31 #define TG3PCI_VENDOR 0x00000000
32 #define TG3PCI_VENDOR_BROADCOM 0x14e4
33 #define TG3PCI_DEVICE 0x00000002
34 #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
35 #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
36 #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
37 #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
38 #define TG3PCI_COMMAND 0x00000004
39 #define TG3PCI_STATUS 0x00000006
40 #define TG3PCI_CCREVID 0x00000008
41 #define TG3PCI_CACHELINESZ 0x0000000c
42 #define TG3PCI_LATTIMER 0x0000000d
43 #define TG3PCI_HEADERTYPE 0x0000000e
44 #define TG3PCI_BIST 0x0000000f
45 #define TG3PCI_BASE0_LOW 0x00000010
46 #define TG3PCI_BASE0_HIGH 0x00000014
47 /* 0x18 --> 0x2c unused */
48 #define TG3PCI_SUBSYSVENID 0x0000002c
49 #define TG3PCI_SUBSYSID 0x0000002e
50 #define TG3PCI_ROMADDR 0x00000030
51 #define TG3PCI_CAPLIST 0x00000034
52 /* 0x35 --> 0x3c unused */
53 #define TG3PCI_IRQ_LINE 0x0000003c
54 #define TG3PCI_IRQ_PIN 0x0000003d
55 #define TG3PCI_MIN_GNT 0x0000003e
56 #define TG3PCI_MAX_LAT 0x0000003f
57 #define TG3PCI_X_CAPS 0x00000040
58 #define PCIX_CAPS_RELAXED_ORDERING 0x00020000
59 #define PCIX_CAPS_SPLIT_MASK 0x00700000
60 #define PCIX_CAPS_SPLIT_SHIFT 20
61 #define PCIX_CAPS_BURST_MASK 0x000c0000
62 #define PCIX_CAPS_BURST_SHIFT 18
63 #define PCIX_CAPS_MAX_BURST_CPIOB 2
64 #define TG3PCI_PM_CAP_PTR 0x00000041
65 #define TG3PCI_X_COMMAND 0x00000042
66 #define TG3PCI_X_STATUS 0x00000044
67 #define TG3PCI_PM_CAP_ID 0x00000048
68 #define TG3PCI_VPD_CAP_PTR 0x00000049
69 #define TG3PCI_PM_CAPS 0x0000004a
70 #define TG3PCI_PM_CTRL_STAT 0x0000004c
71 #define TG3PCI_BR_SUPP_EXT 0x0000004e
72 #define TG3PCI_PM_DATA 0x0000004f
73 #define TG3PCI_VPD_CAP_ID 0x00000050
74 #define TG3PCI_MSI_CAP_PTR 0x00000051
75 #define TG3PCI_VPD_ADDR_FLAG 0x00000052
76 #define VPD_ADDR_FLAG_WRITE 0x00008000
77 #define TG3PCI_VPD_DATA 0x00000054
78 #define TG3PCI_MSI_CAP_ID 0x00000058
79 #define TG3PCI_NXT_CAP_PTR 0x00000059
80 #define TG3PCI_MSI_CTRL 0x0000005a
81 #define TG3PCI_MSI_ADDR_LOW 0x0000005c
82 #define TG3PCI_MSI_ADDR_HIGH 0x00000060
83 #define TG3PCI_MSI_DATA 0x00000064
84 /* 0x66 --> 0x68 unused */
85 #define TG3PCI_MISC_HOST_CTRL 0x00000068
86 #define MISC_HOST_CTRL_CLEAR_INT 0x00000001
87 #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
88 #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
89 #define MISC_HOST_CTRL_WORD_SWAP 0x00000008
90 #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
91 #define MISC_HOST_CTRL_CLKREG_RW 0x00000020
92 #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
93 #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
94 #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
95 #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
96 #define MISC_HOST_CTRL_CHIPREV 0xffff0000
97 #define MISC_HOST_CTRL_CHIPREV_SHIFT 16
98 #define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
99 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
100 MISC_HOST_CTRL_CHIPREV_SHIFT)
101 #define CHIPREV_ID_5700_A0 0x7000
102 #define CHIPREV_ID_5700_A1 0x7001
103 #define CHIPREV_ID_5700_B0 0x7100
104 #define CHIPREV_ID_5700_B1 0x7101
105 #define CHIPREV_ID_5700_B3 0x7102
106 #define CHIPREV_ID_5700_ALTIMA 0x7104
107 #define CHIPREV_ID_5700_C0 0x7200
108 #define CHIPREV_ID_5701_A0 0x0000
109 #define CHIPREV_ID_5701_B0 0x0100
110 #define CHIPREV_ID_5701_B2 0x0102
111 #define CHIPREV_ID_5701_B5 0x0105
112 #define CHIPREV_ID_5703_A0 0x1000
113 #define CHIPREV_ID_5703_A1 0x1001
114 #define CHIPREV_ID_5703_A2 0x1002
115 #define CHIPREV_ID_5703_A3 0x1003
116 #define CHIPREV_ID_5704_A0 0x2000
117 #define CHIPREV_ID_5704_A1 0x2001
118 #define CHIPREV_ID_5704_A2 0x2002
119 #define CHIPREV_ID_5705_A0 0x3000
120 #define CHIPREV_ID_5705_A1 0x3001
121 #define CHIPREV_ID_5705_A2 0x3002
122 #define CHIPREV_ID_5705_A3 0x3003
123 #define CHIPREV_ID_5750_A0 0x4000
124 #define CHIPREV_ID_5750_A1 0x4001
125 #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
126 #define ASIC_REV_5700 0x07
127 #define ASIC_REV_5701 0x00
128 #define ASIC_REV_5703 0x01
129 #define ASIC_REV_5704 0x02
130 #define ASIC_REV_5705 0x03
131 #define ASIC_REV_5750 0x04
132 #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
133 #define CHIPREV_5700_AX 0x70
134 #define CHIPREV_5700_BX 0x71
135 #define CHIPREV_5700_CX 0x72
136 #define CHIPREV_5701_AX 0x00
137 #define CHIPREV_5703_AX 0x10
138 #define CHIPREV_5704_AX 0x20
139 #define CHIPREV_5704_BX 0x21
140 #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
141 #define METAL_REV_A0 0x00
142 #define METAL_REV_A1 0x01
143 #define METAL_REV_B0 0x00
144 #define METAL_REV_B1 0x01
145 #define METAL_REV_B2 0x02
146 #define TG3PCI_DMA_RW_CTRL 0x0000006c
147 #define DMA_RWCTRL_MIN_DMA 0x000000ff
148 #define DMA_RWCTRL_MIN_DMA_SHIFT 0
149 #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
150 #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
151 #define DMA_RWCTRL_READ_BNDRY_16 0x00000100
152 #define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
153 #define DMA_RWCTRL_READ_BNDRY_32 0x00000200
154 #define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
155 #define DMA_RWCTRL_READ_BNDRY_64 0x00000300
156 #define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
157 #define DMA_RWCTRL_READ_BNDRY_128 0x00000400
158 #define DMA_RWCTRL_READ_BNDRY_256 0x00000500
159 #define DMA_RWCTRL_READ_BNDRY_512 0x00000600
160 #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
161 #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
162 #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
163 #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
164 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
165 #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
166 #define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
167 #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
168 #define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
169 #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
170 #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
171 #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
172 #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
173 #define DMA_RWCTRL_ONE_DMA 0x00004000
174 #define DMA_RWCTRL_READ_WATER 0x00070000
175 #define DMA_RWCTRL_READ_WATER_SHIFT 16
176 #define DMA_RWCTRL_WRITE_WATER 0x00380000
177 #define DMA_RWCTRL_WRITE_WATER_SHIFT 19
178 #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
179 #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
180 #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
181 #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
182 #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
183 #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
184 #define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
185 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
186 #define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
187 #define TG3PCI_PCISTATE 0x00000070
188 #define PCISTATE_FORCE_RESET 0x00000001
189 #define PCISTATE_INT_NOT_ACTIVE 0x00000002
190 #define PCISTATE_CONV_PCI_MODE 0x00000004
191 #define PCISTATE_BUS_SPEED_HIGH 0x00000008
192 #define PCISTATE_BUS_32BIT 0x00000010
193 #define PCISTATE_ROM_ENABLE 0x00000020
194 #define PCISTATE_ROM_RETRY_ENABLE 0x00000040
195 #define PCISTATE_FLAT_VIEW 0x00000100
196 #define PCISTATE_RETRY_SAME_DMA 0x00002000
197 #define TG3PCI_CLOCK_CTRL 0x00000074
198 #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
199 #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
200 #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
201 #define CLOCK_CTRL_ALTCLK 0x00001000
202 #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
203 #define CLOCK_CTRL_44MHZ_CORE 0x00040000
204 #define CLOCK_CTRL_625_CORE 0x00100000
205 #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
206 #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
207 #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
208 #define TG3PCI_REG_BASE_ADDR 0x00000078
209 #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
210 #define TG3PCI_REG_DATA 0x00000080
211 #define TG3PCI_MEM_WIN_DATA 0x00000084
212 #define TG3PCI_MODE_CTRL 0x00000088
213 #define TG3PCI_MISC_CFG 0x0000008c
214 #define TG3PCI_MISC_LOCAL_CTRL 0x00000090
215 /* 0x94 --> 0x98 unused */
216 #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
217 #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
218 #define TG3PCI_SND_PROD_IDX 0x000000a8 /* 64-bit */
219 /* 0xb0 --> 0xb8 unused */
220 #define TG3PCI_DUAL_MAC_CTRL 0x000000b8
221 #define DUAL_MAC_CTRL_CH_MASK 0x00000003
222 #define DUAL_MAC_CTRL_ID 0x00000004
223 /* 0xbc --> 0x100 unused */
225 /* 0x100 --> 0x200 unused */
227 /* Mailbox registers */
228 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
229 #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
230 #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
231 #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
232 #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
233 #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
234 #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
235 #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
236 #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
237 #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
238 #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
239 #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
240 #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
241 #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
242 #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
243 #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
244 #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
245 #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
246 #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
247 #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
248 #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
249 #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
250 #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
251 #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
252 #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
253 #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
254 #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
255 #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
256 #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
257 #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
258 #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
259 #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
260 #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
261 #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
262 #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
263 #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
264 #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
265 #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
266 #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
267 #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
268 #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
269 #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
270 #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
271 #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
272 #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
273 #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
274 #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
275 #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
276 #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
277 #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
278 #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
279 #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
280 #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
281 #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
282 #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
283 #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
284 #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
285 #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
286 #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
287 #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
288 #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
289 #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
290 #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
291 #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
293 /* MAC control registers */
294 #define MAC_MODE 0x00000400
295 #define MAC_MODE_RESET 0x00000001
296 #define MAC_MODE_HALF_DUPLEX 0x00000002
297 #define MAC_MODE_PORT_MODE_MASK 0x0000000c
298 #define MAC_MODE_PORT_MODE_TBI 0x0000000c
299 #define MAC_MODE_PORT_MODE_GMII 0x00000008
300 #define MAC_MODE_PORT_MODE_MII 0x00000004
301 #define MAC_MODE_PORT_MODE_NONE 0x00000000
302 #define MAC_MODE_PORT_INT_LPBACK 0x00000010
303 #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
304 #define MAC_MODE_TX_BURSTING 0x00000100
305 #define MAC_MODE_MAX_DEFER 0x00000200
306 #define MAC_MODE_LINK_POLARITY 0x00000400
307 #define MAC_MODE_RXSTAT_ENABLE 0x00000800
308 #define MAC_MODE_RXSTAT_CLEAR 0x00001000
309 #define MAC_MODE_RXSTAT_FLUSH 0x00002000
310 #define MAC_MODE_TXSTAT_ENABLE 0x00004000
311 #define MAC_MODE_TXSTAT_CLEAR 0x00008000
312 #define MAC_MODE_TXSTAT_FLUSH 0x00010000
313 #define MAC_MODE_SEND_CONFIGS 0x00020000
314 #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
315 #define MAC_MODE_ACPI_ENABLE 0x00080000
316 #define MAC_MODE_MIP_ENABLE 0x00100000
317 #define MAC_MODE_TDE_ENABLE 0x00200000
318 #define MAC_MODE_RDE_ENABLE 0x00400000
319 #define MAC_MODE_FHDE_ENABLE 0x00800000
320 #define MAC_STATUS 0x00000404
321 #define MAC_STATUS_PCS_SYNCED 0x00000001
322 #define MAC_STATUS_SIGNAL_DET 0x00000002
323 #define MAC_STATUS_RCVD_CFG 0x00000004
324 #define MAC_STATUS_CFG_CHANGED 0x00000008
325 #define MAC_STATUS_SYNC_CHANGED 0x00000010
326 #define MAC_STATUS_PORT_DEC_ERR 0x00000400
327 #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
328 #define MAC_STATUS_MI_COMPLETION 0x00400000
329 #define MAC_STATUS_MI_INTERRUPT 0x00800000
330 #define MAC_STATUS_AP_ERROR 0x01000000
331 #define MAC_STATUS_ODI_ERROR 0x02000000
332 #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
333 #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
334 #define MAC_EVENT 0x00000408
335 #define MAC_EVENT_PORT_DECODE_ERR 0x00000400
336 #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
337 #define MAC_EVENT_MI_COMPLETION 0x00400000
338 #define MAC_EVENT_MI_INTERRUPT 0x00800000
339 #define MAC_EVENT_AP_ERROR 0x01000000
340 #define MAC_EVENT_ODI_ERROR 0x02000000
341 #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
342 #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
343 #define MAC_LED_CTRL 0x0000040c
344 #define LED_CTRL_LNKLED_OVERRIDE 0x00000001
345 #define LED_CTRL_1000MBPS_ON 0x00000002
346 #define LED_CTRL_100MBPS_ON 0x00000004
347 #define LED_CTRL_10MBPS_ON 0x00000008
348 #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
349 #define LED_CTRL_TRAFFIC_BLINK 0x00000020
350 #define LED_CTRL_TRAFFIC_LED 0x00000040
351 #define LED_CTRL_1000MBPS_STATUS 0x00000080
352 #define LED_CTRL_100MBPS_STATUS 0x00000100
353 #define LED_CTRL_10MBPS_STATUS 0x00000200
354 #define LED_CTRL_TRAFFIC_STATUS 0x00000400
355 #define LED_CTRL_MODE_MAC 0x00000000
356 #define LED_CTRL_MODE_PHY_1 0x00000800
357 #define LED_CTRL_MODE_PHY_2 0x00001000
358 #define LED_CTRL_MODE_SHASTA_MAC 0x00002000
359 #define LED_CTRL_MODE_SHARED 0x00004000
360 #define LED_CTRL_MODE_COMBO 0x00008000
361 #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
362 #define LED_CTRL_BLINK_RATE_SHIFT 19
363 #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
364 #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
365 #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
366 #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
367 #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
368 #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
369 #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
370 #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
371 #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
372 #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
373 #define MAC_ACPI_MBUF_PTR 0x00000430
374 #define MAC_ACPI_LEN_OFFSET 0x00000434
375 #define ACPI_LENOFF_LEN_MASK 0x0000ffff
376 #define ACPI_LENOFF_LEN_SHIFT 0
377 #define ACPI_LENOFF_OFF_MASK 0x0fff0000
378 #define ACPI_LENOFF_OFF_SHIFT 16
379 #define MAC_TX_BACKOFF_SEED 0x00000438
380 #define TX_BACKOFF_SEED_MASK 0x000003ff
381 #define MAC_RX_MTU_SIZE 0x0000043c
382 #define RX_MTU_SIZE_MASK 0x0000ffff
383 #define MAC_PCS_TEST 0x00000440
384 #define PCS_TEST_PATTERN_MASK 0x000fffff
385 #define PCS_TEST_PATTERN_SHIFT 0
386 #define PCS_TEST_ENABLE 0x00100000
387 #define MAC_TX_AUTO_NEG 0x00000444
388 #define TX_AUTO_NEG_MASK 0x0000ffff
389 #define TX_AUTO_NEG_SHIFT 0
390 #define MAC_RX_AUTO_NEG 0x00000448
391 #define RX_AUTO_NEG_MASK 0x0000ffff
392 #define RX_AUTO_NEG_SHIFT 0
393 #define MAC_MI_COM 0x0000044c
394 #define MI_COM_CMD_MASK 0x0c000000
395 #define MI_COM_CMD_WRITE 0x04000000
396 #define MI_COM_CMD_READ 0x08000000
397 #define MI_COM_READ_FAILED 0x10000000
398 #define MI_COM_START 0x20000000
399 #define MI_COM_BUSY 0x20000000
400 #define MI_COM_PHY_ADDR_MASK 0x03e00000
401 #define MI_COM_PHY_ADDR_SHIFT 21
402 #define MI_COM_REG_ADDR_MASK 0x001f0000
403 #define MI_COM_REG_ADDR_SHIFT 16
404 #define MI_COM_DATA_MASK 0x0000ffff
405 #define MAC_MI_STAT 0x00000450
406 #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
407 #define MAC_MI_MODE 0x00000454
408 #define MAC_MI_MODE_CLK_10MHZ 0x00000001
409 #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
410 #define MAC_MI_MODE_AUTO_POLL 0x00000010
411 #define MAC_MI_MODE_CORE_CLK_62MHZ 0x00008000
412 #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
413 #define MAC_AUTO_POLL_STATUS 0x00000458
414 #define MAC_AUTO_POLL_ERROR 0x00000001
415 #define MAC_TX_MODE 0x0000045c
416 #define TX_MODE_RESET 0x00000001
417 #define TX_MODE_ENABLE 0x00000002
418 #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
419 #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
420 #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
421 #define MAC_TX_STATUS 0x00000460
422 #define TX_STATUS_XOFFED 0x00000001
423 #define TX_STATUS_SENT_XOFF 0x00000002
424 #define TX_STATUS_SENT_XON 0x00000004
425 #define TX_STATUS_LINK_UP 0x00000008
426 #define TX_STATUS_ODI_UNDERRUN 0x00000010
427 #define TX_STATUS_ODI_OVERRUN 0x00000020
428 #define MAC_TX_LENGTHS 0x00000464
429 #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
430 #define TX_LENGTHS_SLOT_TIME_SHIFT 0
431 #define TX_LENGTHS_IPG_MASK 0x00000f00
432 #define TX_LENGTHS_IPG_SHIFT 8
433 #define TX_LENGTHS_IPG_CRS_MASK 0x00003000
434 #define TX_LENGTHS_IPG_CRS_SHIFT 12
435 #define MAC_RX_MODE 0x00000468
436 #define RX_MODE_RESET 0x00000001
437 #define RX_MODE_ENABLE 0x00000002
438 #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
439 #define RX_MODE_KEEP_MAC_CTRL 0x00000008
440 #define RX_MODE_KEEP_PAUSE 0x00000010
441 #define RX_MODE_ACCEPT_OVERSIZED 0x00000020
442 #define RX_MODE_ACCEPT_RUNTS 0x00000040
443 #define RX_MODE_LEN_CHECK 0x00000080
444 #define RX_MODE_PROMISC 0x00000100
445 #define RX_MODE_NO_CRC_CHECK 0x00000200
446 #define RX_MODE_KEEP_VLAN_TAG 0x00000400
447 #define MAC_RX_STATUS 0x0000046c
448 #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
449 #define RX_STATUS_XOFF_RCVD 0x00000002
450 #define RX_STATUS_XON_RCVD 0x00000004
451 #define MAC_HASH_REG_0 0x00000470
452 #define MAC_HASH_REG_1 0x00000474
453 #define MAC_HASH_REG_2 0x00000478
454 #define MAC_HASH_REG_3 0x0000047c
455 #define MAC_RCV_RULE_0 0x00000480
456 #define MAC_RCV_VALUE_0 0x00000484
457 #define MAC_RCV_RULE_1 0x00000488
458 #define MAC_RCV_VALUE_1 0x0000048c
459 #define MAC_RCV_RULE_2 0x00000490
460 #define MAC_RCV_VALUE_2 0x00000494
461 #define MAC_RCV_RULE_3 0x00000498
462 #define MAC_RCV_VALUE_3 0x0000049c
463 #define MAC_RCV_RULE_4 0x000004a0
464 #define MAC_RCV_VALUE_4 0x000004a4
465 #define MAC_RCV_RULE_5 0x000004a8
466 #define MAC_RCV_VALUE_5 0x000004ac
467 #define MAC_RCV_RULE_6 0x000004b0
468 #define MAC_RCV_VALUE_6 0x000004b4
469 #define MAC_RCV_RULE_7 0x000004b8
470 #define MAC_RCV_VALUE_7 0x000004bc
471 #define MAC_RCV_RULE_8 0x000004c0
472 #define MAC_RCV_VALUE_8 0x000004c4
473 #define MAC_RCV_RULE_9 0x000004c8
474 #define MAC_RCV_VALUE_9 0x000004cc
475 #define MAC_RCV_RULE_10 0x000004d0
476 #define MAC_RCV_VALUE_10 0x000004d4
477 #define MAC_RCV_RULE_11 0x000004d8
478 #define MAC_RCV_VALUE_11 0x000004dc
479 #define MAC_RCV_RULE_12 0x000004e0
480 #define MAC_RCV_VALUE_12 0x000004e4
481 #define MAC_RCV_RULE_13 0x000004e8
482 #define MAC_RCV_VALUE_13 0x000004ec
483 #define MAC_RCV_RULE_14 0x000004f0
484 #define MAC_RCV_VALUE_14 0x000004f4
485 #define MAC_RCV_RULE_15 0x000004f8
486 #define MAC_RCV_VALUE_15 0x000004fc
487 #define RCV_RULE_DISABLE_MASK 0x7fffffff
488 #define MAC_RCV_RULE_CFG 0x00000500
489 #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
490 #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
491 /* 0x508 --> 0x520 unused */
492 #define MAC_HASHREGU_0 0x00000520
493 #define MAC_HASHREGU_1 0x00000524
494 #define MAC_HASHREGU_2 0x00000528
495 #define MAC_HASHREGU_3 0x0000052c
496 #define MAC_EXTADDR_0_HIGH 0x00000530
497 #define MAC_EXTADDR_0_LOW 0x00000534
498 #define MAC_EXTADDR_1_HIGH 0x00000538
499 #define MAC_EXTADDR_1_LOW 0x0000053c
500 #define MAC_EXTADDR_2_HIGH 0x00000540
501 #define MAC_EXTADDR_2_LOW 0x00000544
502 #define MAC_EXTADDR_3_HIGH 0x00000548
503 #define MAC_EXTADDR_3_LOW 0x0000054c
504 #define MAC_EXTADDR_4_HIGH 0x00000550
505 #define MAC_EXTADDR_4_LOW 0x00000554
506 #define MAC_EXTADDR_5_HIGH 0x00000558
507 #define MAC_EXTADDR_5_LOW 0x0000055c
508 #define MAC_EXTADDR_6_HIGH 0x00000560
509 #define MAC_EXTADDR_6_LOW 0x00000564
510 #define MAC_EXTADDR_7_HIGH 0x00000568
511 #define MAC_EXTADDR_7_LOW 0x0000056c
512 #define MAC_EXTADDR_8_HIGH 0x00000570
513 #define MAC_EXTADDR_8_LOW 0x00000574
514 #define MAC_EXTADDR_9_HIGH 0x00000578
515 #define MAC_EXTADDR_9_LOW 0x0000057c
516 #define MAC_EXTADDR_10_HIGH 0x00000580
517 #define MAC_EXTADDR_10_LOW 0x00000584
518 #define MAC_EXTADDR_11_HIGH 0x00000588
519 #define MAC_EXTADDR_11_LOW 0x0000058c
520 #define MAC_SERDES_CFG 0x00000590
521 #define MAC_SERDES_STAT 0x00000594
522 /* 0x598 --> 0x600 unused */
523 #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
524 #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
525 /* 0x624 --> 0x800 unused */
526 #define MAC_TX_STATS_OCTETS 0x00000800
527 #define MAC_TX_STATS_RESV1 0x00000804
528 #define MAC_TX_STATS_COLLISIONS 0x00000808
529 #define MAC_TX_STATS_XON_SENT 0x0000080c
530 #define MAC_TX_STATS_XOFF_SENT 0x00000810
531 #define MAC_TX_STATS_RESV2 0x00000814
532 #define MAC_TX_STATS_MAC_ERRORS 0x00000818
533 #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
534 #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
535 #define MAC_TX_STATS_DEFERRED 0x00000824
536 #define MAC_TX_STATS_RESV3 0x00000828
537 #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
538 #define MAC_TX_STATS_LATE_COL 0x00000830
539 #define MAC_TX_STATS_RESV4_1 0x00000834
540 #define MAC_TX_STATS_RESV4_2 0x00000838
541 #define MAC_TX_STATS_RESV4_3 0x0000083c
542 #define MAC_TX_STATS_RESV4_4 0x00000840
543 #define MAC_TX_STATS_RESV4_5 0x00000844
544 #define MAC_TX_STATS_RESV4_6 0x00000848
545 #define MAC_TX_STATS_RESV4_7 0x0000084c
546 #define MAC_TX_STATS_RESV4_8 0x00000850
547 #define MAC_TX_STATS_RESV4_9 0x00000854
548 #define MAC_TX_STATS_RESV4_10 0x00000858
549 #define MAC_TX_STATS_RESV4_11 0x0000085c
550 #define MAC_TX_STATS_RESV4_12 0x00000860
551 #define MAC_TX_STATS_RESV4_13 0x00000864
552 #define MAC_TX_STATS_RESV4_14 0x00000868
553 #define MAC_TX_STATS_UCAST 0x0000086c
554 #define MAC_TX_STATS_MCAST 0x00000870
555 #define MAC_TX_STATS_BCAST 0x00000874
556 #define MAC_TX_STATS_RESV5_1 0x00000878
557 #define MAC_TX_STATS_RESV5_2 0x0000087c
558 #define MAC_RX_STATS_OCTETS 0x00000880
559 #define MAC_RX_STATS_RESV1 0x00000884
560 #define MAC_RX_STATS_FRAGMENTS 0x00000888
561 #define MAC_RX_STATS_UCAST 0x0000088c
562 #define MAC_RX_STATS_MCAST 0x00000890
563 #define MAC_RX_STATS_BCAST 0x00000894
564 #define MAC_RX_STATS_FCS_ERRORS 0x00000898
565 #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
566 #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
567 #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
568 #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
569 #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
570 #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
571 #define MAC_RX_STATS_JABBERS 0x000008b4
572 #define MAC_RX_STATS_UNDERSIZE 0x000008b8
573 /* 0x8bc --> 0xc00 unused */
575 /* Send data initiator control registers */
576 #define SNDDATAI_MODE 0x00000c00
577 #define SNDDATAI_MODE_RESET 0x00000001
578 #define SNDDATAI_MODE_ENABLE 0x00000002
579 #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
580 #define SNDDATAI_STATUS 0x00000c04
581 #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
582 #define SNDDATAI_STATSCTRL 0x00000c08
583 #define SNDDATAI_SCTRL_ENABLE 0x00000001
584 #define SNDDATAI_SCTRL_FASTUPD 0x00000002
585 #define SNDDATAI_SCTRL_CLEAR 0x00000004
586 #define SNDDATAI_SCTRL_FLUSH 0x00000008
587 #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
588 #define SNDDATAI_STATSENAB 0x00000c0c
589 #define SNDDATAI_STATSINCMASK 0x00000c10
590 /* 0xc14 --> 0xc80 unused */
591 #define SNDDATAI_COS_CNT_0 0x00000c80
592 #define SNDDATAI_COS_CNT_1 0x00000c84
593 #define SNDDATAI_COS_CNT_2 0x00000c88
594 #define SNDDATAI_COS_CNT_3 0x00000c8c
595 #define SNDDATAI_COS_CNT_4 0x00000c90
596 #define SNDDATAI_COS_CNT_5 0x00000c94
597 #define SNDDATAI_COS_CNT_6 0x00000c98
598 #define SNDDATAI_COS_CNT_7 0x00000c9c
599 #define SNDDATAI_COS_CNT_8 0x00000ca0
600 #define SNDDATAI_COS_CNT_9 0x00000ca4
601 #define SNDDATAI_COS_CNT_10 0x00000ca8
602 #define SNDDATAI_COS_CNT_11 0x00000cac
603 #define SNDDATAI_COS_CNT_12 0x00000cb0
604 #define SNDDATAI_COS_CNT_13 0x00000cb4
605 #define SNDDATAI_COS_CNT_14 0x00000cb8
606 #define SNDDATAI_COS_CNT_15 0x00000cbc
607 #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
608 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
609 #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
610 #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
611 #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
612 #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
613 #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
614 #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
615 /* 0xce0 --> 0x1000 unused */
617 /* Send data completion control registers */
618 #define SNDDATAC_MODE 0x00001000
619 #define SNDDATAC_MODE_RESET 0x00000001
620 #define SNDDATAC_MODE_ENABLE 0x00000002
621 /* 0x1004 --> 0x1400 unused */
623 /* Send BD ring selector */
624 #define SNDBDS_MODE 0x00001400
625 #define SNDBDS_MODE_RESET 0x00000001
626 #define SNDBDS_MODE_ENABLE 0x00000002
627 #define SNDBDS_MODE_ATTN_ENABLE 0x00000004
628 #define SNDBDS_STATUS 0x00001404
629 #define SNDBDS_STATUS_ERROR_ATTN 0x00000004
630 #define SNDBDS_HWDIAG 0x00001408
631 /* 0x140c --> 0x1440 */
632 #define SNDBDS_SEL_CON_IDX_0 0x00001440
633 #define SNDBDS_SEL_CON_IDX_1 0x00001444
634 #define SNDBDS_SEL_CON_IDX_2 0x00001448
635 #define SNDBDS_SEL_CON_IDX_3 0x0000144c
636 #define SNDBDS_SEL_CON_IDX_4 0x00001450
637 #define SNDBDS_SEL_CON_IDX_5 0x00001454
638 #define SNDBDS_SEL_CON_IDX_6 0x00001458
639 #define SNDBDS_SEL_CON_IDX_7 0x0000145c
640 #define SNDBDS_SEL_CON_IDX_8 0x00001460
641 #define SNDBDS_SEL_CON_IDX_9 0x00001464
642 #define SNDBDS_SEL_CON_IDX_10 0x00001468
643 #define SNDBDS_SEL_CON_IDX_11 0x0000146c
644 #define SNDBDS_SEL_CON_IDX_12 0x00001470
645 #define SNDBDS_SEL_CON_IDX_13 0x00001474
646 #define SNDBDS_SEL_CON_IDX_14 0x00001478
647 #define SNDBDS_SEL_CON_IDX_15 0x0000147c
648 /* 0x1480 --> 0x1800 unused */
650 /* Send BD initiator control registers */
651 #define SNDBDI_MODE 0x00001800
652 #define SNDBDI_MODE_RESET 0x00000001
653 #define SNDBDI_MODE_ENABLE 0x00000002
654 #define SNDBDI_MODE_ATTN_ENABLE 0x00000004
655 #define SNDBDI_STATUS 0x00001804
656 #define SNDBDI_STATUS_ERROR_ATTN 0x00000004
657 #define SNDBDI_IN_PROD_IDX_0 0x00001808
658 #define SNDBDI_IN_PROD_IDX_1 0x0000180c
659 #define SNDBDI_IN_PROD_IDX_2 0x00001810
660 #define SNDBDI_IN_PROD_IDX_3 0x00001814
661 #define SNDBDI_IN_PROD_IDX_4 0x00001818
662 #define SNDBDI_IN_PROD_IDX_5 0x0000181c
663 #define SNDBDI_IN_PROD_IDX_6 0x00001820
664 #define SNDBDI_IN_PROD_IDX_7 0x00001824
665 #define SNDBDI_IN_PROD_IDX_8 0x00001828
666 #define SNDBDI_IN_PROD_IDX_9 0x0000182c
667 #define SNDBDI_IN_PROD_IDX_10 0x00001830
668 #define SNDBDI_IN_PROD_IDX_11 0x00001834
669 #define SNDBDI_IN_PROD_IDX_12 0x00001838
670 #define SNDBDI_IN_PROD_IDX_13 0x0000183c
671 #define SNDBDI_IN_PROD_IDX_14 0x00001840
672 #define SNDBDI_IN_PROD_IDX_15 0x00001844
673 /* 0x1848 --> 0x1c00 unused */
675 /* Send BD completion control registers */
676 #define SNDBDC_MODE 0x00001c00
677 #define SNDBDC_MODE_RESET 0x00000001
678 #define SNDBDC_MODE_ENABLE 0x00000002
679 #define SNDBDC_MODE_ATTN_ENABLE 0x00000004
680 /* 0x1c04 --> 0x2000 unused */
682 /* Receive list placement control registers */
683 #define RCVLPC_MODE 0x00002000
684 #define RCVLPC_MODE_RESET 0x00000001
685 #define RCVLPC_MODE_ENABLE 0x00000002
686 #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
687 #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
688 #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
689 #define RCVLPC_STATUS 0x00002004
690 #define RCVLPC_STATUS_CLASS0 0x00000004
691 #define RCVLPC_STATUS_MAPOOR 0x00000008
692 #define RCVLPC_STATUS_STAT_OFLOW 0x00000010
693 #define RCVLPC_LOCK 0x00002008
694 #define RCVLPC_LOCK_REQ_MASK 0x0000ffff
695 #define RCVLPC_LOCK_REQ_SHIFT 0
696 #define RCVLPC_LOCK_GRANT_MASK 0xffff0000
697 #define RCVLPC_LOCK_GRANT_SHIFT 16
698 #define RCVLPC_NON_EMPTY_BITS 0x0000200c
699 #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
700 #define RCVLPC_CONFIG 0x00002010
701 #define RCVLPC_STATSCTRL 0x00002014
702 #define RCVLPC_STATSCTRL_ENABLE 0x00000001
703 #define RCVLPC_STATSCTRL_FASTUPD 0x00000002
704 #define RCVLPC_STATS_ENABLE 0x00002018
705 #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
706 #define RCVLPC_STATS_INCMASK 0x0000201c
707 /* 0x2020 --> 0x2100 unused */
708 #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
709 #define SELLST_TAIL 0x00000004
710 #define SELLST_CONT 0x00000008
711 #define SELLST_UNUSED 0x0000000c
712 #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
713 #define RCVLPC_DROP_FILTER_CNT 0x00002240
714 #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
715 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
716 #define RCVLPC_NO_RCV_BD_CNT 0x0000224c
717 #define RCVLPC_IN_DISCARDS_CNT 0x00002250
718 #define RCVLPC_IN_ERRORS_CNT 0x00002254
719 #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
720 /* 0x225c --> 0x2400 unused */
722 /* Receive Data and Receive BD Initiator Control */
723 #define RCVDBDI_MODE 0x00002400
724 #define RCVDBDI_MODE_RESET 0x00000001
725 #define RCVDBDI_MODE_ENABLE 0x00000002
726 #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
727 #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
728 #define RCVDBDI_MODE_INV_RING_SZ 0x00000010
729 #define RCVDBDI_STATUS 0x00002404
730 #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
731 #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
732 #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
733 #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
734 /* 0x240c --> 0x2440 unused */
735 #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
736 #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
737 #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
738 #define RCVDBDI_JUMBO_CON_IDX 0x00002470
739 #define RCVDBDI_STD_CON_IDX 0x00002474
740 #define RCVDBDI_MINI_CON_IDX 0x00002478
741 /* 0x247c --> 0x2480 unused */
742 #define RCVDBDI_BD_PROD_IDX_0 0x00002480
743 #define RCVDBDI_BD_PROD_IDX_1 0x00002484
744 #define RCVDBDI_BD_PROD_IDX_2 0x00002488
745 #define RCVDBDI_BD_PROD_IDX_3 0x0000248c
746 #define RCVDBDI_BD_PROD_IDX_4 0x00002490
747 #define RCVDBDI_BD_PROD_IDX_5 0x00002494
748 #define RCVDBDI_BD_PROD_IDX_6 0x00002498
749 #define RCVDBDI_BD_PROD_IDX_7 0x0000249c
750 #define RCVDBDI_BD_PROD_IDX_8 0x000024a0
751 #define RCVDBDI_BD_PROD_IDX_9 0x000024a4
752 #define RCVDBDI_BD_PROD_IDX_10 0x000024a8
753 #define RCVDBDI_BD_PROD_IDX_11 0x000024ac
754 #define RCVDBDI_BD_PROD_IDX_12 0x000024b0
755 #define RCVDBDI_BD_PROD_IDX_13 0x000024b4
756 #define RCVDBDI_BD_PROD_IDX_14 0x000024b8
757 #define RCVDBDI_BD_PROD_IDX_15 0x000024bc
758 #define RCVDBDI_HWDIAG 0x000024c0
759 /* 0x24c4 --> 0x2800 unused */
761 /* Receive Data Completion Control */
762 #define RCVDCC_MODE 0x00002800
763 #define RCVDCC_MODE_RESET 0x00000001
764 #define RCVDCC_MODE_ENABLE 0x00000002
765 #define RCVDCC_MODE_ATTN_ENABLE 0x00000004
766 /* 0x2804 --> 0x2c00 unused */
768 /* Receive BD Initiator Control Registers */
769 #define RCVBDI_MODE 0x00002c00
770 #define RCVBDI_MODE_RESET 0x00000001
771 #define RCVBDI_MODE_ENABLE 0x00000002
772 #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
773 #define RCVBDI_STATUS 0x00002c04
774 #define RCVBDI_STATUS_RCB_ATTN 0x00000004
775 #define RCVBDI_JUMBO_PROD_IDX 0x00002c08
776 #define RCVBDI_STD_PROD_IDX 0x00002c0c
777 #define RCVBDI_MINI_PROD_IDX 0x00002c10
778 #define RCVBDI_MINI_THRESH 0x00002c14
779 #define RCVBDI_STD_THRESH 0x00002c18
780 #define RCVBDI_JUMBO_THRESH 0x00002c1c
781 /* 0x2c20 --> 0x3000 unused */
783 /* Receive BD Completion Control Registers */
784 #define RCVCC_MODE 0x00003000
785 #define RCVCC_MODE_RESET 0x00000001
786 #define RCVCC_MODE_ENABLE 0x00000002
787 #define RCVCC_MODE_ATTN_ENABLE 0x00000004
788 #define RCVCC_STATUS 0x00003004
789 #define RCVCC_STATUS_ERROR_ATTN 0x00000004
790 #define RCVCC_JUMP_PROD_IDX 0x00003008
791 #define RCVCC_STD_PROD_IDX 0x0000300c
792 #define RCVCC_MINI_PROD_IDX 0x00003010
793 /* 0x3014 --> 0x3400 unused */
795 /* Receive list selector control registers */
796 #define RCVLSC_MODE 0x00003400
797 #define RCVLSC_MODE_RESET 0x00000001
798 #define RCVLSC_MODE_ENABLE 0x00000002
799 #define RCVLSC_MODE_ATTN_ENABLE 0x00000004
800 #define RCVLSC_STATUS 0x00003404
801 #define RCVLSC_STATUS_ERROR_ATTN 0x00000004
802 /* 0x3408 --> 0x3800 unused */
804 /* Mbuf cluster free registers */
805 #define MBFREE_MODE 0x00003800
806 #define MBFREE_MODE_RESET 0x00000001
807 #define MBFREE_MODE_ENABLE 0x00000002
808 #define MBFREE_STATUS 0x00003804
809 /* 0x3808 --> 0x3c00 unused */
811 /* Host coalescing control registers */
812 #define HOSTCC_MODE 0x00003c00
813 #define HOSTCC_MODE_RESET 0x00000001
814 #define HOSTCC_MODE_ENABLE 0x00000002
815 #define HOSTCC_MODE_ATTN 0x00000004
816 #define HOSTCC_MODE_NOW 0x00000008
817 #define HOSTCC_MODE_FULL_STATUS 0x00000000
818 #define HOSTCC_MODE_64BYTE 0x00000080
819 #define HOSTCC_MODE_32BYTE 0x00000100
820 #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
821 #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
822 #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
823 #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
824 #define HOSTCC_STATUS 0x00003c04
825 #define HOSTCC_STATUS_ERROR_ATTN 0x00000004
826 #define HOSTCC_RXCOL_TICKS 0x00003c08
827 #define LOW_RXCOL_TICKS 0x00000032
828 #define DEFAULT_RXCOL_TICKS 0x00000048
829 #define HIGH_RXCOL_TICKS 0x00000096
830 #define HOSTCC_TXCOL_TICKS 0x00003c0c
831 #define LOW_TXCOL_TICKS 0x00000096
832 #define DEFAULT_TXCOL_TICKS 0x0000012c
833 #define HIGH_TXCOL_TICKS 0x00000145
834 #define HOSTCC_RXMAX_FRAMES 0x00003c10
835 #define LOW_RXMAX_FRAMES 0x00000005
836 #define DEFAULT_RXMAX_FRAMES 0x00000008
837 #define HIGH_RXMAX_FRAMES 0x00000012
838 #define HOSTCC_TXMAX_FRAMES 0x00003c14
839 #define LOW_TXMAX_FRAMES 0x00000035
840 #define DEFAULT_TXMAX_FRAMES 0x0000004b
841 #define HIGH_TXMAX_FRAMES 0x00000052
842 #define HOSTCC_RXCOAL_TICK_INT 0x00003c18
843 #define DEFAULT_RXCOAL_TICK_INT 0x00000019
844 #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
845 #define DEFAULT_TXCOAL_TICK_INT 0x00000019
846 #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
847 #define DEFAULT_RXCOAL_MAXF_INT 0x00000005
848 #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
849 #define DEFAULT_TXCOAL_MAXF_INT 0x00000005
850 #define HOSTCC_STAT_COAL_TICKS 0x00003c28
851 #define DEFAULT_STAT_COAL_TICKS 0x000f4240
852 /* 0x3c2c --> 0x3c30 unused */
853 #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
854 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
855 #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
856 #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
857 #define HOSTCC_FLOW_ATTN 0x00003c48
858 /* 0x3c4c --> 0x3c50 unused */
859 #define HOSTCC_JUMBO_CON_IDX 0x00003c50
860 #define HOSTCC_STD_CON_IDX 0x00003c54
861 #define HOSTCC_MINI_CON_IDX 0x00003c58
862 /* 0x3c5c --> 0x3c80 unused */
863 #define HOSTCC_RET_PROD_IDX_0 0x00003c80
864 #define HOSTCC_RET_PROD_IDX_1 0x00003c84
865 #define HOSTCC_RET_PROD_IDX_2 0x00003c88
866 #define HOSTCC_RET_PROD_IDX_3 0x00003c8c
867 #define HOSTCC_RET_PROD_IDX_4 0x00003c90
868 #define HOSTCC_RET_PROD_IDX_5 0x00003c94
869 #define HOSTCC_RET_PROD_IDX_6 0x00003c98
870 #define HOSTCC_RET_PROD_IDX_7 0x00003c9c
871 #define HOSTCC_RET_PROD_IDX_8 0x00003ca0
872 #define HOSTCC_RET_PROD_IDX_9 0x00003ca4
873 #define HOSTCC_RET_PROD_IDX_10 0x00003ca8
874 #define HOSTCC_RET_PROD_IDX_11 0x00003cac
875 #define HOSTCC_RET_PROD_IDX_12 0x00003cb0
876 #define HOSTCC_RET_PROD_IDX_13 0x00003cb4
877 #define HOSTCC_RET_PROD_IDX_14 0x00003cb8
878 #define HOSTCC_RET_PROD_IDX_15 0x00003cbc
879 #define HOSTCC_SND_CON_IDX_0 0x00003cc0
880 #define HOSTCC_SND_CON_IDX_1 0x00003cc4
881 #define HOSTCC_SND_CON_IDX_2 0x00003cc8
882 #define HOSTCC_SND_CON_IDX_3 0x00003ccc
883 #define HOSTCC_SND_CON_IDX_4 0x00003cd0
884 #define HOSTCC_SND_CON_IDX_5 0x00003cd4
885 #define HOSTCC_SND_CON_IDX_6 0x00003cd8
886 #define HOSTCC_SND_CON_IDX_7 0x00003cdc
887 #define HOSTCC_SND_CON_IDX_8 0x00003ce0
888 #define HOSTCC_SND_CON_IDX_9 0x00003ce4
889 #define HOSTCC_SND_CON_IDX_10 0x00003ce8
890 #define HOSTCC_SND_CON_IDX_11 0x00003cec
891 #define HOSTCC_SND_CON_IDX_12 0x00003cf0
892 #define HOSTCC_SND_CON_IDX_13 0x00003cf4
893 #define HOSTCC_SND_CON_IDX_14 0x00003cf8
894 #define HOSTCC_SND_CON_IDX_15 0x00003cfc
895 /* 0x3d00 --> 0x4000 unused */
897 /* Memory arbiter control registers */
898 #define MEMARB_MODE 0x00004000
899 #define MEMARB_MODE_RESET 0x00000001
900 #define MEMARB_MODE_ENABLE 0x00000002
901 #define MEMARB_STATUS 0x00004004
902 #define MEMARB_TRAP_ADDR_LOW 0x00004008
903 #define MEMARB_TRAP_ADDR_HIGH 0x0000400c
904 /* 0x4010 --> 0x4400 unused */
906 /* Buffer manager control registers */
907 #define BUFMGR_MODE 0x00004400
908 #define BUFMGR_MODE_RESET 0x00000001
909 #define BUFMGR_MODE_ENABLE 0x00000002
910 #define BUFMGR_MODE_ATTN_ENABLE 0x00000004
911 #define BUFMGR_MODE_BM_TEST 0x00000008
912 #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
913 #define BUFMGR_STATUS 0x00004404
914 #define BUFMGR_STATUS_ERROR 0x00000004
915 #define BUFMGR_STATUS_MBLOW 0x00000010
916 #define BUFMGR_MB_POOL_ADDR 0x00004408
917 #define BUFMGR_MB_POOL_SIZE 0x0000440c
918 #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
919 #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
920 #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
921 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
922 #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
923 #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
924 #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
925 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
926 #define BUFMGR_MB_HIGH_WATER 0x00004418
927 #define DEFAULT_MB_HIGH_WATER 0x00000060
928 #define DEFAULT_MB_HIGH_WATER_5705 0x00000060
929 #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
930 #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
931 #define BUFMGR_MB_ALLOC_BIT 0x10000000
932 #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
933 #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
934 #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
935 #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
936 #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
937 #define BUFMGR_DMA_LOW_WATER 0x00004434
938 #define DEFAULT_DMA_LOW_WATER 0x00000005
939 #define BUFMGR_DMA_HIGH_WATER 0x00004438
940 #define DEFAULT_DMA_HIGH_WATER 0x0000000a
941 #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
942 #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
943 #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
944 #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
945 #define BUFMGR_HWDIAG_0 0x0000444c
946 #define BUFMGR_HWDIAG_1 0x00004450
947 #define BUFMGR_HWDIAG_2 0x00004454
948 /* 0x4458 --> 0x4800 unused */
950 /* Read DMA control registers */
951 #define RDMAC_MODE 0x00004800
952 #define RDMAC_MODE_RESET 0x00000001
953 #define RDMAC_MODE_ENABLE 0x00000002
954 #define RDMAC_MODE_TGTABORT_ENAB 0x00000004
955 #define RDMAC_MODE_MSTABORT_ENAB 0x00000008
956 #define RDMAC_MODE_PARITYERR_ENAB 0x00000010
957 #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
958 #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
959 #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
960 #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
961 #define RDMAC_MODE_LNGREAD_ENAB 0x00000200
962 #define RDMAC_MODE_SPLIT_ENABLE 0x00000800
963 #define RDMAC_MODE_SPLIT_RESET 0x00001000
964 #define RDMAC_MODE_FIFO_SIZE_128 0x00020000
965 #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
966 #define RDMAC_STATUS 0x00004804
967 #define RDMAC_STATUS_TGTABORT 0x00000004
968 #define RDMAC_STATUS_MSTABORT 0x00000008
969 #define RDMAC_STATUS_PARITYERR 0x00000010
970 #define RDMAC_STATUS_ADDROFLOW 0x00000020
971 #define RDMAC_STATUS_FIFOOFLOW 0x00000040
972 #define RDMAC_STATUS_FIFOURUN 0x00000080
973 #define RDMAC_STATUS_FIFOOREAD 0x00000100
974 #define RDMAC_STATUS_LNGREAD 0x00000200
975 /* 0x4808 --> 0x4c00 unused */
977 /* Write DMA control registers */
978 #define WDMAC_MODE 0x00004c00
979 #define WDMAC_MODE_RESET 0x00000001
980 #define WDMAC_MODE_ENABLE 0x00000002
981 #define WDMAC_MODE_TGTABORT_ENAB 0x00000004
982 #define WDMAC_MODE_MSTABORT_ENAB 0x00000008
983 #define WDMAC_MODE_PARITYERR_ENAB 0x00000010
984 #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
985 #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
986 #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
987 #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
988 #define WDMAC_MODE_LNGREAD_ENAB 0x00000200
989 #define WDMAC_MODE_RX_ACCEL 0x00000400
990 #define WDMAC_STATUS 0x00004c04
991 #define WDMAC_STATUS_TGTABORT 0x00000004
992 #define WDMAC_STATUS_MSTABORT 0x00000008
993 #define WDMAC_STATUS_PARITYERR 0x00000010
994 #define WDMAC_STATUS_ADDROFLOW 0x00000020
995 #define WDMAC_STATUS_FIFOOFLOW 0x00000040
996 #define WDMAC_STATUS_FIFOURUN 0x00000080
997 #define WDMAC_STATUS_FIFOOREAD 0x00000100
998 #define WDMAC_STATUS_LNGREAD 0x00000200
999 /* 0x4c08 --> 0x5000 unused */
1001 /* Per-cpu register offsets (arm9) */
1002 #define CPU_MODE 0x00000000
1003 #define CPU_MODE_RESET 0x00000001
1004 #define CPU_MODE_HALT 0x00000400
1005 #define CPU_STATE 0x00000004
1006 #define CPU_EVTMASK 0x00000008
1007 /* 0xc --> 0x1c reserved */
1008 #define CPU_PC 0x0000001c
1009 #define CPU_INSN 0x00000020
1010 #define CPU_SPAD_UFLOW 0x00000024
1011 #define CPU_WDOG_CLEAR 0x00000028
1012 #define CPU_WDOG_VECTOR 0x0000002c
1013 #define CPU_WDOG_PC 0x00000030
1014 #define CPU_HW_BP 0x00000034
1015 /* 0x38 --> 0x44 unused */
1016 #define CPU_WDOG_SAVED_STATE 0x00000044
1017 #define CPU_LAST_BRANCH_ADDR 0x00000048
1018 #define CPU_SPAD_UFLOW_SET 0x0000004c
1019 /* 0x50 --> 0x200 unused */
1020 #define CPU_R0 0x00000200
1021 #define CPU_R1 0x00000204
1022 #define CPU_R2 0x00000208
1023 #define CPU_R3 0x0000020c
1024 #define CPU_R4 0x00000210
1025 #define CPU_R5 0x00000214
1026 #define CPU_R6 0x00000218
1027 #define CPU_R7 0x0000021c
1028 #define CPU_R8 0x00000220
1029 #define CPU_R9 0x00000224
1030 #define CPU_R10 0x00000228
1031 #define CPU_R11 0x0000022c
1032 #define CPU_R12 0x00000230
1033 #define CPU_R13 0x00000234
1034 #define CPU_R14 0x00000238
1035 #define CPU_R15 0x0000023c
1036 #define CPU_R16 0x00000240
1037 #define CPU_R17 0x00000244
1038 #define CPU_R18 0x00000248
1039 #define CPU_R19 0x0000024c
1040 #define CPU_R20 0x00000250
1041 #define CPU_R21 0x00000254
1042 #define CPU_R22 0x00000258
1043 #define CPU_R23 0x0000025c
1044 #define CPU_R24 0x00000260
1045 #define CPU_R25 0x00000264
1046 #define CPU_R26 0x00000268
1047 #define CPU_R27 0x0000026c
1048 #define CPU_R28 0x00000270
1049 #define CPU_R29 0x00000274
1050 #define CPU_R30 0x00000278
1051 #define CPU_R31 0x0000027c
1052 /* 0x280 --> 0x400 unused */
1054 #define RX_CPU_BASE 0x00005000
1055 #define TX_CPU_BASE 0x00005400
1058 #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
1059 #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
1060 #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
1061 #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
1062 #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
1063 #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
1064 #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
1065 #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
1066 #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
1067 #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
1068 #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
1069 #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
1070 #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
1071 #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
1072 #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
1073 #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
1074 #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
1075 #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
1076 #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
1077 #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
1078 #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
1079 #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
1080 #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
1081 #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
1082 #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
1083 #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
1084 #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
1085 #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
1086 #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
1087 #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
1088 #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
1089 #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
1090 #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
1091 #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
1092 #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
1093 #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
1094 #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
1095 #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
1096 #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
1097 #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
1098 #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
1099 #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
1100 #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
1101 #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
1102 #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
1103 #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
1104 #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
1105 #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
1106 #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
1107 #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
1108 #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
1109 #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
1110 #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
1111 #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
1112 #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
1113 #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
1114 #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
1115 #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
1116 #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
1117 #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
1118 #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
1119 #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
1120 #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
1121 #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
1122 #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1123 #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1124 #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1125 #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1126 /* 0x5a10 --> 0x5c00 */
1128 /* Flow Through queues */
1129 #define FTQ_RESET 0x00005c00
1130 /* 0x5c04 --> 0x5c10 unused */
1131 #define FTQ_DMA_NORM_READ_CTL 0x00005c10
1132 #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1133 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1134 #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1135 #define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1136 #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1137 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1138 #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1139 #define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1140 #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1141 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1142 #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1143 #define FTQ_SEND_BD_COMP_CTL 0x00005c40
1144 #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1145 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1146 #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1147 #define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1148 #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1149 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1150 #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1151 #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1152 #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1153 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1154 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1155 #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1156 #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1157 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1158 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1159 #define FTQ_SWTYPE1_CTL 0x00005c80
1160 #define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1161 #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1162 #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1163 #define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1164 #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1165 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1166 #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1167 #define FTQ_HOST_COAL_CTL 0x00005ca0
1168 #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1169 #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1170 #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1171 #define FTQ_MAC_TX_CTL 0x00005cb0
1172 #define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1173 #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1174 #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1175 #define FTQ_MB_FREE_CTL 0x00005cc0
1176 #define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1177 #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1178 #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1179 #define FTQ_RCVBD_COMP_CTL 0x00005cd0
1180 #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1181 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1182 #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1183 #define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1184 #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1185 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1186 #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1187 #define FTQ_RCVDATA_INI_CTL 0x00005cf0
1188 #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1189 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1190 #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1191 #define FTQ_RCVDATA_COMP_CTL 0x00005d00
1192 #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1193 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1194 #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1195 #define FTQ_SWTYPE2_CTL 0x00005d10
1196 #define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1197 #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1198 #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1199 /* 0x5d20 --> 0x6000 unused */
1201 /* Message signaled interrupt registers */
1202 #define MSGINT_MODE 0x00006000
1203 #define MSGINT_MODE_RESET 0x00000001
1204 #define MSGINT_MODE_ENABLE 0x00000002
1205 #define MSGINT_STATUS 0x00006004
1206 #define MSGINT_FIFO 0x00006008
1207 /* 0x600c --> 0x6400 unused */
1209 /* DMA completion registers */
1210 #define DMAC_MODE 0x00006400
1211 #define DMAC_MODE_RESET 0x00000001
1212 #define DMAC_MODE_ENABLE 0x00000002
1213 /* 0x6404 --> 0x6800 unused */
1216 #define GRC_MODE 0x00006800
1217 #define GRC_MODE_UPD_ON_COAL 0x00000001
1218 #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1219 #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1220 #define GRC_MODE_BSWAP_DATA 0x00000010
1221 #define GRC_MODE_WSWAP_DATA 0x00000020
1222 #define GRC_MODE_SPLITHDR 0x00000100
1223 #define GRC_MODE_NOFRM_CRACKING 0x00000200
1224 #define GRC_MODE_INCL_CRC 0x00000400
1225 #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1226 #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1227 #define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1228 #define GRC_MODE_FORCE_PCI32BIT 0x00008000
1229 #define GRC_MODE_HOST_STACKUP 0x00010000
1230 #define GRC_MODE_HOST_SENDBDS 0x00020000
1231 #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1232 #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1233 #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1234 #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1235 #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1236 #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1237 #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1238 #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1239 #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1240 #define GRC_MISC_CFG 0x00006804
1241 #define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1242 #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1243 #define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1244 #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1245 #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1246 #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1247 #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1248 #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1249 #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1250 #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1251 #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1252 #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1253 #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1254 #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1255 #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1256 #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1257 #define GRC_LOCAL_CTRL 0x00006808
1258 #define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1259 #define GRC_LCLCTRL_CLEARINT 0x00000002
1260 #define GRC_LCLCTRL_SETINT 0x00000004
1261 #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
1262 #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1263 #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1264 #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1265 #define GRC_LCLCTRL_GPIO_OE0 0x00000800
1266 #define GRC_LCLCTRL_GPIO_OE1 0x00001000
1267 #define GRC_LCLCTRL_GPIO_OE2 0x00002000
1268 #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1269 #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1270 #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1271 #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1272 #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1273 #define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1274 #define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1275 #define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1276 #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1277 #define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1278 #define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1279 #define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1280 #define GRC_LCLCTRL_BANK_SELECT 0x00200000
1281 #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1282 #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1283 #define GRC_TIMER 0x0000680c
1284 #define GRC_RX_CPU_EVENT 0x00006810
1285 #define GRC_RX_TIMER_REF 0x00006814
1286 #define GRC_RX_CPU_SEM 0x00006818
1287 #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1288 #define GRC_TX_CPU_EVENT 0x00006820
1289 #define GRC_TX_TIMER_REF 0x00006824
1290 #define GRC_TX_CPU_SEM 0x00006828
1291 #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1292 #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
1293 #define GRC_EEPROM_ADDR 0x00006838
1294 #define EEPROM_ADDR_WRITE 0x00000000
1295 #define EEPROM_ADDR_READ 0x80000000
1296 #define EEPROM_ADDR_COMPLETE 0x40000000
1297 #define EEPROM_ADDR_FSM_RESET 0x20000000
1298 #define EEPROM_ADDR_DEVID_MASK 0x1c000000
1299 #define EEPROM_ADDR_DEVID_SHIFT 26
1300 #define EEPROM_ADDR_START 0x02000000
1301 #define EEPROM_ADDR_CLKPERD_SHIFT 16
1302 #define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1303 #define EEPROM_ADDR_ADDR_SHIFT 0
1304 #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1305 #define EEPROM_CHIP_SIZE (64 * 1024)
1306 #define GRC_EEPROM_DATA 0x0000683c
1307 #define GRC_EEPROM_CTRL 0x00006840
1308 #define GRC_MDI_CTRL 0x00006844
1309 #define GRC_SEEPROM_DELAY 0x00006848
1310 /* 0x684c --> 0x6c00 unused */
1312 /* 0x6c00 --> 0x7000 unused */
1314 /* NVRAM Control registers */
1315 #define NVRAM_CMD 0x00007000
1316 #define NVRAM_CMD_RESET 0x00000001
1317 #define NVRAM_CMD_DONE 0x00000008
1318 #define NVRAM_CMD_GO 0x00000010
1319 #define NVRAM_CMD_WR 0x00000020
1320 #define NVRAM_CMD_RD 0x00000000
1321 #define NVRAM_CMD_ERASE 0x00000040
1322 #define NVRAM_CMD_FIRST 0x00000080
1323 #define NVRAM_CMD_LAST 0x00000100
1324 #define NVRAM_STAT 0x00007004
1325 #define NVRAM_WRDATA 0x00007008
1326 #define NVRAM_ADDR 0x0000700c
1327 #define NVRAM_ADDR_MSK 0x00ffffff
1328 #define NVRAM_RDDATA 0x00007010
1329 #define NVRAM_CFG1 0x00007014
1330 #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1331 #define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1332 #define NVRAM_CFG1_PASS_THRU 0x00000004
1333 #define NVRAM_CFG1_BIT_BANG 0x00000008
1334 #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1335 #define NVRAM_CFG2 0x00007018
1336 #define NVRAM_CFG3 0x0000701c
1337 #define NVRAM_SWARB 0x00007020
1338 #define SWARB_REQ_SET0 0x00000001
1339 #define SWARB_REQ_SET1 0x00000002
1340 #define SWARB_REQ_SET2 0x00000004
1341 #define SWARB_REQ_SET3 0x00000008
1342 #define SWARB_REQ_CLR0 0x00000010
1343 #define SWARB_REQ_CLR1 0x00000020
1344 #define SWARB_REQ_CLR2 0x00000040
1345 #define SWARB_REQ_CLR3 0x00000080
1346 #define SWARB_GNT0 0x00000100
1347 #define SWARB_GNT1 0x00000200
1348 #define SWARB_GNT2 0x00000400
1349 #define SWARB_GNT3 0x00000800
1350 #define SWARB_REQ0 0x00001000
1351 #define SWARB_REQ1 0x00002000
1352 #define SWARB_REQ2 0x00004000
1353 #define SWARB_REQ3 0x00008000
1354 #define NVRAM_BUFFERED_PAGE_SIZE 264
1355 #define NVRAM_BUFFERED_PAGE_POS 9
1356 #define NVRAM_ACCESS 0x00007024
1357 #define ACCESS_ENABLE 0x00000001
1358 #define ACCESS_WR_ENABLE 0x00000002
1359 /* 0x7024 --> 0x7400 unused */
1361 /* 0x7400 --> 0x8000 unused */
1363 /* 32K Window into NIC internal memory */
1364 #define NIC_SRAM_WIN_BASE 0x00008000
1366 /* Offsets into first 32k of NIC internal memory. */
1367 #define NIC_SRAM_PAGE_ZERO 0x00000000
1368 #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
1369 #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
1370 #define NIC_SRAM_STATS_BLK 0x00000300
1371 #define NIC_SRAM_STATUS_BLK 0x00000b00
1373 #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
1374 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
1375 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
1377 #define NIC_SRAM_DATA_SIG 0x00000b54
1378 #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
1380 #define NIC_SRAM_DATA_CFG 0x00000b58
1381 #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
1382 #define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000
1383 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004
1384 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008
1385 #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
1386 #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
1387 #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
1388 #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
1389 #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
1390 #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
1391 #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
1392 #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
1393 #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
1395 #define NIC_SRAM_DATA_PHY_ID 0x00000b74
1396 #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
1397 #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
1399 #define NIC_SRAM_FW_CMD_MBOX 0x00000b78
1400 #define FWCMD_NICDRV_ALIVE 0x00000001
1401 #define FWCMD_NICDRV_PAUSE_FW 0x00000002
1402 #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
1403 #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
1404 #define FWCMD_NICDRV_FIX_DMAR 0x00000005
1405 #define FWCMD_NICDRV_FIX_DMAW 0x00000006
1406 #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
1407 #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
1408 #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
1409 #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
1410 #define DRV_STATE_START 0x00000001
1411 #define DRV_STATE_START_DONE 0x80000001
1412 #define DRV_STATE_UNLOAD 0x00000002
1413 #define DRV_STATE_UNLOAD_DONE 0x80000002
1414 #define DRV_STATE_WOL 0x00000003
1415 #define DRV_STATE_SUSPEND 0x00000004
1417 #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
1419 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
1420 #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
1422 #define NIC_SRAM_DATA_CFG_2 0x00000d38
1424 #define SHASTA_EXT_LED_MODE_MASK 0x00018000
1425 #define SHASTA_EXT_LED_LEGACY 0x00000000
1426 #define SHASTA_EXT_LED_SHARED 0x00008000
1427 #define SHASTA_EXT_LED_MAC 0x00010000
1428 #define SHASTA_EXT_LED_COMBO 0x00018000
1430 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
1432 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
1433 #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
1434 #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
1435 #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
1436 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
1437 #define NIC_SRAM_MBUF_POOL_BASE 0x00008000
1438 #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
1439 #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
1440 #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
1441 #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
1443 /* Currently this is fixed. */
1444 #define PHY_ADDR 0x01
1446 /* Tigon3 specific PHY MII registers. */
1447 #define TG3_BMCR_SPEED1000 0x0040
1449 #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */
1450 #define MII_TG3_CTRL_ADV_1000_HALF 0x0100
1451 #define MII_TG3_CTRL_ADV_1000_FULL 0x0200
1452 #define MII_TG3_CTRL_AS_MASTER 0x0800
1453 #define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
1455 #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
1456 #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
1457 #define MII_TG3_EXT_CTRL_TBI 0x8000
1459 #define MII_TG3_EXT_STAT 0x11 /* Extended status register */
1460 #define MII_TG3_EXT_STAT_LPASS 0x0100
1462 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
1464 #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
1466 #define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
1468 #define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */
1469 #define MII_TG3_AUX_STAT_LPASS 0x0004
1470 #define MII_TG3_AUX_STAT_SPDMASK 0x0700
1471 #define MII_TG3_AUX_STAT_10HALF 0x0100
1472 #define MII_TG3_AUX_STAT_10FULL 0x0200
1473 #define MII_TG3_AUX_STAT_100HALF 0x0300
1474 #define MII_TG3_AUX_STAT_100_4 0x0400
1475 #define MII_TG3_AUX_STAT_100FULL 0x0500
1476 #define MII_TG3_AUX_STAT_1000HALF 0x0600
1477 #define MII_TG3_AUX_STAT_1000FULL 0x0700
1479 #define MII_TG3_ISTAT 0x1a /* IRQ status register */
1480 #define MII_TG3_IMASK 0x1b /* IRQ mask register */
1482 /* ISTAT/IMASK event bits */
1483 #define MII_TG3_INT_LINKCHG 0x0002
1484 #define MII_TG3_INT_SPEEDCHG 0x0004
1485 #define MII_TG3_INT_DUPLEXCHG 0x0008
1486 #define MII_TG3_INT_ANEG_PAGE_RX 0x0400
1488 /* XXX Add this to mii.h */
1489 #ifndef ADVERTISE_PAUSE
1490 #define ADVERTISE_PAUSE_CAP 0x0400
1492 #ifndef ADVERTISE_PAUSE_ASYM
1493 #define ADVERTISE_PAUSE_ASYM 0x0800
1496 #define LPA_PAUSE_CAP 0x0400
1498 #ifndef LPA_PAUSE_ASYM
1499 #define LPA_PAUSE_ASYM 0x0800
1502 /* There are two ways to manage the TX descriptors on the tigon3.
1503 * Either the descriptors are in host DMA'able memory, or they
1504 * exist only in the cards on-chip SRAM. All 16 send bds are under
1505 * the same mode, they may not be configured individually.
1507 * The mode we use is controlled by TG3_FLAG_HOST_TXDS in tp->tg3_flags.
1509 * To use host memory TX descriptors:
1510 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
1511 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
1512 * 2) Allocate DMA'able memory.
1513 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1514 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
1515 * obtained in step 2
1516 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
1517 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
1518 * of TX descriptors. Leave flags field clear.
1519 * 4) Access TX descriptors via host memory. The chip
1520 * will refetch into local SRAM as needed when producer
1521 * index mailboxes are updated.
1523 * To use on-chip TX descriptors:
1524 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
1525 * Make sure GRC_MODE_HOST_SENDBDS is clear.
1526 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1527 * a) Set TG3_BDINFO_HOST_ADDR to zero.
1528 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
1529 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
1530 * 3) Access TX descriptors directly in on-chip SRAM
1531 * using normal {read,write}l(). (and not using
1532 * pointer dereferencing of ioremap()'d memory like
1533 * the broken Broadcom driver does)
1535 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
1536 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
1538 struct tg3_tx_buffer_desc {
1543 #define TXD_FLAG_TCPUDP_CSUM 0x0001
1544 #define TXD_FLAG_IP_CSUM 0x0002
1545 #define TXD_FLAG_END 0x0004
1546 #define TXD_FLAG_IP_FRAG 0x0008
1547 #define TXD_FLAG_IP_FRAG_END 0x0010
1548 #define TXD_FLAG_VLAN 0x0040
1549 #define TXD_FLAG_COAL_NOW 0x0080
1550 #define TXD_FLAG_CPU_PRE_DMA 0x0100
1551 #define TXD_FLAG_CPU_POST_DMA 0x0200
1552 #define TXD_FLAG_ADD_SRC_ADDR 0x1000
1553 #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
1554 #define TXD_FLAG_NO_CRC 0x8000
1555 #define TXD_LEN_SHIFT 16
1558 #define TXD_VLAN_TAG_SHIFT 0
1559 #define TXD_MSS_SHIFT 16
1562 #define TXD_ADDR 0x00UL /* 64-bit */
1563 #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
1564 #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
1565 #define TXD_SIZE 0x10UL
1567 struct tg3_rx_buffer_desc {
1572 #define RXD_IDX_MASK 0xffff0000
1573 #define RXD_IDX_SHIFT 16
1574 #define RXD_LEN_MASK 0x0000ffff
1575 #define RXD_LEN_SHIFT 0
1578 #define RXD_TYPE_SHIFT 16
1579 #define RXD_FLAGS_SHIFT 0
1581 #define RXD_FLAG_END 0x0004
1582 #define RXD_FLAG_MINI 0x0800
1583 #define RXD_FLAG_JUMBO 0x0020
1584 #define RXD_FLAG_VLAN 0x0040
1585 #define RXD_FLAG_ERROR 0x0400
1586 #define RXD_FLAG_IP_CSUM 0x1000
1587 #define RXD_FLAG_TCPUDP_CSUM 0x2000
1588 #define RXD_FLAG_IS_TCP 0x4000
1591 #define RXD_IPCSUM_MASK 0xffff0000
1592 #define RXD_IPCSUM_SHIFT 16
1593 #define RXD_TCPCSUM_MASK 0x0000ffff
1594 #define RXD_TCPCSUM_SHIFT 0
1598 #define RXD_VLAN_MASK 0x0000ffff
1600 #define RXD_ERR_BAD_CRC 0x00010000
1601 #define RXD_ERR_COLLISION 0x00020000
1602 #define RXD_ERR_LINK_LOST 0x00040000
1603 #define RXD_ERR_PHY_DECODE 0x00080000
1604 #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
1605 #define RXD_ERR_MAC_ABRT 0x00200000
1606 #define RXD_ERR_TOO_SMALL 0x00400000
1607 #define RXD_ERR_NO_RESOURCES 0x00800000
1608 #define RXD_ERR_HUGE_FRAME 0x01000000
1609 #define RXD_ERR_MASK 0xffff0000
1613 #define RXD_OPAQUE_INDEX_MASK 0x0000ffff
1614 #define RXD_OPAQUE_INDEX_SHIFT 0
1615 #define RXD_OPAQUE_RING_STD 0x00010000
1616 #define RXD_OPAQUE_RING_JUMBO 0x00020000
1617 #define RXD_OPAQUE_RING_MINI 0x00040000
1618 #define RXD_OPAQUE_RING_MASK 0x00070000
1621 struct tg3_ext_rx_buffer_desc {
1628 struct tg3_rx_buffer_desc std;
1631 /* We only use this when testing out the DMA engine
1632 * at probe time. This is the internal format of buffer
1633 * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
1635 struct tg3_internal_buffer_desc {
1653 #define TG3_HW_STATUS_SIZE 0x50
1654 struct tg3_hw_status {
1656 #define SD_STATUS_UPDATED 0x00000001
1657 #define SD_STATUS_LINK_CHG 0x00000002
1658 #define SD_STATUS_ERROR 0x00000004
1664 u16 rx_jumbo_consumer;
1666 u16 rx_jumbo_consumer;
1672 u16 rx_mini_consumer;
1674 u16 rx_mini_consumer;
1692 struct tg3_hw_stats {
1693 u8 __reserved0[0x400-0x300];
1695 /* Statistics maintained by Receive MAC. */
1696 tg3_stat64_t rx_octets;
1698 tg3_stat64_t rx_fragments;
1699 tg3_stat64_t rx_ucast_packets;
1700 tg3_stat64_t rx_mcast_packets;
1701 tg3_stat64_t rx_bcast_packets;
1702 tg3_stat64_t rx_fcs_errors;
1703 tg3_stat64_t rx_align_errors;
1704 tg3_stat64_t rx_xon_pause_rcvd;
1705 tg3_stat64_t rx_xoff_pause_rcvd;
1706 tg3_stat64_t rx_mac_ctrl_rcvd;
1707 tg3_stat64_t rx_xoff_entered;
1708 tg3_stat64_t rx_frame_too_long_errors;
1709 tg3_stat64_t rx_jabbers;
1710 tg3_stat64_t rx_undersize_packets;
1711 tg3_stat64_t rx_in_length_errors;
1712 tg3_stat64_t rx_out_length_errors;
1713 tg3_stat64_t rx_64_or_less_octet_packets;
1714 tg3_stat64_t rx_65_to_127_octet_packets;
1715 tg3_stat64_t rx_128_to_255_octet_packets;
1716 tg3_stat64_t rx_256_to_511_octet_packets;
1717 tg3_stat64_t rx_512_to_1023_octet_packets;
1718 tg3_stat64_t rx_1024_to_1522_octet_packets;
1719 tg3_stat64_t rx_1523_to_2047_octet_packets;
1720 tg3_stat64_t rx_2048_to_4095_octet_packets;
1721 tg3_stat64_t rx_4096_to_8191_octet_packets;
1722 tg3_stat64_t rx_8192_to_9022_octet_packets;
1726 /* Statistics maintained by Transmit MAC. */
1727 tg3_stat64_t tx_octets;
1729 tg3_stat64_t tx_collisions;
1730 tg3_stat64_t tx_xon_sent;
1731 tg3_stat64_t tx_xoff_sent;
1732 tg3_stat64_t tx_flow_control;
1733 tg3_stat64_t tx_mac_errors;
1734 tg3_stat64_t tx_single_collisions;
1735 tg3_stat64_t tx_mult_collisions;
1736 tg3_stat64_t tx_deferred;
1738 tg3_stat64_t tx_excessive_collisions;
1739 tg3_stat64_t tx_late_collisions;
1740 tg3_stat64_t tx_collide_2times;
1741 tg3_stat64_t tx_collide_3times;
1742 tg3_stat64_t tx_collide_4times;
1743 tg3_stat64_t tx_collide_5times;
1744 tg3_stat64_t tx_collide_6times;
1745 tg3_stat64_t tx_collide_7times;
1746 tg3_stat64_t tx_collide_8times;
1747 tg3_stat64_t tx_collide_9times;
1748 tg3_stat64_t tx_collide_10times;
1749 tg3_stat64_t tx_collide_11times;
1750 tg3_stat64_t tx_collide_12times;
1751 tg3_stat64_t tx_collide_13times;
1752 tg3_stat64_t tx_collide_14times;
1753 tg3_stat64_t tx_collide_15times;
1754 tg3_stat64_t tx_ucast_packets;
1755 tg3_stat64_t tx_mcast_packets;
1756 tg3_stat64_t tx_bcast_packets;
1757 tg3_stat64_t tx_carrier_sense_errors;
1758 tg3_stat64_t tx_discards;
1759 tg3_stat64_t tx_errors;
1763 /* Statistics maintained by Receive List Placement. */
1764 tg3_stat64_t COS_rx_packets[16];
1765 tg3_stat64_t COS_rx_filter_dropped;
1766 tg3_stat64_t dma_writeq_full;
1767 tg3_stat64_t dma_write_prioq_full;
1768 tg3_stat64_t rxbds_empty;
1769 tg3_stat64_t rx_discards;
1770 tg3_stat64_t rx_errors;
1771 tg3_stat64_t rx_threshold_hit;
1775 /* Statistics maintained by Send Data Initiator. */
1776 tg3_stat64_t COS_out_packets[16];
1777 tg3_stat64_t dma_readq_full;
1778 tg3_stat64_t dma_read_prioq_full;
1779 tg3_stat64_t tx_comp_queue_full;
1781 /* Statistics maintained by Host Coalescing. */
1782 tg3_stat64_t ring_set_send_prod_index;
1783 tg3_stat64_t ring_status_update;
1784 tg3_stat64_t nic_irqs;
1785 tg3_stat64_t nic_avoided_irqs;
1786 tg3_stat64_t nic_tx_threshold_hit;
1788 u8 __reserved4[0xb00-0x9c0];
1791 /* 'mapping' is superfluous as the chip does not write into
1792 * the tx/rx post rings so we could just fetch it from there.
1793 * But the cache behavior is better how we are doing it now.
1796 struct sk_buff *skb;
1797 DECLARE_PCI_UNMAP_ADDR(mapping)
1800 struct tx_ring_info {
1801 struct sk_buff *skb;
1802 DECLARE_PCI_UNMAP_ADDR(mapping)
1806 struct tg3_config_info {
1810 struct tg3_link_config {
1811 /* Describes what we're trying to get. */
1817 /* Describes what we actually have. */
1820 #define SPEED_INVALID 0xffff
1821 #define DUPLEX_INVALID 0xff
1822 #define AUTONEG_INVALID 0xff
1824 /* When we go in and out of low power mode we need
1825 * to swap with this state.
1827 int phy_is_low_power;
1833 struct tg3_bufmgr_config {
1834 u32 mbuf_read_dma_low_water;
1835 u32 mbuf_mac_rx_low_water;
1836 u32 mbuf_high_water;
1838 u32 mbuf_read_dma_low_water_jumbo;
1839 u32 mbuf_mac_rx_low_water_jumbo;
1840 u32 mbuf_high_water_jumbo;
1846 struct tg3_ethtool_stats {
1847 /* Statistics maintained by Receive MAC. */
1850 u64 rx_ucast_packets;
1851 u64 rx_mcast_packets;
1852 u64 rx_bcast_packets;
1854 u64 rx_align_errors;
1855 u64 rx_xon_pause_rcvd;
1856 u64 rx_xoff_pause_rcvd;
1857 u64 rx_mac_ctrl_rcvd;
1858 u64 rx_xoff_entered;
1859 u64 rx_frame_too_long_errors;
1861 u64 rx_undersize_packets;
1862 u64 rx_in_length_errors;
1863 u64 rx_out_length_errors;
1864 u64 rx_64_or_less_octet_packets;
1865 u64 rx_65_to_127_octet_packets;
1866 u64 rx_128_to_255_octet_packets;
1867 u64 rx_256_to_511_octet_packets;
1868 u64 rx_512_to_1023_octet_packets;
1869 u64 rx_1024_to_1522_octet_packets;
1870 u64 rx_1523_to_2047_octet_packets;
1871 u64 rx_2048_to_4095_octet_packets;
1872 u64 rx_4096_to_8191_octet_packets;
1873 u64 rx_8192_to_9022_octet_packets;
1875 /* Statistics maintained by Transmit MAC. */
1880 u64 tx_flow_control;
1882 u64 tx_single_collisions;
1883 u64 tx_mult_collisions;
1885 u64 tx_excessive_collisions;
1886 u64 tx_late_collisions;
1887 u64 tx_collide_2times;
1888 u64 tx_collide_3times;
1889 u64 tx_collide_4times;
1890 u64 tx_collide_5times;
1891 u64 tx_collide_6times;
1892 u64 tx_collide_7times;
1893 u64 tx_collide_8times;
1894 u64 tx_collide_9times;
1895 u64 tx_collide_10times;
1896 u64 tx_collide_11times;
1897 u64 tx_collide_12times;
1898 u64 tx_collide_13times;
1899 u64 tx_collide_14times;
1900 u64 tx_collide_15times;
1901 u64 tx_ucast_packets;
1902 u64 tx_mcast_packets;
1903 u64 tx_bcast_packets;
1904 u64 tx_carrier_sense_errors;
1908 /* Statistics maintained by Receive List Placement. */
1909 u64 dma_writeq_full;
1910 u64 dma_write_prioq_full;
1914 u64 rx_threshold_hit;
1916 /* Statistics maintained by Send Data Initiator. */
1918 u64 dma_read_prioq_full;
1919 u64 tx_comp_queue_full;
1921 /* Statistics maintained by Host Coalescing. */
1922 u64 ring_set_send_prod_index;
1923 u64 ring_status_update;
1925 u64 nic_avoided_irqs;
1926 u64 nic_tx_threshold_hit;
1930 /* begin "general, frequently-used members" cacheline section */
1932 /* SMP locking strategy:
1934 * lock: Held during all operations except TX packet
1937 * tx_lock: Held during tg3_start_xmit{,_4gbug} and tg3_tx
1939 * If you want to shut up all asynchronous processing you must
1940 * acquire both locks, 'lock' taken before 'tx_lock'. IRQs must
1941 * be disabled to take 'lock' but only softirq disabling is
1942 * necessary for acquisition of 'tx_lock'.
1945 spinlock_t indirect_lock;
1948 struct net_device *dev;
1949 struct pci_dev *pdev;
1951 struct tg3_hw_status *hw_status;
1952 dma_addr_t status_mapping;
1956 /* begin "tx thread" cacheline section */
1963 /* TX descs are only used if TG3_FLAG_HOST_TXDS is set. */
1964 struct tg3_tx_buffer_desc *tx_ring;
1965 struct tx_ring_info *tx_buffers;
1966 dma_addr_t tx_desc_mapping;
1968 /* begin "rx thread" cacheline section */
1973 u32 rx_jumbo_pending;
1974 #if TG3_VLAN_TAG_USED
1975 struct vlan_group *vlgrp;
1978 struct tg3_rx_buffer_desc *rx_std;
1979 struct ring_info *rx_std_buffers;
1980 dma_addr_t rx_std_mapping;
1982 struct tg3_rx_buffer_desc *rx_jumbo;
1983 struct ring_info *rx_jumbo_buffers;
1984 dma_addr_t rx_jumbo_mapping;
1986 struct tg3_rx_buffer_desc *rx_rcb;
1987 dma_addr_t rx_rcb_mapping;
1989 /* begin "everything else" cacheline(s) section */
1990 struct net_device_stats net_stats;
1991 struct net_device_stats net_stats_prev;
1992 struct tg3_ethtool_stats estats;
1993 struct tg3_ethtool_stats estats_prev;
1995 unsigned long phy_crc_errors;
1999 #define TG3_FLAG_HOST_TXDS 0x00000001
2000 #define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
2001 #define TG3_FLAG_RX_CHECKSUMS 0x00000004
2002 #define TG3_FLAG_USE_LINKCHG_REG 0x00000008
2003 #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010
2004 #define TG3_FLAG_ENABLE_ASF 0x00000020
2005 #define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040
2006 #define TG3_FLAG_POLL_SERDES 0x00000080
2007 #if defined(CONFIG_X86)
2008 #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
2010 #define TG3_FLAG_MBOX_WRITE_REORDER 0 /* disables code too */
2012 #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
2013 #define TG3_FLAG_WOL_SPEED_100MB 0x00000400
2014 #define TG3_FLAG_WOL_ENABLE 0x00000800
2015 #define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000
2016 #define TG3_FLAG_NVRAM 0x00002000
2017 #define TG3_FLAG_NVRAM_BUFFERED 0x00004000
2018 #define TG3_FLAG_RX_PAUSE 0x00008000
2019 #define TG3_FLAG_TX_PAUSE 0x00010000
2020 #define TG3_FLAG_PCIX_MODE 0x00020000
2021 #define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
2022 #define TG3_FLAG_PCI_32BIT 0x00080000
2023 #define TG3_FLAG_NO_TX_PSEUDO_CSUM 0x00100000
2024 #define TG3_FLAG_NO_RX_PSEUDO_CSUM 0x00200000
2025 #define TG3_FLAG_SERDES_WOL_CAP 0x00400000
2026 #define TG3_FLAG_JUMBO_ENABLE 0x00800000
2027 #define TG3_FLAG_10_100_ONLY 0x01000000
2028 #define TG3_FLAG_PAUSE_AUTONEG 0x02000000
2029 #define TG3_FLAG_PAUSE_RX 0x04000000
2030 #define TG3_FLAG_PAUSE_TX 0x08000000
2031 #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
2032 #define TG3_FLAG_GOT_SERDES_FLOWCTL 0x20000000
2033 #define TG3_FLAG_SPLIT_MODE 0x40000000
2034 #define TG3_FLAG_INIT_COMPLETE 0x80000000
2036 #define TG3_FLG2_RESTART_TIMER 0x00000001
2037 #define TG3_FLG2_SUN_5704 0x00000002
2038 #define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
2039 #define TG3_FLG2_IS_5788 0x00000008
2040 #define TG3_FLG2_MAX_RXPEND_64 0x00000010
2041 #define TG3_FLG2_TSO_CAPABLE 0x00000020
2042 #define TG3_FLG2_PHY_ADC_BUG 0x00000040
2043 #define TG3_FLG2_PHY_5704_A0_BUG 0x00000080
2044 #define TG3_FLG2_PHY_BER_BUG 0x00000100
2045 #define TG3_FLG2_PCI_EXPRESS 0x00000200
2046 #define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400
2048 u32 split_mode_max_reqs;
2049 #define SPLIT_MODE_5704_MAX_REQ 3
2051 struct timer_list timer;
2053 u16 timer_multiplier;
2058 struct tg3_link_config link_config;
2059 struct tg3_bufmgr_config bufmgr_config;
2061 /* cache h/w values, often passed straight to h/w */
2073 u16 pci_chip_rev_id;
2074 u8 pci_cacheline_sz;
2078 u32 pci_cfg_state[64 / sizeof(u32)];
2084 #define PHY_ID_MASK 0xfffffff0
2085 #define PHY_ID_BCM5400 0x60008040
2086 #define PHY_ID_BCM5401 0x60008050
2087 #define PHY_ID_BCM5411 0x60008070
2088 #define PHY_ID_BCM5701 0x60008110
2089 #define PHY_ID_BCM5703 0x60008160
2090 #define PHY_ID_BCM5704 0x60008190
2091 #define PHY_ID_BCM5705 0x600081a0
2092 #define PHY_ID_BCM5750 0x60008180
2093 #define PHY_ID_BCM8002 0x60010140
2094 #define PHY_ID_SERDES 0xfeedbee0
2095 #define PHY_ID_INVALID 0xffffffff
2096 #define PHY_ID_REV_MASK 0x0000000f
2097 #define PHY_REV_BCM5401_B0 0x1
2098 #define PHY_REV_BCM5401_B2 0x3
2099 #define PHY_REV_BCM5401_C0 0x6
2100 #define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
2104 char board_part_number[24];
2105 u32 nic_sram_data_cfg;
2107 struct pci_dev *pdev_peer;
2109 /* This macro assumes the passed PHY ID is already masked
2112 #define KNOWN_PHY_ID(X) \
2113 ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
2114 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
2115 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
2116 (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
2117 (X) == PHY_ID_BCM8002 || (X) == PHY_ID_SERDES)
2119 struct tg3_hw_stats *hw_stats;
2120 dma_addr_t stats_mapping;
2121 struct work_struct reset_task;
2124 #endif /* !(_T3_H) */