1 /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
4 Copyright 1994, 1995 Digital Equipment Corporation.
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
9 The author may be reached at davies@maniac.ultranet.com.
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
38 DE500 10/100 PCI Fasternet
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
50 So far the driver is known to work with the following cards:
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
82 Upto 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
99 To utilise this ability, you have to do 8 things:
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
108 insmod de4x5 io=0xghh where g = bus number
111 NB: autoprobing for modules is now supported by default. You may just
116 to load all available boards. For a specific board, still use
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
207 autosense to set the media/speed; with the following
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
244 Version Date Description
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
255 Fix missed frame counter value and initialisation.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
283 Add new autosense algorithms for media/mode
284 selection using kernel scheduling/timing.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
295 Duh, put the SA_SHIRQ flag into request_interrupt().
296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
310 reported by <koen.gadeyne@barco.com> and
311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
313 reported by <csd@microplex.com> and
314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
356 Added SA_INTERRUPT temporary fix from
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
365 Completed DC2114[23] autosense functions.
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
368 Fix type1_infoblock() bug introduced in 0.53, from
370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
376 Fix the mess in 2.1.67.
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
401 Fix is_anc_capable() bug reported by
402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
416 kernels and modules from bug report by
417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
428 0.545 28-Nov-99 Further Moto SROM bug fix from
429 <mporter@eng.mcd.mot.com>
430 Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
433 was causing a page fault when initializing the
434 variable 'pb', on a non de4x5 PCI device, in this
435 case a PCI bridge (DEC chip 21152). The value of
436 'pb' is now only initialized if a de4x5 chip is
438 <france@handhelds.org>
439 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com>
440 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and
441 generic DMA APIs. Fixed DE425 support on Alpha.
442 <maz@wild-wind.fr.eu.org>
443 =========================================================================
446 #include <linux/config.h>
447 #include <linux/module.h>
448 #include <linux/kernel.h>
449 #include <linux/string.h>
450 #include <linux/interrupt.h>
451 #include <linux/ptrace.h>
452 #include <linux/errno.h>
453 #include <linux/ioport.h>
454 #include <linux/slab.h>
455 #include <linux/pci.h>
456 #include <linux/eisa.h>
457 #include <linux/delay.h>
458 #include <linux/init.h>
459 #include <linux/spinlock.h>
460 #include <linux/crc32.h>
461 #include <linux/netdevice.h>
462 #include <linux/etherdevice.h>
463 #include <linux/skbuff.h>
464 #include <linux/time.h>
465 #include <linux/types.h>
466 #include <linux/unistd.h>
467 #include <linux/ctype.h>
468 #include <linux/dma-mapping.h>
469 #include <linux/moduleparam.h>
471 #include <asm/bitops.h>
474 #include <asm/byteorder.h>
475 #include <asm/unaligned.h>
476 #include <asm/uaccess.h>
477 #ifdef CONFIG_PPC_MULTIPLATFORM
478 #include <asm/machdep.h>
479 #endif /* CONFIG_PPC_MULTIPLATFORM */
483 static char version[] __devinitdata = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
485 #define c_char const char
486 #define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a)))
492 int reset; /* Hard reset required? */
493 int id; /* IEEE OUI */
494 int ta; /* One cycle TA time - 802.3u is confusing here */
495 struct { /* Non autonegotiation (parallel) speed det. */
503 int reset; /* Hard reset required? */
504 int id; /* IEEE OUI */
505 int ta; /* One cycle TA time */
506 struct { /* Non autonegotiation (parallel) speed det. */
511 int addr; /* MII address for the PHY */
512 u_char *gep; /* Start of GEP sequence block in SROM */
513 u_char *rst; /* Start of reset sequence in SROM */
514 u_int mc; /* Media Capabilities */
515 u_int ana; /* NWay Advertisement */
516 u_int fdx; /* Full DupleX capabilites for each media */
517 u_int ttm; /* Transmit Threshold Mode for each media */
518 u_int mci; /* 21142 MII Connector Interrupt info */
521 #define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
524 u_char mc; /* Media Code */
525 u_char ext; /* csr13-15 valid when set */
526 int csr13; /* SIA Connectivity Register */
527 int csr14; /* SIA TX/RX Register */
528 int csr15; /* SIA General Register */
529 int gepc; /* SIA GEP Control Information */
530 int gep; /* SIA GEP Data */
534 ** Define the know universe of PHY devices that can be
535 ** recognised by this driver.
537 static struct phy_table phy_info[] = {
538 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
539 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
540 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
541 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
542 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
546 ** These GENERIC values assumes that the PHY devices follow 802.3u and
547 ** allow parallel detection to set the link partner ability register.
548 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
550 #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
551 #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
552 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
555 ** Define special SROM detection cases
557 static c_char enet_det[][ETH_ALEN] = {
558 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
559 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
566 ** SROM Repair definitions. If a broken SROM is detected a card may
567 ** use this information to help figure out what to do. This is a
568 ** "stab in the dark" and so far for SMC9332's only.
570 static c_char srom_repair_info[][100] = {
571 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
572 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
573 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
579 static int de4x5_debug = DE4X5_DEBUG;
581 /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
582 static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
586 ** Allow per adapter set up. For modules this is simply a command line
588 ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
590 ** For a compiled in driver, place e.g.
591 ** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
595 static char *args = DE4X5_PARM;
605 #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
607 #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
610 ** Ethernet PROM defines
612 #define PROBE_LENGTH 32
613 #define ETH_PROM_SIG 0xAA5500FFUL
618 #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
619 #define IEEE802_3_SZ 1518 /* Packet + CRC */
620 #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
621 #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
622 #define MIN_DAT_SZ 1 /* Minimum ethernet data length */
623 #define PKT_HDR_LEN 14 /* Addresses and data length info */
624 #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
625 #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
631 #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
632 #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
634 #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
636 #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
637 #define DE4X5_NAME_LENGTH 8
639 static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
642 ** Ethernet PROM defines for DC21040
644 #define PROBE_LENGTH 32
645 #define ETH_PROM_SIG 0xAA5500FFUL
650 #define PCI_MAX_BUS_NUM 8
651 #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
652 #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
655 ** Memory Alignment. Each descriptor is 4 longwords long. To force a
656 ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
657 ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
658 ** and hence the RX descriptor ring's first entry.
660 #define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
661 #define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
662 #define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
663 #define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
664 #define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
665 #define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
667 #define DE4X5_ALIGN DE4X5_ALIGN32 /* Keep the DC21040 happy... */
668 #define DE4X5_CACHE_ALIGN CAL_16LONG
669 #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
670 /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
673 #ifndef DEC_ONLY /* See README.de4x5 for using this */
676 static int dec_only = 1;
680 ** DE4X5 IRQ ENABLE/DISABLE
682 #define ENABLE_IRQs { \
684 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
687 #define DISABLE_IRQs {\
688 imr = inl(DE4X5_IMR);\
690 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
693 #define UNMASK_IRQs {\
694 imr |= lp->irq_mask;\
695 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
699 imr = inl(DE4X5_IMR);\
700 imr &= ~lp->irq_mask;\
701 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
707 #define START_DE4X5 {\
708 omr = inl(DE4X5_OMR);\
709 omr |= OMR_ST | OMR_SR;\
710 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
713 #define STOP_DE4X5 {\
714 omr = inl(DE4X5_OMR);\
715 omr &= ~(OMR_ST|OMR_SR);\
716 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
722 #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
725 ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
727 #define DE4X5_AUTOSENSE_MS 250
733 char sub_vendor_id[2];
734 char sub_system_id[2];
739 char num_controllers;
744 #define SUB_VENDOR_ID 0x500a
747 ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
748 ** and have sizes of both a power of 2 and a multiple of 4.
749 ** A size of 256 bytes for each buffer could be chosen because over 90% of
750 ** all packets in our network are <256 bytes long and 64 longword alignment
751 ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
752 ** descriptors are needed for machines with an ALPHA CPU.
754 #define NUM_RX_DESC 8 /* Number of RX descriptors */
755 #define NUM_TX_DESC 32 /* Number of TX descriptors */
756 #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
757 /* Multiple of 4 for DC21040 */
758 /* Allows 512 byte alignment */
768 ** The DE4X5 private structure
770 #define DE4X5_PKT_STAT_SZ 16
771 #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
772 increase DE4X5_PKT_STAT_SZ */
775 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
779 u_int excessive_collisions;
781 u_int excessive_underruns;
782 u_int rx_runt_frames;
788 struct de4x5_private {
789 char adapter_name[80]; /* Adapter name */
790 u_long interrupt; /* Aligned ISR flag */
791 struct de4x5_desc *rx_ring; /* RX descriptor ring */
792 struct de4x5_desc *tx_ring; /* TX descriptor ring */
793 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
794 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
795 int rx_new, rx_old; /* RX descriptor ring pointers */
796 int tx_new, tx_old; /* TX descriptor ring pointers */
797 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
798 char frame[64]; /* Min sized packet for loopback*/
799 spinlock_t lock; /* Adapter specific spinlock */
800 struct net_device_stats stats; /* Public stats */
801 struct pkt_stats pktStats; /* Private stats counters */
804 int bus; /* EISA or PCI */
805 int bus_num; /* PCI Bus number */
806 int device; /* Device number on PCI bus */
807 int state; /* Adapter OPENED or CLOSED */
808 int chipset; /* DC21040, DC21041 or DC21140 */
809 s32 irq_mask; /* Interrupt Mask (Enable) bits */
810 s32 irq_en; /* Summary interrupt bits */
811 int media; /* Media (eg TP), mode (eg 100B)*/
812 int c_media; /* Remember the last media conn */
813 int fdx; /* media full duplex flag */
814 int linkOK; /* Link is OK */
815 int autosense; /* Allow/disallow autosensing */
816 int tx_enable; /* Enable descriptor polling */
817 int setup_f; /* Setup frame filtering type */
818 int local_state; /* State within a 'media' state */
819 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
820 struct sia_phy sia; /* SIA PHY Information */
821 int active; /* Index to active PHY device */
822 int mii_cnt; /* Number of attached PHY's */
823 int timeout; /* Scheduling counter */
824 struct timer_list timer; /* Timer info for kernel */
825 int tmp; /* Temporary global per card */
827 u_long lock; /* Lock the cache accesses */
828 s32 csr0; /* Saved Bus Mode Register */
829 s32 csr6; /* Saved Operating Mode Reg. */
830 s32 csr7; /* Saved IRQ Mask Register */
831 s32 gep; /* Saved General Purpose Reg. */
832 s32 gepc; /* Control info for GEP */
833 s32 csr13; /* Saved SIA Connectivity Reg. */
834 s32 csr14; /* Saved SIA TX/RX Register */
835 s32 csr15; /* Saved SIA General Register */
836 int save_cnt; /* Flag if state already saved */
837 struct sk_buff *skb; /* Save the (re-ordered) skb's */
839 struct de4x5_srom srom; /* A copy of the SROM */
840 int cfrv; /* Card CFRV copy */
841 int rx_ovf; /* Check for 'RX overflow' tag */
842 int useSROM; /* For non-DEC card use SROM */
843 int useMII; /* Infoblock using the MII */
844 int asBitValid; /* Autosense bits in GEP? */
845 int asPolarity; /* 0 => asserted high */
846 int asBit; /* Autosense bit number in GEP */
847 int defMedium; /* SROM default medium */
848 int tcount; /* Last infoblock number */
849 int infoblock_init; /* Initialised this infoblock? */
850 int infoleaf_offset; /* SROM infoleaf for controller */
851 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
852 int infoblock_media; /* infoblock media */
853 int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */
854 u_char *rst; /* Pointer to Type 5 reset info */
855 u_char ibn; /* Infoblock number */
856 struct parameters params; /* Command line/ #defined params */
857 struct device *gendev; /* Generic device */
858 dma_addr_t dma_rings; /* DMA handle for rings */
859 int dma_size; /* Size of the DMA area */
860 char *rx_bufs; /* rx bufs on alpha, sparc, ... */
864 ** To get around certain poxy cards that don't provide an SROM
865 ** for the second and more DECchip, I have to key off the first
866 ** chip's address. I'll assume there's not a bad SROM iff:
868 ** o the chipset is the same
869 ** o the bus number is the same and > 0
870 ** o the sum of all the returned hw address bytes is 0 or 0x5fa
872 ** Also have to save the irq for those cards whose hardware designers
873 ** can't follow the PCI to PCI Bridge Architecture spec.
879 u_char addr[ETH_ALEN];
883 ** The transmit ring full condition is described by the tx_old and tx_new
885 ** tx_old = tx_new Empty ring
886 ** tx_old = tx_new+1 Full ring
887 ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
889 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
890 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
891 lp->tx_old -lp->tx_new-1)
893 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
898 static int de4x5_open(struct net_device *dev);
899 static int de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev);
900 static irqreturn_t de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs);
901 static int de4x5_close(struct net_device *dev);
902 static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
903 static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
904 static void set_multicast_list(struct net_device *dev);
905 static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
910 static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
911 static int de4x5_init(struct net_device *dev);
912 static int de4x5_sw_reset(struct net_device *dev);
913 static int de4x5_rx(struct net_device *dev);
914 static int de4x5_tx(struct net_device *dev);
915 static int de4x5_ast(struct net_device *dev);
916 static int de4x5_txur(struct net_device *dev);
917 static int de4x5_rx_ovfc(struct net_device *dev);
919 static int autoconf_media(struct net_device *dev);
920 static void create_packet(struct net_device *dev, char *frame, int len);
921 static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
922 static int dc21040_autoconf(struct net_device *dev);
923 static int dc21041_autoconf(struct net_device *dev);
924 static int dc21140m_autoconf(struct net_device *dev);
925 static int dc2114x_autoconf(struct net_device *dev);
926 static int srom_autoconf(struct net_device *dev);
927 static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
928 static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
929 static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
930 static int test_for_100Mb(struct net_device *dev, int msec);
931 static int wait_for_link(struct net_device *dev);
932 static int test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec);
933 static int is_spd_100(struct net_device *dev);
934 static int is_100_up(struct net_device *dev);
935 static int is_10_up(struct net_device *dev);
936 static int is_anc_capable(struct net_device *dev);
937 static int ping_media(struct net_device *dev, int msec);
938 static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
939 static void de4x5_free_rx_buffs(struct net_device *dev);
940 static void de4x5_free_tx_buffs(struct net_device *dev);
941 static void de4x5_save_skbs(struct net_device *dev);
942 static void de4x5_rst_desc_ring(struct net_device *dev);
943 static void de4x5_cache_state(struct net_device *dev, int flag);
944 static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
945 static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
946 static struct sk_buff *de4x5_get_cache(struct net_device *dev);
947 static void de4x5_setup_intr(struct net_device *dev);
948 static void de4x5_init_connection(struct net_device *dev);
949 static int de4x5_reset_phy(struct net_device *dev);
950 static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
951 static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
952 static int test_tp(struct net_device *dev, s32 msec);
953 static int EISA_signature(char *name, struct device *device);
954 static int PCI_signature(char *name, struct de4x5_private *lp);
955 static void DevicePresent(struct net_device *dev, u_long iobase);
956 static void enet_addr_rst(u_long aprom_addr);
957 static int de4x5_bad_srom(struct de4x5_private *lp);
958 static short srom_rd(u_long address, u_char offset);
959 static void srom_latch(u_int command, u_long address);
960 static void srom_command(u_int command, u_long address);
961 static void srom_address(u_int command, u_long address, u_char offset);
962 static short srom_data(u_int command, u_long address);
963 /*static void srom_busy(u_int command, u_long address);*/
964 static void sendto_srom(u_int command, u_long addr);
965 static int getfrom_srom(u_long addr);
966 static int srom_map_media(struct net_device *dev);
967 static int srom_infoleaf_info(struct net_device *dev);
968 static void srom_init(struct net_device *dev);
969 static void srom_exec(struct net_device *dev, u_char *p);
970 static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
971 static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
972 static int mii_rdata(u_long ioaddr);
973 static void mii_wdata(int data, int len, u_long ioaddr);
974 static void mii_ta(u_long rw, u_long ioaddr);
975 static int mii_swap(int data, int len);
976 static void mii_address(u_char addr, u_long ioaddr);
977 static void sendto_mii(u32 command, int data, u_long ioaddr);
978 static int getfrom_mii(u32 command, u_long ioaddr);
979 static int mii_get_oui(u_char phyaddr, u_long ioaddr);
980 static int mii_get_phy(struct net_device *dev);
981 static void SetMulticastFilter(struct net_device *dev);
982 static int get_hw_addr(struct net_device *dev);
983 static void srom_repair(struct net_device *dev, int card);
984 static int test_bad_enet(struct net_device *dev, int status);
985 static int an_exception(struct de4x5_private *lp);
986 static char *build_setup_frame(struct net_device *dev, int mode);
987 static void disable_ast(struct net_device *dev);
988 static void enable_ast(struct net_device *dev, u32 time_out);
989 static long de4x5_switch_mac_port(struct net_device *dev);
990 static int gep_rd(struct net_device *dev);
991 static void gep_wr(s32 data, struct net_device *dev);
992 static void timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec);
993 static void yawn(struct net_device *dev, int state);
994 static void de4x5_parse_params(struct net_device *dev);
995 static void de4x5_dbg_open(struct net_device *dev);
996 static void de4x5_dbg_mii(struct net_device *dev, int k);
997 static void de4x5_dbg_media(struct net_device *dev);
998 static void de4x5_dbg_srom(struct de4x5_srom *p);
999 static void de4x5_dbg_rx(struct sk_buff *skb, int len);
1000 static int de4x5_strncmp(char *a, char *b, int n);
1001 static int dc21041_infoleaf(struct net_device *dev);
1002 static int dc21140_infoleaf(struct net_device *dev);
1003 static int dc21142_infoleaf(struct net_device *dev);
1004 static int dc21143_infoleaf(struct net_device *dev);
1005 static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1006 static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1007 static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1008 static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1009 static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1010 static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1011 static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1014 ** Note now that module autoprobing is allowed under EISA and PCI. The
1015 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1016 ** to "do the right thing".
1019 static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
1021 module_param(io, int, 0);
1022 module_param(de4x5_debug, int, 0);
1023 module_param(dec_only, int, 0);
1024 module_param(args, charp, 0);
1026 MODULE_PARM_DESC(io, "de4x5 I/O base address");
1027 MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1028 MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1029 MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1030 MODULE_LICENSE("GPL");
1033 ** List the SROM infoleaf functions and chipsets
1037 int (*fn)(struct net_device *);
1039 static struct InfoLeaf infoleaf_array[] = {
1040 {DC21041, dc21041_infoleaf},
1041 {DC21140, dc21140_infoleaf},
1042 {DC21142, dc21142_infoleaf},
1043 {DC21143, dc21143_infoleaf}
1045 #define INFOLEAF_SIZE (sizeof(infoleaf_array)/(sizeof(int)+sizeof(int *)))
1048 ** List the SROM info block functions
1050 static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1060 #define COMPACT (sizeof(dc_infoblock)/sizeof(int *) - 1)
1063 ** Miscellaneous defines...
1065 #define RESET_DE4X5 {\
1069 outl(i | BMR_SWR, DE4X5_BMR);\
1071 outl(i, DE4X5_BMR);\
1073 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1077 #define PHY_HARD_RESET {\
1078 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1079 mdelay(1); /* Assert for 1ms */\
1080 outl(0x00, DE4X5_GEP);\
1081 mdelay(2); /* Wait for 2ms */\
1085 static int __devinit
1086 de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
1088 char name[DE4X5_NAME_LENGTH + 1];
1089 struct de4x5_private *lp = netdev_priv(dev);
1090 struct pci_dev *pdev = NULL;
1093 gendev->driver_data = dev;
1095 /* Ensure we're not sleeping */
1096 if (lp->bus == EISA) {
1097 outb(WAKEUP, PCI_CFPM);
1099 pdev = to_pci_dev (gendev);
1100 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
1106 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1107 return -ENXIO; /* Hardware could not reset */
1111 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1113 lp->useSROM = FALSE;
1114 if (lp->bus == PCI) {
1115 PCI_signature(name, lp);
1117 EISA_signature(name, gendev);
1120 if (*name == '\0') { /* Not found a board signature */
1124 dev->base_addr = iobase;
1125 printk ("%s: %s at 0x%04lx", gendev->bus_id, name, iobase);
1127 printk(", h/w address ");
1128 status = get_hw_addr(dev);
1129 for (i = 0; i < ETH_ALEN - 1; i++) { /* get the ethernet addr. */
1130 printk("%2.2x:", dev->dev_addr[i]);
1132 printk("%2.2x,\n", dev->dev_addr[i]);
1135 printk(" which has an Ethernet PROM CRC error.\n");
1138 lp->cache.gepc = GEP_INIT;
1139 lp->asBit = GEP_SLNK;
1140 lp->asPolarity = GEP_SLNK;
1141 lp->asBitValid = TRUE;
1143 lp->gendev = gendev;
1144 lp->lock = (spinlock_t) SPIN_LOCK_UNLOCKED;
1145 init_timer(&lp->timer);
1146 de4x5_parse_params(dev);
1149 ** Choose correct autosensing in case someone messed up
1151 lp->autosense = lp->params.autosense;
1152 if (lp->chipset != DC21140) {
1153 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1154 lp->params.autosense = TP;
1156 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1157 lp->params.autosense = BNC;
1160 lp->fdx = lp->params.fdx;
1161 sprintf(lp->adapter_name,"%s (%s)", name, gendev->bus_id);
1163 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1164 #if defined(__alpha__) || defined(__powerpc__) || defined(__sparc_v9__) || defined(DE4X5_DO_MEMCPY)
1165 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1167 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1168 &lp->dma_rings, GFP_ATOMIC);
1169 if (lp->rx_ring == NULL) {
1173 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1176 ** Set up the RX descriptor ring (Intels)
1177 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1179 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
1180 for (i=0; i<NUM_RX_DESC; i++) {
1181 lp->rx_ring[i].status = 0;
1182 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1183 lp->rx_ring[i].buf = 0;
1184 lp->rx_ring[i].next = 0;
1185 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1190 dma_addr_t dma_rx_bufs;
1192 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1193 * sizeof(struct de4x5_desc);
1194 dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1195 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1196 + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1197 for (i=0; i<NUM_RX_DESC; i++) {
1198 lp->rx_ring[i].status = 0;
1199 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1200 lp->rx_ring[i].buf =
1201 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1202 lp->rx_ring[i].next = 0;
1203 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1211 lp->rxRingSize = NUM_RX_DESC;
1212 lp->txRingSize = NUM_TX_DESC;
1214 /* Write the end of list marker to the descriptor lists */
1215 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1216 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1218 /* Tell the adapter where the TX/RX rings are located. */
1219 outl(lp->dma_rings, DE4X5_RRBA);
1220 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1223 /* Initialise the IRQ mask and Enable/Disable */
1224 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1225 lp->irq_en = IMR_NIM | IMR_AIM;
1227 /* Create a loopback packet frame for later media probing */
1228 create_packet(dev, lp->frame, sizeof(lp->frame));
1230 /* Check if the RX overflow bug needs testing for */
1231 i = lp->cfrv & 0x000000fe;
1232 if ((lp->chipset == DC21140) && (i == 0x20)) {
1236 /* Initialise the SROM pointers if possible */
1238 lp->state = INITIALISED;
1239 if (srom_infoleaf_info(dev)) {
1240 dma_free_coherent (gendev, lp->dma_size,
1241 lp->rx_ring, lp->dma_rings);
1250 ** Check for an MII interface
1252 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1256 #ifndef __sparc_v9__
1257 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1259 printk(" and requires IRQ%x (provided by %s).\n", dev->irq,
1261 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1264 if (de4x5_debug & DEBUG_VERSION) {
1268 /* The DE4X5-specific entries in the device structure. */
1269 SET_MODULE_OWNER(dev);
1270 SET_NETDEV_DEV(dev, gendev);
1271 dev->open = &de4x5_open;
1272 dev->hard_start_xmit = &de4x5_queue_pkt;
1273 dev->stop = &de4x5_close;
1274 dev->get_stats = &de4x5_get_stats;
1275 dev->set_multicast_list = &set_multicast_list;
1276 dev->do_ioctl = &de4x5_ioctl;
1280 /* Fill in the generic fields of the device structure. */
1281 if ((status = register_netdev (dev))) {
1282 dma_free_coherent (gendev, lp->dma_size,
1283 lp->rx_ring, lp->dma_rings);
1287 /* Let the adapter sleep to save power */
1295 de4x5_open(struct net_device *dev)
1297 struct de4x5_private *lp = netdev_priv(dev);
1298 u_long iobase = dev->base_addr;
1302 /* Allocate the RX buffers */
1303 for (i=0; i<lp->rxRingSize; i++) {
1304 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1305 de4x5_free_rx_buffs(dev);
1311 ** Wake up the adapter
1316 ** Re-initialize the DE4X5...
1318 status = de4x5_init(dev);
1319 lp->lock = (spinlock_t) SPIN_LOCK_UNLOCKED;
1321 de4x5_dbg_open(dev);
1323 if (request_irq(dev->irq, (void *)de4x5_interrupt, SA_SHIRQ,
1324 lp->adapter_name, dev)) {
1325 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1326 if (request_irq(dev->irq, de4x5_interrupt, SA_INTERRUPT | SA_SHIRQ,
1327 lp->adapter_name, dev)) {
1328 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1330 de4x5_free_rx_buffs(dev);
1331 de4x5_free_tx_buffs(dev);
1336 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1337 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1341 lp->interrupt = UNMASK_INTERRUPTS;
1342 dev->trans_start = jiffies;
1346 de4x5_setup_intr(dev);
1348 if (de4x5_debug & DEBUG_OPEN) {
1349 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1350 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1351 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1352 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1353 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1354 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1355 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1356 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1363 ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1364 ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1365 ** see why I'd want > 14 multicast addresses, I have changed all chips to use
1366 ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1367 ** to be data corruption problems if it is larger (UDP errors seen from a
1371 de4x5_init(struct net_device *dev)
1373 /* Lock out other processes whilst setting up the hardware */
1374 netif_stop_queue(dev);
1376 de4x5_sw_reset(dev);
1378 /* Autoconfigure the connected port */
1379 autoconf_media(dev);
1385 de4x5_sw_reset(struct net_device *dev)
1387 struct de4x5_private *lp = netdev_priv(dev);
1388 u_long iobase = dev->base_addr;
1389 int i, j, status = 0;
1392 /* Select the MII or SRL port now and RESET the MAC */
1394 if (lp->phy[lp->active].id != 0) {
1395 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1397 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1399 de4x5_switch_mac_port(dev);
1403 ** Set the programmable burst length to 8 longwords for all the DC21140
1404 ** Fasternet chips and 4 longwords for all others: DMA errors result
1405 ** without these values. Cache align 16 long.
1407 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1408 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1409 outl(bmr, DE4X5_BMR);
1411 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1412 if (lp->chipset == DC21140) {
1413 omr |= (OMR_SDP | OMR_SB);
1415 lp->setup_f = PERFECT;
1416 outl(lp->dma_rings, DE4X5_RRBA);
1417 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1420 lp->rx_new = lp->rx_old = 0;
1421 lp->tx_new = lp->tx_old = 0;
1423 for (i = 0; i < lp->rxRingSize; i++) {
1424 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1427 for (i = 0; i < lp->txRingSize; i++) {
1428 lp->tx_ring[i].status = cpu_to_le32(0);
1433 /* Build the setup frame depending on filtering mode */
1434 SetMulticastFilter(dev);
1436 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1437 outl(omr|OMR_ST, DE4X5_OMR);
1439 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1441 for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */
1443 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1445 outl(omr, DE4X5_OMR); /* Stop everything! */
1448 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1453 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1454 lp->tx_old = lp->tx_new;
1460 ** Writes a socket buffer address to the next available transmit descriptor.
1463 de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1465 struct de4x5_private *lp = netdev_priv(dev);
1466 u_long iobase = dev->base_addr;
1470 netif_stop_queue(dev);
1471 if (lp->tx_enable == NO) { /* Cannot send for now */
1476 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1477 ** interrupts are lost by delayed descriptor status updates relative to
1478 ** the irq assertion, especially with a busy PCI bus.
1480 spin_lock_irqsave(&lp->lock, flags);
1482 spin_unlock_irqrestore(&lp->lock, flags);
1484 /* Test if cache is already locked - requeue skb if so */
1485 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1488 /* Transmit descriptor ring full or stale skb */
1489 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1490 if (lp->interrupt) {
1491 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1493 de4x5_put_cache(dev, skb);
1495 if (de4x5_debug & DEBUG_TX) {
1496 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1498 } else if (skb->len > 0) {
1499 /* If we already have stuff queued locally, use that first */
1500 if (lp->cache.skb && !lp->interrupt) {
1501 de4x5_put_cache(dev, skb);
1502 skb = de4x5_get_cache(dev);
1505 while (skb && !netif_queue_stopped(dev) &&
1506 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1507 spin_lock_irqsave(&lp->lock, flags);
1508 netif_stop_queue(dev);
1509 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1510 lp->stats.tx_bytes += skb->len;
1511 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1513 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1514 dev->trans_start = jiffies;
1516 if (TX_BUFFS_AVAIL) {
1517 netif_start_queue(dev); /* Another pkt may be queued */
1519 skb = de4x5_get_cache(dev);
1520 spin_unlock_irqrestore(&lp->lock, flags);
1522 if (skb) de4x5_putb_cache(dev, skb);
1531 ** The DE4X5 interrupt handler.
1533 ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1534 ** so that the asserted interrupt always has some real data to work with -
1535 ** if these I/O accesses are ever changed to memory accesses, ensure the
1536 ** STS write is read immediately to complete the transaction if the adapter
1537 ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1538 ** is high and descriptor status bits cannot be set before the associated
1539 ** interrupt is asserted and this routine entered.
1542 de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1544 struct net_device *dev = (struct net_device *)dev_id;
1545 struct de4x5_private *lp;
1546 s32 imr, omr, sts, limit;
1548 unsigned int handled = 0;
1551 printk ("de4x5_interrupt(): irq %d for unknown device.\n", irq);
1554 lp = netdev_priv(dev);
1555 spin_lock(&lp->lock);
1556 iobase = dev->base_addr;
1558 DISABLE_IRQs; /* Ensure non re-entrancy */
1560 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1561 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1563 synchronize_irq(dev->irq);
1565 for (limit=0; limit<8; limit++) {
1566 sts = inl(DE4X5_STS); /* Read IRQ status */
1567 outl(sts, DE4X5_STS); /* Reset the board interrupts */
1569 if (!(sts & lp->irq_mask)) break;/* All done */
1572 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1575 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1578 if (sts & STS_LNF) { /* TP Link has failed */
1579 lp->irq_mask &= ~IMR_LFM;
1582 if (sts & STS_UNF) { /* Transmit underrun */
1586 if (sts & STS_SE) { /* Bus Error */
1588 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1590 spin_unlock(&lp->lock);
1595 /* Load the TX ring with any locally stored packets */
1596 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1597 while (lp->cache.skb && !netif_queue_stopped(dev) && lp->tx_enable) {
1598 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1603 lp->interrupt = UNMASK_INTERRUPTS;
1605 spin_unlock(&lp->lock);
1607 return IRQ_RETVAL(handled);
1611 de4x5_rx(struct net_device *dev)
1613 struct de4x5_private *lp = netdev_priv(dev);
1614 u_long iobase = dev->base_addr;
1618 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1620 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1623 if (inl(DE4X5_MFC) & MFC_FOCM) {
1629 if (status & RD_FS) { /* Remember the start of frame */
1633 if (status & RD_LS) { /* Valid frame status */
1634 if (lp->tx_enable) lp->linkOK++;
1635 if (status & RD_ES) { /* There was an error. */
1636 lp->stats.rx_errors++; /* Update the error stats. */
1637 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1638 if (status & RD_CE) lp->stats.rx_crc_errors++;
1639 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1640 if (status & RD_TL) lp->stats.rx_length_errors++;
1641 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1642 if (status & RD_CS) lp->pktStats.rx_collision++;
1643 if (status & RD_DB) lp->pktStats.rx_dribble++;
1644 if (status & RD_OF) lp->pktStats.rx_overflow++;
1645 } else { /* A valid frame received */
1646 struct sk_buff *skb;
1647 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1650 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1651 printk("%s: Insufficient memory; nuking packet.\n",
1653 lp->stats.rx_dropped++;
1655 de4x5_dbg_rx(skb, pkt_len);
1657 /* Push up the protocol stack */
1658 skb->protocol=eth_type_trans(skb,dev);
1659 de4x5_local_stats(dev, skb->data, pkt_len);
1663 dev->last_rx = jiffies;
1664 lp->stats.rx_packets++;
1665 lp->stats.rx_bytes += pkt_len;
1669 /* Change buffer ownership for this frame, back to the adapter */
1670 for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1671 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1674 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1679 ** Update entry information
1681 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1688 de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1690 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1691 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1693 if ((u_long) lp->tx_skb[entry] > 1)
1694 dev_kfree_skb_irq(lp->tx_skb[entry]);
1695 lp->tx_skb[entry] = NULL;
1699 ** Buffer sent - check for TX buffer errors.
1702 de4x5_tx(struct net_device *dev)
1704 struct de4x5_private *lp = netdev_priv(dev);
1705 u_long iobase = dev->base_addr;
1709 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1710 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1711 if (status < 0) { /* Buffer not sent yet */
1713 } else if (status != 0x7fffffff) { /* Not setup frame */
1714 if (status & TD_ES) { /* An error happened */
1715 lp->stats.tx_errors++;
1716 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1717 if (status & TD_LC) lp->stats.tx_window_errors++;
1718 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1719 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1720 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1722 if (TX_PKT_PENDING) {
1723 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1725 } else { /* Packet sent */
1726 lp->stats.tx_packets++;
1727 if (lp->tx_enable) lp->linkOK++;
1729 /* Update the collision counter */
1730 lp->stats.collisions += ((status & TD_EC) ? 16 :
1731 ((status & TD_CC) >> 3));
1733 /* Free the buffer. */
1734 if (lp->tx_skb[entry] != NULL)
1735 de4x5_free_tx_buff(lp, entry);
1738 /* Update all the pointers */
1739 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1742 /* Any resources available? */
1743 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1745 netif_wake_queue(dev);
1747 netif_start_queue(dev);
1754 de4x5_ast(struct net_device *dev)
1756 struct de4x5_private *lp = netdev_priv(dev);
1757 int next_tick = DE4X5_AUTOSENSE_MS;
1762 next_tick = srom_autoconf(dev);
1763 } else if (lp->chipset == DC21140) {
1764 next_tick = dc21140m_autoconf(dev);
1765 } else if (lp->chipset == DC21041) {
1766 next_tick = dc21041_autoconf(dev);
1767 } else if (lp->chipset == DC21040) {
1768 next_tick = dc21040_autoconf(dev);
1771 enable_ast(dev, next_tick);
1777 de4x5_txur(struct net_device *dev)
1779 struct de4x5_private *lp = netdev_priv(dev);
1780 u_long iobase = dev->base_addr;
1783 omr = inl(DE4X5_OMR);
1784 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1785 omr &= ~(OMR_ST|OMR_SR);
1786 outl(omr, DE4X5_OMR);
1787 while (inl(DE4X5_STS) & STS_TS);
1788 if ((omr & OMR_TR) < OMR_TR) {
1793 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1800 de4x5_rx_ovfc(struct net_device *dev)
1802 struct de4x5_private *lp = netdev_priv(dev);
1803 u_long iobase = dev->base_addr;
1806 omr = inl(DE4X5_OMR);
1807 outl(omr & ~OMR_SR, DE4X5_OMR);
1808 while (inl(DE4X5_STS) & STS_RS);
1810 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1811 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1812 lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1815 outl(omr, DE4X5_OMR);
1821 de4x5_close(struct net_device *dev)
1823 struct de4x5_private *lp = netdev_priv(dev);
1824 u_long iobase = dev->base_addr;
1829 netif_stop_queue(dev);
1831 if (de4x5_debug & DEBUG_CLOSE) {
1832 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1833 dev->name, inl(DE4X5_STS));
1837 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1842 /* Free the associated irq */
1843 free_irq(dev->irq, dev);
1846 /* Free any socket buffers */
1847 de4x5_free_rx_buffs(dev);
1848 de4x5_free_tx_buffs(dev);
1850 /* Put the adapter to sleep to save power */
1856 static struct net_device_stats *
1857 de4x5_get_stats(struct net_device *dev)
1859 struct de4x5_private *lp = netdev_priv(dev);
1860 u_long iobase = dev->base_addr;
1862 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1868 de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1870 struct de4x5_private *lp = netdev_priv(dev);
1873 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1874 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1875 lp->pktStats.bins[i]++;
1876 i = DE4X5_PKT_STAT_SZ;
1879 if (buf[0] & 0x01) { /* Multicast/Broadcast */
1880 if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1881 lp->pktStats.broadcast++;
1883 lp->pktStats.multicast++;
1885 } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1886 (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1887 lp->pktStats.unicast++;
1890 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1891 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1892 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1899 ** Removes the TD_IC flag from previous descriptor to improve TX performance.
1900 ** If the flag is changed on a descriptor that is being read by the hardware,
1901 ** I assume PCI transaction ordering will mean you are either successful or
1902 ** just miss asserting the change to the hardware. Anyway you're messing with
1903 ** a descriptor you don't own, but this shouldn't kill the chip provided
1904 ** the descriptor register is read only to the hardware.
1907 load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1909 struct de4x5_private *lp = netdev_priv(dev);
1910 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1911 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1913 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1914 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1915 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1916 lp->tx_skb[lp->tx_new] = skb;
1917 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1920 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1925 ** Set or clear the multicast filter for this adaptor.
1928 set_multicast_list(struct net_device *dev)
1930 struct de4x5_private *lp = netdev_priv(dev);
1931 u_long iobase = dev->base_addr;
1933 /* First, double check that the adapter is open */
1934 if (lp->state == OPEN) {
1935 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1937 omr = inl(DE4X5_OMR);
1939 outl(omr, DE4X5_OMR);
1941 SetMulticastFilter(dev);
1942 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1943 SETUP_FRAME_LEN, (struct sk_buff *)1);
1945 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1946 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1947 dev->trans_start = jiffies;
1953 ** Calculate the hash code and update the logical address filter
1954 ** from a list of ethernet multicast addresses.
1955 ** Little endian crc one liner from Matt Thomas, DEC.
1958 SetMulticastFilter(struct net_device *dev)
1960 struct de4x5_private *lp = netdev_priv(dev);
1961 struct dev_mc_list *dmi=dev->mc_list;
1962 u_long iobase = dev->base_addr;
1963 int i, j, bit, byte;
1967 unsigned char *addrs;
1969 omr = inl(DE4X5_OMR);
1970 omr &= ~(OMR_PR | OMR_PM);
1971 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
1973 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
1974 omr |= OMR_PM; /* Pass all multicasts */
1975 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
1976 for (i=0;i<dev->mc_count;i++) { /* for each address in the list */
1977 addrs=dmi->dmi_addr;
1979 if ((*addrs & 0x01) == 1) { /* multicast address? */
1980 crc = ether_crc_le(ETH_ALEN, addrs);
1981 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
1983 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
1984 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
1986 byte <<= 1; /* calc offset into setup frame */
1990 lp->setup_frame[byte] |= bit;
1993 } else { /* Perfect filtering */
1994 for (j=0; j<dev->mc_count; j++) {
1995 addrs=dmi->dmi_addr;
1997 for (i=0; i<ETH_ALEN; i++) {
1998 *(pa + (i&1)) = *addrs++;
1999 if (i & 0x01) pa += 4;
2003 outl(omr, DE4X5_OMR);
2010 static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
2012 static int __init de4x5_eisa_probe (struct device *gendev)
2014 struct eisa_device *edev;
2020 struct net_device *dev;
2021 struct de4x5_private *lp;
2023 edev = to_eisa_device (gendev);
2024 iobase = edev->base_addr;
2026 if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5"))
2029 if (!request_region (iobase + DE4X5_EISA_IO_PORTS,
2030 DE4X5_EISA_TOTAL_SIZE, "de4x5")) {
2035 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2039 lp = netdev_priv(dev);
2041 cfid = (u32) inl(PCI_CFID);
2042 lp->cfrv = (u_short) inl(PCI_CFRV);
2043 device = (cfid >> 8) & 0x00ffff00;
2044 vendor = (u_short) cfid;
2046 /* Read the EISA Configuration Registers */
2047 regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT);
2049 /* Looks like the Jensen firmware (rev 2.2) doesn't really
2050 * care about the EISA configuration, and thus doesn't
2051 * configure the PLX bridge properly. Oh well... Simply mimic
2052 * the EISA config file to sort it out. */
2054 /* EISA REG1: Assert DecChip 21040 HW Reset */
2055 outb (ER1_IAM | 1, EISA_REG1);
2058 /* EISA REG1: Deassert DecChip 21040 HW Reset */
2059 outb (ER1_IAM, EISA_REG1);
2062 /* EISA REG3: R/W Burst Transfer Enable */
2063 outb (ER3_BWE | ER3_BRE, EISA_REG3);
2065 /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */
2066 outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0);
2068 irq = de4x5_irq[(regval >> 1) & 0x03];
2071 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2073 lp->chipset = device;
2076 /* Write the PCI Configuration Registers */
2077 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2078 outl(0x00006000, PCI_CFLT);
2079 outl(iobase, PCI_CBIO);
2081 DevicePresent(dev, EISA_APROM);
2085 if (!(status = de4x5_hw_init (dev, iobase, gendev))) {
2091 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2093 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2098 static int __devexit de4x5_eisa_remove (struct device *device)
2100 struct net_device *dev;
2103 dev = device->driver_data;
2104 iobase = dev->base_addr;
2106 unregister_netdev (dev);
2108 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2109 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2114 static struct eisa_device_id de4x5_eisa_ids[] = {
2115 { "DEC4250", 0 }, /* 0 is the board name index... */
2119 static struct eisa_driver de4x5_eisa_driver = {
2120 .id_table = de4x5_eisa_ids,
2123 .probe = de4x5_eisa_probe,
2124 .remove = __devexit_p (de4x5_eisa_remove),
2132 ** This function searches the current bus (which is >0) for a DECchip with an
2133 ** SROM, so that in multiport cards that have one SROM shared between multiple
2134 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2135 ** For single port cards this is a time waster...
2137 static void __devinit
2138 srom_search(struct net_device *dev, struct pci_dev *pdev)
2141 u_short vendor, status;
2142 u_int irq = 0, device;
2143 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2145 struct de4x5_private *lp = netdev_priv(dev);
2146 struct list_head *walk = &pdev->bus_list;
2148 for (walk = walk->next; walk != &pdev->bus_list; walk = walk->next) {
2149 struct pci_dev *this_dev = pci_dev_b(walk);
2151 /* Skip the pci_bus list entry */
2152 if (list_entry(walk, struct pci_bus, devices) == pdev->bus) continue;
2154 vendor = this_dev->vendor;
2155 device = this_dev->device << 8;
2156 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2158 /* Get the chip configuration revision register */
2159 pb = this_dev->bus->number;
2160 pci_read_config_dword(this_dev, PCI_REVISION_ID, &cfrv);
2162 /* Set the device number information */
2163 lp->device = PCI_SLOT(this_dev->devfn);
2166 /* Set the chipset information */
2168 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2170 lp->chipset = device;
2172 /* Get the board I/O address (64 bits on sparc64) */
2173 iobase = pci_resource_start(this_dev, 0);
2175 /* Fetch the IRQ to be used */
2176 irq = this_dev->irq;
2177 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2179 /* Check if I/O accesses are enabled */
2180 pci_read_config_word(this_dev, PCI_COMMAND, &status);
2181 if (!(status & PCI_COMMAND_IO)) continue;
2183 /* Search for a valid SROM attached to this DECchip */
2184 DevicePresent(dev, DE4X5_APROM);
2185 for (j=0, i=0; i<ETH_ALEN; i++) {
2186 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2188 if ((j != 0) && (j != 0x5fa)) {
2189 last.chipset = device;
2192 for (i=0; i<ETH_ALEN; i++) {
2193 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2203 ** PCI bus I/O device probe
2204 ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2205 ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2206 ** enabled by the user first in the set up utility. Hence we just check for
2207 ** enabled features and silently ignore the card if they're not.
2209 ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2210 ** bit. Here, check for I/O accesses and then set BM. If you put the card in
2211 ** a non BM slot, you're on your own (and complain to the PC vendor that your
2212 ** PC doesn't conform to the PCI standard)!
2214 ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2215 ** kernels use the V0.535[n] drivers.
2218 static int __devinit de4x5_pci_probe (struct pci_dev *pdev,
2219 const struct pci_device_id *ent)
2221 u_char pb, pbus = 0, dev_num, dnum = 0, timer;
2222 u_short vendor, status;
2223 u_int irq = 0, device;
2224 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2226 struct net_device *dev;
2227 struct de4x5_private *lp;
2229 dev_num = PCI_SLOT(pdev->devfn);
2230 pb = pdev->bus->number;
2232 if (io) { /* probe a single PCI device */
2233 pbus = (u_short)(io >> 8);
2234 dnum = (u_short)(io & 0xff);
2235 if ((pbus != pb) || (dnum != dev_num))
2239 vendor = pdev->vendor;
2240 device = pdev->device << 8;
2241 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x))
2244 /* Ok, the device seems to be for us. */
2245 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private))))
2248 lp = netdev_priv(dev);
2252 /* Search for an SROM on this bus */
2253 if (lp->bus_num != pb) {
2255 srom_search(dev, pdev);
2258 /* Get the chip configuration revision register */
2259 pci_read_config_dword(pdev, PCI_REVISION_ID, &lp->cfrv);
2261 /* Set the device number information */
2262 lp->device = dev_num;
2265 /* Set the chipset information */
2267 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2269 lp->chipset = device;
2271 /* Get the board I/O address (64 bits on sparc64) */
2272 iobase = pci_resource_start(pdev, 0);
2274 /* Fetch the IRQ to be used */
2276 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) {
2281 /* Check if I/O accesses and Bus Mastering are enabled */
2282 pci_read_config_word(pdev, PCI_COMMAND, &status);
2284 if (!(status & PCI_COMMAND_IO)) {
2285 status |= PCI_COMMAND_IO;
2286 pci_write_config_word(pdev, PCI_COMMAND, status);
2287 pci_read_config_word(pdev, PCI_COMMAND, &status);
2289 #endif /* __powerpc__ */
2290 if (!(status & PCI_COMMAND_IO)) {
2295 if (!(status & PCI_COMMAND_MASTER)) {
2296 status |= PCI_COMMAND_MASTER;
2297 pci_write_config_word(pdev, PCI_COMMAND, status);
2298 pci_read_config_word(pdev, PCI_COMMAND, &status);
2300 if (!(status & PCI_COMMAND_MASTER)) {
2305 /* Check the latency timer for values >= 0x60 */
2306 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer);
2308 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60);
2311 DevicePresent(dev, DE4X5_APROM);
2313 if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) {
2320 if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) {
2327 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2333 static void __devexit de4x5_pci_remove (struct pci_dev *pdev)
2335 struct net_device *dev;
2338 dev = pdev->dev.driver_data;
2339 iobase = dev->base_addr;
2341 unregister_netdev (dev);
2343 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2346 static struct pci_device_id de4x5_pci_tbl[] = {
2347 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
2348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
2349 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
2350 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
2351 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
2352 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
2353 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
2354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
2358 static struct pci_driver de4x5_pci_driver = {
2360 .id_table = de4x5_pci_tbl,
2361 .probe = de4x5_pci_probe,
2362 .remove = __devexit_p (de4x5_pci_remove),
2368 ** Auto configure the media here rather than setting the port at compile
2369 ** time. This routine is called by de4x5_init() and when a loss of media is
2370 ** detected (excessive collisions, loss of carrier, no carrier or link fail
2371 ** [TP] or no recent receive activity) to check whether the user has been
2372 ** sneaky and changed the port on us.
2375 autoconf_media(struct net_device *dev)
2377 struct de4x5_private *lp = netdev_priv(dev);
2378 u_long iobase = dev->base_addr;
2379 int next_tick = DE4X5_AUTOSENSE_MS;
2382 lp->c_media = AUTO; /* Bogus last media */
2384 inl(DE4X5_MFC); /* Zero the lost frames counter */
2389 next_tick = srom_autoconf(dev);
2390 } else if (lp->chipset == DC21040) {
2391 next_tick = dc21040_autoconf(dev);
2392 } else if (lp->chipset == DC21041) {
2393 next_tick = dc21041_autoconf(dev);
2394 } else if (lp->chipset == DC21140) {
2395 next_tick = dc21140m_autoconf(dev);
2398 enable_ast(dev, next_tick);
2404 ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2405 ** from BNC as the port has a jumper to set thick or thin wire. When set for
2406 ** BNC, the BNC port will indicate activity if it's not terminated correctly.
2407 ** The only way to test for that is to place a loopback packet onto the
2408 ** network and watch for errors. Since we're messing with the interrupt mask
2409 ** register, disable the board interrupts and do not allow any more packets to
2410 ** be queued to the hardware. Re-enable everything only when the media is
2412 ** I may have to "age out" locally queued packets so that the higher layer
2413 ** timeouts don't effectively duplicate packets on the network.
2416 dc21040_autoconf(struct net_device *dev)
2418 struct de4x5_private *lp = netdev_priv(dev);
2419 u_long iobase = dev->base_addr;
2420 int next_tick = DE4X5_AUTOSENSE_MS;
2423 switch (lp->media) {
2428 de4x5_save_skbs(dev);
2429 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2431 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2432 lp->media = BNC_AUI;
2433 } else if (lp->autosense == EXT_SIA) {
2434 lp->media = EXT_SIA;
2438 lp->local_state = 0;
2439 next_tick = dc21040_autoconf(dev);
2443 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2444 TP_SUSPECT, test_tp);
2448 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2454 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2455 BNC_AUI_SUSPECT, ping_media);
2458 case BNC_AUI_SUSPECT:
2459 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2463 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2464 NC, EXT_SIA_SUSPECT, ping_media);
2467 case EXT_SIA_SUSPECT:
2468 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2472 /* default to TP for all */
2473 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2474 if (lp->media != lp->c_media) {
2475 de4x5_dbg_media(dev);
2476 lp->c_media = lp->media;
2487 dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2488 int next_state, int suspect_state,
2489 int (*fn)(struct net_device *, int))
2491 struct de4x5_private *lp = netdev_priv(dev);
2492 int next_tick = DE4X5_AUTOSENSE_MS;
2495 switch (lp->local_state) {
2497 reset_init_sia(dev, csr13, csr14, csr15);
2503 if (!lp->tx_enable) {
2504 linkBad = fn(dev, timeout);
2506 next_tick = linkBad & ~TIMER_CB;
2508 if (linkBad && (lp->autosense == AUTO)) {
2509 lp->local_state = 0;
2510 lp->media = next_state;
2512 de4x5_init_connection(dev);
2515 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2516 lp->media = suspect_state;
2526 de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2527 int (*fn)(struct net_device *, int),
2528 int (*asfn)(struct net_device *))
2530 struct de4x5_private *lp = netdev_priv(dev);
2531 int next_tick = DE4X5_AUTOSENSE_MS;
2534 switch (lp->local_state) {
2537 lp->media = prev_state;
2540 next_tick = asfn(dev);
2545 linkBad = fn(dev, timeout);
2547 next_tick = linkBad & ~TIMER_CB;
2548 } else if (!linkBad) {
2550 lp->media = prev_state;
2561 ** Autoconfigure the media when using the DC21041. AUI needs to be tested
2562 ** before BNC, because the BNC port will indicate activity if it's not
2563 ** terminated correctly. The only way to test for that is to place a loopback
2564 ** packet onto the network and watch for errors. Since we're messing with
2565 ** the interrupt mask register, disable the board interrupts and do not allow
2566 ** any more packets to be queued to the hardware. Re-enable everything only
2567 ** when the media is found.
2570 dc21041_autoconf(struct net_device *dev)
2572 struct de4x5_private *lp = netdev_priv(dev);
2573 u_long iobase = dev->base_addr;
2574 s32 sts, irqs, irq_mask, imr, omr;
2575 int next_tick = DE4X5_AUTOSENSE_MS;
2577 switch (lp->media) {
2582 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2583 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2584 lp->media = TP; /* On chip auto negotiation is broken */
2585 } else if (lp->autosense == TP) {
2587 } else if (lp->autosense == BNC) {
2589 } else if (lp->autosense == AUI) {
2594 lp->local_state = 0;
2595 next_tick = dc21041_autoconf(dev);
2599 if (lp->timeout < 0) {
2600 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2601 outl(omr | OMR_FDX, DE4X5_OMR);
2603 irqs = STS_LNF | STS_LNP;
2604 irq_mask = IMR_LFM | IMR_LPM;
2605 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2607 next_tick = sts & ~TIMER_CB;
2609 if (sts & STS_LNP) {
2614 next_tick = dc21041_autoconf(dev);
2619 if (!lp->tx_enable) {
2622 sts = test_ans(dev, irqs, irq_mask, 3000);
2624 next_tick = sts & ~TIMER_CB;
2626 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2628 next_tick = dc21041_autoconf(dev);
2630 lp->local_state = 1;
2631 de4x5_init_connection(dev);
2634 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2635 lp->media = ANS_SUSPECT;
2641 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2645 if (!lp->tx_enable) {
2646 if (lp->timeout < 0) {
2647 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2648 outl(omr & ~OMR_FDX, DE4X5_OMR);
2650 irqs = STS_LNF | STS_LNP;
2651 irq_mask = IMR_LFM | IMR_LPM;
2652 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2654 next_tick = sts & ~TIMER_CB;
2656 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2657 if (inl(DE4X5_SISR) & SISR_NRA) {
2658 lp->media = AUI; /* Non selected port activity */
2662 next_tick = dc21041_autoconf(dev);
2664 lp->local_state = 1;
2665 de4x5_init_connection(dev);
2668 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2669 lp->media = TP_SUSPECT;
2675 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2679 if (!lp->tx_enable) {
2680 if (lp->timeout < 0) {
2681 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2682 outl(omr & ~OMR_FDX, DE4X5_OMR);
2686 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2688 next_tick = sts & ~TIMER_CB;
2690 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2692 next_tick = dc21041_autoconf(dev);
2694 lp->local_state = 1;
2695 de4x5_init_connection(dev);
2698 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2699 lp->media = AUI_SUSPECT;
2705 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2709 switch (lp->local_state) {
2711 if (lp->timeout < 0) {
2712 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2713 outl(omr & ~OMR_FDX, DE4X5_OMR);
2717 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2719 next_tick = sts & ~TIMER_CB;
2721 lp->local_state++; /* Ensure media connected */
2722 next_tick = dc21041_autoconf(dev);
2727 if (!lp->tx_enable) {
2728 if ((sts = ping_media(dev, 3000)) < 0) {
2729 next_tick = sts & ~TIMER_CB;
2732 lp->local_state = 0;
2735 de4x5_init_connection(dev);
2738 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2739 lp->media = BNC_SUSPECT;
2747 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2751 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2752 outl(omr | OMR_FDX, DE4X5_OMR);
2753 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2754 if (lp->media != lp->c_media) {
2755 de4x5_dbg_media(dev);
2756 lp->c_media = lp->media;
2767 ** Some autonegotiation chips are broken in that they do not return the
2768 ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2769 ** register, except at the first power up negotiation.
2772 dc21140m_autoconf(struct net_device *dev)
2774 struct de4x5_private *lp = netdev_priv(dev);
2775 int ana, anlpa, cap, cr, slnk, sr;
2776 int next_tick = DE4X5_AUTOSENSE_MS;
2777 u_long imr, omr, iobase = dev->base_addr;
2781 if (lp->timeout < 0) {
2783 lp->tx_enable = FALSE;
2785 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2787 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2788 next_tick &= ~TIMER_CB;
2791 if (srom_map_media(dev) < 0) {
2795 srom_exec(dev, lp->phy[lp->active].gep);
2796 if (lp->infoblock_media == ANS) {
2797 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2798 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2801 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2803 if (lp->autosense == _100Mb) {
2805 } else if (lp->autosense == _10Mb) {
2807 } else if ((lp->autosense == AUTO) &&
2808 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2809 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2810 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2811 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2813 } else if (lp->autosense == AUTO) {
2814 lp->media = SPD_DET;
2815 } else if (is_spd_100(dev) && is_100_up(dev)) {
2821 lp->local_state = 0;
2822 next_tick = dc21140m_autoconf(dev);
2827 switch (lp->local_state) {
2829 if (lp->timeout < 0) {
2830 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2832 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
2834 next_tick = cr & ~TIMER_CB;
2837 lp->local_state = 0;
2838 lp->media = SPD_DET;
2842 next_tick = dc21140m_autoconf(dev);
2847 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
2848 next_tick = sr & ~TIMER_CB;
2850 lp->media = SPD_DET;
2851 lp->local_state = 0;
2852 if (sr) { /* Success! */
2853 lp->tmp = MII_SR_ASSC;
2854 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2855 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2856 if (!(anlpa & MII_ANLPA_RF) &&
2857 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2858 if (cap & MII_ANA_100M) {
2859 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
2861 } else if (cap & MII_ANA_10M) {
2862 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
2867 } /* Auto Negotiation failed to finish */
2868 next_tick = dc21140m_autoconf(dev);
2869 } /* Auto Negotiation failed to start */
2874 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2875 if (lp->timeout < 0) {
2876 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2877 (~gep_rd(dev) & GEP_LNP));
2880 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2881 next_tick = slnk & ~TIMER_CB;
2883 if (is_spd_100(dev) && is_100_up(dev)) {
2885 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2890 next_tick = dc21140m_autoconf(dev);
2894 case _100Mb: /* Set 100Mb/s */
2896 if (!lp->tx_enable) {
2898 de4x5_init_connection(dev);
2900 if (!lp->linkOK && (lp->autosense == AUTO)) {
2901 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2904 next_tick = DE4X5_AUTOSENSE_MS;
2912 case _10Mb: /* Set 10Mb/s */
2914 if (!lp->tx_enable) {
2916 de4x5_init_connection(dev);
2918 if (!lp->linkOK && (lp->autosense == AUTO)) {
2919 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2922 next_tick = DE4X5_AUTOSENSE_MS;
2929 if (lp->media != lp->c_media) {
2930 de4x5_dbg_media(dev);
2931 lp->c_media = lp->media;
2934 lp->tx_enable = FALSE;
2942 ** This routine may be merged into dc21140m_autoconf() sometime as I'm
2943 ** changing how I figure out the media - but trying to keep it backwards
2944 ** compatible with the de500-xa and de500-aa.
2945 ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2946 ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2947 ** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2949 ** When autonegotiation is working, the ANS part searches the SROM for
2950 ** the highest common speed (TP) link that both can run and if that can
2951 ** be full duplex. That infoblock is executed and then the link speed set.
2953 ** Only _10Mb and _100Mb are tested here.
2956 dc2114x_autoconf(struct net_device *dev)
2958 struct de4x5_private *lp = netdev_priv(dev);
2959 u_long iobase = dev->base_addr;
2960 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2961 int next_tick = DE4X5_AUTOSENSE_MS;
2963 switch (lp->media) {
2965 if (lp->timeout < 0) {
2967 lp->tx_enable = FALSE;
2970 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2971 if (lp->params.autosense & ~AUTO) {
2972 srom_map_media(dev); /* Fixed media requested */
2973 if (lp->media != lp->params.autosense) {
2981 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2982 next_tick &= ~TIMER_CB;
2984 if (lp->autosense == _100Mb) {
2986 } else if (lp->autosense == _10Mb) {
2988 } else if (lp->autosense == TP) {
2990 } else if (lp->autosense == BNC) {
2992 } else if (lp->autosense == AUI) {
2995 lp->media = SPD_DET;
2996 if ((lp->infoblock_media == ANS) &&
2997 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2998 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2999 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
3000 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3004 lp->local_state = 0;
3005 next_tick = dc2114x_autoconf(dev);
3010 switch (lp->local_state) {
3012 if (lp->timeout < 0) {
3013 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3015 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
3017 next_tick = cr & ~TIMER_CB;
3020 lp->local_state = 0;
3021 lp->media = SPD_DET;
3025 next_tick = dc2114x_autoconf(dev);
3030 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
3031 next_tick = sr & ~TIMER_CB;
3033 lp->media = SPD_DET;
3034 lp->local_state = 0;
3035 if (sr) { /* Success! */
3036 lp->tmp = MII_SR_ASSC;
3037 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3038 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3039 if (!(anlpa & MII_ANLPA_RF) &&
3040 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3041 if (cap & MII_ANA_100M) {
3042 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
3044 } else if (cap & MII_ANA_10M) {
3045 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
3049 } /* Auto Negotiation failed to finish */
3050 next_tick = dc2114x_autoconf(dev);
3051 } /* Auto Negotiation failed to start */
3057 if (!lp->tx_enable) {
3058 if (lp->timeout < 0) {
3059 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3060 outl(omr & ~OMR_FDX, DE4X5_OMR);
3064 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3066 next_tick = sts & ~TIMER_CB;
3068 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3070 next_tick = dc2114x_autoconf(dev);
3072 lp->local_state = 1;
3073 de4x5_init_connection(dev);
3076 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3077 lp->media = AUI_SUSPECT;
3083 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3087 switch (lp->local_state) {
3089 if (lp->timeout < 0) {
3090 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3091 outl(omr & ~OMR_FDX, DE4X5_OMR);
3095 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3097 next_tick = sts & ~TIMER_CB;
3099 lp->local_state++; /* Ensure media connected */
3100 next_tick = dc2114x_autoconf(dev);
3105 if (!lp->tx_enable) {
3106 if ((sts = ping_media(dev, 3000)) < 0) {
3107 next_tick = sts & ~TIMER_CB;
3110 lp->local_state = 0;
3114 de4x5_init_connection(dev);
3117 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3118 lp->media = BNC_SUSPECT;
3126 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3129 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3130 if (srom_map_media(dev) < 0) {
3135 if (lp->media == _100Mb) {
3136 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3137 lp->media = SPD_DET;
3138 return (slnk & ~TIMER_CB);
3141 if (wait_for_link(dev) < 0) {
3142 lp->media = SPD_DET;
3143 return PDET_LINK_WAIT;
3146 if (lp->media == ANS) { /* Do MII parallel detection */
3147 if (is_spd_100(dev)) {
3152 next_tick = dc2114x_autoconf(dev);
3153 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3154 (((lp->media == _10Mb) || (lp->media == TP) ||
3155 (lp->media == BNC) || (lp->media == AUI)) &&
3157 next_tick = dc2114x_autoconf(dev);
3166 if (!lp->tx_enable) {
3168 de4x5_init_connection(dev);
3170 if (!lp->linkOK && (lp->autosense == AUTO)) {
3171 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3174 next_tick = DE4X5_AUTOSENSE_MS;
3182 if (!lp->tx_enable) {
3184 de4x5_init_connection(dev);
3186 if (!lp->linkOK && (lp->autosense == AUTO)) {
3187 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3190 next_tick = DE4X5_AUTOSENSE_MS;
3198 printk("Huh?: media:%02x\n", lp->media);
3207 srom_autoconf(struct net_device *dev)
3209 struct de4x5_private *lp = netdev_priv(dev);
3211 return lp->infoleaf_fn(dev);
3215 ** This mapping keeps the original media codes and FDX flag unchanged.
3216 ** While it isn't strictly necessary, it helps me for the moment...
3217 ** The early return avoids a media state / SROM media space clash.
3220 srom_map_media(struct net_device *dev)
3222 struct de4x5_private *lp = netdev_priv(dev);
3225 if (lp->infoblock_media == lp->media)
3228 switch(lp->infoblock_media) {
3230 if (!lp->params.fdx) return -1;
3233 if (lp->params.fdx && !lp->fdx) return -1;
3234 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3249 case SROM_100BASETF:
3250 if (!lp->params.fdx) return -1;
3253 if (lp->params.fdx && !lp->fdx) return -1;
3257 case SROM_100BASET4:
3261 case SROM_100BASEFF:
3262 if (!lp->params.fdx) return -1;
3265 if (lp->params.fdx && !lp->fdx) return -1;
3271 lp->fdx = lp->params.fdx;
3275 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3276 lp->infoblock_media);
3285 de4x5_init_connection(struct net_device *dev)
3287 struct de4x5_private *lp = netdev_priv(dev);
3288 u_long iobase = dev->base_addr;
3291 if (lp->media != lp->c_media) {
3292 de4x5_dbg_media(dev);
3293 lp->c_media = lp->media; /* Stop scrolling media messages */
3296 spin_lock_irqsave(&lp->lock, flags);
3297 de4x5_rst_desc_ring(dev);
3298 de4x5_setup_intr(dev);
3299 lp->tx_enable = YES;
3300 spin_unlock_irqrestore(&lp->lock, flags);
3301 outl(POLL_DEMAND, DE4X5_TPD);
3303 netif_wake_queue(dev);
3309 ** General PHY reset function. Some MII devices don't reset correctly
3310 ** since their MII address pins can float at voltages that are dependent
3311 ** on the signal pin use. Do a double reset to ensure a reset.
3314 de4x5_reset_phy(struct net_device *dev)
3316 struct de4x5_private *lp = netdev_priv(dev);
3317 u_long iobase = dev->base_addr;
3320 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3321 if (lp->timeout < 0) {
3323 if (lp->phy[lp->active].rst) {
3324 srom_exec(dev, lp->phy[lp->active].rst);
3325 srom_exec(dev, lp->phy[lp->active].rst);
3326 } else if (lp->rst) { /* Type 5 infoblock reset */
3327 srom_exec(dev, lp->rst);
3328 srom_exec(dev, lp->rst);
3334 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3338 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, FALSE, 500);
3340 } else if (lp->chipset == DC21140) {
3348 test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3350 struct de4x5_private *lp = netdev_priv(dev);
3351 u_long iobase = dev->base_addr;
3354 if (lp->timeout < 0) {
3355 lp->timeout = msec/100;
3356 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3357 reset_init_sia(dev, csr13, csr14, csr15);
3360 /* set up the interrupt mask */
3361 outl(irq_mask, DE4X5_IMR);
3363 /* clear all pending interrupts */
3364 sts = inl(DE4X5_STS);
3365 outl(sts, DE4X5_STS);
3367 /* clear csr12 NRA and SRA bits */
3368 if ((lp->chipset == DC21041) || lp->useSROM) {
3369 csr12 = inl(DE4X5_SISR);
3370 outl(csr12, DE4X5_SISR);
3374 sts = inl(DE4X5_STS) & ~TIMER_CB;
3376 if (!(sts & irqs) && --lp->timeout) {
3377 sts = 100 | TIMER_CB;
3386 test_tp(struct net_device *dev, s32 msec)
3388 struct de4x5_private *lp = netdev_priv(dev);
3389 u_long iobase = dev->base_addr;
3392 if (lp->timeout < 0) {
3393 lp->timeout = msec/100;
3396 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3398 if (sisr && --lp->timeout) {
3399 sisr = 100 | TIMER_CB;
3408 ** Samples the 100Mb Link State Signal. The sample interval is important
3409 ** because too fast a rate can give erroneous results and confuse the
3410 ** speed sense algorithm.
3412 #define SAMPLE_INTERVAL 500 /* ms */
3413 #define SAMPLE_DELAY 2000 /* ms */
3415 test_for_100Mb(struct net_device *dev, int msec)
3417 struct de4x5_private *lp = netdev_priv(dev);
3418 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3420 if (lp->timeout < 0) {
3421 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3422 if (msec > SAMPLE_DELAY) {
3423 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3424 gep = SAMPLE_DELAY | TIMER_CB;
3427 lp->timeout = msec/SAMPLE_INTERVAL;
3431 if (lp->phy[lp->active].id || lp->useSROM) {
3432 gep = is_100_up(dev) | is_spd_100(dev);
3434 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3436 if (!(gep & ret) && --lp->timeout) {
3437 gep = SAMPLE_INTERVAL | TIMER_CB;
3446 wait_for_link(struct net_device *dev)
3448 struct de4x5_private *lp = netdev_priv(dev);
3450 if (lp->timeout < 0) {
3454 if (lp->timeout--) {
3468 test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec)
3470 struct de4x5_private *lp = netdev_priv(dev);
3472 u_long iobase = dev->base_addr;
3474 if (lp->timeout < 0) {
3475 lp->timeout = msec/100;
3479 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3480 test = (reg ^ pol) & mask;
3482 if (test && --lp->timeout) {
3483 reg = 100 | TIMER_CB;
3492 is_spd_100(struct net_device *dev)
3494 struct de4x5_private *lp = netdev_priv(dev);
3495 u_long iobase = dev->base_addr;
3499 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3500 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3501 spd &= lp->phy[lp->active].spd.mask;
3502 } else if (!lp->useSROM) { /* de500-xa */
3503 spd = ((~gep_rd(dev)) & GEP_SLNK);
3505 if ((lp->ibn == 2) || !lp->asBitValid)
3506 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3508 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3509 (lp->linkOK & ~lp->asBitValid);
3516 is_100_up(struct net_device *dev)
3518 struct de4x5_private *lp = netdev_priv(dev);
3519 u_long iobase = dev->base_addr;
3522 /* Double read for sticky bits & temporary drops */
3523 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3524 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3525 } else if (!lp->useSROM) { /* de500-xa */
3526 return ((~gep_rd(dev)) & GEP_SLNK);
3528 if ((lp->ibn == 2) || !lp->asBitValid)
3529 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3531 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3532 (lp->linkOK & ~lp->asBitValid));
3537 is_10_up(struct net_device *dev)
3539 struct de4x5_private *lp = netdev_priv(dev);
3540 u_long iobase = dev->base_addr;
3543 /* Double read for sticky bits & temporary drops */
3544 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3545 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3546 } else if (!lp->useSROM) { /* de500-xa */
3547 return ((~gep_rd(dev)) & GEP_LNP);
3549 if ((lp->ibn == 2) || !lp->asBitValid)
3550 return (((lp->chipset & ~0x00ff) == DC2114x) ?
3551 (~inl(DE4X5_SISR)&SISR_LS10):
3554 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3555 (lp->linkOK & ~lp->asBitValid));
3560 is_anc_capable(struct net_device *dev)
3562 struct de4x5_private *lp = netdev_priv(dev);
3563 u_long iobase = dev->base_addr;
3565 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3566 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3567 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3568 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3575 ** Send a packet onto the media and watch for send errors that indicate the
3576 ** media is bad or unconnected.
3579 ping_media(struct net_device *dev, int msec)
3581 struct de4x5_private *lp = netdev_priv(dev);
3582 u_long iobase = dev->base_addr;
3585 if (lp->timeout < 0) {
3586 lp->timeout = msec/100;
3588 lp->tmp = lp->tx_new; /* Remember the ring position */
3589 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3590 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3591 outl(POLL_DEMAND, DE4X5_TPD);
3594 sisr = inl(DE4X5_SISR);
3596 if ((!(sisr & SISR_NCR)) &&
3597 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3599 sisr = 100 | TIMER_CB;
3601 if ((!(sisr & SISR_NCR)) &&
3602 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3615 ** This function does 2 things: on Intels it kmalloc's another buffer to
3616 ** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3617 ** into which the packet is copied.
3619 static struct sk_buff *
3620 de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3622 struct de4x5_private *lp = netdev_priv(dev);
3625 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
3626 struct sk_buff *ret;
3629 p = dev_alloc_skb(IEEE802_3_SZ + DE4X5_ALIGN + 2);
3630 if (!p) return NULL;
3633 tmp = virt_to_bus(p->data);
3634 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3636 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3638 ret = lp->rx_skb[index];
3639 lp->rx_skb[index] = p;
3641 if ((u_long) ret > 1) {
3648 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3650 p = dev_alloc_skb(len + 2);
3651 if (!p) return NULL;
3654 skb_reserve(p, 2); /* Align */
3655 if (index < lp->rx_old) { /* Wrapped buffer */
3656 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3657 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3658 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3659 } else { /* Linear buffer */
3660 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3668 de4x5_free_rx_buffs(struct net_device *dev)
3670 struct de4x5_private *lp = netdev_priv(dev);
3673 for (i=0; i<lp->rxRingSize; i++) {
3674 if ((u_long) lp->rx_skb[i] > 1) {
3675 dev_kfree_skb(lp->rx_skb[i]);
3677 lp->rx_ring[i].status = 0;
3678 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3685 de4x5_free_tx_buffs(struct net_device *dev)
3687 struct de4x5_private *lp = netdev_priv(dev);
3690 for (i=0; i<lp->txRingSize; i++) {
3692 de4x5_free_tx_buff(lp, i);
3693 lp->tx_ring[i].status = 0;
3696 /* Unload the locally queued packets */
3697 while (lp->cache.skb) {
3698 dev_kfree_skb(de4x5_get_cache(dev));
3705 ** When a user pulls a connection, the DECchip can end up in a
3706 ** 'running - waiting for end of transmission' state. This means that we
3707 ** have to perform a chip soft reset to ensure that we can synchronize
3708 ** the hardware and software and make any media probes using a loopback
3709 ** packet meaningful.
3712 de4x5_save_skbs(struct net_device *dev)
3714 struct de4x5_private *lp = netdev_priv(dev);
3715 u_long iobase = dev->base_addr;
3718 if (!lp->cache.save_cnt) {
3720 de4x5_tx(dev); /* Flush any sent skb's */
3721 de4x5_free_tx_buffs(dev);
3722 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3723 de4x5_sw_reset(dev);
3724 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3725 lp->cache.save_cnt++;
3733 de4x5_rst_desc_ring(struct net_device *dev)
3735 struct de4x5_private *lp = netdev_priv(dev);
3736 u_long iobase = dev->base_addr;
3740 if (lp->cache.save_cnt) {
3742 outl(lp->dma_rings, DE4X5_RRBA);
3743 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3746 lp->rx_new = lp->rx_old = 0;
3747 lp->tx_new = lp->tx_old = 0;
3749 for (i = 0; i < lp->rxRingSize; i++) {
3750 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3753 for (i = 0; i < lp->txRingSize; i++) {
3754 lp->tx_ring[i].status = cpu_to_le32(0);
3758 lp->cache.save_cnt--;
3766 de4x5_cache_state(struct net_device *dev, int flag)
3768 struct de4x5_private *lp = netdev_priv(dev);
3769 u_long iobase = dev->base_addr;
3772 case DE4X5_SAVE_STATE:
3773 lp->cache.csr0 = inl(DE4X5_BMR);
3774 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3775 lp->cache.csr7 = inl(DE4X5_IMR);
3778 case DE4X5_RESTORE_STATE:
3779 outl(lp->cache.csr0, DE4X5_BMR);
3780 outl(lp->cache.csr6, DE4X5_OMR);
3781 outl(lp->cache.csr7, DE4X5_IMR);
3782 if (lp->chipset == DC21140) {
3783 gep_wr(lp->cache.gepc, dev);
3784 gep_wr(lp->cache.gep, dev);
3786 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3796 de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3798 struct de4x5_private *lp = netdev_priv(dev);
3801 if (lp->cache.skb) {
3802 for (p=lp->cache.skb; p->next; p=p->next);
3805 lp->cache.skb = skb;
3813 de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3815 struct de4x5_private *lp = netdev_priv(dev);
3816 struct sk_buff *p = lp->cache.skb;
3818 lp->cache.skb = skb;
3824 static struct sk_buff *
3825 de4x5_get_cache(struct net_device *dev)
3827 struct de4x5_private *lp = netdev_priv(dev);
3828 struct sk_buff *p = lp->cache.skb;
3831 lp->cache.skb = p->next;
3839 ** Check the Auto Negotiation State. Return OK when a link pass interrupt
3840 ** is received and the auto-negotiation status is NWAY OK.
3843 test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3845 struct de4x5_private *lp = netdev_priv(dev);
3846 u_long iobase = dev->base_addr;
3849 if (lp->timeout < 0) {
3850 lp->timeout = msec/100;
3851 outl(irq_mask, DE4X5_IMR);
3853 /* clear all pending interrupts */
3854 sts = inl(DE4X5_STS);
3855 outl(sts, DE4X5_STS);
3858 ans = inl(DE4X5_SISR) & SISR_ANS;
3859 sts = inl(DE4X5_STS) & ~TIMER_CB;
3861 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3862 sts = 100 | TIMER_CB;
3871 de4x5_setup_intr(struct net_device *dev)
3873 struct de4x5_private *lp = netdev_priv(dev);
3874 u_long iobase = dev->base_addr;
3877 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3880 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3881 outl(sts, DE4X5_STS);
3892 reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3894 struct de4x5_private *lp = netdev_priv(dev);
3895 u_long iobase = dev->base_addr;
3900 srom_exec(dev, lp->phy[lp->active].rst);
3901 srom_exec(dev, lp->phy[lp->active].gep);
3902 outl(1, DE4X5_SICR);
3905 csr15 = lp->cache.csr15;
3906 csr14 = lp->cache.csr14;
3907 csr13 = lp->cache.csr13;
3908 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3909 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3912 outl(csr15, DE4X5_SIGR);
3914 outl(csr14, DE4X5_STRR);
3915 outl(csr13, DE4X5_SICR);
3923 ** Create a loopback ethernet packet
3926 create_packet(struct net_device *dev, char *frame, int len)
3931 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3932 *buf++ = dev->dev_addr[i];
3934 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3935 *buf++ = dev->dev_addr[i];
3938 *buf++ = 0; /* Packet length (2 bytes) */
3945 ** Look for a particular board name in the EISA configuration space
3948 EISA_signature(char *name, struct device *device)
3950 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
3951 struct eisa_device *edev;
3954 edev = to_eisa_device (device);
3955 i = edev->id.driver_data;
3957 if (i >= 0 && i < siglen) {
3958 strcpy (name, de4x5_signatures[i]);
3962 return status; /* return the device name string */
3966 ** Look for a particular board name in the PCI configuration space
3969 PCI_signature(char *name, struct de4x5_private *lp)
3971 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
3973 if (lp->chipset == DC21040) {
3974 strcpy(name, "DE434/5");
3976 } else { /* Search for a DEC name in the SROM */
3977 int i = *((char *)&lp->srom + 19) * 3;
3978 strncpy(name, (char *)&lp->srom + 26 + i, 8);
3981 for (i=0; i<siglen; i++) {
3982 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3987 } else { /* Use chip name to avoid confusion */
3988 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3989 ((lp->chipset == DC21041) ? "DC21041" :
3990 ((lp->chipset == DC21140) ? "DC21140" :
3991 ((lp->chipset == DC21142) ? "DC21142" :
3992 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
3995 if (lp->chipset != DC21041) {
3996 lp->useSROM = TRUE; /* card is not recognisably DEC */
3998 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
4006 ** Set up the Ethernet PROM counter to the start of the Ethernet address on
4007 ** the DC21040, else read the SROM for the other chips.
4008 ** The SROM may not be present in a multi-MAC card, so first read the
4009 ** MAC address and check for a bad address. If there is a bad one then exit
4010 ** immediately with the prior srom contents intact (the h/w address will
4011 ** be fixed up later).
4014 DevicePresent(struct net_device *dev, u_long aprom_addr)
4017 struct de4x5_private *lp = netdev_priv(dev);
4019 if (lp->chipset == DC21040) {
4020 if (lp->bus == EISA) {
4021 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
4023 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
4025 } else { /* Read new srom */
4026 u_short tmp, *p = (short *)((char *)&lp->srom + SROM_HWADD);
4027 for (i=0; i<(ETH_ALEN>>1); i++) {
4028 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
4029 *p = le16_to_cpu(tmp);
4032 if ((j == 0) || (j == 0x2fffd)) {
4036 p=(short *)&lp->srom;
4037 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4038 tmp = srom_rd(aprom_addr, i);
4039 *p++ = le16_to_cpu(tmp);
4041 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4048 ** Since the write on the Enet PROM register doesn't seem to reset the PROM
4049 ** pointer correctly (at least on my DE425 EISA card), this routine should do
4050 ** it...from depca.c.
4053 enet_addr_rst(u_long aprom_addr)
4060 char Sig[sizeof(u32) << 1];
4066 dev.llsig.a = ETH_PROM_SIG;
4067 dev.llsig.b = ETH_PROM_SIG;
4068 sigLength = sizeof(u32) << 1;
4070 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4071 data = inb(aprom_addr);
4072 if (dev.Sig[j] == data) { /* track signature */
4074 } else { /* lost signature; begin search again */
4075 if (data == dev.Sig[0]) { /* rare case.... */
4087 ** For the bad status case and no SROM, then add one to the previous
4088 ** address. However, need to add one backwards in case we have 0xff
4089 ** as one or more of the bytes. Only the last 3 bytes should be checked
4090 ** as the first three are invariant - assigned to an organisation.
4093 get_hw_addr(struct net_device *dev)
4095 u_long iobase = dev->base_addr;
4096 int broken, i, k, tmp, status = 0;
4098 struct de4x5_private *lp = netdev_priv(dev);
4100 broken = de4x5_bad_srom(lp);
4102 for (i=0,k=0,j=0;j<3;j++) {
4104 if (k > 0xffff) k-=0xffff;
4106 if (lp->bus == PCI) {
4107 if (lp->chipset == DC21040) {
4108 while ((tmp = inl(DE4X5_APROM)) < 0);
4110 dev->dev_addr[i++] = (u_char) tmp;
4111 while ((tmp = inl(DE4X5_APROM)) < 0);
4112 k += (u_short) (tmp << 8);
4113 dev->dev_addr[i++] = (u_char) tmp;
4114 } else if (!broken) {
4115 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4116 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4117 } else if ((broken == SMC) || (broken == ACCTON)) {
4118 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4119 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4122 k += (u_char) (tmp = inb(EISA_APROM));
4123 dev->dev_addr[i++] = (u_char) tmp;
4124 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4125 dev->dev_addr[i++] = (u_char) tmp;
4128 if (k > 0xffff) k-=0xffff;
4130 if (k == 0xffff) k=0;
4132 if (lp->bus == PCI) {
4133 if (lp->chipset == DC21040) {
4134 while ((tmp = inl(DE4X5_APROM)) < 0);
4135 chksum = (u_char) tmp;
4136 while ((tmp = inl(DE4X5_APROM)) < 0);
4137 chksum |= (u_short) (tmp << 8);
4138 if ((k != chksum) && (dec_only)) status = -1;
4141 chksum = (u_char) inb(EISA_APROM);
4142 chksum |= (u_short) (inb(EISA_APROM) << 8);
4143 if ((k != chksum) && (dec_only)) status = -1;
4146 /* If possible, try to fix a broken card - SMC only so far */
4147 srom_repair(dev, broken);
4149 #ifdef CONFIG_PPC_MULTIPLATFORM
4151 ** If the address starts with 00 a0, we have to bit-reverse
4152 ** each byte of the address.
4154 if ( (_machine & _MACH_Pmac) &&
4155 (dev->dev_addr[0] == 0) &&
4156 (dev->dev_addr[1] == 0xa0) )
4158 for (i = 0; i < ETH_ALEN; ++i)
4160 int x = dev->dev_addr[i];
4161 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4162 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4163 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4166 #endif /* CONFIG_PPC_MULTIPLATFORM */
4168 /* Test for a bad enet address */
4169 status = test_bad_enet(dev, status);
4175 ** Test for enet addresses in the first 32 bytes. The built-in strncmp
4176 ** didn't seem to work here...?
4179 de4x5_bad_srom(struct de4x5_private *lp)
4183 for (i=0; i<sizeof(enet_det)/ETH_ALEN; i++) {
4184 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4185 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4188 } else if (i == 1) {
4199 de4x5_strncmp(char *a, char *b, int n)
4203 for (;n && !ret;n--) {
4211 srom_repair(struct net_device *dev, int card)
4213 struct de4x5_private *lp = netdev_priv(dev);
4217 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4218 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4219 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4228 ** Assume that the irq's do not follow the PCI spec - this is seems
4229 ** to be true so far (2 for 2).
4232 test_bad_enet(struct net_device *dev, int status)
4234 struct de4x5_private *lp = netdev_priv(dev);
4237 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4238 if ((tmp == 0) || (tmp == 0x5fa)) {
4239 if ((lp->chipset == last.chipset) &&
4240 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4241 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4242 for (i=ETH_ALEN-1; i>2; --i) {
4243 dev->dev_addr[i] += 1;
4244 if (dev->dev_addr[i] != 0) break;
4246 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4247 if (!an_exception(lp)) {
4248 dev->irq = last.irq;
4253 } else if (!status) {
4254 last.chipset = lp->chipset;
4255 last.bus = lp->bus_num;
4256 last.irq = dev->irq;
4257 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4264 ** List of board exceptions with correctly wired IRQs
4267 an_exception(struct de4x5_private *lp)
4269 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4270 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4281 srom_rd(u_long addr, u_char offset)
4283 sendto_srom(SROM_RD | SROM_SR, addr);
4285 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4286 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4287 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4289 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4293 srom_latch(u_int command, u_long addr)
4295 sendto_srom(command, addr);
4296 sendto_srom(command | DT_CLK, addr);
4297 sendto_srom(command, addr);
4303 srom_command(u_int command, u_long addr)
4305 srom_latch(command, addr);
4306 srom_latch(command, addr);
4307 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4313 srom_address(u_int command, u_long addr, u_char offset)
4318 for (i=0; i<6; i++, a <<= 1) {
4319 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4323 i = (getfrom_srom(addr) >> 3) & 0x01;
4329 srom_data(u_int command, u_long addr)
4335 for (i=0; i<16; i++) {
4336 sendto_srom(command | DT_CLK, addr);
4337 tmp = getfrom_srom(addr);
4338 sendto_srom(command, addr);
4340 word = (word << 1) | ((tmp >> 3) & 0x01);
4343 sendto_srom(command & 0x0000ff00, addr);
4350 srom_busy(u_int command, u_long addr)
4352 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4354 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4358 sendto_srom(command & 0x0000ff00, addr);
4365 sendto_srom(u_int command, u_long addr)
4367 outl(command, addr);
4374 getfrom_srom(u_long addr)
4385 srom_infoleaf_info(struct net_device *dev)
4387 struct de4x5_private *lp = netdev_priv(dev);
4391 /* Find the infoleaf decoder function that matches this chipset */
4392 for (i=0; i<INFOLEAF_SIZE; i++) {
4393 if (lp->chipset == infoleaf_array[i].chipset) break;
4395 if (i == INFOLEAF_SIZE) {
4396 lp->useSROM = FALSE;
4397 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4402 lp->infoleaf_fn = infoleaf_array[i].fn;
4404 /* Find the information offset that this function should use */
4405 count = *((u_char *)&lp->srom + 19);
4406 p = (u_char *)&lp->srom + 26;
4409 for (i=count; i; --i, p+=3) {
4410 if (lp->device == *p) break;
4413 lp->useSROM = FALSE;
4414 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4415 dev->name, lp->device);
4420 lp->infoleaf_offset = TWIDDLE(p+1);
4426 ** This routine loads any type 1 or 3 MII info into the mii device
4427 ** struct and executes any type 5 code to reset PHY devices for this
4429 ** The info for the MII devices will be valid since the index used
4430 ** will follow the discovery process from MII address 1-31 then 0.
4433 srom_init(struct net_device *dev)
4435 struct de4x5_private *lp = netdev_priv(dev);
4436 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4440 if (lp->chipset == DC21140) {
4441 lp->cache.gepc = (*p++ | GEP_CTRL);
4442 gep_wr(lp->cache.gepc, dev);
4448 /* Jump the infoblocks to find types */
4449 for (;count; --count) {
4452 } else if (*(p+1) == 5) {
4453 type5_infoblock(dev, 1, p);
4454 p += ((*p & BLOCK_LEN) + 1);
4455 } else if (*(p+1) == 4) {
4456 p += ((*p & BLOCK_LEN) + 1);
4457 } else if (*(p+1) == 3) {
4458 type3_infoblock(dev, 1, p);
4459 p += ((*p & BLOCK_LEN) + 1);
4460 } else if (*(p+1) == 2) {
4461 p += ((*p & BLOCK_LEN) + 1);
4462 } else if (*(p+1) == 1) {
4463 type1_infoblock(dev, 1, p);
4464 p += ((*p & BLOCK_LEN) + 1);
4466 p += ((*p & BLOCK_LEN) + 1);
4474 ** A generic routine that writes GEP control, data and reset information
4475 ** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4478 srom_exec(struct net_device *dev, u_char *p)
4480 struct de4x5_private *lp = netdev_priv(dev);
4481 u_long iobase = dev->base_addr;
4482 u_char count = (p ? *p++ : 0);
4483 u_short *w = (u_short *)p;
4485 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4487 if (lp->chipset != DC21140) RESET_SIA;
4490 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4491 *p++ : TWIDDLE(w++)), dev);
4492 mdelay(2); /* 2ms per action */
4495 if (lp->chipset != DC21140) {
4496 outl(lp->cache.csr14, DE4X5_STRR);
4497 outl(lp->cache.csr13, DE4X5_SICR);
4504 ** Basically this function is a NOP since it will never be called,
4505 ** unless I implement the DC21041 SROM functions. There's no need
4506 ** since the existing code will be satisfactory for all boards.
4509 dc21041_infoleaf(struct net_device *dev)
4511 return DE4X5_AUTOSENSE_MS;
4515 dc21140_infoleaf(struct net_device *dev)
4517 struct de4x5_private *lp = netdev_priv(dev);
4519 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4520 int next_tick = DE4X5_AUTOSENSE_MS;
4522 /* Read the connection type */
4526 lp->cache.gepc = (*p++ | GEP_CTRL);
4531 /* Recursively figure out the info blocks */
4533 next_tick = dc_infoblock[COMPACT](dev, count, p);
4535 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4538 if (lp->tcount == count) {
4540 if (lp->media != lp->c_media) {
4541 de4x5_dbg_media(dev);
4542 lp->c_media = lp->media;
4546 lp->tx_enable = FALSE;
4549 return next_tick & ~TIMER_CB;
4553 dc21142_infoleaf(struct net_device *dev)
4555 struct de4x5_private *lp = netdev_priv(dev);
4557 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4558 int next_tick = DE4X5_AUTOSENSE_MS;
4560 /* Read the connection type */
4566 /* Recursively figure out the info blocks */
4568 next_tick = dc_infoblock[COMPACT](dev, count, p);
4570 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4573 if (lp->tcount == count) {
4575 if (lp->media != lp->c_media) {
4576 de4x5_dbg_media(dev);
4577 lp->c_media = lp->media;
4581 lp->tx_enable = FALSE;
4584 return next_tick & ~TIMER_CB;
4588 dc21143_infoleaf(struct net_device *dev)
4590 struct de4x5_private *lp = netdev_priv(dev);
4592 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4593 int next_tick = DE4X5_AUTOSENSE_MS;
4595 /* Read the connection type */
4601 /* Recursively figure out the info blocks */
4603 next_tick = dc_infoblock[COMPACT](dev, count, p);
4605 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4607 if (lp->tcount == count) {
4609 if (lp->media != lp->c_media) {
4610 de4x5_dbg_media(dev);
4611 lp->c_media = lp->media;
4615 lp->tx_enable = FALSE;
4618 return next_tick & ~TIMER_CB;
4622 ** The compact infoblock is only designed for DC21140[A] chips, so
4623 ** we'll reuse the dc21140m_autoconf function. Non MII media only.
4626 compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4628 struct de4x5_private *lp = netdev_priv(dev);
4631 /* Recursively figure out the info blocks */
4632 if (--count > lp->tcount) {
4633 if (*(p+COMPACT_LEN) < 128) {
4634 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4636 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4640 if ((lp->media == INIT) && (lp->timeout < 0)) {
4643 gep_wr(lp->cache.gepc, dev);
4644 lp->infoblock_media = (*p++) & COMPACT_MC;
4645 lp->cache.gep = *p++;
4649 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4650 lp->defMedium = (flags & 0x40) ? -1 : 0;
4651 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4652 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4653 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4656 de4x5_switch_mac_port(dev);
4659 return dc21140m_autoconf(dev);
4663 ** This block describes non MII media for the DC21140[A] only.
4666 type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4668 struct de4x5_private *lp = netdev_priv(dev);
4669 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4671 /* Recursively figure out the info blocks */
4672 if (--count > lp->tcount) {
4673 if (*(p+len) < 128) {
4674 return dc_infoblock[COMPACT](dev, count, p+len);
4676 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4680 if ((lp->media == INIT) && (lp->timeout < 0)) {
4683 gep_wr(lp->cache.gepc, dev);
4685 lp->infoblock_media = (*p++) & BLOCK0_MC;
4686 lp->cache.gep = *p++;
4690 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4691 lp->defMedium = (flags & 0x40) ? -1 : 0;
4692 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4693 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4694 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4697 de4x5_switch_mac_port(dev);
4700 return dc21140m_autoconf(dev);
4703 /* These functions are under construction! */
4706 type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4708 struct de4x5_private *lp = netdev_priv(dev);
4709 u_char len = (*p & BLOCK_LEN)+1;
4711 /* Recursively figure out the info blocks */
4712 if (--count > lp->tcount) {
4713 if (*(p+len) < 128) {
4714 return dc_infoblock[COMPACT](dev, count, p+len);
4716 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4721 if (lp->state == INITIALISED) {
4724 lp->phy[lp->active].gep = (*p ? p : 0); p += (*p + 1);
4725 lp->phy[lp->active].rst = (*p ? p : 0); p += (*p + 1);
4726 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4727 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4728 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4729 lp->phy[lp->active].ttm = TWIDDLE(p);
4731 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4734 lp->infoblock_csr6 = OMR_MII_100;
4736 lp->infoblock_media = ANS;
4738 de4x5_switch_mac_port(dev);
4741 return dc21140m_autoconf(dev);
4745 type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4747 struct de4x5_private *lp = netdev_priv(dev);
4748 u_char len = (*p & BLOCK_LEN)+1;
4750 /* Recursively figure out the info blocks */
4751 if (--count > lp->tcount) {
4752 if (*(p+len) < 128) {
4753 return dc_infoblock[COMPACT](dev, count, p+len);
4755 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4759 if ((lp->media == INIT) && (lp->timeout < 0)) {
4763 lp->infoblock_media = (*p) & MEDIA_CODE;
4765 if ((*p++) & EXT_FIELD) {
4766 lp->cache.csr13 = TWIDDLE(p); p += 2;
4767 lp->cache.csr14 = TWIDDLE(p); p += 2;
4768 lp->cache.csr15 = TWIDDLE(p); p += 2;
4770 lp->cache.csr13 = CSR13;
4771 lp->cache.csr14 = CSR14;
4772 lp->cache.csr15 = CSR15;
4774 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4775 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16);
4776 lp->infoblock_csr6 = OMR_SIA;
4779 de4x5_switch_mac_port(dev);
4782 return dc2114x_autoconf(dev);
4786 type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4788 struct de4x5_private *lp = netdev_priv(dev);
4789 u_char len = (*p & BLOCK_LEN)+1;
4791 /* Recursively figure out the info blocks */
4792 if (--count > lp->tcount) {
4793 if (*(p+len) < 128) {
4794 return dc_infoblock[COMPACT](dev, count, p+len);
4796 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4801 if (lp->state == INITIALISED) {
4804 if (MOTO_SROM_BUG) lp->active = 0;
4805 lp->phy[lp->active].gep = (*p ? p : 0); p += (2 * (*p) + 1);
4806 lp->phy[lp->active].rst = (*p ? p : 0); p += (2 * (*p) + 1);
4807 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4808 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4809 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4810 lp->phy[lp->active].ttm = TWIDDLE(p); p += 2;
4811 lp->phy[lp->active].mci = *p;
4813 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4816 if (MOTO_SROM_BUG) lp->active = 0;
4817 lp->infoblock_csr6 = OMR_MII_100;
4819 lp->infoblock_media = ANS;
4821 de4x5_switch_mac_port(dev);
4824 return dc2114x_autoconf(dev);
4828 type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4830 struct de4x5_private *lp = netdev_priv(dev);
4831 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4833 /* Recursively figure out the info blocks */
4834 if (--count > lp->tcount) {
4835 if (*(p+len) < 128) {
4836 return dc_infoblock[COMPACT](dev, count, p+len);
4838 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4842 if ((lp->media == INIT) && (lp->timeout < 0)) {
4846 lp->infoblock_media = (*p++) & MEDIA_CODE;
4847 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4848 lp->cache.csr14 = CSR14;
4849 lp->cache.csr15 = CSR15;
4850 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4851 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); p += 2;
4855 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4856 lp->defMedium = (flags & 0x40) ? -1 : 0;
4857 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4858 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4859 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4862 de4x5_switch_mac_port(dev);
4865 return dc2114x_autoconf(dev);
4869 ** This block type provides information for resetting external devices
4870 ** (chips) through the General Purpose Register.
4873 type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4875 struct de4x5_private *lp = netdev_priv(dev);
4876 u_char len = (*p & BLOCK_LEN)+1;
4878 /* Recursively figure out the info blocks */
4879 if (--count > lp->tcount) {
4880 if (*(p+len) < 128) {
4881 return dc_infoblock[COMPACT](dev, count, p+len);
4883 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4887 /* Must be initializing to run this code */
4888 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4891 srom_exec(dev, lp->rst);
4894 return DE4X5_AUTOSENSE_MS;
4902 mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4904 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4905 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4906 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4907 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4908 mii_address(phyreg, ioaddr); /* PHY Register to read */
4909 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4911 return mii_rdata(ioaddr); /* Read data */
4915 mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4917 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4918 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4919 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4920 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4921 mii_address(phyreg, ioaddr); /* PHY Register to write */
4922 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4923 data = mii_swap(data, 16); /* Swap data bit ordering */
4924 mii_wdata(data, 16, ioaddr); /* Write data */
4930 mii_rdata(u_long ioaddr)
4935 for (i=0; i<16; i++) {
4937 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4944 mii_wdata(int data, int len, u_long ioaddr)
4948 for (i=0; i<len; i++) {
4949 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4957 mii_address(u_char addr, u_long ioaddr)
4961 addr = mii_swap(addr, 5);
4962 for (i=0; i<5; i++) {
4963 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4971 mii_ta(u_long rw, u_long ioaddr)
4973 if (rw == MII_STWR) {
4974 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4975 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4977 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
4984 mii_swap(int data, int len)
4988 for (i=0; i<len; i++) {
4998 sendto_mii(u32 command, int data, u_long ioaddr)
5002 j = (data & 1) << 17;
5003 outl(command | j, ioaddr);
5005 outl(command | MII_MDC | j, ioaddr);
5012 getfrom_mii(u32 command, u_long ioaddr)
5014 outl(command, ioaddr);
5016 outl(command | MII_MDC, ioaddr);
5019 return ((inl(ioaddr) >> 19) & 1);
5023 ** Here's 3 ways to calculate the OUI from the ID registers.
5026 mii_get_oui(u_char phyaddr, u_long ioaddr)
5033 int i, r2, r3, ret=0;*/
5036 /* Read r2 and r3 */
5037 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
5038 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
5039 /* SEEQ and Cypress way * /
5040 / * Shuffle r2 and r3 * /
5042 r3 = ((r3>>10)|(r2<<6))&0x0ff;
5043 r2 = ((r2>>2)&0x3fff);
5045 / * Bit reverse r3 * /
5052 / * Bit reverse r2 * /
5053 for (i=0;i<16;i++) {
5059 / * Swap r2 bytes * /
5061 a.breg[0]=a.breg[1];
5064 return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */
5065 /* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */
5066 return r2; /* (I did it) My way */
5070 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5073 mii_get_phy(struct net_device *dev)
5075 struct de4x5_private *lp = netdev_priv(dev);
5076 u_long iobase = dev->base_addr;
5077 int i, j, k, n, limit=sizeof(phy_info)/sizeof(struct phy_table);
5083 /* Search the MII address space for possible PHY devices */
5084 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(++i)%DE4X5_MAX_MII) {
5085 lp->phy[lp->active].addr = i;
5086 if (i==0) n++; /* Count cycles */
5087 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
5088 id = mii_get_oui(i, DE4X5_MII);
5089 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
5090 for (j=0; j<limit; j++) { /* Search PHY table */
5091 if (id != phy_info[j].id) continue; /* ID match? */
5092 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5093 if (k < DE4X5_MAX_PHY) {
5094 memcpy((char *)&lp->phy[k],
5095 (char *)&phy_info[j], sizeof(struct phy_table));
5096 lp->phy[k].addr = i;
5100 goto purgatory; /* Stop the search */
5104 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5105 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5106 lp->phy[k].addr = i;
5108 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5109 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5110 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5113 printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name);
5115 de4x5_debug |= DEBUG_MII;
5116 de4x5_dbg_mii(dev, k);
5123 if (lp->phy[0].id) { /* Reset the PHY devices */
5124 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/
5125 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5126 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5128 de4x5_dbg_mii(dev, k);
5131 if (!lp->mii_cnt) lp->useMII = FALSE;
5137 build_setup_frame(struct net_device *dev, int mode)
5139 struct de4x5_private *lp = netdev_priv(dev);
5141 char *pa = lp->setup_frame;
5143 /* Initialise the setup frame */
5145 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5148 if (lp->setup_f == HASH_PERF) {
5149 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5150 *(pa + i) = dev->dev_addr[i]; /* Host address */
5151 if (i & 0x01) pa += 2;
5153 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5155 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5156 *(pa + (i&1)) = dev->dev_addr[i];
5157 if (i & 0x01) pa += 4;
5159 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5160 *(pa + (i&1)) = (char) 0xff;
5161 if (i & 0x01) pa += 4;
5165 return pa; /* Points to the next entry */
5169 enable_ast(struct net_device *dev, u32 time_out)
5171 timeout(dev, (void *)&de4x5_ast, (u_long)dev, time_out);
5177 disable_ast(struct net_device *dev)
5179 struct de4x5_private *lp = netdev_priv(dev);
5181 del_timer(&lp->timer);
5187 de4x5_switch_mac_port(struct net_device *dev)
5189 struct de4x5_private *lp = netdev_priv(dev);
5190 u_long iobase = dev->base_addr;
5195 /* Assert the OMR_PS bit in CSR6 */
5196 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5198 omr |= lp->infoblock_csr6;
5199 if (omr & OMR_PS) omr |= OMR_HBD;
5200 outl(omr, DE4X5_OMR);
5205 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5206 if (lp->chipset == DC21140) {
5207 gep_wr(lp->cache.gepc, dev);
5208 gep_wr(lp->cache.gep, dev);
5209 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5210 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5214 outl(omr, DE4X5_OMR);
5223 gep_wr(s32 data, struct net_device *dev)
5225 struct de4x5_private *lp = netdev_priv(dev);
5226 u_long iobase = dev->base_addr;
5228 if (lp->chipset == DC21140) {
5229 outl(data, DE4X5_GEP);
5230 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5231 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5238 gep_rd(struct net_device *dev)
5240 struct de4x5_private *lp = netdev_priv(dev);
5241 u_long iobase = dev->base_addr;
5243 if (lp->chipset == DC21140) {
5244 return inl(DE4X5_GEP);
5245 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5246 return (inl(DE4X5_SIGR) & 0x000fffff);
5253 timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec)
5255 struct de4x5_private *lp = netdev_priv(dev);
5258 /* First, cancel any pending timer events */
5259 del_timer(&lp->timer);
5261 /* Convert msec to ticks */
5262 dt = (msec * HZ) / 1000;
5266 init_timer(&lp->timer);
5267 lp->timer.expires = jiffies + dt;
5268 lp->timer.function = fn;
5269 lp->timer.data = data;
5270 add_timer(&lp->timer);
5276 yawn(struct net_device *dev, int state)
5278 struct de4x5_private *lp = netdev_priv(dev);
5279 u_long iobase = dev->base_addr;
5281 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5283 if(lp->bus == EISA) {
5286 outb(WAKEUP, PCI_CFPM);
5291 outb(SNOOZE, PCI_CFPM);
5295 outl(0, DE4X5_SICR);
5296 outb(SLEEP, PCI_CFPM);
5300 struct pci_dev *pdev = to_pci_dev (lp->gendev);
5303 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
5308 pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE);
5312 outl(0, DE4X5_SICR);
5313 pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP);
5322 de4x5_parse_params(struct net_device *dev)
5324 struct de4x5_private *lp = netdev_priv(dev);
5328 lp->params.autosense = AUTO;
5330 if (args == NULL) return;
5332 if ((p = strstr(args, dev->name))) {
5333 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5337 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5339 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5340 if (strstr(p, "TP")) {
5341 lp->params.autosense = TP;
5342 } else if (strstr(p, "TP_NW")) {
5343 lp->params.autosense = TP_NW;
5344 } else if (strstr(p, "BNC")) {
5345 lp->params.autosense = BNC;
5346 } else if (strstr(p, "AUI")) {
5347 lp->params.autosense = AUI;
5348 } else if (strstr(p, "BNC_AUI")) {
5349 lp->params.autosense = BNC;
5350 } else if (strstr(p, "10Mb")) {
5351 lp->params.autosense = _10Mb;
5352 } else if (strstr(p, "100Mb")) {
5353 lp->params.autosense = _100Mb;
5354 } else if (strstr(p, "AUTO")) {
5355 lp->params.autosense = AUTO;
5365 de4x5_dbg_open(struct net_device *dev)
5367 struct de4x5_private *lp = netdev_priv(dev);
5370 if (de4x5_debug & DEBUG_OPEN) {
5371 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5372 printk("\tphysical address: ");
5374 printk("%2.2x:",(short)dev->dev_addr[i]);
5377 printk("Descriptor head addresses:\n");
5378 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5379 printk("Descriptor addresses:\nRX: ");
5380 for (i=0;i<lp->rxRingSize-1;i++){
5382 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5385 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5387 for (i=0;i<lp->txRingSize-1;i++){
5389 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5392 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5393 printk("Descriptor buffers:\nRX: ");
5394 for (i=0;i<lp->rxRingSize-1;i++){
5396 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5399 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5401 for (i=0;i<lp->txRingSize-1;i++){
5403 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5406 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5407 printk("Ring size: \nRX: %d\nTX: %d\n",
5408 (short)lp->rxRingSize,
5409 (short)lp->txRingSize);
5416 de4x5_dbg_mii(struct net_device *dev, int k)
5418 struct de4x5_private *lp = netdev_priv(dev);
5419 u_long iobase = dev->base_addr;
5421 if (de4x5_debug & DEBUG_MII) {
5422 printk("\nMII device address: %d\n", lp->phy[k].addr);
5423 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5424 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5425 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5426 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5427 if (lp->phy[k].id != BROADCOM_T4) {
5428 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5429 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5431 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5432 if (lp->phy[k].id != BROADCOM_T4) {
5433 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5434 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5436 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5444 de4x5_dbg_media(struct net_device *dev)
5446 struct de4x5_private *lp = netdev_priv(dev);
5448 if (lp->media != lp->c_media) {
5449 if (de4x5_debug & DEBUG_MEDIA) {
5450 printk("%s: media is %s%s\n", dev->name,
5451 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5452 (lp->media == TP ? "TP" :
5453 (lp->media == ANS ? "TP/Nway" :
5454 (lp->media == BNC ? "BNC" :
5455 (lp->media == AUI ? "AUI" :
5456 (lp->media == BNC_AUI ? "BNC/AUI" :
5457 (lp->media == EXT_SIA ? "EXT SIA" :
5458 (lp->media == _100Mb ? "100Mb/s" :
5459 (lp->media == _10Mb ? "10Mb/s" :
5461 ))))))))), (lp->fdx?" full duplex.":"."));
5463 lp->c_media = lp->media;
5470 de4x5_dbg_srom(struct de4x5_srom *p)
5474 if (de4x5_debug & DEBUG_SROM) {
5475 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5476 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5477 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5478 printk("SROM version: %02x\n", (u_char)(p->version));
5479 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5481 printk("Hardware Address: ");
5482 for (i=0;i<ETH_ALEN-1;i++) {
5483 printk("%02x:", (u_char)*(p->ieee_addr+i));
5485 printk("%02x\n", (u_char)*(p->ieee_addr+i));
5486 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5487 for (i=0; i<64; i++) {
5488 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5496 de4x5_dbg_rx(struct sk_buff *skb, int len)
5500 if (de4x5_debug & DEBUG_RX) {
5501 printk("R: %02x:%02x:%02x:%02x:%02x:%02x <- %02x:%02x:%02x:%02x:%02x:%02x len/SAP:%02x%02x [%d]\n",
5502 (u_char)skb->data[0],
5503 (u_char)skb->data[1],
5504 (u_char)skb->data[2],
5505 (u_char)skb->data[3],
5506 (u_char)skb->data[4],
5507 (u_char)skb->data[5],
5508 (u_char)skb->data[6],
5509 (u_char)skb->data[7],
5510 (u_char)skb->data[8],
5511 (u_char)skb->data[9],
5512 (u_char)skb->data[10],
5513 (u_char)skb->data[11],
5514 (u_char)skb->data[12],
5515 (u_char)skb->data[13],
5517 for (j=0; len>0;j+=16, len-=16) {
5518 printk(" %03x: ",j);
5519 for (i=0; i<16 && i<len; i++) {
5520 printk("%02x ",(u_char)skb->data[i+j]);
5530 ** Perform IOCTL call functions here. Some are privileged operations and the
5531 ** effective uid is checked in those cases. In the normal course of events
5532 ** this function is only used for my testing.
5535 de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5537 struct de4x5_private *lp = netdev_priv(dev);
5538 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
5539 u_long iobase = dev->base_addr;
5540 int i, j, status = 0;
5550 case DE4X5_GET_HWADDR: /* Get the hardware address */
5551 ioc->len = ETH_ALEN;
5552 for (i=0; i<ETH_ALEN; i++) {
5553 tmp.addr[i] = dev->dev_addr[i];
5555 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5558 case DE4X5_SET_HWADDR: /* Set the hardware address */
5559 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5560 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5561 if (netif_queue_stopped(dev))
5563 netif_stop_queue(dev);
5564 for (i=0; i<ETH_ALEN; i++) {
5565 dev->dev_addr[i] = tmp.addr[i];
5567 build_setup_frame(dev, PHYS_ADDR_ONLY);
5568 /* Set up the descriptor and give ownership to the card */
5569 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5570 SETUP_FRAME_LEN, (struct sk_buff *)1);
5571 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5572 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5573 netif_wake_queue(dev); /* Unlock the TX ring */
5576 case DE4X5_SET_PROM: /* Set Promiscuous Mode */
5577 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5578 omr = inl(DE4X5_OMR);
5580 outl(omr, DE4X5_OMR);
5581 dev->flags |= IFF_PROMISC;
5584 case DE4X5_CLR_PROM: /* Clear Promiscuous Mode */
5585 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5586 omr = inl(DE4X5_OMR);
5588 outl(omr, DE4X5_OMR);
5589 dev->flags &= ~IFF_PROMISC;
5592 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5593 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5594 printk("%s: Boo!\n", dev->name);
5597 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5598 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5599 omr = inl(DE4X5_OMR);
5601 outl(omr, DE4X5_OMR);
5604 case DE4X5_GET_STATS: /* Get the driver statistics */
5606 struct pkt_stats statbuf;
5607 ioc->len = sizeof(statbuf);
5608 spin_lock_irqsave(&lp->lock, flags);
5609 memcpy(&statbuf, &lp->pktStats, ioc->len);
5610 spin_unlock_irqrestore(&lp->lock, flags);
5611 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5615 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5616 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5617 spin_lock_irqsave(&lp->lock, flags);
5618 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5619 spin_unlock_irqrestore(&lp->lock, flags);
5622 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5623 tmp.addr[0] = inl(DE4X5_OMR);
5624 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5627 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5628 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5629 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5630 outl(tmp.addr[0], DE4X5_OMR);
5633 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5635 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5636 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5637 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5638 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5639 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5640 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5641 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5642 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5644 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5647 #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5651 tmp.addr[j++] = dev->irq;
5652 for (i=0; i<ETH_ALEN; i++) {
5653 tmp.addr[j++] = dev->dev_addr[i];
5655 tmp.addr[j++] = lp->rxRingSize;
5656 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5657 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5659 for (i=0;i<lp->rxRingSize-1;i++){
5661 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5664 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5665 for (i=0;i<lp->txRingSize-1;i++){
5667 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5670 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5672 for (i=0;i<lp->rxRingSize-1;i++){
5674 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5677 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5678 for (i=0;i<lp->txRingSize-1;i++){
5680 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5683 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5685 for (i=0;i<lp->rxRingSize;i++){
5686 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5688 for (i=0;i<lp->txRingSize;i++){
5689 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5692 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5693 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5694 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5695 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5696 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5697 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5698 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5699 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5700 tmp.lval[j>>2] = lp->chipset; j+=4;
5701 if (lp->chipset == DC21140) {
5702 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5704 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5705 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5706 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5707 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5709 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5710 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5711 tmp.lval[j>>2] = lp->active; j+=4;
5712 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5713 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5714 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5715 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5716 if (lp->phy[lp->active].id != BROADCOM_T4) {
5717 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5718 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5720 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5721 if (lp->phy[lp->active].id != BROADCOM_T4) {
5722 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5723 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5725 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5729 tmp.addr[j++] = lp->txRingSize;
5730 tmp.addr[j++] = netif_queue_stopped(dev);
5733 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5744 static int __init de4x5_module_init (void)
5749 err = pci_module_init (&de4x5_pci_driver);
5752 err |= eisa_driver_register (&de4x5_eisa_driver);
5758 static void __exit de4x5_module_exit (void)
5761 pci_unregister_driver (&de4x5_pci_driver);
5764 eisa_driver_unregister (&de4x5_eisa_driver);
5768 module_init (de4x5_module_init);
5769 module_exit (de4x5_module_exit);