2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 DAVICOM Web-Site: www.davicom.com.tw
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
26 Alan Cox <alan@redhat.com> :
27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
52 Alan Cox <alan@redhat.com>
53 Added new PCI identifiers provided by Clear Zhang at ALi
54 for their 1563 ethernet device.
58 Implement pci_driver::suspend() and pci_driver::resume()
59 power management methods.
61 Check on 64 bit boxes.
62 Check and fix on big endian boxes.
64 Test and make sure PCI latency is now correct for all cases.
67 #define DRV_NAME "dmfe"
68 #define DRV_VERSION "1.36.4"
69 #define DRV_RELDATE "2002-01-17"
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/string.h>
74 #include <linux/timer.h>
75 #include <linux/ptrace.h>
76 #include <linux/errno.h>
77 #include <linux/ioport.h>
78 #include <linux/slab.h>
79 #include <linux/interrupt.h>
80 #include <linux/pci.h>
81 #include <linux/init.h>
82 #include <linux/netdevice.h>
83 #include <linux/etherdevice.h>
84 #include <linux/ethtool.h>
85 #include <linux/skbuff.h>
86 #include <linux/delay.h>
87 #include <linux/spinlock.h>
88 #include <linux/crc32.h>
90 #include <asm/processor.h>
91 #include <asm/bitops.h>
94 #include <asm/uaccess.h>
97 /* Board/System/Debug information/definition ---------------- */
98 #define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
99 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
100 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
101 #define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
103 #define DM9102_IO_SIZE 0x80
104 #define DM9102A_IO_SIZE 0x100
105 #define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
106 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
107 #define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
108 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
109 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
110 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
111 #define TX_BUF_ALLOC 0x600
112 #define RX_ALLOC_SIZE 0x620
113 #define DM910X_RESET 1
114 #define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
115 #define CR6_DEFAULT 0x00080000 /* HD */
116 #define CR7_DEFAULT 0x180c1
117 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
118 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
119 #define MAX_PACKET_SIZE 1514
120 #define DMFE_MAX_MULTICAST 14
121 #define RX_COPY_SIZE 100
122 #define MAX_CHECK_PACKET 0x8000
123 #define DM9801_NOISE_FLOOR 8
124 #define DM9802_NOISE_FLOOR 5
127 #define DMFE_100MHF 1
129 #define DMFE_100MFD 5
131 #define DMFE_1M_HPNA 0x10
133 #define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
134 #define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
135 #define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
136 #define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
137 #define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
138 #define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
140 #define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
141 #define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
142 #define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
144 #define DMFE_DBUG(dbug_now, msg, value) if (dmfe_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
146 #define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
149 /* CR9 definition: SROM/MII */
150 #define CR9_SROM_READ 0x4800
152 #define CR9_SRCLK 0x2
153 #define CR9_CRDOUT 0x8
154 #define SROM_DATA_0 0x0
155 #define SROM_DATA_1 0x4
156 #define PHY_DATA_1 0x20000
157 #define PHY_DATA_0 0x00000
158 #define MDCLKH 0x10000
160 #define PHY_POWER_DOWN 0x800
162 #define SROM_V41_CODE 0x14
164 #define SROM_CLK_WRITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);
166 #define __CHK_IO_SIZE(pci_id, dev_rev) ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE
167 #define CHK_IO_SIZE(pci_dev, dev_rev) __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)
170 #define DEVICE net_device
172 /* Structure/enum declaration ------------------------------- */
174 u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
175 char *tx_buf_ptr; /* Data for us */
176 struct tx_desc *next_tx_desc;
177 } __attribute__(( aligned(32) ));
180 u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
181 struct sk_buff *rx_skb_ptr; /* Data for us */
182 struct rx_desc *next_rx_desc;
183 } __attribute__(( aligned(32) ));
185 struct dmfe_board_info {
186 u32 chip_id; /* Chip vendor/Device ID */
187 u32 chip_revision; /* Chip revision */
188 struct DEVICE *next_dev; /* next device */
189 struct pci_dev *pdev; /* PCI device */
192 long ioaddr; /* I/O base address */
199 /* pointer for memory physical address */
200 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
201 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
202 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
203 dma_addr_t first_tx_desc_dma;
204 dma_addr_t first_rx_desc_dma;
206 /* descriptor pointer */
207 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
208 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
209 unsigned char *desc_pool_ptr; /* descriptor pool memory */
210 struct tx_desc *first_tx_desc;
211 struct tx_desc *tx_insert_ptr;
212 struct tx_desc *tx_remove_ptr;
213 struct rx_desc *first_rx_desc;
214 struct rx_desc *rx_insert_ptr;
215 struct rx_desc *rx_ready_ptr; /* packet come pointer */
216 unsigned long tx_packet_cnt; /* transmitted packet count */
217 unsigned long tx_queue_cnt; /* wait to send packet count */
218 unsigned long rx_avail_cnt; /* available rx descriptor count */
219 unsigned long interval_rx_cnt; /* rx packet count a callback time */
221 u16 HPNA_command; /* For HPNA register 16 */
222 u16 HPNA_timer; /* For HPNA remote device check */
224 u16 NIC_capability; /* NIC media capability */
225 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
227 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
228 u8 chip_type; /* Keep DM9102A chip type */
229 u8 media_mode; /* user specify media mode */
230 u8 op_mode; /* real work media mode */
232 u8 link_failed; /* Ever link failed */
233 u8 wait_reset; /* Hardware failed, need to reset */
234 u8 dm910x_chk_mode; /* Operating mode check */
235 u8 first_in_callback; /* Flag to record state */
236 struct timer_list timer;
238 /* System defined statistic counter */
239 struct net_device_stats stats;
241 /* Driver defined statistic counter */
242 unsigned long tx_fifo_underrun;
243 unsigned long tx_loss_carrier;
244 unsigned long tx_no_carrier;
245 unsigned long tx_late_collision;
246 unsigned long tx_excessive_collision;
247 unsigned long tx_jabber_timeout;
248 unsigned long reset_count;
249 unsigned long reset_cr8;
250 unsigned long reset_fatal;
251 unsigned long reset_TXtimeout;
254 unsigned char srom[128];
258 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
259 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
260 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
265 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
266 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
267 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
270 /* Global variable declaration ----------------------------- */
271 static int __devinitdata printed_version;
272 static char version[] __devinitdata =
273 KERN_INFO DRV_NAME ": Davicom DM9xxx net driver, version "
274 DRV_VERSION " (" DRV_RELDATE ")\n";
276 static int dmfe_debug;
277 static unsigned char dmfe_media_mode = DMFE_AUTO;
278 static u32 dmfe_cr6_user_set;
280 /* For module input parameter */
283 static unsigned char mode = 8;
284 static u8 chkmode = 1;
285 static u8 HPNA_mode; /* Default: Low Power/High Speed */
286 static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
287 static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
288 static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
289 static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
290 4: TX pause packet */
293 /* function declaration ------------------------------------- */
294 static int dmfe_open(struct DEVICE *);
295 static int dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
296 static int dmfe_stop(struct DEVICE *);
297 static struct net_device_stats * dmfe_get_stats(struct DEVICE *);
298 static void dmfe_set_filter_mode(struct DEVICE *);
299 static struct ethtool_ops netdev_ethtool_ops;
300 static u16 read_srom_word(long ,int);
301 static irqreturn_t dmfe_interrupt(int , void *, struct pt_regs *);
302 #ifdef CONFIG_NET_POLL_CONTROLLER
303 static void poll_dmfe (struct net_device *dev);
305 static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
306 static void allocate_rx_buffer(struct dmfe_board_info *);
307 static void update_cr6(u32, unsigned long);
308 static void send_filter_frame(struct DEVICE * ,int);
309 static void dm9132_id_table(struct DEVICE * ,int);
310 static u16 phy_read(unsigned long, u8, u8, u32);
311 static void phy_write(unsigned long, u8, u8, u16, u32);
312 static void phy_write_1bit(unsigned long, u32);
313 static u16 phy_read_1bit(unsigned long);
314 static u8 dmfe_sense_speed(struct dmfe_board_info *);
315 static void dmfe_process_mode(struct dmfe_board_info *);
316 static void dmfe_timer(unsigned long);
317 static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
318 static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
319 static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
320 static void dmfe_dynamic_reset(struct DEVICE *);
321 static void dmfe_free_rxbuffer(struct dmfe_board_info *);
322 static void dmfe_init_dm910x(struct DEVICE *);
323 static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
324 static void dmfe_parse_srom(struct dmfe_board_info *);
325 static void dmfe_program_DM9801(struct dmfe_board_info *, int);
326 static void dmfe_program_DM9802(struct dmfe_board_info *);
327 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
328 static void dmfe_set_phyxcer(struct dmfe_board_info *);
330 /* DM910X network baord routine ---------------------------- */
333 * Search DM910X board ,allocate space and register it
336 static int __devinit dmfe_init_one (struct pci_dev *pdev,
337 const struct pci_device_id *ent)
339 struct dmfe_board_info *db; /* board information structure */
340 struct net_device *dev;
341 u32 dev_rev, pci_pmr;
344 DMFE_DBUG(0, "dmfe_init_one()", 0);
346 if (!printed_version++)
349 /* Init network device */
350 dev = alloc_etherdev(sizeof(*db));
353 SET_MODULE_OWNER(dev);
354 SET_NETDEV_DEV(dev, &pdev->dev);
356 if (pci_set_dma_mask(pdev, 0xffffffff)) {
357 printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n");
362 /* Enable Master/IO access, Disable memory access */
363 err = pci_enable_device(pdev);
367 if (!pci_resource_start(pdev, 0)) {
368 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
370 goto err_out_disable;
373 /* Read Chip revision */
374 pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
376 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev, dev_rev)) ) {
377 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
379 goto err_out_disable;
382 #if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
384 /* Set Latency Timer 80h */
385 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
386 Need a PCI quirk.. */
388 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
391 if (pci_request_regions(pdev, DRV_NAME)) {
392 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
394 goto err_out_disable;
397 /* Init system & device */
398 db = netdev_priv(dev);
400 /* Allocate Tx/Rx descriptor memory */
401 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
402 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
404 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
405 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
406 db->buf_pool_start = db->buf_pool_ptr;
407 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
409 db->chip_id = ent->driver_data;
410 db->ioaddr = pci_resource_start(pdev, 0);
411 db->chip_revision = dev_rev;
415 dev->base_addr = db->ioaddr;
416 dev->irq = pdev->irq;
417 pci_set_drvdata(pdev, dev);
418 dev->open = &dmfe_open;
419 dev->hard_start_xmit = &dmfe_start_xmit;
420 dev->stop = &dmfe_stop;
421 dev->get_stats = &dmfe_get_stats;
422 dev->set_multicast_list = &dmfe_set_filter_mode;
423 #ifdef CONFIG_NET_POLL_CONTROLLER
424 dev->poll_controller = &poll_dmfe;
426 dev->ethtool_ops = &netdev_ethtool_ops;
427 spin_lock_init(&db->lock);
429 pci_read_config_dword(pdev, 0x50, &pci_pmr);
431 if ( (pci_pmr == 0x10000) && (dev_rev == 0x02000031) )
432 db->chip_type = 1; /* DM9102A E3 */
436 /* read 64 word srom data */
437 for (i = 0; i < 64; i++)
438 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
440 /* Set Node address */
441 for (i = 0; i < 6; i++)
442 dev->dev_addr[i] = db->srom[20 + i];
444 err = register_netdev (dev);
448 printk(KERN_INFO "%s: Davicom DM%04lx at pci%s,",
450 ent->driver_data >> 16,
452 for (i = 0; i < 6; i++)
453 printk("%c%02x", i ? ':' : ' ', dev->dev_addr[i]);
454 printk(", irq %d.\n", dev->irq);
456 pci_set_master(pdev);
461 pci_release_regions(pdev);
463 pci_disable_device(pdev);
465 pci_set_drvdata(pdev, NULL);
472 static void __devexit dmfe_remove_one (struct pci_dev *pdev)
474 struct net_device *dev = pci_get_drvdata(pdev);
475 struct dmfe_board_info *db = netdev_priv(dev);
477 DMFE_DBUG(0, "dmfe_remove_one()", 0);
480 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
481 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
482 db->desc_pool_dma_ptr);
483 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
484 db->buf_pool_ptr, db->buf_pool_dma_ptr);
485 unregister_netdev(dev);
486 pci_release_regions(pdev);
487 free_netdev(dev); /* free board information */
488 pci_set_drvdata(pdev, NULL);
491 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
496 * Open the interface.
497 * The interface is opened whenever "ifconfig" actives it.
500 static int dmfe_open(struct DEVICE *dev)
503 struct dmfe_board_info *db = netdev_priv(dev);
505 DMFE_DBUG(0, "dmfe_open", 0);
507 ret = request_irq(dev->irq, &dmfe_interrupt, SA_SHIRQ, dev->name, dev);
511 /* system variable init */
512 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
513 db->tx_packet_cnt = 0;
514 db->tx_queue_cnt = 0;
515 db->rx_avail_cnt = 0;
519 db->first_in_callback = 0;
520 db->NIC_capability = 0xf; /* All capability*/
521 db->PHY_reg4 = 0x1e0;
523 /* CR6 operation mode decision */
524 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
525 (db->chip_revision >= 0x02000030) ) {
526 db->cr6_data |= DMFE_TXTH_256;
527 db->cr0_data = CR0_DEFAULT;
528 db->dm910x_chk_mode=4; /* Enter the normal mode */
530 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
532 db->dm910x_chk_mode = 1; /* Enter the check mode */
535 /* Initilize DM910X board */
536 dmfe_init_dm910x(dev);
538 /* Active System Interface */
539 netif_wake_queue(dev);
541 /* set and active a timer process */
542 init_timer(&db->timer);
543 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
544 db->timer.data = (unsigned long)dev;
545 db->timer.function = &dmfe_timer;
546 add_timer(&db->timer);
552 /* Initilize DM910X board
554 * Initilize TX/Rx descriptor chain structure
555 * Send the set-up frame
556 * Enable Tx/Rx machine
559 static void dmfe_init_dm910x(struct DEVICE *dev)
561 struct dmfe_board_info *db = netdev_priv(dev);
562 unsigned long ioaddr = db->ioaddr;
564 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
566 /* Reset DM910x MAC controller */
567 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
569 outl(db->cr0_data, ioaddr + DCR0);
572 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
575 /* Parser SROM and media mode */
577 db->media_mode = dmfe_media_mode;
579 /* RESET Phyxcer Chip by GPR port bit 7 */
580 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
581 if (db->chip_id == PCI_DM9009_ID) {
582 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
583 mdelay(300); /* Delay 300 ms */
585 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
587 /* Process Phyxcer Media Mode */
588 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
589 dmfe_set_phyxcer(db);
591 /* Media Mode Process */
592 if ( !(db->media_mode & DMFE_AUTO) )
593 db->op_mode = db->media_mode; /* Force Mode */
595 /* Initiliaze Transmit/Receive decriptor and CR3/4 */
596 dmfe_descriptor_init(db, ioaddr);
598 /* Init CR6 to program DM910x operation */
599 update_cr6(db->cr6_data, ioaddr);
601 /* Send setup frame */
602 if (db->chip_id == PCI_DM9132_ID)
603 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
605 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
607 /* Init CR7, interrupt active bit */
608 db->cr7_data = CR7_DEFAULT;
609 outl(db->cr7_data, ioaddr + DCR7);
611 /* Init CR15, Tx jabber and Rx watchdog timer */
612 outl(db->cr15_data, ioaddr + DCR15);
614 /* Enable DM910X Tx/Rx function */
615 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
616 update_cr6(db->cr6_data, ioaddr);
621 * Hardware start transmission.
622 * Send a packet to media from the upper layer.
625 static int dmfe_start_xmit(struct sk_buff *skb, struct DEVICE *dev)
627 struct dmfe_board_info *db = netdev_priv(dev);
628 struct tx_desc *txptr;
631 DMFE_DBUG(0, "dmfe_start_xmit", 0);
633 /* Resource flag check */
634 netif_stop_queue(dev);
636 /* Too large packet check */
637 if (skb->len > MAX_PACKET_SIZE) {
638 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
643 spin_lock_irqsave(&db->lock, flags);
645 /* No Tx resource check, it never happen nromally */
646 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
647 spin_unlock_irqrestore(&db->lock, flags);
648 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_queue_cnt);
652 /* Disable NIC interrupt */
653 outl(0, dev->base_addr + DCR7);
655 /* transmit this packet */
656 txptr = db->tx_insert_ptr;
657 memcpy(txptr->tx_buf_ptr, skb->data, skb->len);
658 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
660 /* Point to next transmit free descriptor */
661 db->tx_insert_ptr = txptr->next_tx_desc;
663 /* Transmit Packet Process */
664 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
665 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
666 db->tx_packet_cnt++; /* Ready to send */
667 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
668 dev->trans_start = jiffies; /* saved time stamp */
670 db->tx_queue_cnt++; /* queue TX packet */
671 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
674 /* Tx resource check */
675 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
676 netif_wake_queue(dev);
678 /* Restore CR7 to enable interrupt */
679 spin_unlock_irqrestore(&db->lock, flags);
680 outl(db->cr7_data, dev->base_addr + DCR7);
690 * Stop the interface.
691 * The interface is stopped when it is brought.
694 static int dmfe_stop(struct DEVICE *dev)
696 struct dmfe_board_info *db = netdev_priv(dev);
697 unsigned long ioaddr = dev->base_addr;
699 DMFE_DBUG(0, "dmfe_stop", 0);
702 netif_stop_queue(dev);
705 del_timer_sync(&db->timer);
707 /* Reset & stop DM910X board */
708 outl(DM910X_RESET, ioaddr + DCR0);
710 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
713 free_irq(dev->irq, dev);
715 /* free allocated rx buffer */
716 dmfe_free_rxbuffer(db);
719 /* show statistic counter */
720 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
721 db->tx_fifo_underrun, db->tx_excessive_collision,
722 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
723 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
724 db->reset_fatal, db->reset_TXtimeout);
732 * DM9102 insterrupt handler
733 * receive the packet to upper layer, free the transmitted packet
736 static irqreturn_t dmfe_interrupt(int irq, void *dev_id, struct pt_regs *regs)
738 struct DEVICE *dev = dev_id;
739 struct dmfe_board_info *db = netdev_priv(dev);
740 unsigned long ioaddr = dev->base_addr;
743 DMFE_DBUG(0, "dmfe_interrupt()", 0);
746 DMFE_DBUG(1, "dmfe_interrupt() without DEVICE arg", 0);
750 spin_lock_irqsave(&db->lock, flags);
752 /* Got DM910X status */
753 db->cr5_data = inl(ioaddr + DCR5);
754 outl(db->cr5_data, ioaddr + DCR5);
755 if ( !(db->cr5_data & 0xc1) ) {
756 spin_unlock_irqrestore(&db->lock, flags);
760 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
761 outl(0, ioaddr + DCR7);
763 /* Check system status */
764 if (db->cr5_data & 0x2000) {
765 /* system bus error happen */
766 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
768 db->wait_reset = 1; /* Need to RESET */
769 spin_unlock_irqrestore(&db->lock, flags);
773 /* Received the coming packet */
774 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
775 dmfe_rx_packet(dev, db);
777 /* reallocate rx descriptor buffer */
778 if (db->rx_avail_cnt<RX_DESC_CNT)
779 allocate_rx_buffer(db);
781 /* Free the transmitted descriptor */
782 if ( db->cr5_data & 0x01)
783 dmfe_free_tx_pkt(dev, db);
786 if (db->dm910x_chk_mode & 0x2) {
787 db->dm910x_chk_mode = 0x4;
788 db->cr6_data |= 0x100;
789 update_cr6(db->cr6_data, db->ioaddr);
792 /* Restore CR7 to enable interrupt mask */
793 outl(db->cr7_data, ioaddr + DCR7);
795 spin_unlock_irqrestore(&db->lock, flags);
800 #ifdef CONFIG_NET_POLL_CONTROLLER
802 * Polling 'interrupt' - used by things like netconsole to send skbs
803 * without having to re-enable interrupts. It's not called while
804 * the interrupt routine is executing.
807 static void poll_dmfe (struct net_device *dev)
809 /* disable_irq here is not very nice, but with the lockless
810 interrupt handler we have no other choice. */
811 disable_irq(dev->irq);
812 dmfe_interrupt (dev->irq, dev, NULL);
813 enable_irq(dev->irq);
818 * Free TX resource after TX complete
821 static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
823 struct tx_desc *txptr;
824 unsigned long ioaddr = dev->base_addr;
827 txptr = db->tx_remove_ptr;
828 while(db->tx_packet_cnt) {
829 tdes0 = le32_to_cpu(txptr->tdes0);
830 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
831 if (tdes0 & 0x80000000)
834 /* A packet sent completed */
836 db->stats.tx_packets++;
838 /* Transmit statistic counter */
839 if ( tdes0 != 0x7fffffff ) {
840 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
841 db->stats.collisions += (tdes0 >> 3) & 0xf;
842 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
843 if (tdes0 & TDES0_ERR_MASK) {
844 db->stats.tx_errors++;
846 if (tdes0 & 0x0002) { /* UnderRun */
847 db->tx_fifo_underrun++;
848 if ( !(db->cr6_data & CR6_SFT) ) {
849 db->cr6_data = db->cr6_data | CR6_SFT;
850 update_cr6(db->cr6_data, db->ioaddr);
854 db->tx_excessive_collision++;
856 db->tx_late_collision++;
860 db->tx_loss_carrier++;
862 db->tx_jabber_timeout++;
866 txptr = txptr->next_tx_desc;
869 /* Update TX remove pointer to next */
870 db->tx_remove_ptr = txptr;
872 /* Send the Tx packet in queue */
873 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
874 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
875 db->tx_packet_cnt++; /* Ready to send */
877 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
878 dev->trans_start = jiffies; /* saved time stamp */
881 /* Resource available check */
882 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
883 netif_wake_queue(dev); /* Active upper layer, send again */
888 * Receive the come packet and pass to upper layer
891 static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
893 struct rx_desc *rxptr;
898 rxptr = db->rx_ready_ptr;
900 while(db->rx_avail_cnt) {
901 rdes0 = le32_to_cpu(rxptr->rdes0);
902 if (rdes0 & 0x80000000) /* packet owner check */
906 db->interval_rx_cnt++;
908 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
909 if ( (rdes0 & 0x300) != 0x300) {
910 /* A packet without First/Last flag */
912 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
913 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
915 /* A packet with First/Last flag */
916 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
918 /* error summary bit check */
919 if (rdes0 & 0x8000) {
920 /* This is a error packet */
921 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
922 db->stats.rx_errors++;
924 db->stats.rx_fifo_errors++;
926 db->stats.rx_crc_errors++;
928 db->stats.rx_length_errors++;
931 if ( !(rdes0 & 0x8000) ||
932 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
933 skb = rxptr->rx_skb_ptr;
935 /* Received Packet CRC check need or not */
936 if ( (db->dm910x_chk_mode & 1) &&
937 (cal_CRC(skb->tail, rxlen, 1) !=
938 (*(u32 *) (skb->tail+rxlen) ))) { /* FIXME (?) */
939 /* Found a error received packet */
940 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
941 db->dm910x_chk_mode = 3;
943 /* Good packet, send to upper layer */
944 /* Shorst packet used new SKB */
945 if ( (rxlen < RX_COPY_SIZE) &&
946 ( (skb = dev_alloc_skb(rxlen + 2) )
948 /* size less than COPY_SIZE, allocate a rxlen SKB */
950 skb_reserve(skb, 2); /* 16byte align */
951 memcpy(skb_put(skb, rxlen), rxptr->rx_skb_ptr->tail, rxlen);
952 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
957 skb->protocol = eth_type_trans(skb, dev);
959 dev->last_rx = jiffies;
960 db->stats.rx_packets++;
961 db->stats.rx_bytes += rxlen;
964 /* Reuse SKB buffer when the packet is error */
965 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
966 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
970 rxptr = rxptr->next_rx_desc;
973 db->rx_ready_ptr = rxptr;
978 * Get statistics from driver.
981 static struct net_device_stats * dmfe_get_stats(struct DEVICE *dev)
983 struct dmfe_board_info *db = netdev_priv(dev);
985 DMFE_DBUG(0, "dmfe_get_stats", 0);
991 * Set DM910X multicast address
994 static void dmfe_set_filter_mode(struct DEVICE * dev)
996 struct dmfe_board_info *db = netdev_priv(dev);
999 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1000 spin_lock_irqsave(&db->lock, flags);
1002 if (dev->flags & IFF_PROMISC) {
1003 DMFE_DBUG(0, "Enable PROM Mode", 0);
1004 db->cr6_data |= CR6_PM | CR6_PBF;
1005 update_cr6(db->cr6_data, db->ioaddr);
1006 spin_unlock_irqrestore(&db->lock, flags);
1010 if (dev->flags & IFF_ALLMULTI || dev->mc_count > DMFE_MAX_MULTICAST) {
1011 DMFE_DBUG(0, "Pass all multicast address", dev->mc_count);
1012 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1013 db->cr6_data |= CR6_PAM;
1014 spin_unlock_irqrestore(&db->lock, flags);
1018 DMFE_DBUG(0, "Set multicast address", dev->mc_count);
1019 if (db->chip_id == PCI_DM9132_ID)
1020 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
1022 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
1023 spin_unlock_irqrestore(&db->lock, flags);
1026 static void netdev_get_drvinfo(struct net_device *dev,
1027 struct ethtool_drvinfo *info)
1029 struct dmfe_board_info *np = netdev_priv(dev);
1031 strcpy(info->driver, DRV_NAME);
1032 strcpy(info->version, DRV_VERSION);
1034 strcpy(info->bus_info, pci_name(np->pdev));
1036 sprintf(info->bus_info, "EISA 0x%lx %d",
1037 dev->base_addr, dev->irq);
1040 static struct ethtool_ops netdev_ethtool_ops = {
1041 .get_drvinfo = netdev_get_drvinfo,
1045 * A periodic timer routine
1046 * Dynamic media sense, allocate Rx buffer...
1049 static void dmfe_timer(unsigned long data)
1052 unsigned char tmp_cr12;
1053 struct DEVICE *dev = (struct DEVICE *) data;
1054 struct dmfe_board_info *db = netdev_priv(dev);
1055 unsigned long flags;
1057 DMFE_DBUG(0, "dmfe_timer()", 0);
1058 spin_lock_irqsave(&db->lock, flags);
1060 /* Media mode process when Link OK before enter this route */
1061 if (db->first_in_callback == 0) {
1062 db->first_in_callback = 1;
1063 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1064 db->cr6_data &= ~0x40000;
1065 update_cr6(db->cr6_data, db->ioaddr);
1066 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1067 db->cr6_data |= 0x40000;
1068 update_cr6(db->cr6_data, db->ioaddr);
1069 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1070 add_timer(&db->timer);
1071 spin_unlock_irqrestore(&db->lock, flags);
1077 /* Operating Mode Check */
1078 if ( (db->dm910x_chk_mode & 0x1) &&
1079 (db->stats.rx_packets > MAX_CHECK_PACKET) )
1080 db->dm910x_chk_mode = 0x4;
1082 /* Dynamic reset DM910X : system error or transmit time-out */
1083 tmp_cr8 = inl(db->ioaddr + DCR8);
1084 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1088 db->interval_rx_cnt = 0;
1090 /* TX polling kick monitor */
1091 if ( db->tx_packet_cnt &&
1092 time_after(jiffies, dev->trans_start + DMFE_TX_KICK) ) {
1093 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1096 if ( time_after(jiffies, dev->trans_start + DMFE_TX_TIMEOUT) ) {
1097 db->reset_TXtimeout++;
1099 printk(KERN_WARNING "%s: Tx timeout - resetting\n",
1104 if (db->wait_reset) {
1105 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1107 dmfe_dynamic_reset(dev);
1108 db->first_in_callback = 0;
1109 db->timer.expires = DMFE_TIMER_WUT;
1110 add_timer(&db->timer);
1111 spin_unlock_irqrestore(&db->lock, flags);
1115 /* Link status check, Dynamic media type change */
1116 if (db->chip_id == PCI_DM9132_ID)
1117 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1119 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1121 if ( ((db->chip_id == PCI_DM9102_ID) &&
1122 (db->chip_revision == 0x02000030)) ||
1123 ((db->chip_id == PCI_DM9132_ID) &&
1124 (db->chip_revision == 0x02000010)) ) {
1127 tmp_cr12 = 0x0; /* Link failed */
1129 tmp_cr12 = 0x3; /* Link OK */
1132 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1134 DMFE_DBUG(0, "Link Failed", tmp_cr12);
1135 db->link_failed = 1;
1137 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1138 /* AUTO or force 1M Homerun/Longrun don't need */
1139 if ( !(db->media_mode & 0x38) )
1140 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1142 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1143 if (db->media_mode & DMFE_AUTO) {
1144 /* 10/100M link failed, used 1M Home-Net */
1145 db->cr6_data|=0x00040000; /* bit18=1, MII */
1146 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1147 update_cr6(db->cr6_data, db->ioaddr);
1150 if ((tmp_cr12 & 0x3) && db->link_failed) {
1151 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1152 db->link_failed = 0;
1154 /* Auto Sense Speed */
1155 if ( (db->media_mode & DMFE_AUTO) &&
1156 dmfe_sense_speed(db) )
1157 db->link_failed = 1;
1158 dmfe_process_mode(db);
1159 /* SHOW_MEDIA_TYPE(db->op_mode); */
1162 /* HPNA remote command check */
1163 if (db->HPNA_command & 0xf00) {
1165 if (!db->HPNA_timer)
1166 dmfe_HPNA_remote_cmd_chk(db);
1169 /* Timer active again */
1170 db->timer.expires = DMFE_TIMER_WUT;
1171 add_timer(&db->timer);
1172 spin_unlock_irqrestore(&db->lock, flags);
1177 * Dynamic reset the DM910X board
1179 * Free Tx/Rx allocated memory
1180 * Reset DM910X board
1181 * Re-initilize DM910X board
1184 static void dmfe_dynamic_reset(struct DEVICE *dev)
1186 struct dmfe_board_info *db = netdev_priv(dev);
1188 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1190 /* Sopt MAC controller */
1191 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1192 update_cr6(db->cr6_data, dev->base_addr);
1193 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1194 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1196 /* Disable upper layer interface */
1197 netif_stop_queue(dev);
1199 /* Free Rx Allocate buffer */
1200 dmfe_free_rxbuffer(db);
1202 /* system variable init */
1203 db->tx_packet_cnt = 0;
1204 db->tx_queue_cnt = 0;
1205 db->rx_avail_cnt = 0;
1206 db->link_failed = 1;
1209 /* Re-initilize DM910X board */
1210 dmfe_init_dm910x(dev);
1212 /* Restart upper layer interface */
1213 netif_wake_queue(dev);
1218 * free all allocated rx buffer
1221 static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1223 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1225 /* free allocated rx buffer */
1226 while (db->rx_avail_cnt) {
1227 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1228 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1235 * Reuse the SK buffer
1238 static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1240 struct rx_desc *rxptr = db->rx_insert_ptr;
1242 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1243 rxptr->rx_skb_ptr = skb;
1244 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->tail, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1246 rxptr->rdes0 = cpu_to_le32(0x80000000);
1248 db->rx_insert_ptr = rxptr->next_rx_desc;
1250 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1255 * Initialize transmit/Receive descriptor
1256 * Using Chain structure, and allocate Tx/Rx buffer
1259 static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1261 struct tx_desc *tmp_tx;
1262 struct rx_desc *tmp_rx;
1263 unsigned char *tmp_buf;
1264 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1265 dma_addr_t tmp_buf_dma;
1268 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1270 /* tx descriptor start pointer */
1271 db->tx_insert_ptr = db->first_tx_desc;
1272 db->tx_remove_ptr = db->first_tx_desc;
1273 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1275 /* rx descriptor start pointer */
1276 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1277 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1278 db->rx_insert_ptr = db->first_rx_desc;
1279 db->rx_ready_ptr = db->first_rx_desc;
1280 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1282 /* Init Transmit chain */
1283 tmp_buf = db->buf_pool_start;
1284 tmp_buf_dma = db->buf_pool_dma_start;
1285 tmp_tx_dma = db->first_tx_desc_dma;
1286 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1287 tmp_tx->tx_buf_ptr = tmp_buf;
1288 tmp_tx->tdes0 = cpu_to_le32(0);
1289 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1290 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1291 tmp_tx_dma += sizeof(struct tx_desc);
1292 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1293 tmp_tx->next_tx_desc = tmp_tx + 1;
1294 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1295 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1297 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1298 tmp_tx->next_tx_desc = db->first_tx_desc;
1300 /* Init Receive descriptor chain */
1301 tmp_rx_dma=db->first_rx_desc_dma;
1302 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1303 tmp_rx->rdes0 = cpu_to_le32(0);
1304 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1305 tmp_rx_dma += sizeof(struct rx_desc);
1306 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1307 tmp_rx->next_rx_desc = tmp_rx + 1;
1309 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1310 tmp_rx->next_rx_desc = db->first_rx_desc;
1312 /* pre-allocate Rx buffer */
1313 allocate_rx_buffer(db);
1319 * Firstly stop DM910X , then written value and start
1322 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1326 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1327 outl(cr6_tmp, ioaddr + DCR6);
1329 outl(cr6_data, ioaddr + DCR6);
1335 * Send a setup frame for DM9132
1336 * This setup frame initilize DM910X address filter mode
1339 static void dm9132_id_table(struct DEVICE *dev, int mc_cnt)
1341 struct dev_mc_list *mcptr;
1343 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1345 u16 i, hash_table[4];
1347 DMFE_DBUG(0, "dm9132_id_table()", 0);
1350 addrptr = (u16 *) dev->dev_addr;
1351 outw(addrptr[0], ioaddr);
1353 outw(addrptr[1], ioaddr);
1355 outw(addrptr[2], ioaddr);
1358 /* Clear Hash Table */
1359 for (i = 0; i < 4; i++)
1360 hash_table[i] = 0x0;
1362 /* broadcast address */
1363 hash_table[3] = 0x8000;
1365 /* the multicast address in Hash Table : 64 bits */
1366 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1367 hash_val = cal_CRC( (char *) mcptr->dmi_addr, 6, 0) & 0x3f;
1368 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1371 /* Write the hash table to MAC MD table */
1372 for (i = 0; i < 4; i++, ioaddr += 4)
1373 outw(hash_table[i], ioaddr);
1378 * Send a setup frame for DM9102/DM9102A
1379 * This setup frame initilize DM910X address filter mode
1382 static void send_filter_frame(struct DEVICE *dev, int mc_cnt)
1384 struct dmfe_board_info *db = netdev_priv(dev);
1385 struct dev_mc_list *mcptr;
1386 struct tx_desc *txptr;
1391 DMFE_DBUG(0, "send_filter_frame()", 0);
1393 txptr = db->tx_insert_ptr;
1394 suptr = (u32 *) txptr->tx_buf_ptr;
1397 addrptr = (u16 *) dev->dev_addr;
1398 *suptr++ = addrptr[0];
1399 *suptr++ = addrptr[1];
1400 *suptr++ = addrptr[2];
1402 /* broadcast address */
1407 /* fit the multicast address */
1408 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1409 addrptr = (u16 *) mcptr->dmi_addr;
1410 *suptr++ = addrptr[0];
1411 *suptr++ = addrptr[1];
1412 *suptr++ = addrptr[2];
1421 /* prepare the setup frame */
1422 db->tx_insert_ptr = txptr->next_tx_desc;
1423 txptr->tdes1 = cpu_to_le32(0x890000c0);
1425 /* Resource Check and Send the setup packet */
1426 if (!db->tx_packet_cnt) {
1427 /* Resource Empty */
1428 db->tx_packet_cnt++;
1429 txptr->tdes0 = cpu_to_le32(0x80000000);
1430 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1431 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1432 update_cr6(db->cr6_data, dev->base_addr);
1433 dev->trans_start = jiffies;
1435 db->tx_queue_cnt++; /* Put in TX queue */
1440 * Allocate rx buffer,
1441 * As possible as allocate maxiumn Rx buffer
1444 static void allocate_rx_buffer(struct dmfe_board_info *db)
1446 struct rx_desc *rxptr;
1447 struct sk_buff *skb;
1449 rxptr = db->rx_insert_ptr;
1451 while(db->rx_avail_cnt < RX_DESC_CNT) {
1452 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1454 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1455 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->tail, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1457 rxptr->rdes0 = cpu_to_le32(0x80000000);
1458 rxptr = rxptr->next_rx_desc;
1462 db->rx_insert_ptr = rxptr;
1467 * Read one word data from the serial ROM
1470 static u16 read_srom_word(long ioaddr, int offset)
1474 long cr9_ioaddr = ioaddr + DCR9;
1476 outl(CR9_SROM_READ, cr9_ioaddr);
1477 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1479 /* Send the Read Command 110b */
1480 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1481 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1482 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1484 /* Send the offset */
1485 for (i = 5; i >= 0; i--) {
1486 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1487 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1490 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1492 for (i = 16; i > 0; i--) {
1493 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1495 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1496 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1500 outl(CR9_SROM_READ, cr9_ioaddr);
1506 * Auto sense the media mode
1509 static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1514 /* CR6 bit18=0, select 10/100M */
1515 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1517 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1518 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1520 if ( (phy_mode & 0x24) == 0x24 ) {
1521 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
1522 phy_mode = phy_read(db->ioaddr, db->phy_addr, 7, db->chip_id) & 0xf000;
1523 else /* DM9102/DM9102A */
1524 phy_mode = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0xf000;
1525 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1527 case 0x1000: db->op_mode = DMFE_10MHF; break;
1528 case 0x2000: db->op_mode = DMFE_10MFD; break;
1529 case 0x4000: db->op_mode = DMFE_100MHF; break;
1530 case 0x8000: db->op_mode = DMFE_100MFD; break;
1531 default: db->op_mode = DMFE_10MHF;
1536 db->op_mode = DMFE_10MHF;
1537 DMFE_DBUG(0, "Link Failed :", phy_mode);
1546 * Set 10/100 phyxcer capability
1547 * AUTO mode : phyxcer register4 is NIC capability
1548 * Force mode: phyxcer register4 is the force media
1551 static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1555 /* Select 10/100M phyxcer */
1556 db->cr6_data &= ~0x40000;
1557 update_cr6(db->cr6_data, db->ioaddr);
1559 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1560 if (db->chip_id == PCI_DM9009_ID) {
1561 phy_reg = phy_read(db->ioaddr, db->phy_addr, 18, db->chip_id) & ~0x1000;
1562 phy_write(db->ioaddr, db->phy_addr, 18, phy_reg, db->chip_id);
1565 /* Phyxcer capability setting */
1566 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1568 if (db->media_mode & DMFE_AUTO) {
1570 phy_reg |= db->PHY_reg4;
1573 switch(db->media_mode) {
1574 case DMFE_10MHF: phy_reg |= 0x20; break;
1575 case DMFE_10MFD: phy_reg |= 0x40; break;
1576 case DMFE_100MHF: phy_reg |= 0x80; break;
1577 case DMFE_100MFD: phy_reg |= 0x100; break;
1579 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1582 /* Write new capability to Phyxcer Reg4 */
1583 if ( !(phy_reg & 0x01e0)) {
1584 phy_reg|=db->PHY_reg4;
1585 db->media_mode|=DMFE_AUTO;
1587 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1589 /* Restart Auto-Negotiation */
1590 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1591 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1592 if ( !db->chip_type )
1593 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1599 * AUTO mode : PHY controller in Auto-negotiation Mode
1600 * Force mode: PHY controller in force mode with HUB
1601 * N-way force capability with SWITCH
1604 static void dmfe_process_mode(struct dmfe_board_info *db)
1608 /* Full Duplex Mode Check */
1609 if (db->op_mode & 0x4)
1610 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1612 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1614 /* Transciver Selection */
1615 if (db->op_mode & 0x10) /* 1M HomePNA */
1616 db->cr6_data |= 0x40000;/* External MII select */
1618 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1620 update_cr6(db->cr6_data, db->ioaddr);
1622 /* 10/100M phyxcer force mode need */
1623 if ( !(db->media_mode & 0x18)) {
1625 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1626 if ( !(phy_reg & 0x1) ) {
1627 /* parter without N-Way capability */
1629 switch(db->op_mode) {
1630 case DMFE_10MHF: phy_reg = 0x0; break;
1631 case DMFE_10MFD: phy_reg = 0x100; break;
1632 case DMFE_100MHF: phy_reg = 0x2000; break;
1633 case DMFE_100MFD: phy_reg = 0x2100; break;
1635 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1636 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1638 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1645 * Write a word to Phy register
1648 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1651 unsigned long ioaddr;
1653 if (chip_id == PCI_DM9132_ID) {
1654 ioaddr = iobase + 0x80 + offset * 4;
1655 outw(phy_data, ioaddr);
1657 /* DM9102/DM9102A Chip */
1658 ioaddr = iobase + DCR9;
1660 /* Send 33 synchronization clock to Phy controller */
1661 for (i = 0; i < 35; i++)
1662 phy_write_1bit(ioaddr, PHY_DATA_1);
1664 /* Send start command(01) to Phy */
1665 phy_write_1bit(ioaddr, PHY_DATA_0);
1666 phy_write_1bit(ioaddr, PHY_DATA_1);
1668 /* Send write command(01) to Phy */
1669 phy_write_1bit(ioaddr, PHY_DATA_0);
1670 phy_write_1bit(ioaddr, PHY_DATA_1);
1672 /* Send Phy address */
1673 for (i = 0x10; i > 0; i = i >> 1)
1674 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1676 /* Send register address */
1677 for (i = 0x10; i > 0; i = i >> 1)
1678 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1680 /* written trasnition */
1681 phy_write_1bit(ioaddr, PHY_DATA_1);
1682 phy_write_1bit(ioaddr, PHY_DATA_0);
1684 /* Write a word data to PHY controller */
1685 for ( i = 0x8000; i > 0; i >>= 1)
1686 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1692 * Read a word data from phy register
1695 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1699 unsigned long ioaddr;
1701 if (chip_id == PCI_DM9132_ID) {
1703 ioaddr = iobase + 0x80 + offset * 4;
1704 phy_data = inw(ioaddr);
1706 /* DM9102/DM9102A Chip */
1707 ioaddr = iobase + DCR9;
1709 /* Send 33 synchronization clock to Phy controller */
1710 for (i = 0; i < 35; i++)
1711 phy_write_1bit(ioaddr, PHY_DATA_1);
1713 /* Send start command(01) to Phy */
1714 phy_write_1bit(ioaddr, PHY_DATA_0);
1715 phy_write_1bit(ioaddr, PHY_DATA_1);
1717 /* Send read command(10) to Phy */
1718 phy_write_1bit(ioaddr, PHY_DATA_1);
1719 phy_write_1bit(ioaddr, PHY_DATA_0);
1721 /* Send Phy address */
1722 for (i = 0x10; i > 0; i = i >> 1)
1723 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1725 /* Send register address */
1726 for (i = 0x10; i > 0; i = i >> 1)
1727 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1729 /* Skip transition state */
1730 phy_read_1bit(ioaddr);
1732 /* read 16bit data */
1733 for (phy_data = 0, i = 0; i < 16; i++) {
1735 phy_data |= phy_read_1bit(ioaddr);
1744 * Write one bit data to Phy Controller
1747 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1749 outl(phy_data, ioaddr); /* MII Clock Low */
1751 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1753 outl(phy_data, ioaddr); /* MII Clock Low */
1759 * Read one bit phy data from PHY controller
1762 static u16 phy_read_1bit(unsigned long ioaddr)
1766 outl(0x50000, ioaddr);
1768 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1769 outl(0x40000, ioaddr);
1777 * Calculate the CRC valude of the Rx packet
1778 * flag = 1 : return the reverse CRC (for the received packet CRC)
1779 * 0 : return the normal CRC (for Hash Table index)
1782 static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
1784 u32 crc = crc32(~0, Data, Len);
1785 if (flag) crc = ~crc;
1791 * Parser SROM and media mode
1794 static void dmfe_parse_srom(struct dmfe_board_info * db)
1796 char * srom = db->srom;
1797 int dmfe_mode, tmp_reg;
1799 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1802 db->cr15_data = CR15_DEFAULT;
1804 /* Check SROM Version */
1805 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1807 /* Get NIC support media mode */
1808 db->NIC_capability = le16_to_cpup(srom + 34);
1810 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1811 switch( db->NIC_capability & tmp_reg ) {
1812 case 0x1: db->PHY_reg4 |= 0x0020; break;
1813 case 0x2: db->PHY_reg4 |= 0x0040; break;
1814 case 0x4: db->PHY_reg4 |= 0x0080; break;
1815 case 0x8: db->PHY_reg4 |= 0x0100; break;
1819 /* Media Mode Force or not check */
1820 dmfe_mode = le32_to_cpup(srom + 34) & le32_to_cpup(srom + 36);
1822 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1823 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1824 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1826 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1829 /* Special Function setting */
1831 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1832 db->cr15_data |= 0x40;
1835 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1836 db->cr15_data |= 0x400;
1838 /* TX pause packet */
1839 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1840 db->cr15_data |= 0x9800;
1843 /* Parse HPNA parameter */
1844 db->HPNA_command = 1;
1846 /* Accept remote command or not */
1847 if (HPNA_rx_cmd == 0)
1848 db->HPNA_command |= 0x8000;
1850 /* Issue remote command & operation mode */
1851 if (HPNA_tx_cmd == 1)
1852 switch(HPNA_mode) { /* Issue Remote Command */
1853 case 0: db->HPNA_command |= 0x0904; break;
1854 case 1: db->HPNA_command |= 0x0a00; break;
1855 case 2: db->HPNA_command |= 0x0506; break;
1856 case 3: db->HPNA_command |= 0x0602; break;
1859 switch(HPNA_mode) { /* Don't Issue */
1860 case 0: db->HPNA_command |= 0x0004; break;
1861 case 1: db->HPNA_command |= 0x0000; break;
1862 case 2: db->HPNA_command |= 0x0006; break;
1863 case 3: db->HPNA_command |= 0x0002; break;
1866 /* Check DM9801 or DM9802 present or not */
1867 db->HPNA_present = 0;
1868 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1869 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1870 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1871 /* DM9801 or DM9802 present */
1873 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1874 /* DM9801 HomeRun */
1875 db->HPNA_present = 1;
1876 dmfe_program_DM9801(db, tmp_reg);
1878 /* DM9802 LongRun */
1879 db->HPNA_present = 2;
1880 dmfe_program_DM9802(db);
1888 * Init HomeRun DM9801
1891 static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
1895 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
1897 case 0xb900: /* DM9801 E3 */
1898 db->HPNA_command |= 0x1000;
1899 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
1900 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
1901 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1903 case 0xb901: /* DM9801 E4 */
1904 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1905 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
1906 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1907 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
1909 case 0xb902: /* DM9801 E5 */
1910 case 0xb903: /* DM9801 E6 */
1912 db->HPNA_command |= 0x1000;
1913 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1914 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
1915 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1916 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
1919 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1920 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
1921 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
1926 * Init HomeRun DM9802
1929 static void dmfe_program_DM9802(struct dmfe_board_info * db)
1933 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
1934 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1935 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1936 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
1937 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
1942 * Check remote HPNA power and speed status. If not correct,
1943 * issue command again.
1946 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
1950 /* Got remote device status */
1951 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
1953 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
1954 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
1955 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
1956 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
1959 /* Check remote device status match our setting ot not */
1960 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
1961 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1964 db->HPNA_timer=600; /* Match, every 10 minutes, check */
1969 static struct pci_device_id dmfe_pci_tbl[] = {
1970 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
1971 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
1972 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
1973 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
1976 MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
1979 static struct pci_driver dmfe_driver = {
1981 .id_table = dmfe_pci_tbl,
1982 .probe = dmfe_init_one,
1983 .remove = __devexit_p(dmfe_remove_one),
1986 MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
1987 MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
1988 MODULE_LICENSE("GPL");
1990 MODULE_PARM(debug, "i");
1991 MODULE_PARM(mode, "i");
1992 MODULE_PARM(cr6set, "i");
1993 MODULE_PARM(chkmode, "i");
1994 MODULE_PARM(HPNA_mode, "i");
1995 MODULE_PARM(HPNA_rx_cmd, "i");
1996 MODULE_PARM(HPNA_tx_cmd, "i");
1997 MODULE_PARM(HPNA_NoiseFloor, "i");
1998 MODULE_PARM(SF_mode, "i");
1999 MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
2000 MODULE_PARM_DESC(mode, "Davicom DM9xxx: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2001 MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function (bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
2004 * when user used insmod to add module, system invoked init_module()
2005 * to initilize and register.
2008 static int __init dmfe_init_module(void)
2013 printed_version = 1;
2015 DMFE_DBUG(0, "init_module() ", debug);
2018 dmfe_debug = debug; /* set debug flag */
2020 dmfe_cr6_user_set = cr6set;
2028 dmfe_media_mode = mode;
2030 default:dmfe_media_mode = DMFE_AUTO;
2035 HPNA_mode = 0; /* Default: LP/HS */
2036 if (HPNA_rx_cmd > 1)
2037 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2038 if (HPNA_tx_cmd > 1)
2039 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2040 if (HPNA_NoiseFloor > 15)
2041 HPNA_NoiseFloor = 0;
2043 rc = pci_module_init(&dmfe_driver);
2053 * when user used rmmod to delete module, system invoked clean_module()
2054 * to un-register all registered services.
2057 static void __exit dmfe_cleanup_module(void)
2059 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2060 pci_unregister_driver(&dmfe_driver);
2063 module_init(dmfe_init_module);
2064 module_exit(dmfe_cleanup_module);