1 /* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
3 Written 2002-2004 by David Dillow <dave@thedillows.org>
4 Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
5 Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
14 This software is available on a public web site. It may enable
15 cryptographic capabilities of the 3Com hardware, and may be
16 exported from the United States under License Exception "TSU"
17 pursuant to 15 C.F.R. Section 740.13(e).
19 This work was funded by the National Library of Medicine under
20 the Department of Energy project number 0274DD06D1 and NLM project
23 This driver is designed for the 3Com 3CR990 Family of cards with the
24 3XP Processor. It has been tested on x86 and sparc64.
27 *) The current firmware always strips the VLAN tag off, even if
28 we tell it not to. You should filter VLANs at the switch
29 as a workaround (good practice in any event) until we can
31 *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
32 issue. Hopefully 3Com will fix it.
33 *) Waiting for a command response takes 8ms due to non-preemptable
34 polling. Only significant for getting stats and creating
35 SAs, but an ugly wart never the less.
38 *) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
39 *) Add more support for ethtool (especially for NIC stats)
40 *) Allow disabling of RX checksum offloading
41 *) Fix MAC changing to work while the interface is up
42 (Need to put commands on the TX ring, which changes
44 *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
45 http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
48 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
49 * Setting to > 1518 effectively disables this feature.
51 static int rx_copybreak = 200;
53 /* end user-configurable values */
55 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
57 static const int multicast_filter_limit = 32;
59 /* Operational parameters that are set at compile time. */
61 /* Keep the ring sizes a power of two for compile efficiency.
62 * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
63 * Making the Tx ring too large decreases the effectiveness of channel
64 * bonding and packet priority.
65 * There are no ill effects from too-large receive rings.
67 * We don't currently use the Hi Tx ring so, don't make it very big.
69 * Beware that if we start using the Hi Tx ring, we will need to change
70 * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
72 #define TXHI_ENTRIES 2
73 #define TXLO_ENTRIES 128
75 #define COMMAND_ENTRIES 16
76 #define RESPONSE_ENTRIES 32
78 #define COMMAND_RING_SIZE (COMMAND_ENTRIES * sizeof(struct cmd_desc))
79 #define RESPONSE_RING_SIZE (RESPONSE_ENTRIES * sizeof(struct resp_desc))
81 /* The 3XP will preload and remove 64 entries from the free buffer
82 * list, and we need one entry to keep the ring from wrapping, so
83 * to keep this a power of two, we use 128 entries.
85 #define RXFREE_ENTRIES 128
86 #define RXENT_ENTRIES (RXFREE_ENTRIES - 1)
88 /* Operational parameters that usually are not changed. */
90 /* Time in jiffies before concluding the transmitter is hung. */
91 #define TX_TIMEOUT (2*HZ)
93 #define PKT_BUF_SZ 1536
95 #define DRV_MODULE_NAME "typhoon"
96 #define DRV_MODULE_VERSION "1.5.4"
97 #define DRV_MODULE_RELDATE "04/09/09"
98 #define PFX DRV_MODULE_NAME ": "
99 #define ERR_PFX KERN_ERR PFX
101 #include <linux/module.h>
102 #include <linux/kernel.h>
103 #include <linux/string.h>
104 #include <linux/timer.h>
105 #include <linux/errno.h>
106 #include <linux/ioport.h>
107 #include <linux/slab.h>
108 #include <linux/interrupt.h>
109 #include <linux/pci.h>
110 #include <linux/netdevice.h>
111 #include <linux/etherdevice.h>
112 #include <linux/skbuff.h>
113 #include <linux/init.h>
114 #include <linux/delay.h>
115 #include <linux/ethtool.h>
116 #include <linux/if_vlan.h>
117 #include <linux/crc32.h>
118 #include <linux/bitops.h>
119 #include <asm/processor.h>
121 #include <asm/uaccess.h>
122 #include <linux/in6.h>
123 #include <asm/checksum.h>
124 #include <linux/version.h>
125 #include <linux/dma-mapping.h>
128 #include "typhoon-firmware.h"
130 static char version[] __devinitdata =
131 "typhoon.c: version " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
133 MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
134 MODULE_LICENSE("GPL");
135 MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
136 MODULE_PARM(rx_copybreak, "i");
138 #if defined(NETIF_F_TSO) && MAX_SKB_FRAGS > 32
139 #warning Typhoon only supports 32 entries in its SG list for TSO, disabling TSO
143 #if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
144 #error TX ring too small!
147 struct typhoon_card_info {
152 #define TYPHOON_CRYPTO_NONE 0x00
153 #define TYPHOON_CRYPTO_DES 0x01
154 #define TYPHOON_CRYPTO_3DES 0x02
155 #define TYPHOON_CRYPTO_VARIABLE 0x04
156 #define TYPHOON_FIBER 0x08
157 #define TYPHOON_WAKEUP_NEEDS_RESET 0x10
160 TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
161 TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
162 TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
166 /* directly indexed by enum typhoon_cards, above */
167 static struct typhoon_card_info typhoon_card_info[] __devinitdata = {
168 { "3Com Typhoon (3C990-TX)",
169 TYPHOON_CRYPTO_NONE},
170 { "3Com Typhoon (3CR990-TX-95)",
172 { "3Com Typhoon (3CR990-TX-97)",
173 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
174 { "3Com Typhoon (3C990SVR)",
175 TYPHOON_CRYPTO_NONE},
176 { "3Com Typhoon (3CR990SVR95)",
178 { "3Com Typhoon (3CR990SVR97)",
179 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
180 { "3Com Typhoon2 (3C990B-TX-M)",
181 TYPHOON_CRYPTO_VARIABLE},
182 { "3Com Typhoon2 (3C990BSVR)",
183 TYPHOON_CRYPTO_VARIABLE},
184 { "3Com Typhoon (3CR990-FX-95)",
185 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
186 { "3Com Typhoon (3CR990-FX-97)",
187 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
188 { "3Com Typhoon (3CR990-FX-95 Server)",
189 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
190 { "3Com Typhoon (3CR990-FX-97 Server)",
191 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
192 { "3Com Typhoon2 (3C990B-FX-97)",
193 TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
196 /* Notes on the new subsystem numbering scheme:
197 * bits 0-1 indicate crypto capabilites: (0) variable, (1) DES, or (2) 3DES
198 * bit 4 indicates if this card has secured firmware (we don't support it)
199 * bit 8 indicates if this is a (0) copper or (1) fiber card
200 * bits 12-16 indicate card type: (0) client and (1) server
202 static struct pci_device_id typhoon_pci_tbl[] = {
203 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
205 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
207 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
209 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
210 PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
211 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
212 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
213 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
214 PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
215 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
216 PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
217 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
218 PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
219 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
220 PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
221 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
222 PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
223 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
225 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
227 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
231 MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
233 /* Define the shared memory area
234 * Align everything the 3XP will normally be using.
235 * We'll need to move/align txHi if we start using that ring.
237 #define __3xp_aligned ____cacheline_aligned
238 struct typhoon_shared {
239 struct typhoon_interface iface;
240 struct typhoon_indexes indexes __3xp_aligned;
241 struct tx_desc txLo[TXLO_ENTRIES] __3xp_aligned;
242 struct rx_desc rxLo[RX_ENTRIES] __3xp_aligned;
243 struct rx_desc rxHi[RX_ENTRIES] __3xp_aligned;
244 struct cmd_desc cmd[COMMAND_ENTRIES] __3xp_aligned;
245 struct resp_desc resp[RESPONSE_ENTRIES] __3xp_aligned;
246 struct rx_free rxBuff[RXFREE_ENTRIES] __3xp_aligned;
248 struct tx_desc txHi[TXHI_ENTRIES];
249 } __attribute__ ((packed));
257 /* Tx cache line section */
258 struct transmit_ring txLoRing ____cacheline_aligned;
259 struct pci_dev * tx_pdev;
260 void __iomem *tx_ioaddr;
263 /* Irq/Rx cache line section */
264 void __iomem *ioaddr ____cacheline_aligned;
265 struct typhoon_indexes *indexes;
270 struct basic_ring rxLoRing;
271 struct pci_dev * pdev;
272 struct net_device * dev;
273 spinlock_t state_lock;
274 struct vlan_group * vlgrp;
275 struct basic_ring rxHiRing;
276 struct basic_ring rxBuffRing;
277 struct rxbuff_ent rxbuffers[RXENT_ENTRIES];
279 /* general section */
280 spinlock_t command_lock ____cacheline_aligned;
281 struct basic_ring cmdRing;
282 struct basic_ring respRing;
283 struct net_device_stats stats;
284 struct net_device_stats stats_saved;
286 struct typhoon_shared * shared;
287 dma_addr_t shared_dma;
292 /* unused stuff (future use) */
294 struct transmit_ring txHiRing;
297 enum completion_wait_values {
298 NoWait = 0, WaitNoSleep, WaitSleep,
301 /* These are the values for the typhoon.card_state variable.
302 * These determine where the statistics will come from in get_stats().
303 * The sleep image does not support the statistics we need.
306 Sleeping = 0, Running,
309 /* PCI writes are not guaranteed to be posted in order, but outstanding writes
310 * cannot pass a read, so this forces current writes to post.
312 #define typhoon_post_pci_writes(x) \
313 do { readl(x + TYPHOON_REG_HEARTBEAT); } while(0)
315 /* We'll wait up to six seconds for a reset, and half a second normally.
317 #define TYPHOON_UDELAY 50
318 #define TYPHOON_RESET_TIMEOUT_SLEEP (6 * HZ)
319 #define TYPHOON_RESET_TIMEOUT_NOSLEEP ((6 * 1000000) / TYPHOON_UDELAY)
320 #define TYPHOON_WAIT_TIMEOUT ((1000000 / 2) / TYPHOON_UDELAY)
322 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 28)
323 #define typhoon_synchronize_irq(x) synchronize_irq()
325 #define typhoon_synchronize_irq(x) synchronize_irq(x)
328 #if defined(NETIF_F_TSO)
329 #define skb_tso_size(x) (skb_shinfo(x)->tso_size)
330 #define TSO_NUM_DESCRIPTORS 2
331 #define TSO_OFFLOAD_ON TYPHOON_OFFLOAD_TCP_SEGMENT
333 #define NETIF_F_TSO 0
334 #define skb_tso_size(x) 0
335 #define TSO_NUM_DESCRIPTORS 0
336 #define TSO_OFFLOAD_ON 0
340 typhoon_inc_index(u32 *index, const int count, const int num_entries)
342 /* Increment a ring index -- we can use this for all rings execept
343 * the Rx rings, as they use different size descriptors
344 * otherwise, everything is the same size as a cmd_desc
346 *index += count * sizeof(struct cmd_desc);
347 *index %= num_entries * sizeof(struct cmd_desc);
351 typhoon_inc_cmd_index(u32 *index, const int count)
353 typhoon_inc_index(index, count, COMMAND_ENTRIES);
357 typhoon_inc_resp_index(u32 *index, const int count)
359 typhoon_inc_index(index, count, RESPONSE_ENTRIES);
363 typhoon_inc_rxfree_index(u32 *index, const int count)
365 typhoon_inc_index(index, count, RXFREE_ENTRIES);
369 typhoon_inc_tx_index(u32 *index, const int count)
371 /* if we start using the Hi Tx ring, this needs updateing */
372 typhoon_inc_index(index, count, TXLO_ENTRIES);
376 typhoon_inc_rx_index(u32 *index, const int count)
378 /* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
379 *index += count * sizeof(struct rx_desc);
380 *index %= RX_ENTRIES * sizeof(struct rx_desc);
384 typhoon_reset(void __iomem *ioaddr, int wait_type)
389 if(wait_type == WaitNoSleep)
390 timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
392 timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
394 writel(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
395 writel(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
397 writel(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
398 typhoon_post_pci_writes(ioaddr);
400 writel(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
402 if(wait_type != NoWait) {
403 for(i = 0; i < timeout; i++) {
404 if(readl(ioaddr + TYPHOON_REG_STATUS) ==
405 TYPHOON_STATUS_WAITING_FOR_HOST)
408 if(wait_type == WaitSleep) {
409 set_current_state(TASK_UNINTERRUPTIBLE);
412 udelay(TYPHOON_UDELAY);
419 writel(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
420 writel(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
422 /* The 3XP seems to need a little extra time to complete the load
423 * of the sleep image before we can reliably boot it. Failure to
424 * do this occasionally results in a hung adapter after boot in
425 * typhoon_init_one() while trying to read the MAC address or
426 * putting the card to sleep. 3Com's driver waits 5ms, but
427 * that seems to be overkill. However, if we can sleep, we might
428 * as well give it that much time. Otherwise, we'll give it 500us,
429 * which should be enough (I've see it work well at 100us, but still
430 * saw occasional problems.)
432 if(wait_type == WaitSleep)
440 typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
444 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
445 if(readl(ioaddr + TYPHOON_REG_STATUS) == wait_value)
447 udelay(TYPHOON_UDELAY);
457 typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
459 if(resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
460 netif_carrier_off(dev);
462 netif_carrier_on(dev);
466 typhoon_hello(struct typhoon *tp)
468 struct basic_ring *ring = &tp->cmdRing;
469 struct cmd_desc *cmd;
471 /* We only get a hello request if we've not sent anything to the
472 * card in a long while. If the lock is held, then we're in the
473 * process of issuing a command, so we don't need to respond.
475 if(spin_trylock(&tp->command_lock)) {
476 cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
477 typhoon_inc_cmd_index(&ring->lastWrite, 1);
479 INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
481 writel(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
482 spin_unlock(&tp->command_lock);
487 typhoon_process_response(struct typhoon *tp, int resp_size,
488 struct resp_desc *resp_save)
490 struct typhoon_indexes *indexes = tp->indexes;
491 struct resp_desc *resp;
492 u8 *base = tp->respRing.ringBase;
493 int count, len, wrap_len;
497 cleared = le32_to_cpu(indexes->respCleared);
498 ready = le32_to_cpu(indexes->respReady);
499 while(cleared != ready) {
500 resp = (struct resp_desc *)(base + cleared);
501 count = resp->numDesc + 1;
502 if(resp_save && resp->seqNo) {
503 if(count > resp_size) {
504 resp_save->flags = TYPHOON_RESP_ERROR;
509 len = count * sizeof(*resp);
510 if(unlikely(cleared + len > RESPONSE_RING_SIZE)) {
511 wrap_len = cleared + len - RESPONSE_RING_SIZE;
512 len = RESPONSE_RING_SIZE - cleared;
515 memcpy(resp_save, resp, len);
516 if(unlikely(wrap_len)) {
517 resp_save += len / sizeof(*resp);
518 memcpy(resp_save, base, wrap_len);
522 } else if(resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
523 typhoon_media_status(tp->dev, resp);
524 } else if(resp->cmd == TYPHOON_CMD_HELLO_RESP) {
527 printk(KERN_ERR "%s: dumping unexpected response "
528 "0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
529 tp->name, le16_to_cpu(resp->cmd),
530 resp->numDesc, resp->flags,
531 le16_to_cpu(resp->parm1),
532 le32_to_cpu(resp->parm2),
533 le32_to_cpu(resp->parm3));
537 typhoon_inc_resp_index(&cleared, count);
540 indexes->respCleared = cpu_to_le32(cleared);
542 return (resp_save == NULL);
546 typhoon_num_free(int lastWrite, int lastRead, int ringSize)
548 /* this works for all descriptors but rx_desc, as they are a
549 * different size than the cmd_desc -- everyone else is the same
551 lastWrite /= sizeof(struct cmd_desc);
552 lastRead /= sizeof(struct cmd_desc);
553 return (ringSize + lastRead - lastWrite - 1) % ringSize;
557 typhoon_num_free_cmd(struct typhoon *tp)
559 int lastWrite = tp->cmdRing.lastWrite;
560 int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
562 return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
566 typhoon_num_free_resp(struct typhoon *tp)
568 int respReady = le32_to_cpu(tp->indexes->respReady);
569 int respCleared = le32_to_cpu(tp->indexes->respCleared);
571 return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
575 typhoon_num_free_tx(struct transmit_ring *ring)
577 /* if we start using the Hi Tx ring, this needs updating */
578 return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
582 typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
583 int num_resp, struct resp_desc *resp)
585 struct typhoon_indexes *indexes = tp->indexes;
586 struct basic_ring *ring = &tp->cmdRing;
587 struct resp_desc local_resp;
590 int freeCmd, freeResp;
593 spin_lock(&tp->command_lock);
595 freeCmd = typhoon_num_free_cmd(tp);
596 freeResp = typhoon_num_free_resp(tp);
598 if(freeCmd < num_cmd || freeResp < num_resp) {
599 printk("%s: no descs for cmd, had (needed) %d (%d) cmd, "
600 "%d (%d) resp\n", tp->name, freeCmd, num_cmd,
606 if(cmd->flags & TYPHOON_CMD_RESPOND) {
607 /* If we're expecting a response, but the caller hasn't given
608 * us a place to put it, we'll provide one.
610 tp->awaiting_resp = 1;
618 len = num_cmd * sizeof(*cmd);
619 if(unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
620 wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
621 len = COMMAND_RING_SIZE - ring->lastWrite;
624 memcpy(ring->ringBase + ring->lastWrite, cmd, len);
625 if(unlikely(wrap_len)) {
626 struct cmd_desc *wrap_ptr = cmd;
627 wrap_ptr += len / sizeof(*cmd);
628 memcpy(ring->ringBase, wrap_ptr, wrap_len);
631 typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
633 /* "I feel a presence... another warrior is on the the mesa."
636 writel(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
637 typhoon_post_pci_writes(tp->ioaddr);
639 if((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
642 /* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
643 * preempt or do anything other than take interrupts. So, don't
644 * wait for a response unless you have to.
646 * I've thought about trying to sleep here, but we're called
647 * from many contexts that don't allow that. Also, given the way
648 * 3Com has implemented irq coalescing, we would likely timeout --
649 * this has been observed in real life!
651 * The big killer is we have to wait to get stats from the card,
652 * though we could go to a periodic refresh of those if we don't
653 * mind them getting somewhat stale. The rest of the waiting
654 * commands occur during open/close/suspend/resume, so they aren't
655 * time critical. Creating SAs in the future will also have to
659 for(i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
660 if(indexes->respCleared != indexes->respReady)
661 got_resp = typhoon_process_response(tp, num_resp,
663 udelay(TYPHOON_UDELAY);
671 /* Collect the error response even if we don't care about the
672 * rest of the response
674 if(resp->flags & TYPHOON_RESP_ERROR)
678 if(tp->awaiting_resp) {
679 tp->awaiting_resp = 0;
682 /* Ugh. If a response was added to the ring between
683 * the call to typhoon_process_response() and the clearing
684 * of tp->awaiting_resp, we could have missed the interrupt
685 * and it could hang in the ring an indeterminate amount of
686 * time. So, check for it, and interrupt ourselves if this
689 if(indexes->respCleared != indexes->respReady)
690 writel(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
693 spin_unlock(&tp->command_lock);
698 typhoon_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
700 struct typhoon *tp = netdev_priv(dev);
701 struct cmd_desc xp_cmd;
704 spin_lock_bh(&tp->state_lock);
705 if(!tp->vlgrp != !grp) {
706 /* We've either been turned on for the first time, or we've
707 * been turned off. Update the 3XP.
710 tp->offload |= TYPHOON_OFFLOAD_VLAN;
712 tp->offload &= ~TYPHOON_OFFLOAD_VLAN;
714 /* If the interface is up, the runtime is running -- and we
715 * must be up for the vlan core to call us.
717 * Do the command outside of the spin lock, as it is slow.
719 INIT_COMMAND_WITH_RESPONSE(&xp_cmd,
720 TYPHOON_CMD_SET_OFFLOAD_TASKS);
721 xp_cmd.parm2 = tp->offload;
722 xp_cmd.parm3 = tp->offload;
723 spin_unlock_bh(&tp->state_lock);
724 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
726 printk("%s: vlan offload error %d\n", tp->name, -err);
727 spin_lock_bh(&tp->state_lock);
730 /* now make the change visible */
732 spin_unlock_bh(&tp->state_lock);
736 typhoon_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
738 struct typhoon *tp = netdev_priv(dev);
739 spin_lock_bh(&tp->state_lock);
741 tp->vlgrp->vlan_devices[vid] = NULL;
742 spin_unlock_bh(&tp->state_lock);
746 typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
749 struct tcpopt_desc *tcpd;
750 u32 tcpd_offset = ring_dma;
752 tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
753 tcpd_offset += txRing->lastWrite;
754 tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
755 typhoon_inc_tx_index(&txRing->lastWrite, 1);
757 tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
759 tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
760 tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
761 tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
762 tcpd->bytesTx = cpu_to_le32(skb->len);
767 typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
769 struct typhoon *tp = netdev_priv(dev);
770 struct transmit_ring *txRing;
771 struct tx_desc *txd, *first_txd;
775 /* we have two rings to choose from, but we only use txLo for now
776 * If we start using the Hi ring as well, we'll need to update
777 * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
778 * and TXHI_ENTIRES to match, as well as update the TSO code below
779 * to get the right DMA address
781 txRing = &tp->txLoRing;
783 /* We need one descriptor for each fragment of the sk_buff, plus the
784 * one for the ->data area of it.
786 * The docs say a maximum of 16 fragment descriptors per TCP option
787 * descriptor, then make a new packet descriptor and option descriptor
788 * for the next 16 fragments. The engineers say just an option
789 * descriptor is needed. I've tested up to 26 fragments with a single
790 * packet descriptor/option descriptor combo, so I use that for now.
792 * If problems develop with TSO, check this first.
794 numDesc = skb_shinfo(skb)->nr_frags + 1;
795 if(skb_tso_size(skb))
798 /* When checking for free space in the ring, we need to also
799 * account for the initial Tx descriptor, and we always must leave
800 * at least one descriptor unused in the ring so that it doesn't
801 * wrap and look empty.
803 * The only time we should loop here is when we hit the race
804 * between marking the queue awake and updating the cleared index.
805 * Just loop and it will appear. This comes from the acenic driver.
807 while(unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
810 first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
811 typhoon_inc_tx_index(&txRing->lastWrite, 1);
813 first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
814 first_txd->numDesc = 0;
816 first_txd->addr = (u64)((unsigned long) skb) & 0xffffffff;
817 first_txd->addrHi = (u64)((unsigned long) skb) >> 32;
818 first_txd->processFlags = 0;
820 if(skb->ip_summed == CHECKSUM_HW) {
821 /* The 3XP will figure out if this is UDP/TCP */
822 first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
823 first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
824 first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
827 if(vlan_tx_tag_present(skb)) {
828 first_txd->processFlags |=
829 TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
830 first_txd->processFlags |=
831 cpu_to_le32(htons(vlan_tx_tag_get(skb)) <<
832 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
835 if(skb_tso_size(skb)) {
836 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
837 first_txd->numDesc++;
839 typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
842 txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
843 typhoon_inc_tx_index(&txRing->lastWrite, 1);
845 /* No need to worry about padding packet -- the firmware pads
846 * it with zeros to ETH_ZLEN for us.
848 if(skb_shinfo(skb)->nr_frags == 0) {
849 skb_dma = pci_map_single(tp->tx_pdev, skb->data, skb->len,
851 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
852 txd->len = cpu_to_le16(skb->len);
853 txd->addr = cpu_to_le32(skb_dma);
855 first_txd->numDesc++;
859 len = skb_headlen(skb);
860 skb_dma = pci_map_single(tp->tx_pdev, skb->data, len,
862 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
863 txd->len = cpu_to_le16(len);
864 txd->addr = cpu_to_le32(skb_dma);
866 first_txd->numDesc++;
868 for(i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
869 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
872 txd = (struct tx_desc *) (txRing->ringBase +
874 typhoon_inc_tx_index(&txRing->lastWrite, 1);
877 frag_addr = (void *) page_address(frag->page) +
879 skb_dma = pci_map_single(tp->tx_pdev, frag_addr, len,
881 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
882 txd->len = cpu_to_le16(len);
883 txd->addr = cpu_to_le32(skb_dma);
885 first_txd->numDesc++;
892 writel(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
894 dev->trans_start = jiffies;
896 /* If we don't have room to put the worst case packet on the
897 * queue, then we must stop the queue. We need 2 extra
898 * descriptors -- one to prevent ring wrap, and one for the
901 numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
903 if(typhoon_num_free_tx(txRing) < (numDesc + 2)) {
904 netif_stop_queue(dev);
906 /* A Tx complete IRQ could have gotten inbetween, making
907 * the ring free again. Only need to recheck here, since
910 if(typhoon_num_free_tx(txRing) >= (numDesc + 2))
911 netif_wake_queue(dev);
918 typhoon_set_rx_mode(struct net_device *dev)
920 struct typhoon *tp = netdev_priv(dev);
921 struct cmd_desc xp_cmd;
925 filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
926 if(dev->flags & IFF_PROMISC) {
927 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
929 filter |= TYPHOON_RX_FILTER_PROMISCOUS;
930 } else if((dev->mc_count > multicast_filter_limit) ||
931 (dev->flags & IFF_ALLMULTI)) {
932 /* Too many to match, or accept all multicasts. */
933 filter |= TYPHOON_RX_FILTER_ALL_MCAST;
934 } else if(dev->mc_count) {
935 struct dev_mc_list *mclist;
938 memset(mc_filter, 0, sizeof(mc_filter));
939 for(i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
940 i++, mclist = mclist->next) {
941 int bit = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
942 mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
945 INIT_COMMAND_NO_RESPONSE(&xp_cmd,
946 TYPHOON_CMD_SET_MULTICAST_HASH);
947 xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
948 xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
949 xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
950 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
952 filter |= TYPHOON_RX_FILTER_MCAST_HASH;
955 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
956 xp_cmd.parm1 = filter;
957 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
961 typhoon_do_get_stats(struct typhoon *tp)
963 struct net_device_stats *stats = &tp->stats;
964 struct net_device_stats *saved = &tp->stats_saved;
965 struct cmd_desc xp_cmd;
966 struct resp_desc xp_resp[7];
967 struct stats_resp *s = (struct stats_resp *) xp_resp;
970 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
971 err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
975 /* 3Com's Linux driver uses txMultipleCollisions as it's
976 * collisions value, but there is some other collision info as well...
978 * The extra status reported would be a good candidate for
979 * ethtool_ops->get_{strings,stats}()
981 stats->tx_packets = le32_to_cpu(s->txPackets);
982 stats->tx_bytes = le32_to_cpu(s->txBytes);
983 stats->tx_errors = le32_to_cpu(s->txCarrierLost);
984 stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost);
985 stats->collisions = le32_to_cpu(s->txMultipleCollisions);
986 stats->rx_packets = le32_to_cpu(s->rxPacketsGood);
987 stats->rx_bytes = le32_to_cpu(s->rxBytesGood);
988 stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns);
989 stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
990 le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors);
991 stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors);
992 stats->rx_length_errors = le32_to_cpu(s->rxOversized);
993 tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
994 SPEED_100 : SPEED_10;
995 tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
996 DUPLEX_FULL : DUPLEX_HALF;
998 /* add in the saved statistics
1000 stats->tx_packets += saved->tx_packets;
1001 stats->tx_bytes += saved->tx_bytes;
1002 stats->tx_errors += saved->tx_errors;
1003 stats->collisions += saved->collisions;
1004 stats->rx_packets += saved->rx_packets;
1005 stats->rx_bytes += saved->rx_bytes;
1006 stats->rx_fifo_errors += saved->rx_fifo_errors;
1007 stats->rx_errors += saved->rx_errors;
1008 stats->rx_crc_errors += saved->rx_crc_errors;
1009 stats->rx_length_errors += saved->rx_length_errors;
1014 static struct net_device_stats *
1015 typhoon_get_stats(struct net_device *dev)
1017 struct typhoon *tp = netdev_priv(dev);
1018 struct net_device_stats *stats = &tp->stats;
1019 struct net_device_stats *saved = &tp->stats_saved;
1022 if(tp->card_state == Sleeping)
1025 if(typhoon_do_get_stats(tp) < 0) {
1026 printk(KERN_ERR "%s: error getting stats\n", dev->name);
1034 typhoon_set_mac_address(struct net_device *dev, void *addr)
1036 struct sockaddr *saddr = (struct sockaddr *) addr;
1038 if(netif_running(dev))
1041 memcpy(dev->dev_addr, saddr->sa_data, dev->addr_len);
1046 typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1048 struct typhoon *tp = netdev_priv(dev);
1049 struct pci_dev *pci_dev = tp->pdev;
1050 struct cmd_desc xp_cmd;
1051 struct resp_desc xp_resp[3];
1054 if(tp->card_state == Sleeping) {
1055 strcpy(info->fw_version, "Sleep image");
1057 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
1058 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
1059 strcpy(info->fw_version, "Unknown runtime");
1061 strncpy(info->fw_version, (char *) &xp_resp[1], 32);
1062 info->fw_version[31] = 0;
1066 strcpy(info->driver, DRV_MODULE_NAME);
1067 strcpy(info->version, DRV_MODULE_VERSION);
1068 strcpy(info->bus_info, pci_name(pci_dev));
1072 typhoon_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1074 struct typhoon *tp = netdev_priv(dev);
1076 cmd->supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1079 switch (tp->xcvr_select) {
1080 case TYPHOON_XCVR_10HALF:
1081 cmd->advertising = ADVERTISED_10baseT_Half;
1083 case TYPHOON_XCVR_10FULL:
1084 cmd->advertising = ADVERTISED_10baseT_Full;
1086 case TYPHOON_XCVR_100HALF:
1087 cmd->advertising = ADVERTISED_100baseT_Half;
1089 case TYPHOON_XCVR_100FULL:
1090 cmd->advertising = ADVERTISED_100baseT_Full;
1092 case TYPHOON_XCVR_AUTONEG:
1093 cmd->advertising = ADVERTISED_10baseT_Half |
1094 ADVERTISED_10baseT_Full |
1095 ADVERTISED_100baseT_Half |
1096 ADVERTISED_100baseT_Full |
1101 if(tp->capabilities & TYPHOON_FIBER) {
1102 cmd->supported |= SUPPORTED_FIBRE;
1103 cmd->advertising |= ADVERTISED_FIBRE;
1104 cmd->port = PORT_FIBRE;
1106 cmd->supported |= SUPPORTED_10baseT_Half |
1107 SUPPORTED_10baseT_Full |
1109 cmd->advertising |= ADVERTISED_TP;
1110 cmd->port = PORT_TP;
1113 /* need to get stats to make these link speed/duplex valid */
1114 typhoon_do_get_stats(tp);
1115 cmd->speed = tp->speed;
1116 cmd->duplex = tp->duplex;
1117 cmd->phy_address = 0;
1118 cmd->transceiver = XCVR_INTERNAL;
1119 if(tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
1120 cmd->autoneg = AUTONEG_ENABLE;
1122 cmd->autoneg = AUTONEG_DISABLE;
1130 typhoon_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1132 struct typhoon *tp = netdev_priv(dev);
1133 struct cmd_desc xp_cmd;
1138 if(cmd->autoneg == AUTONEG_ENABLE) {
1139 xcvr = TYPHOON_XCVR_AUTONEG;
1141 if(cmd->duplex == DUPLEX_HALF) {
1142 if(cmd->speed == SPEED_10)
1143 xcvr = TYPHOON_XCVR_10HALF;
1144 else if(cmd->speed == SPEED_100)
1145 xcvr = TYPHOON_XCVR_100HALF;
1148 } else if(cmd->duplex == DUPLEX_FULL) {
1149 if(cmd->speed == SPEED_10)
1150 xcvr = TYPHOON_XCVR_10FULL;
1151 else if(cmd->speed == SPEED_100)
1152 xcvr = TYPHOON_XCVR_100FULL;
1159 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1160 xp_cmd.parm1 = cpu_to_le16(xcvr);
1161 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1165 tp->xcvr_select = xcvr;
1166 if(cmd->autoneg == AUTONEG_ENABLE) {
1167 tp->speed = 0xff; /* invalid */
1168 tp->duplex = 0xff; /* invalid */
1170 tp->speed = cmd->speed;
1171 tp->duplex = cmd->duplex;
1179 typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1181 struct typhoon *tp = netdev_priv(dev);
1183 wol->supported = WAKE_PHY | WAKE_MAGIC;
1185 if(tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
1186 wol->wolopts |= WAKE_PHY;
1187 if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
1188 wol->wolopts |= WAKE_MAGIC;
1189 memset(&wol->sopass, 0, sizeof(wol->sopass));
1193 typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1195 struct typhoon *tp = netdev_priv(dev);
1197 if(wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
1201 if(wol->wolopts & WAKE_PHY)
1202 tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
1203 if(wol->wolopts & WAKE_MAGIC)
1204 tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
1210 typhoon_get_rx_csum(struct net_device *dev)
1212 /* For now, we don't allow turning off RX checksums.
1218 typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
1220 ering->rx_max_pending = RXENT_ENTRIES;
1221 ering->rx_mini_max_pending = 0;
1222 ering->rx_jumbo_max_pending = 0;
1223 ering->tx_max_pending = TXLO_ENTRIES - 1;
1225 ering->rx_pending = RXENT_ENTRIES;
1226 ering->rx_mini_pending = 0;
1227 ering->rx_jumbo_pending = 0;
1228 ering->tx_pending = TXLO_ENTRIES - 1;
1231 static struct ethtool_ops typhoon_ethtool_ops = {
1232 .get_settings = typhoon_get_settings,
1233 .set_settings = typhoon_set_settings,
1234 .get_drvinfo = typhoon_get_drvinfo,
1235 .get_wol = typhoon_get_wol,
1236 .set_wol = typhoon_set_wol,
1237 .get_link = ethtool_op_get_link,
1238 .get_rx_csum = typhoon_get_rx_csum,
1239 .get_tx_csum = ethtool_op_get_tx_csum,
1240 .set_tx_csum = ethtool_op_set_tx_csum,
1241 .get_sg = ethtool_op_get_sg,
1242 .set_sg = ethtool_op_set_sg,
1243 .get_tso = ethtool_op_get_tso,
1244 .set_tso = ethtool_op_set_tso,
1245 .get_ringparam = typhoon_get_ringparam,
1249 typhoon_wait_interrupt(void __iomem *ioaddr)
1253 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1254 if(readl(ioaddr + TYPHOON_REG_INTR_STATUS) &
1255 TYPHOON_INTR_BOOTCMD)
1257 udelay(TYPHOON_UDELAY);
1263 writel(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1267 #define shared_offset(x) offsetof(struct typhoon_shared, x)
1270 typhoon_init_interface(struct typhoon *tp)
1272 struct typhoon_interface *iface = &tp->shared->iface;
1273 dma_addr_t shared_dma;
1275 memset(tp->shared, 0, sizeof(struct typhoon_shared));
1277 /* The *Hi members of iface are all init'd to zero by the memset().
1279 shared_dma = tp->shared_dma + shared_offset(indexes);
1280 iface->ringIndex = cpu_to_le32(shared_dma);
1282 shared_dma = tp->shared_dma + shared_offset(txLo);
1283 iface->txLoAddr = cpu_to_le32(shared_dma);
1284 iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
1286 shared_dma = tp->shared_dma + shared_offset(txHi);
1287 iface->txHiAddr = cpu_to_le32(shared_dma);
1288 iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
1290 shared_dma = tp->shared_dma + shared_offset(rxBuff);
1291 iface->rxBuffAddr = cpu_to_le32(shared_dma);
1292 iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
1293 sizeof(struct rx_free));
1295 shared_dma = tp->shared_dma + shared_offset(rxLo);
1296 iface->rxLoAddr = cpu_to_le32(shared_dma);
1297 iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1299 shared_dma = tp->shared_dma + shared_offset(rxHi);
1300 iface->rxHiAddr = cpu_to_le32(shared_dma);
1301 iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1303 shared_dma = tp->shared_dma + shared_offset(cmd);
1304 iface->cmdAddr = cpu_to_le32(shared_dma);
1305 iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
1307 shared_dma = tp->shared_dma + shared_offset(resp);
1308 iface->respAddr = cpu_to_le32(shared_dma);
1309 iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
1311 shared_dma = tp->shared_dma + shared_offset(zeroWord);
1312 iface->zeroAddr = cpu_to_le32(shared_dma);
1314 tp->indexes = &tp->shared->indexes;
1315 tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
1316 tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
1317 tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
1318 tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
1319 tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
1320 tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
1321 tp->respRing.ringBase = (u8 *) tp->shared->resp;
1323 tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
1324 tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
1326 tp->txlo_dma_addr = iface->txLoAddr;
1327 tp->card_state = Sleeping;
1330 tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
1331 tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
1333 spin_lock_init(&tp->command_lock);
1334 spin_lock_init(&tp->state_lock);
1338 typhoon_init_rings(struct typhoon *tp)
1340 memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
1342 tp->txLoRing.lastWrite = 0;
1343 tp->txHiRing.lastWrite = 0;
1344 tp->rxLoRing.lastWrite = 0;
1345 tp->rxHiRing.lastWrite = 0;
1346 tp->rxBuffRing.lastWrite = 0;
1347 tp->cmdRing.lastWrite = 0;
1348 tp->cmdRing.lastWrite = 0;
1350 tp->txLoRing.lastRead = 0;
1351 tp->txHiRing.lastRead = 0;
1355 typhoon_download_firmware(struct typhoon *tp)
1357 void __iomem *ioaddr = tp->ioaddr;
1358 struct pci_dev *pdev = tp->pdev;
1359 struct typhoon_file_header *fHdr;
1360 struct typhoon_section_header *sHdr;
1363 dma_addr_t dpage_dma;
1376 fHdr = (struct typhoon_file_header *) typhoon_firmware_image;
1377 image_data = (u8 *) fHdr;
1379 if(memcmp(fHdr->tag, "TYPHOON", 8)) {
1380 printk(KERN_ERR "%s: Invalid firmware image!\n", tp->name);
1384 /* Cannot just map the firmware image using pci_map_single() as
1385 * the firmware is part of the kernel/module image, so we allocate
1386 * some consistent memory to copy the sections into, as it is simpler,
1387 * and short-lived. If we ever split out and require a userland
1388 * firmware loader, then we can revisit this.
1391 dpage = pci_alloc_consistent(pdev, PAGE_SIZE, &dpage_dma);
1393 printk(KERN_ERR "%s: no DMA mem for firmware\n", tp->name);
1397 irqEnabled = readl(ioaddr + TYPHOON_REG_INTR_ENABLE);
1398 writel(irqEnabled | TYPHOON_INTR_BOOTCMD,
1399 ioaddr + TYPHOON_REG_INTR_ENABLE);
1400 irqMasked = readl(ioaddr + TYPHOON_REG_INTR_MASK);
1401 writel(irqMasked | TYPHOON_INTR_BOOTCMD,
1402 ioaddr + TYPHOON_REG_INTR_MASK);
1405 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
1406 printk(KERN_ERR "%s: card ready timeout\n", tp->name);
1410 numSections = le32_to_cpu(fHdr->numSections);
1411 load_addr = le32_to_cpu(fHdr->startAddr);
1413 writel(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1414 writel(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
1415 hmac = le32_to_cpu(fHdr->hmacDigest[0]);
1416 writel(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
1417 hmac = le32_to_cpu(fHdr->hmacDigest[1]);
1418 writel(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
1419 hmac = le32_to_cpu(fHdr->hmacDigest[2]);
1420 writel(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
1421 hmac = le32_to_cpu(fHdr->hmacDigest[3]);
1422 writel(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
1423 hmac = le32_to_cpu(fHdr->hmacDigest[4]);
1424 writel(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
1425 typhoon_post_pci_writes(ioaddr);
1426 writel(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
1428 image_data += sizeof(struct typhoon_file_header);
1430 /* The readl() in typhoon_wait_interrupt() will force the
1431 * last write to the command register to post, so
1432 * we don't need a typhoon_post_pci_writes() after it.
1434 for(i = 0; i < numSections; i++) {
1435 sHdr = (struct typhoon_section_header *) image_data;
1436 image_data += sizeof(struct typhoon_section_header);
1437 load_addr = le32_to_cpu(sHdr->startAddr);
1438 section_len = le32_to_cpu(sHdr->len);
1440 while(section_len) {
1441 len = min_t(u32, section_len, PAGE_SIZE);
1443 if(typhoon_wait_interrupt(ioaddr) < 0 ||
1444 readl(ioaddr + TYPHOON_REG_STATUS) !=
1445 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1446 printk(KERN_ERR "%s: segment ready timeout\n",
1451 /* Do an pseudo IPv4 checksum on the data -- first
1452 * need to convert each u16 to cpu order before
1453 * summing. Fortunately, due to the properties of
1454 * the checksum, we can do this once, at the end.
1456 csum = csum_partial_copy_nocheck(image_data, dpage,
1458 csum = csum_fold(csum);
1459 csum = le16_to_cpu(csum);
1461 writel(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
1462 writel(csum, ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
1463 writel(load_addr, ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
1464 writel(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
1465 writel(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
1466 typhoon_post_pci_writes(ioaddr);
1467 writel(TYPHOON_BOOTCMD_SEG_AVAILABLE,
1468 ioaddr + TYPHOON_REG_COMMAND);
1476 if(typhoon_wait_interrupt(ioaddr) < 0 ||
1477 readl(ioaddr + TYPHOON_REG_STATUS) !=
1478 TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1479 printk(KERN_ERR "%s: final segment ready timeout\n", tp->name);
1483 writel(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
1485 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1486 printk(KERN_ERR "%s: boot ready timeout, status 0x%0x\n",
1487 tp->name, readl(ioaddr + TYPHOON_REG_STATUS));
1494 writel(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
1495 writel(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
1497 pci_free_consistent(pdev, PAGE_SIZE, dpage, dpage_dma);
1504 typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
1506 void __iomem *ioaddr = tp->ioaddr;
1508 if(typhoon_wait_status(ioaddr, initial_status) < 0) {
1509 printk(KERN_ERR "%s: boot ready timeout\n", tp->name);
1513 writel(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
1514 writel(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
1515 typhoon_post_pci_writes(ioaddr);
1516 writel(TYPHOON_BOOTCMD_REG_BOOT_RECORD, ioaddr + TYPHOON_REG_COMMAND);
1518 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
1519 printk(KERN_ERR "%s: boot finish timeout (status 0x%x)\n",
1520 tp->name, readl(ioaddr + TYPHOON_REG_STATUS));
1524 /* Clear the Transmit and Command ready registers
1526 writel(0, ioaddr + TYPHOON_REG_TX_HI_READY);
1527 writel(0, ioaddr + TYPHOON_REG_CMD_READY);
1528 writel(0, ioaddr + TYPHOON_REG_TX_LO_READY);
1529 typhoon_post_pci_writes(ioaddr);
1530 writel(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
1539 typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
1540 volatile u32 * index)
1542 u32 lastRead = txRing->lastRead;
1548 while(lastRead != le32_to_cpu(*index)) {
1549 tx = (struct tx_desc *) (txRing->ringBase + lastRead);
1550 type = tx->flags & TYPHOON_TYPE_MASK;
1552 if(type == TYPHOON_TX_DESC) {
1553 /* This tx_desc describes a packet.
1555 unsigned long ptr = tx->addr | ((u64)tx->addrHi << 32);
1556 struct sk_buff *skb = (struct sk_buff *) ptr;
1557 dev_kfree_skb_irq(skb);
1558 } else if(type == TYPHOON_FRAG_DESC) {
1559 /* This tx_desc describes a memory mapping. Free it.
1561 skb_dma = (dma_addr_t) le32_to_cpu(tx->addr);
1562 dma_len = le16_to_cpu(tx->len);
1563 pci_unmap_single(tp->pdev, skb_dma, dma_len,
1568 typhoon_inc_tx_index(&lastRead, 1);
1575 typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
1576 volatile u32 * index)
1579 int numDesc = MAX_SKB_FRAGS + 1;
1581 /* This will need changing if we start to use the Hi Tx ring. */
1582 lastRead = typhoon_clean_tx(tp, txRing, index);
1583 if(netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
1584 lastRead, TXLO_ENTRIES) > (numDesc + 2))
1585 netif_wake_queue(tp->dev);
1587 txRing->lastRead = lastRead;
1592 typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
1594 struct typhoon_indexes *indexes = tp->indexes;
1595 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1596 struct basic_ring *ring = &tp->rxBuffRing;
1599 if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1600 indexes->rxBuffCleared) {
1601 /* no room in ring, just drop the skb
1603 dev_kfree_skb_any(rxb->skb);
1608 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1609 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1611 r->physAddr = cpu_to_le32(rxb->dma_addr);
1613 /* Tell the card about it */
1615 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1619 typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
1621 struct typhoon_indexes *indexes = tp->indexes;
1622 struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1623 struct basic_ring *ring = &tp->rxBuffRing;
1625 struct sk_buff *skb;
1626 dma_addr_t dma_addr;
1630 if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1631 indexes->rxBuffCleared)
1634 skb = dev_alloc_skb(PKT_BUF_SZ);
1639 /* Please, 3com, fix the firmware to allow DMA to a unaligned
1640 * address! Pretty please?
1642 skb_reserve(skb, 2);
1646 dma_addr = pci_map_single(tp->pdev, skb->tail,
1647 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
1649 /* Since no card does 64 bit DAC, the high bits will never
1652 r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1653 typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1655 r->physAddr = cpu_to_le32(dma_addr);
1657 rxb->dma_addr = dma_addr;
1659 /* Tell the card about it */
1661 indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1666 typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile u32 * ready,
1667 volatile u32 * cleared, int budget)
1670 struct sk_buff *skb, *new_skb;
1671 struct rxbuff_ent *rxb;
1672 dma_addr_t dma_addr;
1681 local_ready = le32_to_cpu(*ready);
1682 rxaddr = le32_to_cpu(*cleared);
1683 while(rxaddr != local_ready && budget > 0) {
1684 rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
1686 rxb = &tp->rxbuffers[idx];
1688 dma_addr = rxb->dma_addr;
1690 rxaddr += sizeof(struct rx_desc);
1691 rxaddr %= RX_ENTRIES * sizeof(struct rx_desc);
1693 if(rx->flags & TYPHOON_RX_ERROR) {
1694 typhoon_recycle_rx_skb(tp, idx);
1698 pkt_len = le16_to_cpu(rx->frameLen);
1700 if(pkt_len < rx_copybreak &&
1701 (new_skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1702 new_skb->dev = tp->dev;
1703 skb_reserve(new_skb, 2);
1704 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr,
1706 PCI_DMA_FROMDEVICE);
1707 eth_copy_and_sum(new_skb, skb->tail, pkt_len, 0);
1708 pci_dma_sync_single_for_device(tp->pdev, dma_addr,
1710 PCI_DMA_FROMDEVICE);
1711 skb_put(new_skb, pkt_len);
1712 typhoon_recycle_rx_skb(tp, idx);
1715 skb_put(new_skb, pkt_len);
1716 pci_unmap_single(tp->pdev, dma_addr, PKT_BUF_SZ,
1717 PCI_DMA_FROMDEVICE);
1718 typhoon_alloc_rx_skb(tp, idx);
1720 new_skb->protocol = eth_type_trans(new_skb, tp->dev);
1721 csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
1722 TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
1724 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD)
1726 (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
1727 new_skb->ip_summed = CHECKSUM_UNNECESSARY;
1729 new_skb->ip_summed = CHECKSUM_NONE;
1731 spin_lock(&tp->state_lock);
1732 if(tp->vlgrp != NULL && rx->rxStatus & TYPHOON_RX_VLAN)
1733 vlan_hwaccel_receive_skb(new_skb, tp->vlgrp,
1734 ntohl(rx->vlanTag) & 0xffff);
1736 netif_receive_skb(new_skb);
1737 spin_unlock(&tp->state_lock);
1739 tp->dev->last_rx = jiffies;
1743 *cleared = cpu_to_le32(rxaddr);
1749 typhoon_fill_free_ring(struct typhoon *tp)
1753 for(i = 0; i < RXENT_ENTRIES; i++) {
1754 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1757 if(typhoon_alloc_rx_skb(tp, i) < 0)
1763 typhoon_poll(struct net_device *dev, int *total_budget)
1765 struct typhoon *tp = netdev_priv(dev);
1766 struct typhoon_indexes *indexes = tp->indexes;
1767 int orig_budget = *total_budget;
1768 int budget, work_done, done;
1771 if(!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
1772 typhoon_process_response(tp, 0, NULL);
1774 if(le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
1775 typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
1777 if(orig_budget > dev->quota)
1778 orig_budget = dev->quota;
1780 budget = orig_budget;
1784 if(indexes->rxHiCleared != indexes->rxHiReady) {
1785 work_done = typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
1786 &indexes->rxHiCleared, budget);
1787 budget -= work_done;
1790 if(indexes->rxLoCleared != indexes->rxLoReady) {
1791 work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
1792 &indexes->rxLoCleared, budget);
1796 *total_budget -= work_done;
1797 dev->quota -= work_done;
1799 if(work_done >= orig_budget)
1803 if(le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
1804 /* rxBuff ring is empty, try to fill it. */
1805 typhoon_fill_free_ring(tp);
1809 netif_rx_complete(dev);
1810 writel(TYPHOON_INTR_NONE, tp->ioaddr + TYPHOON_REG_INTR_MASK);
1811 typhoon_post_pci_writes(tp->ioaddr);
1814 return (done ? 0 : 1);
1818 typhoon_interrupt(int irq, void *dev_instance, struct pt_regs *rgs)
1820 struct net_device *dev = (struct net_device *) dev_instance;
1821 struct typhoon *tp = dev->priv;
1822 void __iomem *ioaddr = tp->ioaddr;
1825 intr_status = readl(ioaddr + TYPHOON_REG_INTR_STATUS);
1826 if(!(intr_status & TYPHOON_INTR_HOST_INT))
1829 writel(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
1831 if(netif_rx_schedule_prep(dev)) {
1832 writel(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
1833 typhoon_post_pci_writes(ioaddr);
1834 __netif_rx_schedule(dev);
1836 printk(KERN_ERR "%s: Error, poll already scheduled\n",
1843 typhoon_free_rx_rings(struct typhoon *tp)
1847 for(i = 0; i < RXENT_ENTRIES; i++) {
1848 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1850 pci_unmap_single(tp->pdev, rxb->dma_addr, PKT_BUF_SZ,
1851 PCI_DMA_FROMDEVICE);
1852 dev_kfree_skb(rxb->skb);
1859 typhoon_sleep(struct typhoon *tp, int state, u16 events)
1861 struct pci_dev *pdev = tp->pdev;
1862 void __iomem *ioaddr = tp->ioaddr;
1863 struct cmd_desc xp_cmd;
1866 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
1867 xp_cmd.parm1 = events;
1868 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1870 printk(KERN_ERR "%s: typhoon_sleep(): wake events cmd err %d\n",
1875 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
1876 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1878 printk(KERN_ERR "%s: typhoon_sleep(): sleep cmd err %d\n",
1883 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
1886 /* Since we cannot monitor the status of the link while sleeping,
1887 * tell the world it went away.
1889 netif_carrier_off(tp->dev);
1891 pci_enable_wake(tp->pdev, state, 1);
1892 pci_disable_device(pdev);
1893 return pci_set_power_state(pdev, state);
1897 typhoon_wakeup(struct typhoon *tp, int wait_type)
1899 struct pci_dev *pdev = tp->pdev;
1900 void __iomem *ioaddr = tp->ioaddr;
1902 pci_set_power_state(pdev, 0);
1903 pci_restore_state(pdev);
1905 /* Post 2.x.x versions of the Sleep Image require a reset before
1906 * we can download the Runtime Image. But let's not make users of
1907 * the old firmware pay for the reset.
1909 writel(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
1910 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
1911 (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
1912 return typhoon_reset(ioaddr, wait_type);
1918 typhoon_start_runtime(struct typhoon *tp)
1920 struct net_device *dev = tp->dev;
1921 void __iomem *ioaddr = tp->ioaddr;
1922 struct cmd_desc xp_cmd;
1925 typhoon_init_rings(tp);
1926 typhoon_fill_free_ring(tp);
1928 err = typhoon_download_firmware(tp);
1930 printk("%s: cannot load runtime on 3XP\n", tp->name);
1934 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1935 printk("%s: cannot boot 3XP\n", tp->name);
1940 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
1941 xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
1942 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1946 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
1947 xp_cmd.parm1 = cpu_to_le16(ntohs(*(u16 *)&dev->dev_addr[0]));
1948 xp_cmd.parm2 = cpu_to_le32(ntohl(*(u32 *)&dev->dev_addr[2]));
1949 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1953 /* Disable IRQ coalescing -- we can reenable it when 3Com gives
1954 * us some more information on how to control it.
1956 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
1958 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1962 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1963 xp_cmd.parm1 = tp->xcvr_select;
1964 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1968 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
1969 xp_cmd.parm1 = __constant_cpu_to_le16(ETH_P_8021Q);
1970 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1974 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
1975 spin_lock_bh(&tp->state_lock);
1976 xp_cmd.parm2 = tp->offload;
1977 xp_cmd.parm3 = tp->offload;
1978 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1979 spin_unlock_bh(&tp->state_lock);
1983 typhoon_set_rx_mode(dev);
1985 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
1986 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1990 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
1991 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1995 tp->card_state = Running;
1998 writel(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
1999 writel(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
2000 typhoon_post_pci_writes(ioaddr);
2005 typhoon_reset(ioaddr, WaitNoSleep);
2006 typhoon_free_rx_rings(tp);
2007 typhoon_init_rings(tp);
2012 typhoon_stop_runtime(struct typhoon *tp, int wait_type)
2014 struct typhoon_indexes *indexes = tp->indexes;
2015 struct transmit_ring *txLo = &tp->txLoRing;
2016 void __iomem *ioaddr = tp->ioaddr;
2017 struct cmd_desc xp_cmd;
2020 /* Disable interrupts early, since we can't schedule a poll
2021 * when called with !netif_running(). This will be posted
2022 * when we force the posting of the command.
2024 writel(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2026 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
2027 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2029 /* Wait 1/2 sec for any outstanding transmits to occur
2030 * We'll cleanup after the reset if this times out.
2032 for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
2033 if(indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
2035 udelay(TYPHOON_UDELAY);
2038 if(i == TYPHOON_WAIT_TIMEOUT)
2040 "%s: halt timed out waiting for Tx to complete\n",
2043 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
2044 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2046 /* save the statistics so when we bring the interface up again,
2047 * the values reported to userspace are correct.
2049 tp->card_state = Sleeping;
2051 typhoon_do_get_stats(tp);
2052 memcpy(&tp->stats_saved, &tp->stats, sizeof(struct net_device_stats));
2054 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
2055 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2057 if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
2058 printk(KERN_ERR "%s: timed out waiting for 3XP to halt\n",
2061 if(typhoon_reset(ioaddr, wait_type) < 0) {
2062 printk(KERN_ERR "%s: unable to reset 3XP\n", tp->name);
2066 /* cleanup any outstanding Tx packets */
2067 if(indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
2068 indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
2069 typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
2076 typhoon_tx_timeout(struct net_device *dev)
2078 struct typhoon *tp = netdev_priv(dev);
2080 if(typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
2081 printk(KERN_WARNING "%s: could not reset in tx timeout\n",
2086 /* If we ever start using the Hi ring, it will need cleaning too */
2087 typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
2088 typhoon_free_rx_rings(tp);
2090 if(typhoon_start_runtime(tp) < 0) {
2091 printk(KERN_ERR "%s: could not start runtime in tx timeout\n",
2096 netif_wake_queue(dev);
2100 /* Reset the hardware, and turn off carrier to avoid more timeouts */
2101 typhoon_reset(tp->ioaddr, NoWait);
2102 netif_carrier_off(dev);
2106 typhoon_open(struct net_device *dev)
2108 struct typhoon *tp = netdev_priv(dev);
2111 err = typhoon_wakeup(tp, WaitSleep);
2113 printk(KERN_ERR "%s: unable to wakeup device\n", dev->name);
2117 err = request_irq(dev->irq, &typhoon_interrupt, SA_SHIRQ,
2122 err = typhoon_start_runtime(tp);
2126 netif_start_queue(dev);
2130 free_irq(dev->irq, dev);
2133 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2134 printk(KERN_ERR "%s: unable to reboot into sleep img\n",
2136 typhoon_reset(tp->ioaddr, NoWait);
2140 if(typhoon_sleep(tp, 3, 0) < 0)
2141 printk(KERN_ERR "%s: unable to go back to sleep\n", dev->name);
2148 typhoon_close(struct net_device *dev)
2150 struct typhoon *tp = netdev_priv(dev);
2152 netif_stop_queue(dev);
2154 if(typhoon_stop_runtime(tp, WaitSleep) < 0)
2155 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2157 /* Make sure there is no irq handler running on a different CPU. */
2158 typhoon_synchronize_irq(dev->irq);
2159 free_irq(dev->irq, dev);
2161 typhoon_free_rx_rings(tp);
2162 typhoon_init_rings(tp);
2164 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
2165 printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
2167 if(typhoon_sleep(tp, 3, 0) < 0)
2168 printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
2175 typhoon_resume(struct pci_dev *pdev)
2177 struct net_device *dev = pci_get_drvdata(pdev);
2178 struct typhoon *tp = netdev_priv(dev);
2180 /* If we're down, resume when we are upped.
2182 if(!netif_running(dev))
2185 if(typhoon_wakeup(tp, WaitNoSleep) < 0) {
2186 printk(KERN_ERR "%s: critical: could not wake up in resume\n",
2191 if(typhoon_start_runtime(tp) < 0) {
2192 printk(KERN_ERR "%s: critical: could not start runtime in "
2193 "resume\n", dev->name);
2197 netif_device_attach(dev);
2198 netif_start_queue(dev);
2202 typhoon_reset(tp->ioaddr, NoWait);
2207 typhoon_suspend(struct pci_dev *pdev, u32 state)
2209 struct net_device *dev = pci_get_drvdata(pdev);
2210 struct typhoon *tp = netdev_priv(dev);
2211 struct cmd_desc xp_cmd;
2213 /* If we're down, we're already suspended.
2215 if(!netif_running(dev))
2218 spin_lock_bh(&tp->state_lock);
2219 if(tp->vlgrp && tp->wol_events & TYPHOON_WAKE_MAGIC_PKT) {
2220 spin_unlock_bh(&tp->state_lock);
2221 printk(KERN_ERR "%s: cannot do WAKE_MAGIC with VLANS\n",
2225 spin_unlock_bh(&tp->state_lock);
2227 netif_device_detach(dev);
2229 if(typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
2230 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2234 typhoon_free_rx_rings(tp);
2235 typhoon_init_rings(tp);
2237 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2238 printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
2242 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
2243 xp_cmd.parm1 = cpu_to_le16(ntohs(*(u16 *)&dev->dev_addr[0]));
2244 xp_cmd.parm2 = cpu_to_le32(ntohl(*(u32 *)&dev->dev_addr[2]));
2245 if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2246 printk(KERN_ERR "%s: unable to set mac address in suspend\n",
2251 INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
2252 xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
2253 if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2254 printk(KERN_ERR "%s: unable to set rx filter in suspend\n",
2259 if(typhoon_sleep(tp, state, tp->wol_events) < 0) {
2260 printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
2267 typhoon_resume(pdev);
2272 typhoon_enable_wake(struct pci_dev *pdev, u32 state, int enable)
2274 return pci_enable_wake(pdev, state, enable);
2278 static int __devinit
2279 typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2281 static int did_version = 0;
2282 struct net_device *dev;
2284 int card_id = (int) ent->driver_data;
2285 unsigned long ioaddr;
2286 void __iomem *ioaddr_mapped;
2288 dma_addr_t shared_dma;
2289 struct cmd_desc xp_cmd;
2290 struct resp_desc xp_resp[3];
2295 printk(KERN_INFO "%s", version);
2297 dev = alloc_etherdev(sizeof(*tp));
2299 printk(ERR_PFX "%s: unable to alloc new net device\n",
2304 SET_MODULE_OWNER(dev);
2305 SET_NETDEV_DEV(dev, &pdev->dev);
2307 err = pci_enable_device(pdev);
2309 printk(ERR_PFX "%s: unable to enable device\n",
2314 err = pci_set_mwi(pdev);
2316 printk(ERR_PFX "%s: unable to set MWI\n", pci_name(pdev));
2317 goto error_out_disable;
2320 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2322 printk(ERR_PFX "%s: No usable DMA configuration\n",
2327 /* sanity checks, resource #1 is our mmio area
2329 if(!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2331 "%s: region #1 not a PCI MMIO resource, aborting\n",
2336 if(pci_resource_len(pdev, 1) < 128) {
2337 printk(ERR_PFX "%s: Invalid PCI MMIO region size, aborting\n",
2343 err = pci_request_regions(pdev, "typhoon");
2345 printk(ERR_PFX "%s: could not request regions\n",
2350 /* map our MMIO region
2352 ioaddr = pci_resource_start(pdev, 1);
2353 ioaddr_mapped = ioremap(ioaddr, 128);
2354 if (!ioaddr_mapped) {
2355 printk(ERR_PFX "%s: cannot remap MMIO, aborting\n",
2358 goto error_out_regions;
2361 /* allocate pci dma space for rx and tx descriptor rings
2363 shared = pci_alloc_consistent(pdev, sizeof(struct typhoon_shared),
2366 printk(ERR_PFX "%s: could not allocate DMA memory\n",
2369 goto error_out_remap;
2372 dev->irq = pdev->irq;
2373 tp = netdev_priv(dev);
2374 tp->shared = (struct typhoon_shared *) shared;
2375 tp->shared_dma = shared_dma;
2378 tp->ioaddr = ioaddr_mapped;
2379 tp->tx_ioaddr = ioaddr_mapped;
2382 /* need to be able to restore PCI state after a suspend */
2383 pci_save_state(pdev);
2386 * 1) Reset the adapter to clear any bad juju
2387 * 2) Reload the sleep image
2388 * 3) Boot the sleep image
2389 * 4) Get the hardware address.
2390 * 5) Put the card to sleep.
2392 if (typhoon_reset(ioaddr_mapped, WaitSleep) < 0) {
2393 printk(ERR_PFX "%s: could not reset 3XP\n", pci_name(pdev));
2398 /* Now that we've reset the 3XP and are sure it's not going to
2399 * write all over memory, enable bus mastering.
2401 pci_set_master(pdev);
2403 /* dev->name is not valid until we register, but we need to
2404 * use some common routines to initialize the card. So that those
2405 * routines print the right name, we keep our oun pointer to the name
2407 tp->name = pci_name(pdev);
2409 typhoon_init_interface(tp);
2410 typhoon_init_rings(tp);
2412 if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2413 printk(ERR_PFX "%s: cannot boot 3XP sleep image\n",
2416 goto error_out_reset;
2419 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
2420 if(typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp) < 0) {
2421 printk(ERR_PFX "%s: cannot read MAC address\n",
2424 goto error_out_reset;
2427 *(u16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
2428 *(u32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
2430 if(!is_valid_ether_addr(dev->dev_addr)) {
2431 printk(ERR_PFX "%s: Could not obtain valid ethernet address, "
2432 "aborting\n", pci_name(pdev));
2433 goto error_out_reset;
2436 /* Read the Sleep Image version last, so the response is valid
2437 * later when we print out the version reported.
2439 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
2440 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
2441 printk(ERR_PFX "%s: Could not get Sleep Image version\n",
2443 goto error_out_reset;
2446 tp->capabilities = typhoon_card_info[card_id].capabilities;
2447 tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
2449 /* Typhoon 1.0 Sleep Images return one response descriptor to the
2450 * READ_VERSIONS command. Those versions are OK after waking up
2451 * from sleep without needing a reset. Typhoon 1.1+ Sleep Images
2452 * seem to need a little extra help to get started. Since we don't
2453 * know how to nudge it along, just kick it.
2455 if(xp_resp[0].numDesc != 0)
2456 tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
2458 if(typhoon_sleep(tp, 3, 0) < 0) {
2459 printk(ERR_PFX "%s: cannot put adapter to sleep\n",
2462 goto error_out_reset;
2465 /* The chip-specific entries in the device structure. */
2466 dev->open = typhoon_open;
2467 dev->hard_start_xmit = typhoon_start_tx;
2468 dev->stop = typhoon_close;
2469 dev->set_multicast_list = typhoon_set_rx_mode;
2470 dev->tx_timeout = typhoon_tx_timeout;
2471 dev->poll = typhoon_poll;
2473 dev->watchdog_timeo = TX_TIMEOUT;
2474 dev->get_stats = typhoon_get_stats;
2475 dev->set_mac_address = typhoon_set_mac_address;
2476 dev->vlan_rx_register = typhoon_vlan_rx_register;
2477 dev->vlan_rx_kill_vid = typhoon_vlan_rx_kill_vid;
2478 SET_ETHTOOL_OPS(dev, &typhoon_ethtool_ops);
2480 /* We can handle scatter gather, up to 16 entries, and
2481 * we can do IP checksumming (only version 4, doh...)
2483 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2484 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2485 dev->features |= NETIF_F_TSO;
2487 if(register_netdev(dev) < 0)
2488 goto error_out_reset;
2490 /* fixup our local name */
2491 tp->name = dev->name;
2493 pci_set_drvdata(pdev, dev);
2495 printk(KERN_INFO "%s: %s at 0x%lx, ",
2496 dev->name, typhoon_card_info[card_id].name, ioaddr);
2497 for(i = 0; i < 5; i++)
2498 printk("%2.2x:", dev->dev_addr[i]);
2499 printk("%2.2x\n", dev->dev_addr[i]);
2501 /* xp_resp still contains the response to the READ_VERSIONS command.
2502 * For debugging, let the user know what version he has.
2504 if(xp_resp[0].numDesc == 0) {
2505 /* This is the Typhoon 1.0 type Sleep Image, last 16 bits
2506 * of version is Month/Day of build.
2508 u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
2509 printk(KERN_INFO "%s: Typhoon 1.0 Sleep Image built "
2510 "%02u/%02u/2000\n", dev->name, monthday >> 8,
2512 } else if(xp_resp[0].numDesc == 2) {
2513 /* This is the Typhoon 1.1+ type Sleep Image
2515 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
2516 u8 *ver_string = (u8 *) &xp_resp[1];
2518 printk(KERN_INFO "%s: Typhoon 1.1+ Sleep Image version "
2519 "%u.%u.%u.%u %s\n", dev->name, HIPQUAD(sleep_ver),
2522 printk(KERN_WARNING "%s: Unknown Sleep Image version "
2523 "(%u:%04x)\n", dev->name, xp_resp[0].numDesc,
2524 le32_to_cpu(xp_resp[0].parm2));
2530 typhoon_reset(ioaddr_mapped, NoWait);
2533 pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2534 shared, shared_dma);
2536 iounmap(ioaddr_mapped);
2538 pci_release_regions(pdev);
2540 pci_clear_mwi(pdev);
2542 pci_disable_device(pdev);
2549 static void __devexit
2550 typhoon_remove_one(struct pci_dev *pdev)
2552 struct net_device *dev = pci_get_drvdata(pdev);
2553 struct typhoon *tp = netdev_priv(dev);
2555 unregister_netdev(dev);
2556 pci_set_power_state(pdev, 0);
2557 pci_restore_state(pdev);
2558 typhoon_reset(tp->ioaddr, NoWait);
2559 iounmap(tp->ioaddr);
2560 pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2561 tp->shared, tp->shared_dma);
2562 pci_release_regions(pdev);
2563 pci_clear_mwi(pdev);
2564 pci_disable_device(pdev);
2565 pci_set_drvdata(pdev, NULL);
2569 static struct pci_driver typhoon_driver = {
2570 .name = DRV_MODULE_NAME,
2571 .id_table = typhoon_pci_tbl,
2572 .probe = typhoon_init_one,
2573 .remove = __devexit_p(typhoon_remove_one),
2575 .suspend = typhoon_suspend,
2576 .resume = typhoon_resume,
2577 .enable_wake = typhoon_enable_wake,
2584 return pci_module_init(&typhoon_driver);
2588 typhoon_cleanup(void)
2590 pci_unregister_driver(&typhoon_driver);
2593 module_init(typhoon_init);
2594 module_exit(typhoon_cleanup);