2 * drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux
4 * This software may be used and distributed according to the terms of the
5 * GNU General Public License.
7 * The author may be reached as romieu@cogenit.fr.
8 * Specific bug reports/asian food will be welcome.
10 * Special thanks to the nice people at CS-Telecom for the hardware and the
11 * access to the test/measure tools.
16 * I. Board Compatibility
18 * This device driver is designed for the Siemens PEB20534 4 ports serial
19 * controller as found on Etinc PCISYNC cards. The documentation for the
20 * chipset is available at http://www.infineon.com:
21 * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with
22 * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1";
23 * - Application Hint "Management of DSCC4 on-chip FIFO resources".
24 * - Errata sheet DS5 (courtesy of Michael Skerritt).
25 * Jens David has built an adapter based on the same chipset. Take a look
26 * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific
28 * Sample code (2 revisions) is available at Infineon.
30 * II. Board-specific settings
32 * Pcisync can transmit some clock signal to the outside world on the
33 * *first two* ports provided you put a quartz and a line driver on it and
34 * remove the jumpers. The operation is described on Etinc web site. If you
35 * go DCE on these ports, don't forget to use an adequate cable.
37 * Sharing of the PCI interrupt line for this board is possible.
39 * III. Driver operation
41 * The rx/tx operations are based on a linked list of descriptors. The driver
42 * doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more
43 * I tried to fix it, the more it started to look like (convoluted) software
44 * mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider
45 * this a rfc2119 MUST.
48 * When the tx ring is full, the xmit routine issues a call to netdev_stop.
49 * The device is supposed to be enabled again during an ALLS irq (we could
50 * use HI but as it's easy to lose events, it's fscked).
53 * The received frames aren't supposed to span over multiple receiving areas.
54 * I may implement it some day but it isn't the highest ranked item.
57 * The current error (XDU, RFO) recovery code is untested.
58 * So far, RDO takes his RX channel down and the right sequence to enable it
59 * again is still a mistery. If RDO happens, plan a reboot. More details
60 * in the code (NB: as this happens, TX still works).
61 * Don't mess the cables during operation, especially on DTE ports. I don't
62 * suggest it for DCE either but at least one can get some messages instead
63 * of a complete instant freeze.
64 * Tests are done on Rev. 20 of the silicium. The RDO handling changes with
65 * the documentation/chipset releases.
69 * - use polling at high irq/s,
70 * - performance analysis,
73 * 2001/12/10 Daniela Squassoni <daniela@cyclades.com>
74 * - Contribution to support the new generic HDLC layer.
77 * - old style interface removal
78 * - dscc4_release_ring fix (related to DMA mapping)
79 * - hard_start_xmit fix (hint: TxSizeMax)
83 #include <linux/module.h>
84 #include <linux/types.h>
85 #include <linux/errno.h>
86 #include <linux/list.h>
87 #include <linux/ioport.h>
88 #include <linux/pci.h>
89 #include <linux/kernel.h>
92 #include <asm/system.h>
93 #include <asm/cache.h>
94 #include <asm/byteorder.h>
95 #include <asm/uaccess.h>
99 #include <linux/init.h>
100 #include <linux/string.h>
102 #include <linux/if_arp.h>
103 #include <linux/netdevice.h>
104 #include <linux/skbuff.h>
105 #include <linux/delay.h>
106 #include <net/syncppp.h>
107 #include <linux/hdlc.h>
110 static const char version[] = "$Id: dscc4.c,v 1.173 2003/09/20 23:55:34 romieu Exp $ for Linux\n";
114 #ifdef CONFIG_DSCC4_PCI_RST
115 static DECLARE_MUTEX(dscc4_sem);
116 static u32 dscc4_pci_config_store[16];
119 #define DRV_NAME "dscc4"
123 /* Module parameters */
125 MODULE_AUTHOR("Maintainer: Francois Romieu <romieu@cogenit.fr>");
126 MODULE_DESCRIPTION("Siemens PEB20534 PCI Controler");
127 MODULE_LICENSE("GPL");
128 MODULE_PARM(debug,"i");
129 MODULE_PARM_DESC(debug,"Enable/disable extra messages");
130 MODULE_PARM(quartz,"i");
131 MODULE_PARM_DESC(quartz,"If present, on-board quartz frequency (Hz)");
145 u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */
156 #define DUMMY_SKB_SIZE 64
158 #define TX_RING_SIZE 32
159 #define RX_RING_SIZE 32
160 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD)
161 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD)
162 #define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */
163 #define TX_TIMEOUT (HZ/10)
164 #define DSCC4_HZ_MAX 33000000
165 #define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */
166 #define dev_per_card 4
167 #define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */
169 #define SOURCE_ID(flags) (((flags) >> 28) & 0x03)
170 #define TO_SIZE(state) (((state) >> 16) & 0x1fff)
173 * Given the operating range of Linux HDLC, the 2 defines below could be
174 * made simpler. However they are a fine reminder for the limitations of
175 * the driver: it's better to stay < TxSizeMax and < RxSizeMax.
177 #define TO_STATE_TX(len) cpu_to_le32(((len) & TxSizeMax) << 16)
178 #define TO_STATE_RX(len) cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16)
179 #define RX_MAX(len) ((((len) >> 5) + 1) << 5) /* Cf RLCR */
180 #define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET)
182 struct dscc4_pci_priv {
186 struct pci_dev *pdev;
188 struct dscc4_dev_priv *root;
189 dma_addr_t iqcfg_dma;
193 struct dscc4_dev_priv {
194 struct sk_buff *rx_skbuff[RX_RING_SIZE];
195 struct sk_buff *tx_skbuff[TX_RING_SIZE];
202 /* FIXME: check all the volatile are required */
203 volatile u32 tx_current;
208 volatile u32 tx_dirty;
213 dma_addr_t tx_fd_dma;
214 dma_addr_t rx_fd_dma;
218 u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */
220 struct timer_list timer;
222 struct dscc4_pci_priv *pci_priv;
229 unsigned short encoding;
230 unsigned short parity;
231 struct net_device *dev;
232 sync_serial_settings settings;
233 u32 __pad __attribute__ ((aligned (4)));
236 /* GLOBAL registers definitions */
257 /* SCC registers definitions */
258 #define SCC_START 0x0100
259 #define SCC_OFFSET 0x80
271 #define GPDATA 0x0404
275 #define EncodingMask 0x00700000
276 #define CrcMask 0x00000003
278 #define IntRxScc0 0x10000000
279 #define IntTxScc0 0x01000000
281 #define TxPollCmd 0x00000400
282 #define RxActivate 0x08000000
283 #define MTFi 0x04000000
284 #define Rdr 0x00400000
285 #define Rdt 0x00200000
286 #define Idr 0x00100000
287 #define Idt 0x00080000
288 #define TxSccRes 0x01000000
289 #define RxSccRes 0x00010000
290 #define TxSizeMax 0x1fff /* Datasheet DS1 - 11.1.1.1 */
291 #define RxSizeMax 0x1ffc /* Datasheet DS1 - 11.1.2.1 */
293 #define Ccr0ClockMask 0x0000003f
294 #define Ccr1LoopMask 0x00000200
295 #define IsrMask 0x000fffff
296 #define BrrExpMask 0x00000f00
297 #define BrrMultMask 0x0000003f
298 #define EncodingMask 0x00700000
299 #define Hold 0x40000000
300 #define SccBusy 0x10000000
301 #define PowerUp 0x80000000
302 #define Vis 0x00001000
303 #define FrameOk (FrameVfr | FrameCrc)
304 #define FrameVfr 0x80
305 #define FrameRdo 0x40
306 #define FrameCrc 0x20
307 #define FrameRab 0x10
308 #define FrameAborted 0x00000200
309 #define FrameEnd 0x80000000
310 #define DataComplete 0x40000000
311 #define LengthCheck 0x00008000
312 #define SccEvt 0x02000000
313 #define NoAck 0x00000200
314 #define Action 0x00000001
315 #define HiDesc 0x20000000
318 #define RxEvt 0xf0000000
319 #define TxEvt 0x0f000000
320 #define Alls 0x00040000
321 #define Xdu 0x00010000
322 #define Cts 0x00004000
323 #define Xmr 0x00002000
324 #define Xpr 0x00001000
325 #define Rdo 0x00000080
326 #define Rfs 0x00000040
327 #define Cd 0x00000004
328 #define Rfo 0x00000002
329 #define Flex 0x00000001
331 /* DMA core events */
332 #define Cfg 0x00200000
333 #define Hi 0x00040000
334 #define Fi 0x00020000
335 #define Err 0x00010000
336 #define Arf 0x00000002
337 #define ArAck 0x00000001
340 #define Ready 0x00000000
341 #define NeedIDR 0x00000001
342 #define NeedIDT 0x00000002
343 #define RdoSet 0x00000004
344 #define FakeReset 0x00000008
346 /* Don't mask RDO. Ever. */
348 #define EventsMask 0xfffeef7f
350 #define EventsMask 0xfffa8f7a
353 /* Functions prototypes */
354 static inline void dscc4_rx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
355 static inline void dscc4_tx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
356 static int dscc4_found1(struct pci_dev *, unsigned long ioaddr);
357 static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent);
358 static int dscc4_open(struct net_device *);
359 static int dscc4_start_xmit(struct sk_buff *, struct net_device *);
360 static int dscc4_close(struct net_device *);
361 static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
362 static int dscc4_init_ring(struct net_device *);
363 static void dscc4_release_ring(struct dscc4_dev_priv *);
364 static void dscc4_timer(unsigned long);
365 static void dscc4_tx_timeout(struct net_device *);
366 static irqreturn_t dscc4_irq(int irq, void *dev_id, struct pt_regs *ptregs);
367 static int dscc4_hdlc_attach(struct net_device *, unsigned short, unsigned short);
368 static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *);
369 static inline int dscc4_set_quartz(struct dscc4_dev_priv *, int);
371 static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *);
374 static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev)
376 return dev_to_hdlc(dev)->priv;
379 static inline struct net_device *dscc4_to_dev(struct dscc4_dev_priv *p)
384 static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv,
385 struct net_device *dev, int offset)
389 /* Cf scc_writel for concern regarding thread-safety */
390 state = dpriv->scc_regs[offset >> 2];
393 dpriv->scc_regs[offset >> 2] = state;
394 writel(state, dev->base_addr + SCC_REG_START(dpriv) + offset);
397 static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,
398 struct net_device *dev, int offset)
402 * As of 2002/02/16, there are no thread racing for access.
404 dpriv->scc_regs[offset >> 2] = bits;
405 writel(bits, dev->base_addr + SCC_REG_START(dpriv) + offset);
408 static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset)
410 return dpriv->scc_regs[offset >> 2];
413 static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev)
415 /* Cf errata DS5 p.4 */
416 readl(dev->base_addr + SCC_REG_START(dpriv) + STAR);
417 return readl(dev->base_addr + SCC_REG_START(dpriv) + STAR);
420 static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv,
421 struct net_device *dev)
423 dpriv->ltda = dpriv->tx_fd_dma +
424 ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD);
425 writel(dpriv->ltda, dev->base_addr + CH0LTDA + dpriv->dev_id*4);
426 /* Flush posted writes *NOW* */
427 readl(dev->base_addr + CH0LTDA + dpriv->dev_id*4);
430 static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv,
431 struct net_device *dev)
433 dpriv->lrda = dpriv->rx_fd_dma +
434 ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD);
435 writel(dpriv->lrda, dev->base_addr + CH0LRDA + dpriv->dev_id*4);
438 static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv)
440 return dpriv->tx_current == dpriv->tx_dirty;
443 static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv,
444 struct net_device *dev)
446 return readl(dev->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda;
449 int state_check(u32 state, struct dscc4_dev_priv *dpriv, struct net_device *dev,
455 if (SOURCE_ID(state) != dpriv->dev_id) {
456 printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n",
457 dev->name, msg, SOURCE_ID(state), state );
460 if (state & 0x0df80c00) {
461 printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n",
462 dev->name, msg, state);
469 void dscc4_tx_print(struct net_device *dev, struct dscc4_dev_priv *dpriv,
472 printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n",
473 dev->name, dpriv->tx_current, dpriv->tx_dirty, msg);
476 static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
478 struct pci_dev *pdev = dpriv->pci_priv->pdev;
479 struct TxFD *tx_fd = dpriv->tx_fd;
480 struct RxFD *rx_fd = dpriv->rx_fd;
481 struct sk_buff **skbuff;
484 pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma);
485 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
487 skbuff = dpriv->tx_skbuff;
488 for (i = 0; i < TX_RING_SIZE; i++) {
490 pci_unmap_single(pdev, tx_fd->data, (*skbuff)->len,
492 dev_kfree_skb(*skbuff);
498 skbuff = dpriv->rx_skbuff;
499 for (i = 0; i < RX_RING_SIZE; i++) {
501 pci_unmap_single(pdev, rx_fd->data,
502 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
503 dev_kfree_skb(*skbuff);
510 inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv, struct net_device *dev)
512 unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE;
513 struct RxFD *rx_fd = dpriv->rx_fd + dirty;
514 const int len = RX_MAX(HDLC_MAX_MRU);
518 skb = dev_alloc_skb(len);
519 dpriv->rx_skbuff[dirty] = skb;
522 skb->protocol = hdlc_type_trans(skb, dev);
523 skb->mac.raw = skb->data;
524 rx_fd->data = pci_map_single(dpriv->pci_priv->pdev, skb->data,
525 len, PCI_DMA_FROMDEVICE);
527 rx_fd->data = (u32) NULL;
534 * IRQ/thread/whatever safe
536 static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv,
537 struct net_device *dev, char *msg)
542 if (!(scc_readl_star(dpriv, dev) & SccBusy)) {
543 printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name,
547 set_current_state(TASK_UNINTERRUPTIBLE);
548 schedule_timeout(10);
551 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
553 return (i >= 0) ? i : -EAGAIN;
556 static int dscc4_do_action(struct net_device *dev, char *msg)
558 unsigned long ioaddr = dev->base_addr;
561 writel(Action, ioaddr + GCMDR);
564 u32 state = readl(ioaddr);
567 printk(KERN_DEBUG "%s: %s ack\n", dev->name, msg);
568 writel(ArAck, ioaddr);
570 } else if (state & Arf) {
571 printk(KERN_ERR "%s: %s failed\n", dev->name, msg);
578 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
583 static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv)
585 int cur = dpriv->iqtx_current%IRQ_RING_SIZE;
589 if (!(dpriv->flags & (NeedIDR | NeedIDT)) ||
590 (dpriv->iqtx[cur] & Xpr))
593 set_current_state(TASK_UNINTERRUPTIBLE);
594 schedule_timeout(10);
597 return (i >= 0 ) ? i : -EAGAIN;
600 #if 0 /* dscc4_{rx/tx}_reset are both unreliable - more tweak needed */
601 static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
605 spin_lock_irqsave(&dpriv->pci_priv->lock, flags);
606 /* Cf errata DS5 p.6 */
607 writel(0x00000000, dev->base_addr + CH0LRDA + dpriv->dev_id*4);
608 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
609 readl(dev->base_addr + CH0LRDA + dpriv->dev_id*4);
610 writel(MTFi|Rdr, dev->base_addr + dpriv->dev_id*0x0c + CH0CFG);
611 writel(Action, dev->base_addr + GCMDR);
612 spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags);
618 static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
622 /* Cf errata DS5 p.7 */
623 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
624 scc_writel(0x00050000, dpriv, dev, CCR2);
626 * Must be longer than the time required to fill the fifo.
628 while (!dscc4_tx_quiescent(dpriv, dev) && ++i) {
633 writel(MTFi|Rdt, dev->base_addr + dpriv->dev_id*0x0c + CH0CFG);
634 if (dscc4_do_action(dev, "Rdt") < 0)
635 printk(KERN_ERR "%s: Tx reset failed\n", dev->name);
639 /* TODO: (ab)use this function to refill a completely depleted RX ring. */
640 static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
641 struct net_device *dev)
643 struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE;
644 struct net_device_stats *stats = hdlc_stats(dev);
645 struct pci_dev *pdev = dpriv->pci_priv->pdev;
649 skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE];
651 printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __FUNCTION__);
654 pkt_len = TO_SIZE(rx_fd->state2);
655 pci_unmap_single(pdev, rx_fd->data, RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
656 if ((skb->data[--pkt_len] & FrameOk) == FrameOk) {
658 stats->rx_bytes += pkt_len;
659 skb_put(skb, pkt_len);
660 if (netif_running(dev))
661 skb->protocol = hdlc_type_trans(skb, dev);
662 skb->dev->last_rx = jiffies;
665 if (skb->data[pkt_len] & FrameRdo)
666 stats->rx_fifo_errors++;
667 else if (!(skb->data[pkt_len] | ~FrameCrc))
668 stats->rx_crc_errors++;
669 else if (!(skb->data[pkt_len] | ~(FrameVfr | FrameRab)))
670 stats->rx_length_errors++;
673 dev_kfree_skb_irq(skb);
676 while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) {
677 if (try_get_rx_skb(dpriv, dev) < 0)
681 dscc4_rx_update(dpriv, dev);
682 rx_fd->state2 = 0x00000000;
683 rx_fd->end = 0xbabeface;
686 static void dscc4_free1(struct pci_dev *pdev)
688 struct dscc4_pci_priv *ppriv;
689 struct dscc4_dev_priv *root;
692 ppriv = pci_get_drvdata(pdev);
695 for (i = 0; i < dev_per_card; i++)
696 unregister_hdlc_device(dscc4_to_dev(&root[i]));
698 pci_set_drvdata(pdev, NULL);
700 for (i = 0; i < dev_per_card; i++)
701 free_netdev(root[i].dev);
706 static int __devinit dscc4_init_one(struct pci_dev *pdev,
707 const struct pci_device_id *ent)
709 struct dscc4_pci_priv *priv;
710 struct dscc4_dev_priv *dpriv;
711 static int cards_found = 0;
712 unsigned long ioaddr;
715 printk(KERN_DEBUG "%s", version);
717 if (pci_enable_device(pdev))
719 if (!request_mem_region(pci_resource_start(pdev, 0),
720 pci_resource_len(pdev, 0), "registers")) {
721 printk(KERN_ERR "%s: can't reserve MMIO region (regs)\n",
725 if (!request_mem_region(pci_resource_start(pdev, 1),
726 pci_resource_len(pdev, 1), "LBI interface")) {
727 printk(KERN_ERR "%s: can't reserve MMIO region (lbi)\n",
729 goto err_out_free_mmio_region0;
731 ioaddr = (unsigned long)ioremap(pci_resource_start(pdev, 0),
732 pci_resource_len(pdev, 0));
734 printk(KERN_ERR "%s: cannot remap MMIO region %lx @ %lx\n",
735 DRV_NAME, pci_resource_len(pdev, 0),
736 pci_resource_start(pdev, 0));
737 goto err_out_free_mmio_region;
739 printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#lx (regs), %#lx (lbi), IRQ %d\n",
740 pci_resource_start(pdev, 0),
741 pci_resource_start(pdev, 1), pdev->irq);
743 /* Cf errata DS5 p.2 */
744 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8);
745 pci_set_master(pdev);
747 if (dscc4_found1(pdev, ioaddr))
748 goto err_out_iounmap;
750 priv = (struct dscc4_pci_priv *)pci_get_drvdata(pdev);
752 if (request_irq(pdev->irq, &dscc4_irq, SA_SHIRQ, DRV_NAME, priv->root)){
753 printk(KERN_WARNING "%s: IRQ %d busy\n", DRV_NAME, pdev->irq);
757 /* power up/little endian/dma core controlled via lrda/ltda */
758 writel(0x00000001, ioaddr + GMODE);
759 /* Shared interrupt queue */
763 bits = (IRQ_RING_SIZE >> 5) - 1;
767 writel(bits, ioaddr + IQLENR0);
769 /* Global interrupt queue */
770 writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1);
771 priv->iqcfg = (u32 *) pci_alloc_consistent(pdev,
772 IRQ_RING_SIZE*sizeof(u32), &priv->iqcfg_dma);
774 goto err_out_free_irq;
775 writel(priv->iqcfg_dma, ioaddr + IQCFG);
778 * SCC 0-3 private rx/tx irq structures
779 * IQRX/TXi needs to be set soon. Learned it the hard way...
781 for (i = 0; i < dev_per_card; i++) {
782 dpriv = priv->root + i;
783 dpriv->iqtx = (u32 *) pci_alloc_consistent(pdev,
784 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma);
786 goto err_out_free_iqtx;
787 writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4);
789 for (i = 0; i < dev_per_card; i++) {
790 dpriv = priv->root + i;
791 dpriv->iqrx = (u32 *) pci_alloc_consistent(pdev,
792 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma);
794 goto err_out_free_iqrx;
795 writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4);
798 /* Cf application hint. Beware of hard-lock condition on threshold. */
799 writel(0x42104000, ioaddr + FIFOCR1);
800 //writel(0x9ce69800, ioaddr + FIFOCR2);
801 writel(0xdef6d800, ioaddr + FIFOCR2);
802 //writel(0x11111111, ioaddr + FIFOCR4);
803 writel(0x18181818, ioaddr + FIFOCR4);
804 // FIXME: should depend on the chipset revision
805 writel(0x0000000e, ioaddr + FIFOCR3);
807 writel(0xff200001, ioaddr + GCMDR);
814 dpriv = priv->root + i;
815 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
816 dpriv->iqrx, dpriv->iqrx_dma);
821 dpriv = priv->root + i;
822 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
823 dpriv->iqtx, dpriv->iqtx_dma);
825 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg,
828 free_irq(pdev->irq, priv->root);
832 iounmap ((void *)ioaddr);
833 err_out_free_mmio_region:
834 release_mem_region(pci_resource_start(pdev, 1),
835 pci_resource_len(pdev, 1));
836 err_out_free_mmio_region0:
837 release_mem_region(pci_resource_start(pdev, 0),
838 pci_resource_len(pdev, 0));
844 * Let's hope the default values are decent enough to protect my
845 * feet from the user's gun - Ueimor
847 static void dscc4_init_registers(struct dscc4_dev_priv *dpriv,
848 struct net_device *dev)
850 /* No interrupts, SCC core disabled. Let's relax */
851 scc_writel(0x00000000, dpriv, dev, CCR0);
853 scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);
856 * No address recognition/crc-CCITT/cts enabled
857 * Shared flags transmission disabled - cf errata DS5 p.11
858 * Carrier detect disabled - cf errata p.14
859 * FIXME: carrier detection/polarity may be handled more gracefully.
861 scc_writel(0x02408000, dpriv, dev, CCR1);
863 /* crc not forwarded - Cf errata DS5 p.11 */
864 scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);
866 //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2);
869 static int dscc4_found1(struct pci_dev *pdev, unsigned long ioaddr)
871 struct dscc4_pci_priv *ppriv;
872 struct dscc4_dev_priv *root;
873 int i, ret = -ENOMEM;
875 root = (struct dscc4_dev_priv *)
876 kmalloc(dev_per_card*sizeof(*root), GFP_KERNEL);
878 printk(KERN_ERR "%s: can't allocate data\n", DRV_NAME);
881 memset(root, 0, dev_per_card*sizeof(*root));
883 for (i = 0; i < dev_per_card; i++) {
884 root[i].dev = alloc_hdlcdev(root + i);
887 free_netdev(root[i].dev);
892 ppriv = (struct dscc4_pci_priv *) kmalloc(sizeof(*ppriv), GFP_KERNEL);
894 printk(KERN_ERR "%s: can't allocate private data\n", DRV_NAME);
897 memset(ppriv, 0, sizeof(struct dscc4_pci_priv));
898 ret = dscc4_set_quartz(root, quartz);
902 spin_lock_init(&ppriv->lock);
904 for (i = 0; i < dev_per_card; i++) {
905 struct dscc4_dev_priv *dpriv = root + i;
906 struct net_device *d = dscc4_to_dev(dpriv);
907 hdlc_device *hdlc = dev_to_hdlc(d);
909 d->base_addr = ioaddr;
912 d->open = dscc4_open;
913 d->stop = dscc4_close;
914 d->set_multicast_list = NULL;
915 d->do_ioctl = dscc4_ioctl;
916 d->tx_timeout = dscc4_tx_timeout;
917 d->watchdog_timeo = TX_TIMEOUT;
919 SET_NETDEV_DEV(d, &pdev->dev);
922 dpriv->pci_priv = ppriv;
923 spin_lock_init(&dpriv->lock);
925 hdlc->xmit = dscc4_start_xmit;
926 hdlc->attach = dscc4_hdlc_attach;
928 dscc4_init_registers(dpriv, d);
929 dpriv->parity = PARITY_CRC16_PR0_CCITT;
930 dpriv->encoding = ENCODING_NRZ;
932 ret = dscc4_init_ring(d);
936 ret = register_hdlc_device(d);
938 printk(KERN_ERR "%s: unable to register\n", DRV_NAME);
939 dscc4_release_ring(dpriv);
943 pci_set_drvdata(pdev, ppriv);
948 dscc4_release_ring(root + i);
949 unregister_hdlc_device(dscc4_to_dev(&root[i]));
954 for (i = 0; i < dev_per_card; i++)
955 free_netdev(root[i].dev);
962 /* FIXME: get rid of the unneeded code */
963 static void dscc4_timer(unsigned long data)
965 struct net_device *dev = (struct net_device *)data;
966 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
967 // struct dscc4_pci_priv *ppriv;
971 dpriv->timer.expires = jiffies + TX_TIMEOUT;
972 add_timer(&dpriv->timer);
975 static void dscc4_tx_timeout(struct net_device *dev)
977 /* FIXME: something is missing there */
980 static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv)
982 sync_serial_settings *settings = &dpriv->settings;
984 if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
985 struct net_device *dev = dscc4_to_dev(dpriv);
987 printk(KERN_INFO "%s: loopback requires clock\n", dev->name);
993 #ifdef CONFIG_DSCC4_PCI_RST
995 * Some DSCC4-based cards wires the GPIO port and the PCI #RST pin together
996 * so as to provide a safe way to reset the asic while not the whole machine
999 * This code doesn't need to be efficient. Keep It Simple
1001 static void dscc4_pci_reset(struct pci_dev *pdev, unsigned long ioaddr)
1006 for (i = 0; i < 16; i++)
1007 pci_read_config_dword(pdev, i << 2, dscc4_pci_config_store + i);
1009 /* Maximal LBI clock divider (who cares ?) and whole GPIO range. */
1010 writel(0x001c0000, ioaddr + GMODE);
1011 /* Configure GPIO port as output */
1012 writel(0x0000ffff, ioaddr + GPDIR);
1013 /* Disable interruption */
1014 writel(0x0000ffff, ioaddr + GPIM);
1016 writel(0x0000ffff, ioaddr + GPDATA);
1017 writel(0x00000000, ioaddr + GPDATA);
1019 /* Flush posted writes */
1020 readl(ioaddr + GSTAR);
1022 set_current_state(TASK_UNINTERRUPTIBLE);
1023 schedule_timeout(10);
1025 for (i = 0; i < 16; i++)
1026 pci_write_config_dword(pdev, i << 2, dscc4_pci_config_store[i]);
1030 #define dscc4_pci_reset(pdev,ioaddr) do {} while (0)
1031 #endif /* CONFIG_DSCC4_PCI_RST */
1033 static int dscc4_open(struct net_device *dev)
1035 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1036 struct dscc4_pci_priv *ppriv;
1039 if ((dscc4_loopback_check(dpriv) < 0) || !dev->hard_start_xmit)
1042 if ((ret = hdlc_open(dev)))
1045 ppriv = dpriv->pci_priv;
1048 * Due to various bugs, there is no way to reliably reset a
1049 * specific port (manufacturer's dependant special PCI #RST wiring
1050 * apart: it affects all ports). Thus the device goes in the best
1051 * silent mode possible at dscc4_close() time and simply claims to
1052 * be up if it's opened again. It still isn't possible to change
1053 * the HDLC configuration without rebooting but at least the ports
1054 * can be up/down ifconfig'ed without killing the host.
1056 if (dpriv->flags & FakeReset) {
1057 dpriv->flags &= ~FakeReset;
1058 scc_patchl(0, PowerUp, dpriv, dev, CCR0);
1059 scc_patchl(0, 0x00050000, dpriv, dev, CCR2);
1060 scc_writel(EventsMask, dpriv, dev, IMR);
1061 printk(KERN_INFO "%s: up again.\n", dev->name);
1065 /* IDT+IDR during XPR */
1066 dpriv->flags = NeedIDR | NeedIDT;
1068 scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0);
1071 * The following is a bit paranoid...
1073 * NB: the datasheet "...CEC will stay active if the SCC is in
1074 * power-down mode or..." and CCR2.RAC = 1 are two different
1077 if (scc_readl_star(dpriv, dev) & SccBusy) {
1078 printk(KERN_ERR "%s busy. Try later\n", dev->name);
1082 printk(KERN_INFO "%s: available. Good\n", dev->name);
1084 scc_writel(EventsMask, dpriv, dev, IMR);
1086 /* Posted write is flushed in the wait_ack loop */
1087 scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);
1089 if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0)
1090 goto err_disable_scc_events;
1093 * I would expect XPR near CE completion (before ? after ?).
1094 * At worst, this code won't see a late XPR and people
1095 * will have to re-issue an ifconfig (this is harmless).
1096 * WARNING, a really missing XPR usually means a hardware
1097 * reset is needed. Suggestions anyone ?
1099 if ((ret = dscc4_xpr_ack(dpriv)) < 0) {
1100 printk(KERN_ERR "%s: %s timeout\n", DRV_NAME, "XPR");
1101 goto err_disable_scc_events;
1105 dscc4_tx_print(dev, dpriv, "Open");
1108 netif_start_queue(dev);
1110 init_timer(&dpriv->timer);
1111 dpriv->timer.expires = jiffies + 10*HZ;
1112 dpriv->timer.data = (unsigned long)dev;
1113 dpriv->timer.function = &dscc4_timer;
1114 add_timer(&dpriv->timer);
1115 netif_carrier_on(dev);
1119 err_disable_scc_events:
1120 scc_writel(0xffffffff, dpriv, dev, IMR);
1121 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1128 #ifdef DSCC4_POLLING
1129 static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1131 /* FIXME: it's gonna be easy (TM), for sure */
1133 #endif /* DSCC4_POLLING */
1135 static int dscc4_start_xmit(struct sk_buff *skb, struct net_device *dev)
1137 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1138 struct dscc4_pci_priv *ppriv = dpriv->pci_priv;
1142 next = dpriv->tx_current%TX_RING_SIZE;
1143 dpriv->tx_skbuff[next] = skb;
1144 tx_fd = dpriv->tx_fd + next;
1145 tx_fd->state = FrameEnd | TO_STATE_TX(skb->len);
1146 tx_fd->data = pci_map_single(ppriv->pdev, skb->data, skb->len,
1148 tx_fd->complete = 0x00000000;
1149 tx_fd->jiffies = jiffies;
1152 #ifdef DSCC4_POLLING
1153 spin_lock(&dpriv->lock);
1154 while (dscc4_tx_poll(dpriv, dev));
1155 spin_unlock(&dpriv->lock);
1158 dev->trans_start = jiffies;
1161 dscc4_tx_print(dev, dpriv, "Xmit");
1162 /* To be cleaned(unsigned int)/optimized. Later, ok ? */
1163 if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE))
1164 netif_stop_queue(dev);
1166 if (dscc4_tx_quiescent(dpriv, dev))
1167 dscc4_do_tx(dpriv, dev);
1172 static int dscc4_close(struct net_device *dev)
1174 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1176 del_timer_sync(&dpriv->timer);
1177 netif_stop_queue(dev);
1179 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1180 scc_patchl(0x00050000, 0, dpriv, dev, CCR2);
1181 scc_writel(0xffffffff, dpriv, dev, IMR);
1183 dpriv->flags |= FakeReset;
1190 static inline int dscc4_check_clock_ability(int port)
1194 #ifdef CONFIG_DSCC4_PCISYNC
1202 * DS1 p.137: "There are a total of 13 different clocking modes..."
1205 * - by default, assume a clock is provided on pin RxClk/TxClk (clock mode 0a).
1206 * Clock mode 3b _should_ work but the testing seems to make this point
1207 * dubious (DIY testing requires setting CCR0 at 0x00000033).
1208 * This is supposed to provide least surprise "DTE like" behavior.
1209 * - if line rate is specified, clocks are assumed to be locally generated.
1210 * A quartz must be available (on pin XTAL1). Modes 6b/7b are used. Choosing
1211 * between these it automagically done according on the required frequency
1212 * scaling. Of course some rounding may take place.
1213 * - no high speed mode (40Mb/s). May be trivial to do but I don't have an
1214 * appropriate external clocking device for testing.
1215 * - no time-slot/clock mode 5: shameless lazyness.
1217 * The clock signals wiring can be (is ?) manufacturer dependant. Good luck.
1219 * BIG FAT WARNING: if the device isn't provided enough clocking signal, it
1220 * won't pass the init sequence. For example, straight back-to-back DTE without
1221 * external clock will fail when dscc4_open() (<- 'ifconfig hdlcx xxx') is
1224 * Typos lurk in datasheet (missing divier in clock mode 7a figure 51 p.153
1227 * Clock mode related bits of CCR0:
1228 * +------------ TOE: output TxClk (0b/2b/3a/3b/6b/7a/7b only)
1229 * | +---------- SSEL: sub-mode select 0 -> a, 1 -> b
1230 * | | +-------- High Speed: say 0
1231 * | | | +-+-+-- Clock Mode: 0..7
1234 * x|x|5|4|3|2|1|0| lower bits
1236 * Division factor of BRR: k = (N+1)x2^M (total divider = 16xk in mode 6b)
1237 * +-+-+-+------------------ M (0..15)
1238 * | | | | +-+-+-+-+-+-- N (0..63)
1239 * 0 0 0 0 | | | | 0 0 | | | | | |
1240 * ...-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1241 * f|e|d|c|b|a|9|8|7|6|5|4|3|2|1|0| lower bits
1244 static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
1246 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1250 *state &= ~Ccr0ClockMask;
1251 if (*bps) { /* Clock generated - required for DCE */
1252 u32 n = 0, m = 0, divider;
1255 xtal = dpriv->pci_priv->xtal_hz;
1258 if (dscc4_check_clock_ability(dpriv->dev_id) < 0)
1260 divider = xtal / *bps;
1261 if (divider > BRR_DIVIDER_MAX) {
1263 *state |= 0x00000036; /* Clock mode 6b (BRG/16) */
1265 *state |= 0x00000037; /* Clock mode 7b (BRG) */
1266 if (divider >> 22) {
1269 } else if (divider) {
1270 /* Extraction of the 6 highest weighted bits */
1272 while (0xffffffc0 & divider) {
1280 if (!(*state & 0x00000001)) /* ?b mode mask => clock mode 6b */
1282 *bps = xtal / divider;
1285 * External clock - DTE
1286 * "state" already reflects Clock mode 0a (CCR0 = 0xzzzzzz00).
1287 * Nothing more to be done
1291 scc_writel(brr, dpriv, dev, BRR);
1297 static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1299 sync_serial_settings *line = ifr->ifr_settings.ifs_ifsu.sync;
1300 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1301 const size_t size = sizeof(dpriv->settings);
1304 if (dev->flags & IFF_UP)
1307 if (cmd != SIOCWANDEV)
1310 switch(ifr->ifr_settings.type) {
1312 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1313 if (ifr->ifr_settings.size < size) {
1314 ifr->ifr_settings.size = size; /* data size wanted */
1317 if (copy_to_user(line, &dpriv->settings, size))
1321 case IF_IFACE_SYNC_SERIAL:
1322 if (!capable(CAP_NET_ADMIN))
1325 if (dpriv->flags & FakeReset) {
1326 printk(KERN_INFO "%s: please reset the device"
1327 " before this command\n", dev->name);
1330 if (copy_from_user(&dpriv->settings, line, size))
1332 ret = dscc4_set_iface(dpriv, dev);
1336 ret = hdlc_ioctl(dev, ifr, cmd);
1343 static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz)
1347 if ((hz < 0) || (hz > DSCC4_HZ_MAX))
1350 dpriv->pci_priv->xtal_hz = hz;
1355 static int dscc4_match(struct thingie *p, int value)
1359 for (i = 0; p[i].define != -1; i++) {
1360 if (value == p[i].define)
1363 if (p[i].define == -1)
1369 static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv,
1370 struct net_device *dev)
1372 sync_serial_settings *settings = &dpriv->settings;
1373 int ret = -EOPNOTSUPP;
1376 bps = settings->clock_rate;
1377 state = scc_readl(dpriv, CCR0);
1378 if (dscc4_set_clock(dev, &bps, &state) < 0)
1380 if (bps) { /* DCE */
1381 printk(KERN_DEBUG "%s: generated RxClk (DCE)\n", dev->name);
1382 if (settings->clock_rate != bps) {
1383 printk(KERN_DEBUG "%s: clock adjusted (%08d -> %08d)\n",
1384 dev->name, settings->clock_rate, bps);
1385 settings->clock_rate = bps;
1388 state |= PowerUp | Vis;
1389 printk(KERN_DEBUG "%s: external RxClk (DTE)\n", dev->name);
1391 scc_writel(state, dpriv, dev, CCR0);
1397 static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv,
1398 struct net_device *dev)
1400 struct thingie encoding[] = {
1401 { ENCODING_NRZ, 0x00000000 },
1402 { ENCODING_NRZI, 0x00200000 },
1403 { ENCODING_FM_MARK, 0x00400000 },
1404 { ENCODING_FM_SPACE, 0x00500000 },
1405 { ENCODING_MANCHESTER, 0x00600000 },
1410 i = dscc4_match(encoding, dpriv->encoding);
1412 scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0);
1418 static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv,
1419 struct net_device *dev)
1421 sync_serial_settings *settings = &dpriv->settings;
1424 state = scc_readl(dpriv, CCR1);
1425 if (settings->loopback) {
1426 printk(KERN_DEBUG "%s: loopback\n", dev->name);
1427 state |= 0x00000100;
1429 printk(KERN_DEBUG "%s: normal\n", dev->name);
1430 state &= ~0x00000100;
1432 scc_writel(state, dpriv, dev, CCR1);
1436 static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv,
1437 struct net_device *dev)
1439 struct thingie crc[] = {
1440 { PARITY_CRC16_PR0_CCITT, 0x00000010 },
1441 { PARITY_CRC16_PR1_CCITT, 0x00000000 },
1442 { PARITY_CRC32_PR0_CCITT, 0x00000011 },
1443 { PARITY_CRC32_PR1_CCITT, 0x00000001 }
1447 i = dscc4_match(crc, dpriv->parity);
1449 scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1);
1455 static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1458 int (*action)(struct dscc4_dev_priv *, struct net_device *);
1459 } *p, do_setting[] = {
1460 { dscc4_encoding_setting },
1461 { dscc4_clock_setting },
1462 { dscc4_loopback_setting },
1463 { dscc4_crc_setting },
1468 for (p = do_setting; p->action; p++) {
1469 if ((ret = p->action(dpriv, dev)) < 0)
1475 static irqreturn_t dscc4_irq(int irq, void *token, struct pt_regs *ptregs)
1477 struct dscc4_dev_priv *root = token;
1478 struct dscc4_pci_priv *priv;
1479 struct net_device *dev;
1480 unsigned long ioaddr;
1482 unsigned long flags;
1485 priv = root->pci_priv;
1486 dev = dscc4_to_dev(root);
1488 spin_lock_irqsave(&priv->lock, flags);
1490 ioaddr = dev->base_addr;
1492 state = readl(ioaddr + GSTAR);
1498 printk(KERN_DEBUG "%s: GSTAR = 0x%08x\n", DRV_NAME, state);
1499 writel(state, ioaddr + GSTAR);
1502 printk(KERN_ERR "%s: failure (Arf). Harass the maintener\n",
1509 printk(KERN_DEBUG "%s: CfgIV\n", DRV_NAME);
1510 if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & Arf)
1511 printk(KERN_ERR "%s: %s failed\n", dev->name, "CFG");
1512 if (!(state &= ~Cfg))
1515 if (state & RxEvt) {
1516 i = dev_per_card - 1;
1518 dscc4_rx_irq(priv, root + i);
1522 if (state & TxEvt) {
1523 i = dev_per_card - 1;
1525 dscc4_tx_irq(priv, root + i);
1530 spin_unlock_irqrestore(&priv->lock, flags);
1531 return IRQ_RETVAL(handled);
1534 static inline void dscc4_tx_irq(struct dscc4_pci_priv *ppriv,
1535 struct dscc4_dev_priv *dpriv)
1537 struct net_device *dev = dscc4_to_dev(dpriv);
1542 cur = dpriv->iqtx_current%IRQ_RING_SIZE;
1543 state = dpriv->iqtx[cur];
1546 printk(KERN_DEBUG "%s: Tx ISR = 0x%08x\n", dev->name,
1548 if ((debug > 1) && (loop > 1))
1549 printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop);
1550 if (loop && netif_queue_stopped(dev))
1551 if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)
1552 netif_wake_queue(dev);
1554 if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) &&
1555 !dscc4_tx_done(dpriv))
1556 dscc4_do_tx(dpriv, dev);
1560 dpriv->iqtx[cur] = 0;
1561 dpriv->iqtx_current++;
1563 if (state_check(state, dpriv, dev, "Tx") < 0)
1566 if (state & SccEvt) {
1568 struct net_device_stats *stats = hdlc_stats(dev);
1569 struct sk_buff *skb;
1573 dscc4_tx_print(dev, dpriv, "Alls");
1575 * DataComplete can't be trusted for Tx completion.
1578 cur = dpriv->tx_dirty%TX_RING_SIZE;
1579 tx_fd = dpriv->tx_fd + cur;
1580 skb = dpriv->tx_skbuff[cur];
1582 pci_unmap_single(ppriv->pdev, tx_fd->data,
1583 skb->len, PCI_DMA_TODEVICE);
1584 if (tx_fd->state & FrameEnd) {
1585 stats->tx_packets++;
1586 stats->tx_bytes += skb->len;
1588 dev_kfree_skb_irq(skb);
1589 dpriv->tx_skbuff[cur] = NULL;
1593 printk(KERN_ERR "%s Tx: NULL skb %d\n",
1597 * If the driver ends sending crap on the wire, it
1598 * will be way easier to diagnose than the (not so)
1599 * random freeze induced by null sized tx frames.
1601 tx_fd->data = tx_fd->next;
1602 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1603 tx_fd->complete = 0x00000000;
1606 if (!(state &= ~Alls))
1610 * Transmit Data Underrun
1613 printk(KERN_ERR "%s: XDU. Ask maintainer\n", DRV_NAME);
1614 dpriv->flags = NeedIDT;
1617 dev->base_addr + 0x0c*dpriv->dev_id + CH0CFG);
1618 writel(Action, dev->base_addr + GCMDR);
1622 printk(KERN_INFO "%s: CTS transition\n", dev->name);
1623 if (!(state &= ~Cts)) /* DEBUG */
1627 /* Frame needs to be sent again - FIXME */
1628 printk(KERN_ERR "%s: Xmr. Ask maintainer\n", DRV_NAME);
1629 if (!(state &= ~Xmr)) /* DEBUG */
1633 unsigned long scc_addr, ring;
1637 * - the busy condition happens (sometimes);
1638 * - it doesn't seem to make the handler unreliable.
1640 for (i = 1; i; i <<= 1) {
1641 if (!(scc_readl_star(dpriv, dev) & SccBusy))
1645 printk(KERN_INFO "%s busy in irq\n", dev->name);
1647 scc_addr = dev->base_addr + 0x0c*dpriv->dev_id;
1648 /* Keep this order: IDT before IDR */
1649 if (dpriv->flags & NeedIDT) {
1651 dscc4_tx_print(dev, dpriv, "Xpr");
1652 ring = dpriv->tx_fd_dma +
1653 (dpriv->tx_dirty%TX_RING_SIZE)*
1654 sizeof(struct TxFD);
1655 writel(ring, scc_addr + CH0BTDA);
1656 dscc4_do_tx(dpriv, dev);
1657 writel(MTFi | Idt, scc_addr + CH0CFG);
1658 if (dscc4_do_action(dev, "IDT") < 0)
1660 dpriv->flags &= ~NeedIDT;
1662 if (dpriv->flags & NeedIDR) {
1663 ring = dpriv->rx_fd_dma +
1664 (dpriv->rx_current%RX_RING_SIZE)*
1665 sizeof(struct RxFD);
1666 writel(ring, scc_addr + CH0BRDA);
1667 dscc4_rx_update(dpriv, dev);
1668 writel(MTFi | Idr, scc_addr + CH0CFG);
1669 if (dscc4_do_action(dev, "IDR") < 0)
1671 dpriv->flags &= ~NeedIDR;
1673 /* Activate receiver and misc */
1674 scc_writel(0x08050008, dpriv, dev, CCR2);
1677 if (!(state &= ~Xpr))
1682 printk(KERN_INFO "%s: CD transition\n", dev->name);
1683 if (!(state &= ~Cd)) /* DEBUG */
1686 } else { /* ! SccEvt */
1688 #ifdef DSCC4_POLLING
1689 while (!dscc4_tx_poll(dpriv, dev));
1691 printk(KERN_INFO "%s: Tx Hi\n", dev->name);
1695 printk(KERN_INFO "%s: Tx ERR\n", dev->name);
1696 hdlc_stats(dev)->tx_errors++;
1703 static inline void dscc4_rx_irq(struct dscc4_pci_priv *priv,
1704 struct dscc4_dev_priv *dpriv)
1706 struct net_device *dev = dscc4_to_dev(dpriv);
1711 cur = dpriv->iqrx_current%IRQ_RING_SIZE;
1712 state = dpriv->iqrx[cur];
1715 dpriv->iqrx[cur] = 0;
1716 dpriv->iqrx_current++;
1718 if (state_check(state, dpriv, dev, "Rx") < 0)
1721 if (!(state & SccEvt)){
1725 printk(KERN_DEBUG "%s: Rx ISR = 0x%08x\n", dev->name,
1727 state &= 0x00ffffff;
1728 if (state & Err) { /* Hold or reset */
1729 printk(KERN_DEBUG "%s: Rx ERR\n", dev->name);
1730 cur = dpriv->rx_current%RX_RING_SIZE;
1731 rx_fd = dpriv->rx_fd + cur;
1733 * Presume we're not facing a DMAC receiver reset.
1734 * As We use the rx size-filtering feature of the
1735 * DSCC4, the beginning of a new frame is waiting in
1736 * the rx fifo. I bet a Receive Data Overflow will
1737 * happen most of time but let's try and avoid it.
1738 * Btw (as for RDO) if one experiences ERR whereas
1739 * the system looks rather idle, there may be a
1740 * problem with latency. In this case, increasing
1741 * RX_RING_SIZE may help.
1743 //while (dpriv->rx_needs_refill) {
1744 while (!(rx_fd->state1 & Hold)) {
1747 if (!(cur = cur%RX_RING_SIZE))
1748 rx_fd = dpriv->rx_fd;
1750 //dpriv->rx_needs_refill--;
1751 try_get_rx_skb(dpriv, dev);
1754 rx_fd->state1 &= ~Hold;
1755 rx_fd->state2 = 0x00000000;
1756 rx_fd->end = 0xbabeface;
1761 dscc4_rx_skb(dpriv, dev);
1764 if (state & Hi ) { /* HI bit */
1765 printk(KERN_INFO "%s: Rx Hi\n", dev->name);
1769 } else { /* SccEvt */
1771 //FIXME: verifier la presence de tous les evenements
1774 const char *irq_name;
1776 { 0x00008000, "TIN"},
1777 { 0x00000020, "RSC"},
1778 { 0x00000010, "PCE"},
1779 { 0x00000008, "PLLA"},
1783 for (evt = evts; evt->irq_name; evt++) {
1784 if (state & evt->mask) {
1785 printk(KERN_DEBUG "%s: %s\n",
1786 dev->name, evt->irq_name);
1787 if (!(state &= ~evt->mask))
1792 if (!(state &= ~0x0000c03c))
1796 printk(KERN_INFO "%s: CTS transition\n", dev->name);
1797 if (!(state &= ~Cts)) /* DEBUG */
1801 * Receive Data Overflow (FIXME: fscked)
1809 // dscc4_rx_dump(dpriv);
1810 scc_addr = dev->base_addr + 0x0c*dpriv->dev_id;
1812 scc_patchl(RxActivate, 0, dpriv, dev, CCR2);
1814 * This has no effect. Why ?
1815 * ORed with TxSccRes, one sees the CFG ack (for
1816 * the TX part only).
1818 scc_writel(RxSccRes, dpriv, dev, CMDR);
1819 dpriv->flags |= RdoSet;
1822 * Let's try and save something in the received data.
1823 * rx_current must be incremented at least once to
1824 * avoid HOLD in the BRDA-to-be-pointed desc.
1827 cur = dpriv->rx_current++%RX_RING_SIZE;
1828 rx_fd = dpriv->rx_fd + cur;
1829 if (!(rx_fd->state2 & DataComplete))
1831 if (rx_fd->state2 & FrameAborted) {
1832 hdlc_stats(dev)->rx_over_errors++;
1833 rx_fd->state1 |= Hold;
1834 rx_fd->state2 = 0x00000000;
1835 rx_fd->end = 0xbabeface;
1837 dscc4_rx_skb(dpriv, dev);
1841 if (dpriv->flags & RdoSet)
1843 "%s: no RDO in Rx data\n", DRV_NAME);
1845 #ifdef DSCC4_RDO_EXPERIMENTAL_RECOVERY
1847 * FIXME: must the reset be this violent ?
1849 #warning "FIXME: CH0BRDA"
1850 writel(dpriv->rx_fd_dma +
1851 (dpriv->rx_current%RX_RING_SIZE)*
1852 sizeof(struct RxFD), scc_addr + CH0BRDA);
1853 writel(MTFi|Rdr|Idr, scc_addr + CH0CFG);
1854 if (dscc4_do_action(dev, "RDR") < 0) {
1855 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1859 writel(MTFi|Idr, scc_addr + CH0CFG);
1860 if (dscc4_do_action(dev, "IDR") < 0) {
1861 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1867 scc_patchl(0, RxActivate, dpriv, dev, CCR2);
1871 printk(KERN_INFO "%s: CD transition\n", dev->name);
1872 if (!(state &= ~Cd)) /* DEBUG */
1876 printk(KERN_DEBUG "%s: Flex. Ttttt...\n", DRV_NAME);
1877 if (!(state &= ~Flex))
1884 * I had expected the following to work for the first descriptor
1885 * (tx_fd->state = 0xc0000000)
1886 * - Hold=1 (don't try and branch to the next descripto);
1887 * - No=0 (I want an empty data section, i.e. size=0);
1888 * - Fe=1 (required by No=0 or we got an Err irq and must reset).
1889 * It failed and locked solid. Thus the introduction of a dummy skb.
1890 * Problem is acknowledged in errata sheet DS5. Joy :o/
1892 struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv)
1894 struct sk_buff *skb;
1896 skb = dev_alloc_skb(DUMMY_SKB_SIZE);
1898 int last = dpriv->tx_dirty%TX_RING_SIZE;
1899 struct TxFD *tx_fd = dpriv->tx_fd + last;
1901 skb->len = DUMMY_SKB_SIZE;
1902 memcpy(skb->data, version, strlen(version)%DUMMY_SKB_SIZE);
1903 tx_fd->state = FrameEnd | TO_STATE_TX(DUMMY_SKB_SIZE);
1904 tx_fd->data = pci_map_single(dpriv->pci_priv->pdev, skb->data,
1905 DUMMY_SKB_SIZE, PCI_DMA_TODEVICE);
1906 dpriv->tx_skbuff[last] = skb;
1911 static int dscc4_init_ring(struct net_device *dev)
1913 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1914 struct pci_dev *pdev = dpriv->pci_priv->pdev;
1920 ring = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &dpriv->rx_fd_dma);
1923 dpriv->rx_fd = rx_fd = (struct RxFD *) ring;
1925 ring = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &dpriv->tx_fd_dma);
1927 goto err_free_dma_rx;
1928 dpriv->tx_fd = tx_fd = (struct TxFD *) ring;
1930 memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE);
1931 dpriv->tx_dirty = 0xffffffff;
1932 i = dpriv->tx_current = 0;
1934 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1935 tx_fd->complete = 0x00000000;
1936 /* FIXME: NULL should be ok - to be tried */
1937 tx_fd->data = dpriv->tx_fd_dma;
1938 (tx_fd++)->next = (u32)(dpriv->tx_fd_dma +
1939 (++i%TX_RING_SIZE)*sizeof(*tx_fd));
1940 } while (i < TX_RING_SIZE);
1942 if (dscc4_init_dummy_skb(dpriv) < 0)
1943 goto err_free_dma_tx;
1945 memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE);
1946 i = dpriv->rx_dirty = dpriv->rx_current = 0;
1948 /* size set by the host. Multiple of 4 bytes please */
1949 rx_fd->state1 = HiDesc;
1950 rx_fd->state2 = 0x00000000;
1951 rx_fd->end = 0xbabeface;
1952 rx_fd->state1 |= TO_STATE_RX(HDLC_MAX_MRU);
1953 // FIXME: return value verifiee mais traitement suspect
1954 if (try_get_rx_skb(dpriv, dev) >= 0)
1956 (rx_fd++)->next = (u32)(dpriv->rx_fd_dma +
1957 (++i%RX_RING_SIZE)*sizeof(*rx_fd));
1958 } while (i < RX_RING_SIZE);
1963 pci_free_consistent(pdev, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma);
1965 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
1970 static void __devexit dscc4_remove_one(struct pci_dev *pdev)
1972 struct dscc4_pci_priv *ppriv;
1973 struct dscc4_dev_priv *root;
1974 unsigned long ioaddr;
1977 ppriv = pci_get_drvdata(pdev);
1980 ioaddr = dscc4_to_dev(root)->base_addr;
1982 dscc4_pci_reset(pdev, ioaddr);
1984 free_irq(pdev->irq, root);
1985 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), ppriv->iqcfg,
1987 for (i = 0; i < dev_per_card; i++) {
1988 struct dscc4_dev_priv *dpriv = root + i;
1990 dscc4_release_ring(dpriv);
1991 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1992 dpriv->iqrx, dpriv->iqrx_dma);
1993 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1994 dpriv->iqtx, dpriv->iqtx_dma);
1999 iounmap((void *)ioaddr);
2001 release_mem_region(pci_resource_start(pdev, 1),
2002 pci_resource_len(pdev, 1));
2003 release_mem_region(pci_resource_start(pdev, 0),
2004 pci_resource_len(pdev, 0));
2007 static int dscc4_hdlc_attach(struct net_device *dev, unsigned short encoding,
2008 unsigned short parity)
2010 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
2012 if (encoding != ENCODING_NRZ &&
2013 encoding != ENCODING_NRZI &&
2014 encoding != ENCODING_FM_MARK &&
2015 encoding != ENCODING_FM_SPACE &&
2016 encoding != ENCODING_MANCHESTER)
2019 if (parity != PARITY_NONE &&
2020 parity != PARITY_CRC16_PR0_CCITT &&
2021 parity != PARITY_CRC16_PR1_CCITT &&
2022 parity != PARITY_CRC32_PR0_CCITT &&
2023 parity != PARITY_CRC32_PR1_CCITT)
2026 dpriv->encoding = encoding;
2027 dpriv->parity = parity;
2032 static int __init dscc4_setup(char *str)
2034 int *args[] = { &debug, &quartz, NULL }, **p = args;
2036 while (*p && (get_option(&str, *p) == 2))
2041 __setup("dscc4.setup=", dscc4_setup);
2044 static struct pci_device_id dscc4_pci_tbl[] = {
2045 { PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4,
2046 PCI_ANY_ID, PCI_ANY_ID, },
2049 MODULE_DEVICE_TABLE(pci, dscc4_pci_tbl);
2051 static struct pci_driver dscc4_driver = {
2053 .id_table = dscc4_pci_tbl,
2054 .probe = dscc4_init_one,
2055 .remove = __devexit_p(dscc4_remove_one),
2058 static int __init dscc4_init_module(void)
2060 return pci_module_init(&dscc4_driver);
2063 static void __exit dscc4_cleanup_module(void)
2065 pci_unregister_driver(&dscc4_driver);
2068 module_init(dscc4_init_module);
2069 module_exit(dscc4_cleanup_module);