2 * Defines for comx-hw-slicecom.c - FALC-LH specific
4 * Author: Bartok Istvan <bartoki@itc.hu>
5 * Last modified: Mon Feb 7 20:00:38 CET 2000
11 * Control register offsets on the LBI (page 90)
18 #define IMR0 0x14 /* Interrupt Mask Register 0 */
24 #define FMR0 0x1a /* Framer Mode Register 0 */
37 #define IDLE 0x29 /* Idle Code */
45 * Status registers on the LBI (page 134)
46 * these are read-only, use it like:
47 * if( lbi[ FRS0 ] ) ...
50 #define FRS0 0x4c /* Framer Receive Status register 0 */
51 #define FRS1 0x4d /* Framer Receive Status register 1 */
52 #define FECL 0x50 /* Framing Error Counter low byte */ /* Counts FAS word receive errors */
53 #define FECH 0x51 /* high byte */
54 #define CVCL 0x52 /* Code Violation Counter low byte */ /* Counts bipolar and HDB3 code violations */
55 #define CVCH 0x53 /* high byte */
56 #define CEC1L 0x54 /* CRC4 Error Counter 1 low byte */ /* Counts CRC4 errors in the incoming stream */
57 #define CEC1H 0x55 /* high byte */
58 #define EBCL 0x56 /* E Bit error Counter low byte */ /* E-bits: the remote end sends them, when */
59 #define EBCH 0x57 /* high byte */ /* it detected a CRC4-error */
60 #define ISR0 0x68 /* Interrupt Status Register 0 */
61 #define ISR1 0x69 /* Interrupt Status Register 1 */
62 #define ISR2 0x6a /* Interrupt Status Register 2 */
63 #define ISR3 0x6b /* Interrupt Status Register 3 */
64 #define ISR5 0x6c /* Interrupt Status Register 5 */
65 #define GIS 0x6e /* Global Interrupt Status Register */
66 #define VSTR 0x6f /* version information */
72 #define FRS0_LOS (1 << 7)
73 #define FRS0_AIS (1 << 6)
74 #define FRS0_LFA (1 << 5)
75 #define FRS0_RRA (1 << 4)
76 #define FRS0_AUXP (1 << 3)
77 #define FRS0_NMF (1 << 2)
78 #define FRS0_LMFA (1 << 1)
80 #define FRS1_XLS (1 << 1)
83 #define ISR2_FAR (1 << 7)
84 #define ISR2_LFA (1 << 6)
85 #define ISR2_MFAR (1 << 5)
86 #define ISR2_T400MS (1 << 4)
87 #define ISR2_AIS (1 << 3)
88 #define ISR2_LOS (1 << 2)
89 #define ISR2_RAR (1 << 1)
92 #define ISR3_ES (1 << 7)
93 #define ISR3_SEC (1 << 6)
94 #define ISR3_LMFA16 (1 << 5)
95 #define ISR3_AIS16 (1 << 4)
96 #define ISR3_RA16 (1 << 3)
97 #define ISR3_API (1 << 2)
98 #define ISR3_RSN (1 << 1)
101 #define ISR5_XSP (1 << 7)
102 #define ISR5_XSN (1 << 6)