2 * Defines for comx-hw-slicecom.c - MUNICH32X specific
4 * Author: Bartok Istvan <bartoki@itc.hu>
5 * Last modified: Tue Jan 11 14:27:36 CET 2000
10 #define TXBUFFER_SIZE 1536 /* Max mennyit tud a kartya hardver atvenni */
11 #define RXBUFFER_SIZE (TXBUFFER_SIZE+4) /* For Rx reasons it must be a multiple of 4, and =>4 (page 265) */
12 /* +4 .. see page 265, bit FE */
13 /* TOD: a MODE1-be nem is ezt teszem, hanem a TXBUFFER-t, lehet hogy nem is kell? */
15 //#define PCI_VENDOR_ID_SIEMENS 0x110a
16 #define PCI_DEVICE_ID_SIEMENS_MUNICH32X 0x2101
19 * PCI config space registers (page 120)
22 #define MUNICH_PCI_PCIRES 0x4c /* 0xe0000 resets the chip */
26 * MUNICH slave register offsets relative to base_address[0] (PCI BAR1) (page 181):
27 * offsets are in bytes, registers are u32's, so we need a >>2 for indexing
28 * the int[] by byte offsets. Use it like:
30 * bar1[ STAT ] = ~0L; or
34 #define CONF (0x00 >> 2)
35 #define CMD (0x04 >> 2)
36 #define STAT (0x08 >> 2)
37 #define STACK (0x08 >> 2)
38 #define IMASK (0x0c >> 2)
39 #define PIQBA (0x14 >> 2)
40 #define PIQL (0x18 >> 2)
41 #define MODE1 (0x20 >> 2)
42 #define MODE2 (0x24 >> 2)
43 #define CCBA (0x28 >> 2)
44 #define TXPOLL (0x2c >> 2)
45 #define TIQBA (0x30 >> 2)
46 #define TIQL (0x34 >> 2)
47 #define RIQBA (0x38 >> 2)
48 #define RIQL (0x3c >> 2)
49 #define LCONF (0x40 >> 2) /* LBI Configuration Register */
50 #define LCCBA (0x44 >> 2) /* LBI Configuration Control Block */ /* DE: lehet hogy nem is kell? */
51 #define LTIQBA (0x50 >> 2) /* DE: lehet hogy nem is kell? page 210: LBI DMA Controller intq - nem hasznalunk DMA-t.. */
52 #define LTIQL (0x54 >> 2) /* DE: lehet hogy nem is kell? */
53 #define LRIQBA (0x58 >> 2) /* DE: lehet hogy nem is kell? */
54 #define LRIQL (0x5c >> 2) /* DE: lehet hogy nem is kell? */
55 #define LREG0 (0x60 >> 2) /* LBI Indirect External Configuration register 0 */
56 #define LREG1 (0x64 >> 2)
57 #define LREG2 (0x68 >> 2)
58 #define LREG3 (0x6c >> 2)
59 #define LREG4 (0x70 >> 2)
60 #define LREG5 (0x74 >> 2)
61 #define LREG6 (0x78 >> 2) /* LBI Indirect External Configuration register 6 */
62 #define LSTAT (0x7c >> 2) /* LBI Status Register */
63 #define GPDIR (0x80 >> 2) /* General Purpose Bus DIRection - 0..input, 1..output */
64 #define GPDATA (0x84 >> 2) /* General Purpose Bus DATA */
68 * MUNICH commands: (they go into register CMD)
71 #define CMD_ARPCM 0x01 /* Action Request Serial PCM Core */
72 #define CMD_ARLBI 0x02 /* Action Request LBI */
76 * MUNICH event bits in the STAT, STACK, IMASK registers (page 188,189)
79 #define STAT_PTI (1 << 15)
80 #define STAT_PRI (1 << 14)
81 #define STAT_LTI (1 << 13)
82 #define STAT_LRI (1 << 12)
83 #define STAT_IOMI (1 << 11)
84 #define STAT_SSCI (1 << 10)
85 #define STAT_LBII (1 << 9)
86 #define STAT_MBI (1 << 8)
88 #define STAT_TI (1 << 6)
89 #define STAT_TSPA (1 << 5)
90 #define STAT_RSPA (1 << 4)
91 #define STAT_LBIF (1 << 3)
92 #define STAT_LBIA (1 << 2)
93 #define STAT_PCMF (1 << 1)
97 * We do not handle these (and do not touch their STAT bits) in the interrupt loop
100 #define STAT_NOT_HANDLED_BY_INTERRUPT (STAT_PCMF | STAT_PCMA)
104 * MUNICH MODE1/MODE2 slave register fields (page 193,196)
105 * these are not all masks, MODE1_XX_YY are my magic values!
108 #define MODE1_PCM_E1 (1 << 31) /* E1, 2.048 Mbit/sec */
109 #define MODE1_TBS_4 (1 << 24) /* TBS = 4 .. no Tx bit shift */
110 #define MODE1_RBS_4 (1 << 18) /* RBS = 4 .. no Rx bit shift */
111 #define MODE1_REN (1 << 15) /* Rx Enable */
112 #define MODE1_MFL_MY TXBUFFER_SIZE /* Maximum Frame Length */
113 #define MODE1_MAGIC (MODE1_PCM_E1 | MODE1_TBS_4 | MODE1_RBS_4 | MODE1_REN | MODE1_MFL_MY)
115 #define MODE2_HPOLL (1 << 8) /* Hold Poll */
116 #define MODE2_SPOLL (1 << 7) /* Slow Poll */
117 #define MODE2_TSF (1) /* real magic - discovered by probing :) */
118 // #define MODE2_MAGIC (MODE2_TSF)
119 #define MODE2_MAGIC (MODE2_SPOLL | MODE2_TSF)
123 * LCONF bits (page 205)
124 * these are not all masks, LCONF_XX_YY are my magic values!
127 #define LCONF_IPA (1 << 31) /* Interrupt Pass. Use 1 for FALC54 */
128 #define LCONF_DCA (1 << 30) /* Disregard the int's for Channel A - DMSM does not try to handle them */
129 #define LCONF_DCB (1 << 29) /* Disregard the int's for Channel B */
130 #define LCONF_EBCRES (1 << 22) /* Reset LBI External Bus Controller, 0..reset, 1..normal operation */
131 #define LCONF_LBIRES (1 << 21) /* Reset LBI DMSM, 0..reset, 1..normal operation */
132 #define LCONF_BTYP_16DEMUX (1 << 7) /* 16-bit demultiplexed bus */
133 #define LCONF_ABM (1 << 4) /* Arbitration Master */
135 /* writing LCONF_MAGIC1 followed by a LCONF_MAGIC2 into LCONF resets the EBC and DMSM: */
137 #define LCONF_MAGIC1 (LCONF_BTYP_16DEMUX | LCONF_ABM | LCONF_IPA | LCONF_DCA | LCONF_DCB)
138 #define LCONF_MAGIC2 (LCONF_MAGIC1 | LCONF_EBCRES | LCONF_LBIRES)
142 * LREGx magic values if a FALC54 is on the LBI (page 217)
145 #define LREG0_MAGIC 0x00000264
146 #define LREG1_MAGIC 0x6e6a6b66
147 #define LREG2_MAGIC 0x00000264
148 #define LREG3_MAGIC 0x6e686966
149 #define LREG4_MAGIC 0x00000000
150 #define LREG5_MAGIC ( (7<<27) | (3<<24) | (1<<21) | (7<<3) | (2<<9) )
154 * PCM Action Specification fields (munich_ccb_t.action_spec)
157 #define CCB_ACTIONSPEC_IN (1 << 15) /* init */
158 #define CCB_ACTIONSPEC_ICO (1 << 14) /* init only this channel */
159 #define CCB_ACTIONSPEC_RES (1 << 6) /* reset all channels */
160 #define CCB_ACTIONSPEC_LOC (1 << 5)
161 #define CCB_ACTIONSPEC_LOOP (1 << 4)
162 #define CCB_ACTIONSPEC_LOOPI (1 << 3)
163 #define CCB_ACTIONSPEC_IA (1 << 2)
167 * Interrupt Information bits in the TIQ, RIQ
170 #define PCM_INT_HI (1 << 12)
171 #define PCM_INT_FI (1 << 11)
172 #define PCM_INT_IFC (1 << 10)
173 #define PCM_INT_SF (1 << 9)
174 #define PCM_INT_ERR (1 << 8)
175 #define PCM_INT_FO (1 << 7)
176 #define PCM_INT_FE2 (1 << 6)
178 #define PCM_INT_CHANNEL( info ) (info & 0x1F)
182 * Rx status info in the rx_desc_t.status
185 #define RX_STATUS_SF (1 << 6)
186 #define RX_STATUS_LOSS (1 << 5)
187 #define RX_STATUS_CRCO (1 << 4)
188 #define RX_STATUS_NOB (1 << 3)
189 #define RX_STATUS_LFD (1 << 2)
190 #define RX_STATUS_RA (1 << 1)
191 #define RX_STATUS_ROF 1