2 * Goramo PCI200SYN synchronous serial card driver for Linux
4 * Copyright (C) 2002-2003 Krzysztof Halasa <khc@pm.waw.pl>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
10 * For information see http://hq.pm.waw.pl/hdlc/
12 * Sources of information:
13 * Hitachi HD64572 SCA-II User's Manual
14 * PLX Technology Inc. PCI9052 Data Book
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/sched.h>
21 #include <linux/types.h>
22 #include <linux/fcntl.h>
24 #include <linux/string.h>
25 #include <linux/errno.h>
26 #include <linux/init.h>
27 #include <linux/ioport.h>
28 #include <linux/moduleparam.h>
29 #include <linux/netdevice.h>
30 #include <linux/hdlc.h>
31 #include <linux/pci.h>
32 #include <asm/delay.h>
37 static const char* version = "Goramo PCI200SYN driver version: 1.16";
38 static const char* devname = "PCI200SYN";
43 #define PCI200SYN_PLX_SIZE 0x80 /* PLX control window size (128b) */
44 #define PCI200SYN_SCA_SIZE 0x400 /* SCA window size (1Kb) */
45 #define ALL_PAGES_ALWAYS_MAPPED
46 #define NEED_DETECT_RAM
47 #define NEED_SCA_MSCI_INTR
48 #define MAX_TX_BUFFERS 10
50 static int pci_clock_freq = 33000000;
51 #define CLOCK_BASE pci_clock_freq
53 #define PCI_VENDOR_ID_GORAMO 0x10B5 /* uses PLX:9050 ID - this card */
54 #define PCI_DEVICE_ID_PCI200SYN 0x9050 /* doesn't have its own ID */
58 * PLX PCI9052 local configuration and shared runtime registers.
59 * This structure can be used to access 9052 registers (memory mapped).
62 u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
63 u32 loc_rom_range; /* 10h : Local ROM Range */
64 u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
65 u32 loc_rom_base; /* 24h : Local ROM Base */
66 u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
67 u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */
68 u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
69 u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
70 u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
75 typedef struct port_s {
76 struct net_device *dev;
78 spinlock_t lock; /* TX lock */
79 sync_serial_settings settings;
80 int rxpart; /* partial frame received, next frame invalid*/
81 unsigned short encoding;
82 unsigned short parity;
83 u16 rxin; /* rx ring buffer 'in' pointer */
84 u16 txin; /* tx ring buffer 'in' and 'last' pointers */
86 u8 rxs, txs, tmc; /* SCA registers */
87 u8 phy_node; /* physical port # - 0 or 1 */
92 typedef struct card_s {
93 u8* rambase; /* buffer memory base (virtual) */
94 u8* scabase; /* SCA memory base (virtual) */
95 plx9052* plxbase; /* PLX registers memory base (virtual) */
96 u16 rx_ring_buffers; /* number of buffers in a ring */
98 u16 buff_offset; /* offset of first buffer of first channel */
99 u8 irq; /* interrupt request level */
105 #define sca_in(reg, card) readb(card->scabase + (reg))
106 #define sca_out(value, reg, card) writeb(value, card->scabase + (reg))
107 #define sca_inw(reg, card) readw(card->scabase + (reg))
108 #define sca_outw(value, reg, card) writew(value, card->scabase + (reg))
109 #define sca_inl(reg, card) readl(card->scabase + (reg))
110 #define sca_outl(value, reg, card) writel(value, card->scabase + (reg))
112 #define port_to_card(port) (port->card)
113 #define log_node(port) (port->phy_node)
114 #define phy_node(port) (port->phy_node)
115 #define winbase(card) (card->rambase)
116 #define get_port(card, port) (&card->ports[port])
117 #define sca_flush(card) (sca_in(IER0, card));
119 static inline void new_memcpy_toio(char *dest, char *src, int length)
123 len = length > 256 ? 256 : length;
124 memcpy_toio(dest, src, len);
133 #define memcpy_toio new_memcpy_toio
138 static void pci200_set_iface(port_t *port)
140 card_t *card = port->card;
141 u16 msci = get_msci(port);
142 u8 rxs = port->rxs & CLK_BRG_MASK;
143 u8 txs = port->txs & CLK_BRG_MASK;
145 sca_out(EXS_TES1, (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
147 switch(port->settings.clock_type) {
149 rxs |= CLK_BRG; /* BRG output */
150 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
154 rxs |= CLK_LINE; /* RXC input */
155 txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */
159 rxs |= CLK_LINE; /* RXC input */
160 txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
163 default: /* EXTernal clock */
164 rxs |= CLK_LINE; /* RXC input */
165 txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */
171 sca_out(rxs, msci + RXS, card);
172 sca_out(txs, msci + TXS, card);
178 static int pci200_open(struct net_device *dev)
180 port_t *port = dev_to_port(dev);
182 int result = hdlc_open(dev);
187 pci200_set_iface(port);
188 sca_flush(port_to_card(port));
194 static int pci200_close(struct net_device *dev)
197 sca_flush(port_to_card(dev_to_port(dev)));
204 static int pci200_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
206 const size_t size = sizeof(sync_serial_settings);
207 sync_serial_settings new_line, *line = ifr->ifr_settings.ifs_ifsu.sync;
208 port_t *port = dev_to_port(dev);
211 if (cmd == SIOCDEVPRIVATE) {
216 if (cmd != SIOCWANDEV)
217 return hdlc_ioctl(dev, ifr, cmd);
219 switch(ifr->ifr_settings.type) {
221 ifr->ifr_settings.type = IF_IFACE_V35;
222 if (ifr->ifr_settings.size < size) {
223 ifr->ifr_settings.size = size; /* data size wanted */
226 if (copy_to_user(line, &port->settings, size))
231 case IF_IFACE_SYNC_SERIAL:
232 if (!capable(CAP_NET_ADMIN))
235 if (copy_from_user(&new_line, line, size))
238 if (new_line.clock_type != CLOCK_EXT &&
239 new_line.clock_type != CLOCK_TXFROMRX &&
240 new_line.clock_type != CLOCK_INT &&
241 new_line.clock_type != CLOCK_TXINT)
242 return -EINVAL; /* No such clock setting */
244 if (new_line.loopback != 0 && new_line.loopback != 1)
247 memcpy(&port->settings, &new_line, size); /* Update settings */
248 pci200_set_iface(port);
249 sca_flush(port_to_card(port));
253 return hdlc_ioctl(dev, ifr, cmd);
259 static void pci200_pci_remove_one(struct pci_dev *pdev)
262 card_t *card = pci_get_drvdata(pdev);
264 for(i = 0; i < 2; i++)
265 if (card->ports[i].card) {
266 struct net_device *dev = port_to_dev(&card->ports[i]);
267 unregister_hdlc_device(dev);
271 free_irq(card->irq, card);
274 iounmap(card->rambase);
276 iounmap(card->scabase);
278 iounmap(card->plxbase);
280 pci_release_regions(pdev);
281 pci_disable_device(pdev);
282 pci_set_drvdata(pdev, NULL);
283 if (card->ports[0].dev)
284 free_netdev(card->ports[0].dev);
285 if (card->ports[1].dev)
286 free_netdev(card->ports[1].dev);
292 static int __devinit pci200_pci_init_one(struct pci_dev *pdev,
293 const struct pci_device_id *ent)
300 u32 ramphys; /* buffer memory base */
301 u32 scaphys; /* SCA memory base */
302 u32 plxphys; /* PLX registers memory base */
305 static int printed_version;
306 if (!printed_version++)
307 printk(KERN_INFO "%s\n", version);
310 i = pci_enable_device(pdev);
314 i = pci_request_regions(pdev, "PCI200SYN");
316 pci_disable_device(pdev);
320 card = kmalloc(sizeof(card_t), GFP_KERNEL);
322 printk(KERN_ERR "pci200syn: unable to allocate memory\n");
323 pci_release_regions(pdev);
324 pci_disable_device(pdev);
327 memset(card, 0, sizeof(card_t));
328 pci_set_drvdata(pdev, card);
329 card->ports[0].dev = alloc_hdlcdev(&card->ports[0]);
330 card->ports[1].dev = alloc_hdlcdev(&card->ports[1]);
331 if (!card->ports[0].dev || !card->ports[1].dev) {
332 printk(KERN_ERR "pci200syn: unable to allocate memory\n");
333 pci200_pci_remove_one(pdev);
337 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
338 if (pci_resource_len(pdev, 0) != PCI200SYN_PLX_SIZE ||
339 pci_resource_len(pdev, 2) != PCI200SYN_SCA_SIZE ||
340 pci_resource_len(pdev, 3) < 16384) {
341 printk(KERN_ERR "pci200syn: invalid card EEPROM parameters\n");
342 pci200_pci_remove_one(pdev);
346 plxphys = pci_resource_start(pdev,0) & PCI_BASE_ADDRESS_MEM_MASK;
347 card->plxbase = ioremap(plxphys, PCI200SYN_PLX_SIZE);
349 scaphys = pci_resource_start(pdev,2) & PCI_BASE_ADDRESS_MEM_MASK;
350 card->scabase = ioremap(scaphys, PCI200SYN_SCA_SIZE);
352 ramphys = pci_resource_start(pdev,3) & PCI_BASE_ADDRESS_MEM_MASK;
353 card->rambase = ioremap(ramphys, pci_resource_len(pdev,3));
355 if (card->plxbase == NULL ||
356 card->scabase == NULL ||
357 card->rambase == NULL) {
358 printk(KERN_ERR "pci200syn: ioremap() failed\n");
359 pci200_pci_remove_one(pdev);
363 p = &card->plxbase->init_ctrl;
364 writel(readl(p) | 0x40000000, p);
365 readl(p); /* Flush the write - do not use sca_flush */
368 writel(readl(p) & ~0x40000000, p);
369 readl(p); /* Flush the write - do not use sca_flush */
372 ramsize = sca_detect_ram(card, card->rambase,
373 pci_resource_len(pdev, 3));
375 /* number of TX + RX buffers for one port - this is dual port card */
376 i = ramsize / (2 * (sizeof(pkt_desc) + HDLC_MAX_MRU));
377 card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
378 card->rx_ring_buffers = i - card->tx_ring_buffers;
380 card->buff_offset = 2 * sizeof(pkt_desc) * (card->tx_ring_buffers +
381 card->rx_ring_buffers);
383 printk(KERN_INFO "pci200syn: %u KB RAM at 0x%x, IRQ%u, using %u TX +"
384 " %u RX packets rings\n", ramsize / 1024, ramphys,
385 pdev->irq, card->tx_ring_buffers, card->rx_ring_buffers);
387 if (card->tx_ring_buffers < 1) {
388 printk(KERN_ERR "pci200syn: RAM test failed\n");
389 pci200_pci_remove_one(pdev);
393 /* Enable interrupts on the PCI bridge */
394 p = &card->plxbase->intr_ctrl_stat;
395 writew(readw(p) | 0x0040, p);
398 if(request_irq(pdev->irq, sca_intr, SA_SHIRQ, devname, card)) {
399 printk(KERN_WARNING "pci200syn: could not allocate IRQ%d.\n",
401 pci200_pci_remove_one(pdev);
404 card->irq = pdev->irq;
408 for(i = 0; i < 2; i++) {
409 port_t *port = &card->ports[i];
410 struct net_device *dev = port_to_dev(port);
411 hdlc_device *hdlc = dev_to_hdlc(dev);
414 spin_lock_init(&port->lock);
415 SET_MODULE_OWNER(dev);
416 dev->irq = card->irq;
417 dev->mem_start = ramphys;
418 dev->mem_end = ramphys + ramsize - 1;
419 dev->tx_queue_len = 50;
420 dev->do_ioctl = pci200_ioctl;
421 dev->open = pci200_open;
422 dev->stop = pci200_close;
423 hdlc->attach = sca_attach;
424 hdlc->xmit = sca_xmit;
425 port->settings.clock_type = CLOCK_EXT;
427 if(register_hdlc_device(dev)) {
428 printk(KERN_ERR "pci200syn: unable to register hdlc "
431 pci200_pci_remove_one(pdev);
434 sca_init_sync_port(port); /* Set up SCA memory */
436 printk(KERN_INFO "%s: PCI200SYN node %d\n",
437 dev->name, port->phy_node);
446 static struct pci_device_id pci200_pci_tbl[] __devinitdata = {
447 { PCI_VENDOR_ID_GORAMO, PCI_DEVICE_ID_PCI200SYN, PCI_ANY_ID,
448 PCI_ANY_ID, 0, 0, 0 },
453 static struct pci_driver pci200_pci_driver = {
455 .id_table = pci200_pci_tbl,
456 .probe = pci200_pci_init_one,
457 .remove = pci200_pci_remove_one,
461 static int __init pci200_init_module(void)
464 printk(KERN_INFO "%s\n", version);
466 if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) {
467 printk(KERN_ERR "pci200syn: Invalid PCI clock frequency\n");
470 return pci_module_init(&pci200_pci_driver);
475 static void __exit pci200_cleanup_module(void)
477 pci_unregister_driver(&pci200_pci_driver);
480 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
481 MODULE_DESCRIPTION("Goramo PCI200SYN serial port driver");
482 MODULE_LICENSE("GPL v2");
483 MODULE_DEVICE_TABLE(pci, pci200_pci_tbl);
484 module_param(pci_clock_freq, int, 0444);
485 MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz");
486 module_init(pci200_init_module);
487 module_exit(pci200_cleanup_module);