2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version
5 * 2 of the License, or (at your option) any later version.
7 * (c) Copyright 1998 Alan Cox <alan@lxorguk.ukuu.org.uk>
8 * (c) Copyright 2000, 2001 Red Hat Inc
10 * Development of this driver was funded by Equiinet Ltd
11 * http://www.equiinet.com
15 * Asynchronous mode dropped for 2.2. For 2.5 we will attempt the
16 * unification of all the Z85x30 asynchronous drivers for real.
18 * DMA now uses get_free_page as kmalloc buffers may span a 64K
21 * Modified for SMP safety and SMP locking by Alan Cox <alan@redhat.com>
26 * Non DMA you want a 486DX50 or better to do 64Kbits. 9600 baud
27 * X.25 is not unrealistic on all machines. DMA mode can in theory
28 * handle T1/E1 quite nicely. In practice the limit seems to be about
29 * 512Kbit->1Mbit depending on motherboard.
32 * 64K will take DMA, 9600 baud X.25 should be ok.
35 * Synchronous mode without DMA is unlikely to pass about 2400 baud.
38 #include <linux/module.h>
39 #include <linux/kernel.h>
41 #include <linux/net.h>
42 #include <linux/skbuff.h>
43 #include <linux/netdevice.h>
44 #include <linux/if_arp.h>
45 #include <linux/delay.h>
46 #include <linux/ioport.h>
47 #include <linux/init.h>
52 #include <linux/spinlock.h>
54 #include <net/syncppp.h>
59 * z8530_read_port - Architecture specific interface function
62 * Provided port access methods. The Comtrol SV11 requires no delays
63 * between accesses and uses PC I/O. Some drivers may need a 5uS delay
65 * In the longer term this should become an architecture specific
66 * section so that this can become a generic driver interface for all
67 * platforms. For now we only handle PC I/O ports with or without the
68 * dread 5uS sanity delay.
70 * The caller must hold sufficient locks to avoid violating the horrible
74 static inline int z8530_read_port(unsigned long p)
76 u8 r=inb(Z8530_PORT_OF(p));
77 if(p&Z8530_PORT_SLEEP) /* gcc should figure this out efficiently ! */
83 * z8530_write_port - Architecture specific interface function
87 * Write a value to a port with delays if need be. Note that the
88 * caller must hold locks to avoid read/writes from other contexts
89 * violating the 5uS rule
91 * In the longer term this should become an architecture specific
92 * section so that this can become a generic driver interface for all
93 * platforms. For now we only handle PC I/O ports with or without the
94 * dread 5uS sanity delay.
98 static inline void z8530_write_port(unsigned long p, u8 d)
100 outb(d,Z8530_PORT_OF(p));
101 if(p&Z8530_PORT_SLEEP)
107 static void z8530_rx_done(struct z8530_channel *c);
108 static void z8530_tx_done(struct z8530_channel *c);
112 * read_zsreg - Read a register from a Z85230
113 * @c: Z8530 channel to read from (2 per chip)
114 * @reg: Register to read
115 * FIXME: Use a spinlock.
117 * Most of the Z8530 registers are indexed off the control registers.
118 * A read is done by writing to the control register and reading the
119 * register back. The caller must hold the lock
122 static inline u8 read_zsreg(struct z8530_channel *c, u8 reg)
125 z8530_write_port(c->ctrlio, reg);
126 return z8530_read_port(c->ctrlio);
130 * read_zsdata - Read the data port of a Z8530 channel
131 * @c: The Z8530 channel to read the data port from
133 * The data port provides fast access to some things. We still
134 * have all the 5uS delays to worry about.
137 static inline u8 read_zsdata(struct z8530_channel *c)
140 r=z8530_read_port(c->dataio);
145 * write_zsreg - Write to a Z8530 channel register
146 * @c: The Z8530 channel
147 * @reg: Register number
148 * @val: Value to write
150 * Write a value to an indexed register. The caller must hold the lock
151 * to honour the irritating delay rules. We know about register 0
152 * being fast to access.
154 * Assumes c->lock is held.
156 static inline void write_zsreg(struct z8530_channel *c, u8 reg, u8 val)
159 z8530_write_port(c->ctrlio, reg);
160 z8530_write_port(c->ctrlio, val);
165 * write_zsctrl - Write to a Z8530 control register
166 * @c: The Z8530 channel
167 * @val: Value to write
169 * Write directly to the control register on the Z8530
172 static inline void write_zsctrl(struct z8530_channel *c, u8 val)
174 z8530_write_port(c->ctrlio, val);
178 * write_zsdata - Write to a Z8530 control register
179 * @c: The Z8530 channel
180 * @val: Value to write
182 * Write directly to the data register on the Z8530
186 static inline void write_zsdata(struct z8530_channel *c, u8 val)
188 z8530_write_port(c->dataio, val);
192 * Register loading parameters for a dead port
195 u8 z8530_dead_port[]=
200 EXPORT_SYMBOL(z8530_dead_port);
203 * Register loading parameters for currently supported circuit types
208 * Data clocked by telco end. This is the correct data for the UK
209 * "kilostream" service, and most other similar services.
212 u8 z8530_hdlc_kilostream[]=
214 4, SYNC_ENAB|SDLC|X1CLK,
215 2, 0, /* No vector */
217 3, ENT_HM|RxCRC_ENAB|Rx8,
218 5, TxCRC_ENAB|RTS|TxENAB|Tx8|DTR,
219 9, 0, /* Disable interrupts */
222 10, ABUNDER|NRZ|CRCPS,/*MARKIDLE ??*/
225 15, DCDIE|SYNCIE|CTSIE|TxUIE|BRKIE,
226 1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx,
231 EXPORT_SYMBOL(z8530_hdlc_kilostream);
234 * As above but for enhanced chips.
237 u8 z8530_hdlc_kilostream_85230[]=
239 4, SYNC_ENAB|SDLC|X1CLK,
240 2, 0, /* No vector */
242 3, ENT_HM|RxCRC_ENAB|Rx8,
243 5, TxCRC_ENAB|RTS|TxENAB|Tx8|DTR,
244 9, 0, /* Disable interrupts */
247 10, ABUNDER|NRZ|CRCPS, /* MARKIDLE?? */
250 15, DCDIE|SYNCIE|CTSIE|TxUIE|BRKIE,
251 1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx,
253 23, 3, /* Extended mode AUTO TX and EOM*/
258 EXPORT_SYMBOL(z8530_hdlc_kilostream_85230);
261 * z8530_flush_fifo - Flush on chip RX FIFO
262 * @c: Channel to flush
264 * Flush the receive FIFO. There is no specific option for this, we
265 * blindly read bytes and discard them. Reading when there is no data
266 * is harmless. The 8530 has a 4 byte FIFO, the 85230 has 8 bytes.
268 * All locking is handled for the caller. On return data may still be
269 * present if it arrived during the flush.
272 static void z8530_flush_fifo(struct z8530_channel *c)
278 if(c->dev->type==Z85230)
288 * z8530_rtsdtr - Control the outgoing DTS/RTS line
289 * @c: The Z8530 channel to control;
290 * @set: 1 to set, 0 to clear
292 * Sets or clears DTR/RTS on the requested line. All locking is handled
293 * by the caller. For now we assume all boards use the actual RTS/DTR
294 * on the chip. Apparently one or two don't. We'll scream about them
298 static void z8530_rtsdtr(struct z8530_channel *c, int set)
301 c->regs[5] |= (RTS | DTR);
303 c->regs[5] &= ~(RTS | DTR);
304 write_zsreg(c, R5, c->regs[5]);
308 * z8530_rx - Handle a PIO receive event
309 * @c: Z8530 channel to process
311 * Receive handler for receiving in PIO mode. This is much like the
312 * async one but not quite the same or as complex
314 * Note: Its intended that this handler can easily be separated from
315 * the main code to run realtime. That'll be needed for some machines
316 * (eg to ever clock 64kbits on a sparc ;)).
318 * The RT_LOCK macros don't do anything now. Keep the code covered
319 * by them as short as possible in all circumstances - clocks cost
320 * baud. The interrupt handler is assumed to be atomic w.r.t. to
321 * other code - this is true in the RT case too.
323 * We only cover the sync cases for this. If you want 2Mbit async
324 * do it yourself but consider medical assistance first. This non DMA
325 * synchronous mode is portable code. The DMA mode assumes PCI like
328 * Called with the device lock held
331 static void z8530_rx(struct z8530_channel *c)
339 if(!(read_zsreg(c, R0)&1))
342 stat=read_zsreg(c, R1);
347 if(c->count < c->max)
359 if(stat&(Rx_OVR|CRC_ERR))
361 /* Rewind the buffer and return */
363 c->dptr=c->skb->data;
367 printk(KERN_WARNING "%s: overrun\n", c->dev->name);
373 /* printk("crc error\n"); */
375 /* Shove the frame upstream */
380 * Drop the lock for RX processing, or
381 * there are deadlocks
384 write_zsctrl(c, RES_Rx_CRC);
391 write_zsctrl(c, ERR_RES);
392 write_zsctrl(c, RES_H_IUS);
393 spin_unlock(c->lock);
398 * z8530_tx - Handle a PIO transmit event
399 * @c: Z8530 channel to process
401 * Z8530 transmit interrupt handler for the PIO mode. The basic
402 * idea is to attempt to keep the FIFO fed. We fill as many bytes
403 * in as possible, its quite possible that we won't keep up with the
404 * data rate otherwise.
407 static void z8530_tx(struct z8530_channel *c)
412 if(!(read_zsreg(c, R0)&4))
416 * Shovel out the byte
418 write_zsreg(c, R8, *c->tx_ptr++);
419 write_zsctrl(c, RES_H_IUS);
420 /* We are about to underflow */
423 write_zsctrl(c, RES_EOM_L);
424 write_zsreg(c, R10, c->regs[10]&~ABUNDER);
430 * End of frame TX - fire another one
433 write_zsctrl(c, RES_Tx_P);
436 write_zsctrl(c, RES_H_IUS);
437 spin_unlock(c->lock);
441 * z8530_status - Handle a PIO status exception
442 * @chan: Z8530 channel to process
444 * A status event occurred in PIO synchronous mode. There are several
445 * reasons the chip will bother us here. A transmit underrun means we
446 * failed to feed the chip fast enough and just broke a packet. A DCD
447 * change is a line up or down. We communicate that back to the protocol
448 * layer for synchronous PPP to renegotiate.
451 static void z8530_status(struct z8530_channel *chan)
455 spin_lock(chan->lock);
456 status=read_zsreg(chan, R0);
457 altered=chan->status^status;
463 /* printk("%s: Tx underrun.\n", chan->dev->name); */
464 chan->stats.tx_fifo_errors++;
465 write_zsctrl(chan, ERR_RES);
469 if(altered&chan->dcdcheck)
471 if(status&chan->dcdcheck)
473 printk(KERN_INFO "%s: DCD raised\n", chan->dev->name);
474 write_zsreg(chan, R3, chan->regs[3]|RxENABLE);
475 if(chan->netdevice &&
476 ((chan->netdevice->type == ARPHRD_HDLC) ||
477 (chan->netdevice->type == ARPHRD_PPP)))
478 sppp_reopen(chan->netdevice);
482 printk(KERN_INFO "%s: DCD lost\n", chan->dev->name);
483 write_zsreg(chan, R3, chan->regs[3]&~RxENABLE);
484 z8530_flush_fifo(chan);
488 write_zsctrl(chan, RES_EXT_INT);
489 write_zsctrl(chan, RES_H_IUS);
490 spin_unlock(chan->lock);
493 struct z8530_irqhandler z8530_sync=
500 EXPORT_SYMBOL(z8530_sync);
503 * z8530_dma_rx - Handle a DMA RX event
504 * @chan: Channel to handle
506 * Non bus mastering DMA interfaces for the Z8x30 devices. This
507 * is really pretty PC specific. The DMA mode means that most receive
508 * events are handled by the DMA hardware. We get a kick here only if
512 static void z8530_dma_rx(struct z8530_channel *chan)
514 spin_lock(chan->lock);
517 /* Special condition check only */
520 read_zsreg(chan, R7);
521 read_zsreg(chan, R6);
523 status=read_zsreg(chan, R1);
527 z8530_rx_done(chan); /* Fire up the next one */
529 write_zsctrl(chan, ERR_RES);
530 write_zsctrl(chan, RES_H_IUS);
534 /* DMA is off right now, drain the slow way */
537 spin_unlock(chan->lock);
541 * z8530_dma_tx - Handle a DMA TX event
542 * @chan: The Z8530 channel to handle
544 * We have received an interrupt while doing DMA transmissions. It
545 * shouldn't happen. Scream loudly if it does.
548 static void z8530_dma_tx(struct z8530_channel *chan)
550 spin_lock(chan->lock);
553 printk(KERN_WARNING "Hey who turned the DMA off?\n");
557 /* This shouldnt occur in DMA mode */
558 printk(KERN_ERR "DMA tx - bogus event!\n");
560 spin_unlock(chan->lock);
564 * z8530_dma_status - Handle a DMA status exception
565 * @chan: Z8530 channel to process
567 * A status event occurred on the Z8530. We receive these for two reasons
568 * when in DMA mode. Firstly if we finished a packet transfer we get one
569 * and kick the next packet out. Secondly we may see a DCD change and
570 * have to poke the protocol layer.
574 static void z8530_dma_status(struct z8530_channel *chan)
578 status=read_zsreg(chan, R0);
579 altered=chan->status^status;
590 flags=claim_dma_lock();
591 disable_dma(chan->txdma);
592 clear_dma_ff(chan->txdma);
594 release_dma_lock(flags);
599 spin_lock(chan->lock);
600 if(altered&chan->dcdcheck)
602 if(status&chan->dcdcheck)
604 printk(KERN_INFO "%s: DCD raised\n", chan->dev->name);
605 write_zsreg(chan, R3, chan->regs[3]|RxENABLE);
606 if(chan->netdevice &&
607 ((chan->netdevice->type == ARPHRD_HDLC) ||
608 (chan->netdevice->type == ARPHRD_PPP)))
609 sppp_reopen(chan->netdevice);
613 printk(KERN_INFO "%s:DCD lost\n", chan->dev->name);
614 write_zsreg(chan, R3, chan->regs[3]&~RxENABLE);
615 z8530_flush_fifo(chan);
619 write_zsctrl(chan, RES_EXT_INT);
620 write_zsctrl(chan, RES_H_IUS);
621 spin_unlock(chan->lock);
624 struct z8530_irqhandler z8530_dma_sync=
631 EXPORT_SYMBOL(z8530_dma_sync);
633 struct z8530_irqhandler z8530_txdma_sync=
640 EXPORT_SYMBOL(z8530_txdma_sync);
643 * z8530_rx_clear - Handle RX events from a stopped chip
644 * @c: Z8530 channel to shut up
646 * Receive interrupt vectors for a Z8530 that is in 'parked' mode.
647 * For machines with PCI Z85x30 cards, or level triggered interrupts
648 * (eg the MacII) we must clear the interrupt cause or die.
652 static void z8530_rx_clear(struct z8530_channel *c)
655 * Data and status bytes
660 stat=read_zsreg(c, R1);
663 write_zsctrl(c, RES_Rx_CRC);
667 write_zsctrl(c, ERR_RES);
668 write_zsctrl(c, RES_H_IUS);
672 * z8530_tx_clear - Handle TX events from a stopped chip
673 * @c: Z8530 channel to shut up
675 * Transmit interrupt vectors for a Z8530 that is in 'parked' mode.
676 * For machines with PCI Z85x30 cards, or level triggered interrupts
677 * (eg the MacII) we must clear the interrupt cause or die.
680 static void z8530_tx_clear(struct z8530_channel *c)
682 write_zsctrl(c, RES_Tx_P);
683 write_zsctrl(c, RES_H_IUS);
687 * z8530_status_clear - Handle status events from a stopped chip
688 * @chan: Z8530 channel to shut up
690 * Status interrupt vectors for a Z8530 that is in 'parked' mode.
691 * For machines with PCI Z85x30 cards, or level triggered interrupts
692 * (eg the MacII) we must clear the interrupt cause or die.
695 static void z8530_status_clear(struct z8530_channel *chan)
697 u8 status=read_zsreg(chan, R0);
699 write_zsctrl(chan, ERR_RES);
700 write_zsctrl(chan, RES_EXT_INT);
701 write_zsctrl(chan, RES_H_IUS);
704 struct z8530_irqhandler z8530_nop=
712 EXPORT_SYMBOL(z8530_nop);
715 * z8530_interrupt - Handle an interrupt from a Z8530
716 * @irq: Interrupt number
717 * @dev_id: The Z8530 device that is interrupting.
720 * A Z85[2]30 device has stuck its hand in the air for attention.
721 * We scan both the channels on the chip for events and then call
722 * the channel specific call backs for each channel that has events.
723 * We have to use callback functions because the two channels can be
724 * in different modes.
726 * Locking is done for the handlers. Note that locking is done
727 * at the chip level (the 5uS delay issue is per chip not per
728 * channel). c->lock for both channels points to dev->lock
731 irqreturn_t z8530_interrupt(int irq, void *dev_id, struct pt_regs *regs)
733 struct z8530_dev *dev=dev_id;
735 static volatile int locker=0;
737 struct z8530_irqhandler *irqs=dev->chanA.irqs;
741 printk(KERN_ERR "IRQ re-enter\n");
746 spin_lock(&dev->lock);
751 intr = read_zsreg(&dev->chanA, R3);
752 if(!(intr & (CHARxIP|CHATxIP|CHAEXT|CHBRxIP|CHBTxIP|CHBEXT)))
755 /* This holds the IRQ status. On the 8530 you must read it from chan
756 A even though it applies to the whole chip */
758 /* Now walk the chip and see what it is wanting - it may be
759 an IRQ for someone else remember */
761 if(intr & (CHARxIP|CHATxIP|CHAEXT))
764 irqs->rx(&dev->chanA);
766 irqs->tx(&dev->chanA);
768 irqs->status(&dev->chanA);
771 irqs=dev->chanB.irqs;
773 if(intr & (CHBRxIP|CHBTxIP|CHBEXT))
776 irqs->rx(&dev->chanB);
778 irqs->tx(&dev->chanB);
780 irqs->status(&dev->chanB);
783 spin_unlock(&dev->lock);
785 printk(KERN_ERR "%s: interrupt jammed - abort(0x%X)!\n", dev->name, intr);
791 EXPORT_SYMBOL(z8530_interrupt);
793 static char reg_init[16]=
803 * z8530_sync_open - Open a Z8530 channel for PIO
804 * @dev: The network interface we are using
805 * @c: The Z8530 channel to open in synchronous PIO mode
807 * Switch a Z8530 into synchronous mode without DMA assist. We
808 * raise the RTS/DTR and commence network operation.
811 int z8530_sync_open(struct net_device *dev, struct z8530_channel *c)
815 spin_lock_irqsave(c->lock, flags);
818 c->mtu = dev->mtu+64;
822 c->irqs = &z8530_sync;
824 /* This loads the double buffer up */
825 z8530_rx_done(c); /* Load the frame ring */
826 z8530_rx_done(c); /* Load the backup frame */
829 c->regs[R1]|=TxINT_ENAB;
830 write_zsreg(c, R1, c->regs[R1]);
831 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
833 spin_unlock_irqrestore(c->lock, flags);
838 EXPORT_SYMBOL(z8530_sync_open);
841 * z8530_sync_close - Close a PIO Z8530 channel
842 * @dev: Network device to close
843 * @c: Z8530 channel to disassociate and move to idle
845 * Close down a Z8530 interface and switch its interrupt handlers
846 * to discard future events.
849 int z8530_sync_close(struct net_device *dev, struct z8530_channel *c)
854 spin_lock_irqsave(c->lock, flags);
855 c->irqs = &z8530_nop;
859 chk=read_zsreg(c,R0);
860 write_zsreg(c, R3, c->regs[R3]);
863 spin_unlock_irqrestore(c->lock, flags);
867 EXPORT_SYMBOL(z8530_sync_close);
870 * z8530_sync_dma_open - Open a Z8530 for DMA I/O
871 * @dev: The network device to attach
872 * @c: The Z8530 channel to configure in sync DMA mode.
874 * Set up a Z85x30 device for synchronous DMA in both directions. Two
875 * ISA DMA channels must be available for this to work. We assume ISA
876 * DMA driven I/O and PC limits on access.
879 int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c)
881 unsigned long cflags, dflags;
884 c->mtu = dev->mtu+64;
889 * Load the DMA interfaces up
895 * Allocate the DMA flip buffers. Limit by page size.
896 * Everyone runs 1500 mtu or less on wan links so this
900 if(c->mtu > PAGE_SIZE/2)
903 c->rx_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA);
904 if(c->rx_buf[0]==NULL)
906 c->rx_buf[1]=c->rx_buf[0]+PAGE_SIZE/2;
908 c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA);
909 if(c->tx_dma_buf[0]==NULL)
911 free_page((unsigned long)c->rx_buf[0]);
915 c->tx_dma_buf[1]=c->tx_dma_buf[0]+PAGE_SIZE/2;
923 * Enable DMA control mode
926 spin_lock_irqsave(c->lock, cflags);
932 c->regs[R14]|= DTRREQ;
933 write_zsreg(c, R14, c->regs[R14]);
935 c->regs[R1]&= ~TxINT_ENAB;
936 write_zsreg(c, R1, c->regs[R1]);
942 c->regs[R1]|= WT_FN_RDYFN;
943 c->regs[R1]|= WT_RDY_RT;
944 c->regs[R1]|= INT_ERR_Rx;
945 c->regs[R1]&= ~TxINT_ENAB;
946 write_zsreg(c, R1, c->regs[R1]);
947 c->regs[R1]|= WT_RDY_ENAB;
948 write_zsreg(c, R1, c->regs[R1]);
955 * Set up the DMA configuration
958 dflags=claim_dma_lock();
960 disable_dma(c->rxdma);
961 clear_dma_ff(c->rxdma);
962 set_dma_mode(c->rxdma, DMA_MODE_READ|0x10);
963 set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[0]));
964 set_dma_count(c->rxdma, c->mtu);
965 enable_dma(c->rxdma);
967 disable_dma(c->txdma);
968 clear_dma_ff(c->txdma);
969 set_dma_mode(c->txdma, DMA_MODE_WRITE);
970 disable_dma(c->txdma);
972 release_dma_lock(dflags);
975 * Select the DMA interrupt handlers
982 c->irqs = &z8530_dma_sync;
984 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
986 spin_unlock_irqrestore(c->lock, cflags);
991 EXPORT_SYMBOL(z8530_sync_dma_open);
994 * z8530_sync_dma_close - Close down DMA I/O
995 * @dev: Network device to detach
996 * @c: Z8530 channel to move into discard mode
998 * Shut down a DMA mode synchronous interface. Halt the DMA, and
1002 int z8530_sync_dma_close(struct net_device *dev, struct z8530_channel *c)
1005 unsigned long flags;
1007 c->irqs = &z8530_nop;
1012 * Disable the PC DMA channels
1015 flags=claim_dma_lock();
1016 disable_dma(c->rxdma);
1017 clear_dma_ff(c->rxdma);
1021 disable_dma(c->txdma);
1022 clear_dma_ff(c->txdma);
1023 release_dma_lock(flags);
1028 spin_lock_irqsave(c->lock, flags);
1031 * Disable DMA control mode
1034 c->regs[R1]&= ~WT_RDY_ENAB;
1035 write_zsreg(c, R1, c->regs[R1]);
1036 c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx);
1037 c->regs[R1]|= INT_ALL_Rx;
1038 write_zsreg(c, R1, c->regs[R1]);
1039 c->regs[R14]&= ~DTRREQ;
1040 write_zsreg(c, R14, c->regs[R14]);
1044 free_page((unsigned long)c->rx_buf[0]);
1047 if(c->tx_dma_buf[0])
1049 free_page((unsigned long)c->tx_dma_buf[0]);
1050 c->tx_dma_buf[0]=NULL;
1052 chk=read_zsreg(c,R0);
1053 write_zsreg(c, R3, c->regs[R3]);
1056 spin_unlock_irqrestore(c->lock, flags);
1061 EXPORT_SYMBOL(z8530_sync_dma_close);
1064 * z8530_sync_txdma_open - Open a Z8530 for TX driven DMA
1065 * @dev: The network device to attach
1066 * @c: The Z8530 channel to configure in sync DMA mode.
1068 * Set up a Z85x30 device for synchronous DMA tranmission. One
1069 * ISA DMA channel must be available for this to work. The receive
1070 * side is run in PIO mode, but then it has the bigger FIFO.
1073 int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c)
1075 unsigned long cflags, dflags;
1077 printk("Opening sync interface for TX-DMA\n");
1079 c->mtu = dev->mtu+64;
1085 * Allocate the DMA flip buffers. Limit by page size.
1086 * Everyone runs 1500 mtu or less on wan links so this
1090 if(c->mtu > PAGE_SIZE/2)
1093 c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA);
1094 if(c->tx_dma_buf[0]==NULL)
1097 c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE/2;
1100 spin_lock_irqsave(c->lock, cflags);
1103 * Load the PIO receive ring
1110 * Load the DMA interfaces up
1122 * Enable DMA control mode
1126 * TX DMA via DIR/REQ
1128 c->regs[R14]|= DTRREQ;
1129 write_zsreg(c, R14, c->regs[R14]);
1131 c->regs[R1]&= ~TxINT_ENAB;
1132 write_zsreg(c, R1, c->regs[R1]);
1135 * Set up the DMA configuration
1138 dflags = claim_dma_lock();
1140 disable_dma(c->txdma);
1141 clear_dma_ff(c->txdma);
1142 set_dma_mode(c->txdma, DMA_MODE_WRITE);
1143 disable_dma(c->txdma);
1145 release_dma_lock(dflags);
1148 * Select the DMA interrupt handlers
1155 c->irqs = &z8530_txdma_sync;
1157 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
1158 spin_unlock_irqrestore(c->lock, cflags);
1163 EXPORT_SYMBOL(z8530_sync_txdma_open);
1166 * z8530_sync_txdma_close - Close down a TX driven DMA channel
1167 * @dev: Network device to detach
1168 * @c: Z8530 channel to move into discard mode
1170 * Shut down a DMA/PIO split mode synchronous interface. Halt the DMA,
1171 * and free the buffers.
1174 int z8530_sync_txdma_close(struct net_device *dev, struct z8530_channel *c)
1176 unsigned long dflags, cflags;
1180 spin_lock_irqsave(c->lock, cflags);
1182 c->irqs = &z8530_nop;
1187 * Disable the PC DMA channels
1190 dflags = claim_dma_lock();
1192 disable_dma(c->txdma);
1193 clear_dma_ff(c->txdma);
1197 release_dma_lock(dflags);
1200 * Disable DMA control mode
1203 c->regs[R1]&= ~WT_RDY_ENAB;
1204 write_zsreg(c, R1, c->regs[R1]);
1205 c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx);
1206 c->regs[R1]|= INT_ALL_Rx;
1207 write_zsreg(c, R1, c->regs[R1]);
1208 c->regs[R14]&= ~DTRREQ;
1209 write_zsreg(c, R14, c->regs[R14]);
1211 if(c->tx_dma_buf[0])
1213 free_page((unsigned long)c->tx_dma_buf[0]);
1214 c->tx_dma_buf[0]=NULL;
1216 chk=read_zsreg(c,R0);
1217 write_zsreg(c, R3, c->regs[R3]);
1220 spin_unlock_irqrestore(c->lock, cflags);
1225 EXPORT_SYMBOL(z8530_sync_txdma_close);
1229 * Name strings for Z8530 chips. SGI claim to have a 130, Zilog deny
1233 static char *z8530_type_name[]={
1240 * z8530_describe - Uniformly describe a Z8530 port
1241 * @dev: Z8530 device to describe
1242 * @mapping: string holding mapping type (eg "I/O" or "Mem")
1243 * @io: the port value in question
1245 * Describe a Z8530 in a standard format. We must pass the I/O as
1246 * the port offset isnt predictable. The main reason for this function
1247 * is to try and get a common format of report.
1250 void z8530_describe(struct z8530_dev *dev, char *mapping, unsigned long io)
1252 printk(KERN_INFO "%s: %s found at %s 0x%lX, IRQ %d.\n",
1254 z8530_type_name[dev->type],
1260 EXPORT_SYMBOL(z8530_describe);
1263 * Locked operation part of the z8530 init code
1266 static inline int do_z8530_init(struct z8530_dev *dev)
1268 /* NOP the interrupt handlers first - we might get a
1269 floating IRQ transition when we reset the chip */
1270 dev->chanA.irqs=&z8530_nop;
1271 dev->chanB.irqs=&z8530_nop;
1272 dev->chanA.dcdcheck=DCD;
1273 dev->chanB.dcdcheck=DCD;
1275 /* Reset the chip */
1276 write_zsreg(&dev->chanA, R9, 0xC0);
1278 /* Now check its valid */
1279 write_zsreg(&dev->chanA, R12, 0xAA);
1280 if(read_zsreg(&dev->chanA, R12)!=0xAA)
1282 write_zsreg(&dev->chanA, R12, 0x55);
1283 if(read_zsreg(&dev->chanA, R12)!=0x55)
1289 * See the application note.
1292 write_zsreg(&dev->chanA, R15, 0x01);
1295 * If we can set the low bit of R15 then
1296 * the chip is enhanced.
1299 if(read_zsreg(&dev->chanA, R15)==0x01)
1301 /* This C30 versus 230 detect is from Klaus Kudielka's dmascc */
1302 /* Put a char in the fifo */
1303 write_zsreg(&dev->chanA, R8, 0);
1304 if(read_zsreg(&dev->chanA, R0)&Tx_BUF_EMP)
1305 dev->type = Z85230; /* Has a FIFO */
1307 dev->type = Z85C30; /* Z85C30, 1 byte FIFO */
1311 * The code assumes R7' and friends are
1312 * off. Use write_zsext() for these and keep
1316 write_zsreg(&dev->chanA, R15, 0);
1319 * At this point it looks like the chip is behaving
1322 memcpy(dev->chanA.regs, reg_init, 16);
1323 memcpy(dev->chanB.regs, reg_init ,16);
1329 * z8530_init - Initialise a Z8530 device
1330 * @dev: Z8530 device to initialise.
1332 * Configure up a Z8530/Z85C30 or Z85230 chip. We check the device
1333 * is present, identify the type and then program it to hopefully
1334 * keep quite and behave. This matters a lot, a Z8530 in the wrong
1335 * state will sometimes get into stupid modes generating 10Khz
1336 * interrupt streams and the like.
1338 * We set the interrupt handler up to discard any events, in case
1339 * we get them during reset or setp.
1341 * Return 0 for success, or a negative value indicating the problem
1345 int z8530_init(struct z8530_dev *dev)
1347 unsigned long flags;
1350 /* Set up the chip level lock */
1351 spin_lock_init(&dev->lock);
1352 dev->chanA.lock = &dev->lock;
1353 dev->chanB.lock = &dev->lock;
1355 spin_lock_irqsave(&dev->lock, flags);
1356 ret = do_z8530_init(dev);
1357 spin_unlock_irqrestore(&dev->lock, flags);
1363 EXPORT_SYMBOL(z8530_init);
1366 * z8530_shutdown - Shutdown a Z8530 device
1367 * @dev: The Z8530 chip to shutdown
1369 * We set the interrupt handlers to silence any interrupts. We then
1370 * reset the chip and wait 100uS to be sure the reset completed. Just
1371 * in case the caller then tries to do stuff.
1373 * This is called without the lock held
1376 int z8530_shutdown(struct z8530_dev *dev)
1378 unsigned long flags;
1379 /* Reset the chip */
1381 spin_lock_irqsave(&dev->lock, flags);
1382 dev->chanA.irqs=&z8530_nop;
1383 dev->chanB.irqs=&z8530_nop;
1384 write_zsreg(&dev->chanA, R9, 0xC0);
1385 /* We must lock the udelay, the chip is offlimits here */
1387 spin_unlock_irqrestore(&dev->lock, flags);
1391 EXPORT_SYMBOL(z8530_shutdown);
1394 * z8530_channel_load - Load channel data
1395 * @c: Z8530 channel to configure
1396 * @rtable: table of register, value pairs
1397 * FIXME: ioctl to allow user uploaded tables
1399 * Load a Z8530 channel up from the system data. We use +16 to
1400 * indicate the "prime" registers. The value 255 terminates the
1404 int z8530_channel_load(struct z8530_channel *c, u8 *rtable)
1406 unsigned long flags;
1408 spin_lock_irqsave(c->lock, flags);
1414 write_zsreg(c, R15, c->regs[15]|1);
1415 write_zsreg(c, reg&0x0F, *rtable);
1417 write_zsreg(c, R15, c->regs[15]&~1);
1418 c->regs[reg]=*rtable++;
1420 c->rx_function=z8530_null_rx;
1423 c->tx_next_skb=NULL;
1427 c->status=read_zsreg(c, R0);
1429 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
1431 spin_unlock_irqrestore(c->lock, flags);
1435 EXPORT_SYMBOL(z8530_channel_load);
1439 * z8530_tx_begin - Begin packet transmission
1440 * @c: The Z8530 channel to kick
1442 * This is the speed sensitive side of transmission. If we are called
1443 * and no buffer is being transmitted we commence the next buffer. If
1444 * nothing is queued we idle the sync.
1446 * Note: We are handling this code path in the interrupt path, keep it
1447 * fast or bad things will happen.
1449 * Called with the lock held.
1452 static void z8530_tx_begin(struct z8530_channel *c)
1454 unsigned long flags;
1458 c->tx_skb=c->tx_next_skb;
1459 c->tx_next_skb=NULL;
1460 c->tx_ptr=c->tx_next_ptr;
1467 flags=claim_dma_lock();
1468 disable_dma(c->txdma);
1470 * Check if we crapped out.
1472 if(get_dma_residue(c->txdma))
1474 c->stats.tx_dropped++;
1475 c->stats.tx_fifo_errors++;
1477 release_dma_lock(flags);
1483 c->txcount=c->tx_skb->len;
1489 * FIXME. DMA is broken for the original 8530,
1490 * on the older parts we need to set a flag and
1491 * wait for a further TX interrupt to fire this
1495 flags=claim_dma_lock();
1496 disable_dma(c->txdma);
1499 * These two are needed by the 8530/85C30
1500 * and must be issued when idling.
1503 if(c->dev->type!=Z85230)
1505 write_zsctrl(c, RES_Tx_CRC);
1506 write_zsctrl(c, RES_EOM_L);
1508 write_zsreg(c, R10, c->regs[10]&~ABUNDER);
1509 clear_dma_ff(c->txdma);
1510 set_dma_addr(c->txdma, virt_to_bus(c->tx_ptr));
1511 set_dma_count(c->txdma, c->txcount);
1512 enable_dma(c->txdma);
1513 release_dma_lock(flags);
1514 write_zsctrl(c, RES_EOM_L);
1515 write_zsreg(c, R5, c->regs[R5]|TxENAB);
1521 write_zsreg(c, R10, c->regs[10]);
1522 write_zsctrl(c, RES_Tx_CRC);
1524 while(c->txcount && (read_zsreg(c,R0)&Tx_BUF_EMP))
1526 write_zsreg(c, R8, *c->tx_ptr++);
1533 * Since we emptied tx_skb we can ask for more
1535 netif_wake_queue(c->netdevice);
1539 * z8530_tx_done - TX complete callback
1540 * @c: The channel that completed a transmit.
1542 * This is called when we complete a packet send. We wake the queue,
1543 * start the next packet going and then free the buffer of the existing
1544 * packet. This code is fairly timing sensitive.
1546 * Called with the register lock held.
1549 static void z8530_tx_done(struct z8530_channel *c)
1551 struct sk_buff *skb;
1553 /* Actually this can happen.*/
1560 c->stats.tx_packets++;
1561 c->stats.tx_bytes+=skb->len;
1562 dev_kfree_skb_irq(skb);
1566 * z8530_null_rx - Discard a packet
1567 * @c: The channel the packet arrived on
1570 * We point the receive handler at this function when idle. Instead
1571 * of syncppp processing the frames we get to throw them away.
1574 void z8530_null_rx(struct z8530_channel *c, struct sk_buff *skb)
1576 dev_kfree_skb_any(skb);
1579 EXPORT_SYMBOL(z8530_null_rx);
1582 * z8530_rx_done - Receive completion callback
1583 * @c: The channel that completed a receive
1585 * A new packet is complete. Our goal here is to get back into receive
1586 * mode as fast as possible. On the Z85230 we could change to using
1587 * ESCC mode, but on the older chips we have no choice. We flip to the
1588 * new buffer immediately in DMA mode so that the DMA of the next
1589 * frame can occur while we are copying the previous buffer to an sk_buff
1591 * Called with the lock held
1594 static void z8530_rx_done(struct z8530_channel *c)
1596 struct sk_buff *skb;
1600 * Is our receive engine in DMA mode
1606 * Save the ready state and the buffer currently
1607 * being used as the DMA target
1610 int ready=c->dma_ready;
1611 unsigned char *rxb=c->rx_buf[c->dma_num];
1612 unsigned long flags;
1615 * Complete this DMA. Neccessary to find the length
1618 flags=claim_dma_lock();
1620 disable_dma(c->rxdma);
1621 clear_dma_ff(c->rxdma);
1623 ct=c->mtu-get_dma_residue(c->rxdma);
1625 ct=2; /* Shit happens.. */
1629 * Normal case: the other slot is free, start the next DMA
1630 * into it immediately.
1636 set_dma_mode(c->rxdma, DMA_MODE_READ|0x10);
1637 set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[c->dma_num]));
1638 set_dma_count(c->rxdma, c->mtu);
1640 enable_dma(c->rxdma);
1641 /* Stop any frames that we missed the head of
1643 write_zsreg(c, R0, RES_Rx_CRC);
1646 /* Can't occur as we dont reenable the DMA irq until
1647 after the flip is done */
1648 printk(KERN_WARNING "%s: DMA flip overrun!\n", c->netdevice->name);
1650 release_dma_lock(flags);
1653 * Shove the old buffer into an sk_buff. We can't DMA
1654 * directly into one on a PC - it might be above the 16Mb
1655 * boundary. Optimisation - we could check to see if we
1656 * can avoid the copy. Optimisation 2 - make the memcpy
1660 skb=dev_alloc_skb(ct);
1663 c->stats.rx_dropped++;
1664 printk(KERN_WARNING "%s: Memory squeeze.\n", c->netdevice->name);
1669 memcpy(skb->data, rxb, ct);
1670 c->stats.rx_packets++;
1671 c->stats.rx_bytes+=ct;
1681 * The game we play for non DMA is similar. We want to
1682 * get the controller set up for the next packet as fast
1683 * as possible. We potentially only have one byte + the
1684 * fifo length for this. Thus we want to flip to the new
1685 * buffer and then mess around copying and allocating
1686 * things. For the current case it doesn't matter but
1687 * if you build a system where the sync irq isnt blocked
1688 * by the kernel IRQ disable then you need only block the
1689 * sync IRQ for the RT_LOCK area.
1699 c->dptr = c->skb->data;
1709 c->skb2 = dev_alloc_skb(c->mtu);
1711 printk(KERN_WARNING "%s: memory squeeze.\n",
1712 c->netdevice->name);
1715 skb_put(c->skb2,c->mtu);
1717 c->stats.rx_packets++;
1718 c->stats.rx_bytes+=ct;
1722 * If we received a frame we must now process it.
1727 c->rx_function(c,skb);
1731 c->stats.rx_dropped++;
1732 printk(KERN_ERR "%s: Lost a frame\n", c->netdevice->name);
1737 * spans_boundary - Check a packet can be ISA DMA'd
1738 * @skb: The buffer to check
1740 * Returns true if the buffer cross a DMA boundary on a PC. The poor
1741 * thing can only DMA within a 64K block not across the edges of it.
1744 static inline int spans_boundary(struct sk_buff *skb)
1746 unsigned long a=(unsigned long)skb->data;
1748 if(a&0x00010000) /* If the 64K bit is different.. */
1754 * z8530_queue_xmit - Queue a packet
1755 * @c: The channel to use
1756 * @skb: The packet to kick down the channel
1758 * Queue a packet for transmission. Because we have rather
1759 * hard to hit interrupt latencies for the Z85230 per packet
1760 * even in DMA mode we do the flip to DMA buffer if needed here
1763 * Called from the network code. The lock is not held at this
1767 int z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb)
1769 unsigned long flags;
1771 netif_stop_queue(c->netdevice);
1777 /* PC SPECIFIC - DMA limits */
1780 * If we will DMA the transmit and its gone over the ISA bus
1781 * limit, then copy to the flip buffer
1784 if(c->dma_tx && ((unsigned long)(virt_to_bus(skb->data+skb->len))>=16*1024*1024 || spans_boundary(skb)))
1787 * Send the flip buffer, and flip the flippy bit.
1788 * We don't care which is used when just so long as
1789 * we never use the same buffer twice in a row. Since
1790 * only one buffer can be going out at a time the other
1793 c->tx_next_ptr=c->tx_dma_buf[c->tx_dma_used];
1794 c->tx_dma_used^=1; /* Flip temp buffer */
1795 memcpy(c->tx_next_ptr, skb->data, skb->len);
1798 c->tx_next_ptr=skb->data;
1803 spin_lock_irqsave(c->lock, flags);
1805 spin_unlock_irqrestore(c->lock, flags);
1810 EXPORT_SYMBOL(z8530_queue_xmit);
1813 * z8530_get_stats - Get network statistics
1814 * @c: The channel to use
1816 * Get the statistics block. We keep the statistics in software as
1817 * the chip doesn't do it for us.
1819 * Locking is ignored here - we could lock for a copy but its
1820 * not likely to be that big an issue
1823 struct net_device_stats *z8530_get_stats(struct z8530_channel *c)
1828 EXPORT_SYMBOL(z8530_get_stats);
1833 static char banner[] __initdata = KERN_INFO "Generic Z85C30/Z85230 interface driver v0.02\n";
1835 static int __init z85230_init_driver(void)
1840 module_init(z85230_init_driver);
1842 static void __exit z85230_cleanup_driver(void)
1845 module_exit(z85230_cleanup_driver);
1847 MODULE_AUTHOR("Red Hat Inc.");
1848 MODULE_DESCRIPTION("Z85x30 synchronous driver core");
1849 MODULE_LICENSE("GPL");