3 Broadcom BCM43xx wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Stefano Brivio <st3@riseup.net>
7 Michael Buesch <mbuesch@freenet.de>
8 Danny van Dyk <kugelfang@gentoo.org>
9 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <net/iw_handler.h>
45 #include "bcm43xx_main.h"
46 #include "bcm43xx_debugfs.h"
47 #include "bcm43xx_radio.h"
48 #include "bcm43xx_phy.h"
49 #include "bcm43xx_dma.h"
50 #include "bcm43xx_pio.h"
51 #include "bcm43xx_power.h"
52 #include "bcm43xx_wx.h"
53 #include "bcm43xx_ethtool.h"
54 #include "bcm43xx_xmit.h"
55 #include "bcm43xx_sysfs.h"
58 MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
59 MODULE_AUTHOR("Martin Langer");
60 MODULE_AUTHOR("Stefano Brivio");
61 MODULE_AUTHOR("Michael Buesch");
62 MODULE_LICENSE("GPL");
64 #ifdef CONFIG_BCM947XX
65 extern char *nvram_get(char *name);
68 #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
69 static int modparam_pio;
70 module_param_named(pio, modparam_pio, int, 0444);
71 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
72 #elif defined(CONFIG_BCM43XX_DMA)
73 # define modparam_pio 0
74 #elif defined(CONFIG_BCM43XX_PIO)
75 # define modparam_pio 1
78 static int modparam_bad_frames_preempt;
79 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
80 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames Preemption");
82 static int modparam_short_retry = BCM43xx_DEFAULT_SHORT_RETRY_LIMIT;
83 module_param_named(short_retry, modparam_short_retry, int, 0444);
84 MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
86 static int modparam_long_retry = BCM43xx_DEFAULT_LONG_RETRY_LIMIT;
87 module_param_named(long_retry, modparam_long_retry, int, 0444);
88 MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
90 static int modparam_locale = -1;
91 module_param_named(locale, modparam_locale, int, 0444);
92 MODULE_PARM_DESC(country, "Select LocaleCode 0-11 (For travelers)");
94 static int modparam_noleds;
95 module_param_named(noleds, modparam_noleds, int, 0444);
96 MODULE_PARM_DESC(noleds, "Turn off all LED activity");
98 #ifdef CONFIG_BCM43XX_DEBUG
99 static char modparam_fwpostfix[64];
100 module_param_string(fwpostfix, modparam_fwpostfix, 64, 0444);
101 MODULE_PARM_DESC(fwpostfix, "Postfix for .fw files. Useful for debugging.");
103 # define modparam_fwpostfix ""
104 #endif /* CONFIG_BCM43XX_DEBUG*/
107 /* If you want to debug with just a single device, enable this,
108 * where the string is the pci device ID (as given by the kernel's
109 * pci_name function) of the device to be used.
111 //#define DEBUG_SINGLE_DEVICE_ONLY "0001:11:00.0"
113 /* If you want to enable printing of each MMIO access, enable this. */
114 //#define DEBUG_ENABLE_MMIO_PRINT
116 /* If you want to enable printing of MMIO access within
117 * ucode/pcm upload, initvals write, enable this.
119 //#define DEBUG_ENABLE_UCODE_MMIO_PRINT
121 /* If you want to enable printing of PCI Config Space access, enable this */
122 //#define DEBUG_ENABLE_PCILOG
125 /* Detailed list maintained at:
126 * http://openfacts.berlios.de/index-en.phtml?title=Bcm43xxDevices
128 static struct pci_device_id bcm43xx_pci_tbl[] = {
129 /* Broadcom 4303 802.11b */
130 { PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 /* Broadcom 4307 802.11b */
132 { PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 /* Broadcom 4318 802.11b/g */
134 { PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 /* Broadcom 4319 802.11a/b/g */
136 { PCI_VENDOR_ID_BROADCOM, 0x4319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 /* Broadcom 4306 802.11b/g */
138 { PCI_VENDOR_ID_BROADCOM, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 /* Broadcom 4306 802.11a */
140 // { PCI_VENDOR_ID_BROADCOM, 0x4321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 /* Broadcom 4309 802.11a/b/g */
142 { PCI_VENDOR_ID_BROADCOM, 0x4324, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
143 /* Broadcom 43XG 802.11b/g */
144 { PCI_VENDOR_ID_BROADCOM, 0x4325, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
145 #ifdef CONFIG_BCM947XX
146 /* SB bus on BCM947xx */
147 { PCI_VENDOR_ID_BROADCOM, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
151 MODULE_DEVICE_TABLE(pci, bcm43xx_pci_tbl);
153 static void bcm43xx_ram_write(struct bcm43xx_private *bcm, u16 offset, u32 val)
157 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
158 if (!(status & BCM43xx_SBF_XFER_REG_BYTESWAP))
161 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_CONTROL, offset);
163 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_DATA, val);
167 void bcm43xx_shm_control_word(struct bcm43xx_private *bcm,
168 u16 routing, u16 offset)
172 /* "offset" is the WORD offset. */
177 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_CONTROL, control);
180 u32 bcm43xx_shm_read32(struct bcm43xx_private *bcm,
181 u16 routing, u16 offset)
185 if (routing == BCM43xx_SHM_SHARED) {
186 if (offset & 0x0003) {
187 /* Unaligned access */
188 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
189 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
191 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
192 ret |= bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
198 bcm43xx_shm_control_word(bcm, routing, offset);
199 ret = bcm43xx_read32(bcm, BCM43xx_MMIO_SHM_DATA);
204 u16 bcm43xx_shm_read16(struct bcm43xx_private *bcm,
205 u16 routing, u16 offset)
209 if (routing == BCM43xx_SHM_SHARED) {
210 if (offset & 0x0003) {
211 /* Unaligned access */
212 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
213 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
219 bcm43xx_shm_control_word(bcm, routing, offset);
220 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
225 void bcm43xx_shm_write32(struct bcm43xx_private *bcm,
226 u16 routing, u16 offset,
229 if (routing == BCM43xx_SHM_SHARED) {
230 if (offset & 0x0003) {
231 /* Unaligned access */
232 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
234 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
235 (value >> 16) & 0xffff);
237 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
239 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA,
245 bcm43xx_shm_control_word(bcm, routing, offset);
247 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, value);
250 void bcm43xx_shm_write16(struct bcm43xx_private *bcm,
251 u16 routing, u16 offset,
254 if (routing == BCM43xx_SHM_SHARED) {
255 if (offset & 0x0003) {
256 /* Unaligned access */
257 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
259 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
265 bcm43xx_shm_control_word(bcm, routing, offset);
267 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA, value);
270 void bcm43xx_tsf_read(struct bcm43xx_private *bcm, u64 *tsf)
272 /* We need to be careful. As we read the TSF from multiple
273 * registers, we should take care of register overflows.
274 * In theory, the whole tsf read process should be atomic.
275 * We try to be atomic here, by restaring the read process,
276 * if any of the high registers changed (overflew).
278 if (bcm->current_core->rev >= 3) {
279 u32 low, high, high2;
282 high = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
283 low = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW);
284 high2 = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
285 } while (unlikely(high != high2));
293 u16 test1, test2, test3;
296 v3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
297 v2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
298 v1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
299 v0 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_0);
301 test3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
302 test2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
303 test1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
304 } while (v3 != test3 || v2 != test2 || v1 != test1);
318 void bcm43xx_tsf_write(struct bcm43xx_private *bcm, u64 tsf)
322 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
323 status |= BCM43xx_SBF_TIME_UPDATE;
324 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
327 /* Be careful with the in-progress timer.
328 * First zero out the low register, so we have a full
329 * register-overflow duration to complete the operation.
331 if (bcm->current_core->rev >= 3) {
332 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
333 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
335 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, 0);
337 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH, hi);
339 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, lo);
341 u16 v0 = (tsf & 0x000000000000FFFFULL);
342 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
343 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
344 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
346 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, 0);
348 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_3, v3);
350 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_2, v2);
352 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_1, v1);
354 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, v0);
357 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
358 status &= ~BCM43xx_SBF_TIME_UPDATE;
359 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
363 void bcm43xx_macfilter_set(struct bcm43xx_private *bcm,
370 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_CONTROL, offset);
374 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
377 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
380 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
383 static void bcm43xx_macfilter_clear(struct bcm43xx_private *bcm,
386 const u8 zero_addr[ETH_ALEN] = { 0 };
388 bcm43xx_macfilter_set(bcm, offset, zero_addr);
391 static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_private *bcm)
393 const u8 *mac = (const u8 *)(bcm->net_dev->dev_addr);
394 const u8 *bssid = (const u8 *)(bcm->ieee->bssid);
395 u8 mac_bssid[ETH_ALEN * 2];
398 memcpy(mac_bssid, mac, ETH_ALEN);
399 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
401 /* Write our MAC address and BSSID to template ram */
402 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
403 bcm43xx_ram_write(bcm, 0x20 + i, *((u32 *)(mac_bssid + i)));
404 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
405 bcm43xx_ram_write(bcm, 0x78 + i, *((u32 *)(mac_bssid + i)));
406 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
407 bcm43xx_ram_write(bcm, 0x478 + i, *((u32 *)(mac_bssid + i)));
410 //FIXME: Well, we should probably call them from somewhere.
412 static void bcm43xx_set_slot_time(struct bcm43xx_private *bcm, u16 slot_time)
414 /* slot_time is in usec. */
415 if (bcm43xx_current_phy(bcm)->type != BCM43xx_PHYTYPE_G)
417 bcm43xx_write16(bcm, 0x684, 510 + slot_time);
418 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0010, slot_time);
421 static void bcm43xx_short_slot_timing_enable(struct bcm43xx_private *bcm)
423 bcm43xx_set_slot_time(bcm, 9);
426 static void bcm43xx_short_slot_timing_disable(struct bcm43xx_private *bcm)
428 bcm43xx_set_slot_time(bcm, 20);
432 /* FIXME: To get the MAC-filter working, we need to implement the
433 * following functions (and rename them :)
436 static void bcm43xx_disassociate(struct bcm43xx_private *bcm)
438 bcm43xx_mac_suspend(bcm);
439 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
441 bcm43xx_ram_write(bcm, 0x0026, 0x0000);
442 bcm43xx_ram_write(bcm, 0x0028, 0x0000);
443 bcm43xx_ram_write(bcm, 0x007E, 0x0000);
444 bcm43xx_ram_write(bcm, 0x0080, 0x0000);
445 bcm43xx_ram_write(bcm, 0x047E, 0x0000);
446 bcm43xx_ram_write(bcm, 0x0480, 0x0000);
448 if (bcm->current_core->rev < 3) {
449 bcm43xx_write16(bcm, 0x0610, 0x8000);
450 bcm43xx_write16(bcm, 0x060E, 0x0000);
452 bcm43xx_write32(bcm, 0x0188, 0x80000000);
454 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
456 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G &&
457 ieee80211_is_ofdm_rate(bcm->softmac->txrates.default_rate))
458 bcm43xx_short_slot_timing_enable(bcm);
460 bcm43xx_mac_enable(bcm);
463 static void bcm43xx_associate(struct bcm43xx_private *bcm,
466 memcpy(bcm->ieee->bssid, mac, ETH_ALEN);
468 bcm43xx_mac_suspend(bcm);
469 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_ASSOC, mac);
470 bcm43xx_write_mac_bssid_templates(bcm);
471 bcm43xx_mac_enable(bcm);
475 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
476 * Returns the _previously_ enabled IRQ mask.
478 static inline u32 bcm43xx_interrupt_enable(struct bcm43xx_private *bcm, u32 mask)
482 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
483 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask | mask);
488 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
489 * Returns the _previously_ enabled IRQ mask.
491 static inline u32 bcm43xx_interrupt_disable(struct bcm43xx_private *bcm, u32 mask)
495 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
496 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
501 /* Synchronize IRQ top- and bottom-half.
502 * IRQs must be masked before calling this.
503 * This must not be called with the irq_lock held.
505 static void bcm43xx_synchronize_irq(struct bcm43xx_private *bcm)
507 synchronize_irq(bcm->irq);
508 tasklet_disable(&bcm->isr_tasklet);
511 /* Make sure we don't receive more data from the device. */
512 static int bcm43xx_disable_interrupts_sync(struct bcm43xx_private *bcm)
516 spin_lock_irqsave(&bcm->irq_lock, flags);
517 if (unlikely(bcm43xx_status(bcm) != BCM43xx_STAT_INITIALIZED)) {
518 spin_unlock_irqrestore(&bcm->irq_lock, flags);
521 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
522 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK); /* flush */
523 spin_unlock_irqrestore(&bcm->irq_lock, flags);
524 bcm43xx_synchronize_irq(bcm);
529 static int bcm43xx_read_radioinfo(struct bcm43xx_private *bcm)
531 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
532 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
538 if (bcm->chip_id == 0x4317) {
539 if (bcm->chip_rev == 0x00)
540 radio_id = 0x3205017F;
541 else if (bcm->chip_rev == 0x01)
542 radio_id = 0x4205017F;
544 radio_id = 0x5205017F;
546 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
547 radio_id = bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_HIGH);
549 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
550 radio_id |= bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_LOW);
553 manufact = (radio_id & 0x00000FFF);
554 version = (radio_id & 0x0FFFF000) >> 12;
555 revision = (radio_id & 0xF0000000) >> 28;
557 dprintk(KERN_INFO PFX "Detected Radio: ID: %x (Manuf: %x Ver: %x Rev: %x)\n",
558 radio_id, manufact, version, revision);
561 case BCM43xx_PHYTYPE_A:
562 if ((version != 0x2060) || (revision != 1) || (manufact != 0x17f))
563 goto err_unsupported_radio;
565 case BCM43xx_PHYTYPE_B:
566 if ((version & 0xFFF0) != 0x2050)
567 goto err_unsupported_radio;
569 case BCM43xx_PHYTYPE_G:
570 if (version != 0x2050)
571 goto err_unsupported_radio;
575 radio->manufact = manufact;
576 radio->version = version;
577 radio->revision = revision;
579 if (phy->type == BCM43xx_PHYTYPE_A)
580 radio->txpower_desired = bcm->sprom.maxpower_aphy;
582 radio->txpower_desired = bcm->sprom.maxpower_bgphy;
586 err_unsupported_radio:
587 printk(KERN_ERR PFX "Unsupported Radio connected to the PHY!\n");
591 static const char * bcm43xx_locale_iso(u8 locale)
593 /* ISO 3166-1 country codes.
594 * Note that there aren't ISO 3166-1 codes for
595 * all or locales. (Not all locales are countries)
598 case BCM43xx_LOCALE_WORLD:
599 case BCM43xx_LOCALE_ALL:
601 case BCM43xx_LOCALE_THAILAND:
603 case BCM43xx_LOCALE_ISRAEL:
605 case BCM43xx_LOCALE_JORDAN:
607 case BCM43xx_LOCALE_CHINA:
609 case BCM43xx_LOCALE_JAPAN:
610 case BCM43xx_LOCALE_JAPAN_HIGH:
612 case BCM43xx_LOCALE_USA_CANADA_ANZ:
613 case BCM43xx_LOCALE_USA_LOW:
615 case BCM43xx_LOCALE_EUROPE:
617 case BCM43xx_LOCALE_NONE:
624 static const char * bcm43xx_locale_string(u8 locale)
627 case BCM43xx_LOCALE_WORLD:
629 case BCM43xx_LOCALE_THAILAND:
631 case BCM43xx_LOCALE_ISRAEL:
633 case BCM43xx_LOCALE_JORDAN:
635 case BCM43xx_LOCALE_CHINA:
637 case BCM43xx_LOCALE_JAPAN:
639 case BCM43xx_LOCALE_USA_CANADA_ANZ:
640 return "USA/Canada/ANZ";
641 case BCM43xx_LOCALE_EUROPE:
643 case BCM43xx_LOCALE_USA_LOW:
645 case BCM43xx_LOCALE_JAPAN_HIGH:
647 case BCM43xx_LOCALE_ALL:
649 case BCM43xx_LOCALE_NONE:
656 static inline u8 bcm43xx_crc8(u8 crc, u8 data)
658 static const u8 t[] = {
659 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
660 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
661 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
662 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
663 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
664 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
665 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
666 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
667 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
668 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
669 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
670 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
671 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
672 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
673 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
674 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
675 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
676 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
677 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
678 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
679 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
680 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
681 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
682 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
683 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
684 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
685 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
686 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
687 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
688 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
689 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
690 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
692 return t[crc ^ data];
695 static u8 bcm43xx_sprom_crc(const u16 *sprom)
700 for (word = 0; word < BCM43xx_SPROM_SIZE - 1; word++) {
701 crc = bcm43xx_crc8(crc, sprom[word] & 0x00FF);
702 crc = bcm43xx_crc8(crc, (sprom[word] & 0xFF00) >> 8);
704 crc = bcm43xx_crc8(crc, sprom[BCM43xx_SPROM_VERSION] & 0x00FF);
710 int bcm43xx_sprom_read(struct bcm43xx_private *bcm, u16 *sprom)
713 u8 crc, expected_crc;
715 for (i = 0; i < BCM43xx_SPROM_SIZE; i++)
716 sprom[i] = bcm43xx_read16(bcm, BCM43xx_SPROM_BASE + (i * 2));
718 crc = bcm43xx_sprom_crc(sprom);
719 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
720 if (crc != expected_crc) {
721 printk(KERN_WARNING PFX "WARNING: Invalid SPROM checksum "
722 "(0x%02X, expected: 0x%02X)\n",
730 int bcm43xx_sprom_write(struct bcm43xx_private *bcm, const u16 *sprom)
733 u8 crc, expected_crc;
736 /* CRC-8 validation of the input data. */
737 crc = bcm43xx_sprom_crc(sprom);
738 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
739 if (crc != expected_crc) {
740 printk(KERN_ERR PFX "SPROM input data: Invalid CRC\n");
744 printk(KERN_INFO PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
745 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_SPROMCTL, &spromctl);
748 spromctl |= 0x10; /* SPROM WRITE enable. */
749 bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
752 /* We must burn lots of CPU cycles here, but that does not
753 * really matter as one does not write the SPROM every other minute...
755 printk(KERN_INFO PFX "[ 0%%");
757 for (i = 0; i < BCM43xx_SPROM_SIZE; i++) {
766 bcm43xx_write16(bcm, BCM43xx_SPROM_BASE + (i * 2), sprom[i]);
770 spromctl &= ~0x10; /* SPROM WRITE enable. */
771 bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
776 printk(KERN_INFO PFX "SPROM written.\n");
777 bcm43xx_controller_restart(bcm, "SPROM update");
781 printk(KERN_ERR PFX "Could not access SPROM control register.\n");
785 static int bcm43xx_sprom_extract(struct bcm43xx_private *bcm)
789 #ifdef CONFIG_BCM947XX
793 sprom = kzalloc(BCM43xx_SPROM_SIZE * sizeof(u16),
796 printk(KERN_ERR PFX "sprom_extract OOM\n");
799 #ifdef CONFIG_BCM947XX
800 sprom[BCM43xx_SPROM_BOARDFLAGS2] = atoi(nvram_get("boardflags2"));
801 sprom[BCM43xx_SPROM_BOARDFLAGS] = atoi(nvram_get("boardflags"));
803 if ((c = nvram_get("il0macaddr")) != NULL)
804 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_IL0MACADDR]));
806 if ((c = nvram_get("et1macaddr")) != NULL)
807 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_ET1MACADDR]));
809 sprom[BCM43xx_SPROM_PA0B0] = atoi(nvram_get("pa0b0"));
810 sprom[BCM43xx_SPROM_PA0B1] = atoi(nvram_get("pa0b1"));
811 sprom[BCM43xx_SPROM_PA0B2] = atoi(nvram_get("pa0b2"));
813 sprom[BCM43xx_SPROM_PA1B0] = atoi(nvram_get("pa1b0"));
814 sprom[BCM43xx_SPROM_PA1B1] = atoi(nvram_get("pa1b1"));
815 sprom[BCM43xx_SPROM_PA1B2] = atoi(nvram_get("pa1b2"));
817 sprom[BCM43xx_SPROM_BOARDREV] = atoi(nvram_get("boardrev"));
819 bcm43xx_sprom_read(bcm, sprom);
823 value = sprom[BCM43xx_SPROM_BOARDFLAGS2];
824 bcm->sprom.boardflags2 = value;
827 value = sprom[BCM43xx_SPROM_IL0MACADDR + 0];
828 *(((u16 *)bcm->sprom.il0macaddr) + 0) = cpu_to_be16(value);
829 value = sprom[BCM43xx_SPROM_IL0MACADDR + 1];
830 *(((u16 *)bcm->sprom.il0macaddr) + 1) = cpu_to_be16(value);
831 value = sprom[BCM43xx_SPROM_IL0MACADDR + 2];
832 *(((u16 *)bcm->sprom.il0macaddr) + 2) = cpu_to_be16(value);
835 value = sprom[BCM43xx_SPROM_ET0MACADDR + 0];
836 *(((u16 *)bcm->sprom.et0macaddr) + 0) = cpu_to_be16(value);
837 value = sprom[BCM43xx_SPROM_ET0MACADDR + 1];
838 *(((u16 *)bcm->sprom.et0macaddr) + 1) = cpu_to_be16(value);
839 value = sprom[BCM43xx_SPROM_ET0MACADDR + 2];
840 *(((u16 *)bcm->sprom.et0macaddr) + 2) = cpu_to_be16(value);
843 value = sprom[BCM43xx_SPROM_ET1MACADDR + 0];
844 *(((u16 *)bcm->sprom.et1macaddr) + 0) = cpu_to_be16(value);
845 value = sprom[BCM43xx_SPROM_ET1MACADDR + 1];
846 *(((u16 *)bcm->sprom.et1macaddr) + 1) = cpu_to_be16(value);
847 value = sprom[BCM43xx_SPROM_ET1MACADDR + 2];
848 *(((u16 *)bcm->sprom.et1macaddr) + 2) = cpu_to_be16(value);
850 /* ethernet phy settings */
851 value = sprom[BCM43xx_SPROM_ETHPHY];
852 bcm->sprom.et0phyaddr = (value & 0x001F);
853 bcm->sprom.et1phyaddr = (value & 0x03E0) >> 5;
854 bcm->sprom.et0mdcport = (value & (1 << 14)) >> 14;
855 bcm->sprom.et1mdcport = (value & (1 << 15)) >> 15;
857 /* boardrev, antennas, locale */
858 value = sprom[BCM43xx_SPROM_BOARDREV];
859 bcm->sprom.boardrev = (value & 0x00FF);
860 bcm->sprom.locale = (value & 0x0F00) >> 8;
861 bcm->sprom.antennas_aphy = (value & 0x3000) >> 12;
862 bcm->sprom.antennas_bgphy = (value & 0xC000) >> 14;
863 if (modparam_locale != -1) {
864 if (modparam_locale >= 0 && modparam_locale <= 11) {
865 bcm->sprom.locale = modparam_locale;
866 printk(KERN_WARNING PFX "Operating with modified "
867 "LocaleCode %u (%s)\n",
869 bcm43xx_locale_string(bcm->sprom.locale));
871 printk(KERN_WARNING PFX "Module parameter \"locale\" "
872 "invalid value. (0 - 11)\n");
877 value = sprom[BCM43xx_SPROM_PA0B0];
878 bcm->sprom.pa0b0 = value;
879 value = sprom[BCM43xx_SPROM_PA0B1];
880 bcm->sprom.pa0b1 = value;
881 value = sprom[BCM43xx_SPROM_PA0B2];
882 bcm->sprom.pa0b2 = value;
885 value = sprom[BCM43xx_SPROM_WL0GPIO0];
888 bcm->sprom.wl0gpio0 = value & 0x00FF;
889 bcm->sprom.wl0gpio1 = (value & 0xFF00) >> 8;
890 value = sprom[BCM43xx_SPROM_WL0GPIO2];
893 bcm->sprom.wl0gpio2 = value & 0x00FF;
894 bcm->sprom.wl0gpio3 = (value & 0xFF00) >> 8;
897 value = sprom[BCM43xx_SPROM_MAXPWR];
898 bcm->sprom.maxpower_aphy = (value & 0xFF00) >> 8;
899 bcm->sprom.maxpower_bgphy = value & 0x00FF;
902 value = sprom[BCM43xx_SPROM_PA1B0];
903 bcm->sprom.pa1b0 = value;
904 value = sprom[BCM43xx_SPROM_PA1B1];
905 bcm->sprom.pa1b1 = value;
906 value = sprom[BCM43xx_SPROM_PA1B2];
907 bcm->sprom.pa1b2 = value;
909 /* idle tssi target */
910 value = sprom[BCM43xx_SPROM_IDL_TSSI_TGT];
911 bcm->sprom.idle_tssi_tgt_aphy = value & 0x00FF;
912 bcm->sprom.idle_tssi_tgt_bgphy = (value & 0xFF00) >> 8;
915 value = sprom[BCM43xx_SPROM_BOARDFLAGS];
918 bcm->sprom.boardflags = value;
919 /* boardflags workarounds */
920 if (bcm->board_vendor == PCI_VENDOR_ID_DELL &&
921 bcm->chip_id == 0x4301 &&
922 bcm->board_revision == 0x74)
923 bcm->sprom.boardflags |= BCM43xx_BFL_BTCOEXIST;
924 if (bcm->board_vendor == PCI_VENDOR_ID_APPLE &&
925 bcm->board_type == 0x4E &&
926 bcm->board_revision > 0x40)
927 bcm->sprom.boardflags |= BCM43xx_BFL_PACTRL;
930 value = sprom[BCM43xx_SPROM_ANTENNA_GAIN];
931 if (value == 0x0000 || value == 0xFFFF)
933 /* convert values to Q5.2 */
934 bcm->sprom.antennagain_aphy = ((value & 0xFF00) >> 8) * 4;
935 bcm->sprom.antennagain_bgphy = (value & 0x00FF) * 4;
942 static int bcm43xx_geo_init(struct bcm43xx_private *bcm)
944 struct ieee80211_geo *geo;
945 struct ieee80211_channel *chan;
946 int have_a = 0, have_bg = 0;
949 struct bcm43xx_phyinfo *phy;
950 const char *iso_country;
952 geo = kzalloc(sizeof(*geo), GFP_KERNEL);
956 for (i = 0; i < bcm->nr_80211_available; i++) {
957 phy = &(bcm->core_80211_ext[i].phy);
959 case BCM43xx_PHYTYPE_B:
960 case BCM43xx_PHYTYPE_G:
963 case BCM43xx_PHYTYPE_A:
970 iso_country = bcm43xx_locale_iso(bcm->sprom.locale);
973 for (i = 0, channel = IEEE80211_52GHZ_MIN_CHANNEL;
974 channel <= IEEE80211_52GHZ_MAX_CHANNEL; channel++) {
976 chan->freq = bcm43xx_channel_to_freq_a(channel);
977 chan->channel = channel;
982 for (i = 0, channel = IEEE80211_24GHZ_MIN_CHANNEL;
983 channel <= IEEE80211_24GHZ_MAX_CHANNEL; channel++) {
984 chan = &geo->bg[i++];
985 chan->freq = bcm43xx_channel_to_freq_bg(channel);
986 chan->channel = channel;
988 geo->bg_channels = i;
990 memcpy(geo->name, iso_country, 2);
991 if (0 /*TODO: Outdoor use only */)
993 else if (0 /*TODO: Indoor use only */)
999 ieee80211_set_geo(bcm->ieee, geo);
1005 /* DummyTransmission function, as documented on
1006 * http://bcm-specs.sipsolutions.net/DummyTransmission
1008 void bcm43xx_dummy_transmission(struct bcm43xx_private *bcm)
1010 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1011 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1012 unsigned int i, max_loop;
1022 switch (phy->type) {
1023 case BCM43xx_PHYTYPE_A:
1025 buffer[0] = 0xCC010200;
1027 case BCM43xx_PHYTYPE_B:
1028 case BCM43xx_PHYTYPE_G:
1030 buffer[0] = 0x6E840B00;
1037 for (i = 0; i < 5; i++)
1038 bcm43xx_ram_write(bcm, i * 4, buffer[i]);
1040 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
1042 bcm43xx_write16(bcm, 0x0568, 0x0000);
1043 bcm43xx_write16(bcm, 0x07C0, 0x0000);
1044 bcm43xx_write16(bcm, 0x050C, ((phy->type == BCM43xx_PHYTYPE_A) ? 1 : 0));
1045 bcm43xx_write16(bcm, 0x0508, 0x0000);
1046 bcm43xx_write16(bcm, 0x050A, 0x0000);
1047 bcm43xx_write16(bcm, 0x054C, 0x0000);
1048 bcm43xx_write16(bcm, 0x056A, 0x0014);
1049 bcm43xx_write16(bcm, 0x0568, 0x0826);
1050 bcm43xx_write16(bcm, 0x0500, 0x0000);
1051 bcm43xx_write16(bcm, 0x0502, 0x0030);
1053 if (radio->version == 0x2050 && radio->revision <= 0x5)
1054 bcm43xx_radio_write16(bcm, 0x0051, 0x0017);
1055 for (i = 0x00; i < max_loop; i++) {
1056 value = bcm43xx_read16(bcm, 0x050E);
1061 for (i = 0x00; i < 0x0A; i++) {
1062 value = bcm43xx_read16(bcm, 0x050E);
1067 for (i = 0x00; i < 0x0A; i++) {
1068 value = bcm43xx_read16(bcm, 0x0690);
1069 if (!(value & 0x0100))
1073 if (radio->version == 0x2050 && radio->revision <= 0x5)
1074 bcm43xx_radio_write16(bcm, 0x0051, 0x0037);
1077 static void key_write(struct bcm43xx_private *bcm,
1078 u8 index, u8 algorithm, const u16 *key)
1080 unsigned int i, basic_wep = 0;
1084 /* Write associated key information */
1085 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x100 + (index * 2),
1086 ((index << 4) | (algorithm & 0x0F)));
1088 /* The first 4 WEP keys need extra love */
1089 if (((algorithm == BCM43xx_SEC_ALGO_WEP) ||
1090 (algorithm == BCM43xx_SEC_ALGO_WEP104)) && (index < 4))
1093 /* Write key payload, 8 little endian words */
1094 offset = bcm->security_offset + (index * BCM43xx_SEC_KEYSIZE);
1095 for (i = 0; i < (BCM43xx_SEC_KEYSIZE / sizeof(u16)); i++) {
1096 value = cpu_to_le16(key[i]);
1097 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1098 offset + (i * 2), value);
1103 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1104 offset + (i * 2) + 4 * BCM43xx_SEC_KEYSIZE,
1109 static void keymac_write(struct bcm43xx_private *bcm,
1110 u8 index, const u32 *addr)
1112 /* for keys 0-3 there is no associated mac address */
1117 if (bcm->current_core->rev >= 5) {
1118 bcm43xx_shm_write32(bcm,
1121 cpu_to_be32(*addr));
1122 bcm43xx_shm_write16(bcm,
1125 cpu_to_be16(*((u16 *)(addr + 1))));
1128 TODO(); /* Put them in the macaddress filter */
1131 /* Put them BCM43xx_SHM_SHARED, stating index 0x0120.
1132 Keep in mind to update the count of keymacs in 0x003E as well! */
1137 static int bcm43xx_key_write(struct bcm43xx_private *bcm,
1138 u8 index, u8 algorithm,
1139 const u8 *_key, int key_len,
1142 u8 key[BCM43xx_SEC_KEYSIZE] = { 0 };
1144 if (index >= ARRAY_SIZE(bcm->key))
1146 if (key_len > ARRAY_SIZE(key))
1148 if (algorithm < 1 || algorithm > 5)
1151 memcpy(key, _key, key_len);
1152 key_write(bcm, index, algorithm, (const u16 *)key);
1153 keymac_write(bcm, index, (const u32 *)mac_addr);
1155 bcm->key[index].algorithm = algorithm;
1160 static void bcm43xx_clear_keys(struct bcm43xx_private *bcm)
1162 static const u32 zero_mac[2] = { 0 };
1163 unsigned int i,j, nr_keys = 54;
1166 if (bcm->current_core->rev < 5)
1168 assert(nr_keys <= ARRAY_SIZE(bcm->key));
1170 for (i = 0; i < nr_keys; i++) {
1171 bcm->key[i].enabled = 0;
1172 /* returns for i < 4 immediately */
1173 keymac_write(bcm, i, zero_mac);
1174 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1175 0x100 + (i * 2), 0x0000);
1176 for (j = 0; j < 8; j++) {
1177 offset = bcm->security_offset + (j * 4) + (i * BCM43xx_SEC_KEYSIZE);
1178 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1182 dprintk(KERN_INFO PFX "Keys cleared\n");
1185 /* Lowlevel core-switch function. This is only to be used in
1186 * bcm43xx_switch_core() and bcm43xx_probe_cores()
1188 static int _switch_core(struct bcm43xx_private *bcm, int core)
1196 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1197 (core * 0x1000) + 0x18000000);
1200 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1204 current_core = (current_core - 0x18000000) / 0x1000;
1205 if (current_core == core)
1208 if (unlikely(attempts++ > BCM43xx_SWITCH_CORE_MAX_RETRIES))
1212 #ifdef CONFIG_BCM947XX
1213 if (bcm->pci_dev->bus->number == 0)
1214 bcm->current_core_offset = 0x1000 * core;
1216 bcm->current_core_offset = 0;
1221 printk(KERN_ERR PFX "Failed to switch to core %d\n", core);
1225 int bcm43xx_switch_core(struct bcm43xx_private *bcm, struct bcm43xx_coreinfo *new_core)
1229 if (unlikely(!new_core))
1231 if (!new_core->available)
1233 if (bcm->current_core == new_core)
1235 err = _switch_core(bcm, new_core->index);
1239 bcm->current_core = new_core;
1244 static int bcm43xx_core_enabled(struct bcm43xx_private *bcm)
1248 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1249 value &= BCM43xx_SBTMSTATELOW_CLOCK | BCM43xx_SBTMSTATELOW_RESET
1250 | BCM43xx_SBTMSTATELOW_REJECT;
1252 return (value == BCM43xx_SBTMSTATELOW_CLOCK);
1255 /* disable current core */
1256 static int bcm43xx_core_disable(struct bcm43xx_private *bcm, u32 core_flags)
1262 /* fetch sbtmstatelow from core information registers */
1263 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1265 /* core is already in reset */
1266 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_RESET)
1269 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_CLOCK) {
1270 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1271 BCM43xx_SBTMSTATELOW_REJECT;
1272 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1274 for (i = 0; i < 1000; i++) {
1275 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1276 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_REJECT) {
1283 printk(KERN_ERR PFX "Error: core_disable() REJECT timeout!\n");
1287 for (i = 0; i < 1000; i++) {
1288 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1289 if (!(sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_BUSY)) {
1296 printk(KERN_ERR PFX "Error: core_disable() BUSY timeout!\n");
1300 sbtmstatelow = BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1301 BCM43xx_SBTMSTATELOW_REJECT |
1302 BCM43xx_SBTMSTATELOW_RESET |
1303 BCM43xx_SBTMSTATELOW_CLOCK |
1305 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1309 sbtmstatelow = BCM43xx_SBTMSTATELOW_RESET |
1310 BCM43xx_SBTMSTATELOW_REJECT |
1312 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1315 bcm->current_core->enabled = 0;
1320 /* enable (reset) current core */
1321 static int bcm43xx_core_enable(struct bcm43xx_private *bcm, u32 core_flags)
1328 err = bcm43xx_core_disable(bcm, core_flags);
1332 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1333 BCM43xx_SBTMSTATELOW_RESET |
1334 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1336 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1339 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1340 if (sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_SERROR) {
1341 sbtmstatehigh = 0x00000000;
1342 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATEHIGH, sbtmstatehigh);
1345 sbimstate = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMSTATE);
1346 if (sbimstate & (BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT)) {
1347 sbimstate &= ~(BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT);
1348 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMSTATE, sbimstate);
1351 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1352 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1354 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1357 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK | core_flags;
1358 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1361 bcm->current_core->enabled = 1;
1367 /* http://bcm-specs.sipsolutions.net/80211CoreReset */
1368 void bcm43xx_wireless_core_reset(struct bcm43xx_private *bcm, int connect_phy)
1370 u32 flags = 0x00040000;
1372 if ((bcm43xx_core_enabled(bcm)) &&
1373 !bcm43xx_using_pio(bcm)) {
1374 //FIXME: Do we _really_ want #ifndef CONFIG_BCM947XX here?
1376 #ifndef CONFIG_BCM947XX
1377 /* reset all used DMA controllers. */
1378 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1379 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA2_BASE);
1380 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA3_BASE);
1381 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1382 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1383 if (bcm->current_core->rev < 5)
1384 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1388 if (bcm43xx_status(bcm) == BCM43xx_STAT_SHUTTINGDOWN) {
1389 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1390 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1391 & ~(BCM43xx_SBF_MAC_ENABLED | 0x00000002));
1394 flags |= 0x20000000;
1395 bcm43xx_phy_connect(bcm, connect_phy);
1396 bcm43xx_core_enable(bcm, flags);
1397 bcm43xx_write16(bcm, 0x03E6, 0x0000);
1398 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1399 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1404 static void bcm43xx_wireless_core_disable(struct bcm43xx_private *bcm)
1406 bcm43xx_radio_turn_off(bcm);
1407 bcm43xx_write16(bcm, 0x03E6, 0x00F4);
1408 bcm43xx_core_disable(bcm, 0);
1411 /* Mark the current 80211 core inactive. */
1412 static void bcm43xx_wireless_core_mark_inactive(struct bcm43xx_private *bcm)
1416 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1417 bcm43xx_radio_turn_off(bcm);
1418 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1419 sbtmstatelow &= 0xDFF5FFFF;
1420 sbtmstatelow |= 0x000A0000;
1421 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1423 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1424 sbtmstatelow &= 0xFFF5FFFF;
1425 sbtmstatelow |= 0x00080000;
1426 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1430 static void handle_irq_transmit_status(struct bcm43xx_private *bcm)
1434 struct bcm43xx_xmitstatus stat;
1437 v0 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_0);
1440 v1 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_1);
1442 stat.cookie = (v0 >> 16) & 0x0000FFFF;
1443 tmp = (u16)((v0 & 0xFFF0) | ((v0 & 0xF) >> 1));
1444 stat.flags = tmp & 0xFF;
1445 stat.cnt1 = (tmp & 0x0F00) >> 8;
1446 stat.cnt2 = (tmp & 0xF000) >> 12;
1447 stat.seq = (u16)(v1 & 0xFFFF);
1448 stat.unknown = (u16)((v1 >> 16) & 0xFF);
1450 bcm43xx_debugfs_log_txstat(bcm, &stat);
1452 if (stat.flags & BCM43xx_TXSTAT_FLAG_IGNORE)
1454 if (!(stat.flags & BCM43xx_TXSTAT_FLAG_ACK)) {
1455 //TODO: packet was not acked (was lost)
1457 //TODO: There are more (unknown) flags to test. see bcm43xx_main.h
1459 if (bcm43xx_using_pio(bcm))
1460 bcm43xx_pio_handle_xmitstatus(bcm, &stat);
1462 bcm43xx_dma_handle_xmitstatus(bcm, &stat);
1466 static void bcm43xx_generate_noise_sample(struct bcm43xx_private *bcm)
1468 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x408, 0x7F7F);
1469 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x40A, 0x7F7F);
1470 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1471 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD) | (1 << 4));
1472 assert(bcm->noisecalc.core_at_start == bcm->current_core);
1473 assert(bcm->noisecalc.channel_at_start == bcm43xx_current_radio(bcm)->channel);
1476 static void bcm43xx_calculate_link_quality(struct bcm43xx_private *bcm)
1478 /* Top half of Link Quality calculation. */
1480 if (bcm->noisecalc.calculation_running)
1482 bcm->noisecalc.core_at_start = bcm->current_core;
1483 bcm->noisecalc.channel_at_start = bcm43xx_current_radio(bcm)->channel;
1484 bcm->noisecalc.calculation_running = 1;
1485 bcm->noisecalc.nr_samples = 0;
1487 bcm43xx_generate_noise_sample(bcm);
1490 static void handle_irq_noise(struct bcm43xx_private *bcm)
1492 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1498 /* Bottom half of Link Quality calculation. */
1500 assert(bcm->noisecalc.calculation_running);
1501 if (bcm->noisecalc.core_at_start != bcm->current_core ||
1502 bcm->noisecalc.channel_at_start != radio->channel)
1503 goto drop_calculation;
1504 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x408);
1505 noise[0] = (tmp & 0x00FF);
1506 noise[1] = (tmp & 0xFF00) >> 8;
1507 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40A);
1508 noise[2] = (tmp & 0x00FF);
1509 noise[3] = (tmp & 0xFF00) >> 8;
1510 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1511 noise[2] == 0x7F || noise[3] == 0x7F)
1514 /* Get the noise samples. */
1515 assert(bcm->noisecalc.nr_samples < 8);
1516 i = bcm->noisecalc.nr_samples;
1517 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1518 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1519 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1520 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1521 bcm->noisecalc.samples[i][0] = radio->nrssi_lt[noise[0]];
1522 bcm->noisecalc.samples[i][1] = radio->nrssi_lt[noise[1]];
1523 bcm->noisecalc.samples[i][2] = radio->nrssi_lt[noise[2]];
1524 bcm->noisecalc.samples[i][3] = radio->nrssi_lt[noise[3]];
1525 bcm->noisecalc.nr_samples++;
1526 if (bcm->noisecalc.nr_samples == 8) {
1527 /* Calculate the Link Quality by the noise samples. */
1529 for (i = 0; i < 8; i++) {
1530 for (j = 0; j < 4; j++)
1531 average += bcm->noisecalc.samples[i][j];
1538 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40C);
1539 tmp = (tmp / 128) & 0x1F;
1549 bcm->stats.noise = average;
1551 bcm->noisecalc.calculation_running = 0;
1555 bcm43xx_generate_noise_sample(bcm);
1558 static void handle_irq_ps(struct bcm43xx_private *bcm)
1560 if (bcm->ieee->iw_mode == IW_MODE_MASTER) {
1563 if (1/*FIXME: the last PSpoll frame was sent successfully */)
1564 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
1566 if (bcm->ieee->iw_mode == IW_MODE_ADHOC)
1567 bcm->reg124_set_0x4 = 1;
1568 //FIXME else set to false?
1571 static void handle_irq_reg124(struct bcm43xx_private *bcm)
1573 if (!bcm->reg124_set_0x4)
1575 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1576 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD)
1578 //FIXME: reset reg124_set_0x4 to false?
1581 static void handle_irq_pmq(struct bcm43xx_private *bcm)
1588 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_PS_STATUS);
1589 if (!(tmp & 0x00000008))
1592 /* 16bit write is odd, but correct. */
1593 bcm43xx_write16(bcm, BCM43xx_MMIO_PS_STATUS, 0x0002);
1596 static void bcm43xx_generate_beacon_template(struct bcm43xx_private *bcm,
1597 u16 ram_offset, u16 shm_size_offset)
1603 //FIXME: assumption: The chip sets the timestamp
1605 bcm43xx_ram_write(bcm, ram_offset++, value);
1606 bcm43xx_ram_write(bcm, ram_offset++, value);
1609 /* Beacon Interval / Capability Information */
1610 value = 0x0000;//FIXME: Which interval?
1611 value |= (1 << 0) << 16; /* ESS */
1612 value |= (1 << 2) << 16; /* CF Pollable */ //FIXME?
1613 value |= (1 << 3) << 16; /* CF Poll Request */ //FIXME?
1614 if (!bcm->ieee->open_wep)
1615 value |= (1 << 4) << 16; /* Privacy */
1616 bcm43xx_ram_write(bcm, ram_offset++, value);
1622 /* FH Parameter Set */
1625 /* DS Parameter Set */
1628 /* CF Parameter Set */
1634 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, shm_size_offset, size);
1637 static void handle_irq_beacon(struct bcm43xx_private *bcm)
1641 bcm->irq_savedstate &= ~BCM43xx_IRQ_BEACON;
1642 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD);
1644 if ((status & 0x1) && (status & 0x2)) {
1645 /* ACK beacon IRQ. */
1646 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON,
1647 BCM43xx_IRQ_BEACON);
1648 bcm->irq_savedstate |= BCM43xx_IRQ_BEACON;
1651 if (!(status & 0x1)) {
1652 bcm43xx_generate_beacon_template(bcm, 0x68, 0x18);
1654 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1656 if (!(status & 0x2)) {
1657 bcm43xx_generate_beacon_template(bcm, 0x468, 0x1A);
1659 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1663 /* Interrupt handler bottom-half */
1664 static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm)
1668 u32 merged_dma_reason = 0;
1669 int i, activity = 0;
1670 unsigned long flags;
1672 #ifdef CONFIG_BCM43XX_DEBUG
1673 u32 _handled = 0x00000000;
1674 # define bcmirq_handled(irq) do { _handled |= (irq); } while (0)
1676 # define bcmirq_handled(irq) do { /* nothing */ } while (0)
1677 #endif /* CONFIG_BCM43XX_DEBUG*/
1679 spin_lock_irqsave(&bcm->irq_lock, flags);
1680 reason = bcm->irq_reason;
1681 for (i = 5; i >= 0; i--) {
1682 dma_reason[i] = bcm->dma_reason[i];
1683 merged_dma_reason |= dma_reason[i];
1686 if (unlikely(reason & BCM43xx_IRQ_XMIT_ERROR)) {
1687 /* TX error. We get this when Template Ram is written in wrong endianess
1688 * in dummy_tx(). We also get this if something is wrong with the TX header
1689 * on DMA or PIO queues.
1690 * Maybe we get this in other error conditions, too.
1692 printkl(KERN_ERR PFX "FATAL ERROR: BCM43xx_IRQ_XMIT_ERROR\n");
1693 bcmirq_handled(BCM43xx_IRQ_XMIT_ERROR);
1695 if (unlikely(merged_dma_reason & BCM43xx_DMAIRQ_FATALMASK)) {
1696 printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "
1697 "0x%08X, 0x%08X, 0x%08X, "
1698 "0x%08X, 0x%08X, 0x%08X\n",
1699 dma_reason[0], dma_reason[1],
1700 dma_reason[2], dma_reason[3],
1701 dma_reason[4], dma_reason[5]);
1702 bcm43xx_controller_restart(bcm, "DMA error");
1704 spin_unlock_irqrestore(&bcm->irq_lock, flags);
1707 if (unlikely(merged_dma_reason & BCM43xx_DMAIRQ_NONFATALMASK)) {
1708 printkl(KERN_ERR PFX "DMA error: "
1709 "0x%08X, 0x%08X, 0x%08X, "
1710 "0x%08X, 0x%08X, 0x%08X\n",
1711 dma_reason[0], dma_reason[1],
1712 dma_reason[2], dma_reason[3],
1713 dma_reason[4], dma_reason[5]);
1716 if (reason & BCM43xx_IRQ_PS) {
1718 bcmirq_handled(BCM43xx_IRQ_PS);
1721 if (reason & BCM43xx_IRQ_REG124) {
1722 handle_irq_reg124(bcm);
1723 bcmirq_handled(BCM43xx_IRQ_REG124);
1726 if (reason & BCM43xx_IRQ_BEACON) {
1727 if (bcm->ieee->iw_mode == IW_MODE_MASTER)
1728 handle_irq_beacon(bcm);
1729 bcmirq_handled(BCM43xx_IRQ_BEACON);
1732 if (reason & BCM43xx_IRQ_PMQ) {
1733 handle_irq_pmq(bcm);
1734 bcmirq_handled(BCM43xx_IRQ_PMQ);
1737 if (reason & BCM43xx_IRQ_SCAN) {
1739 //bcmirq_handled(BCM43xx_IRQ_SCAN);
1742 if (reason & BCM43xx_IRQ_NOISE) {
1743 handle_irq_noise(bcm);
1744 bcmirq_handled(BCM43xx_IRQ_NOISE);
1747 /* Check the DMA reason registers for received data. */
1748 if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {
1749 if (bcm43xx_using_pio(bcm))
1750 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue0);
1752 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring0);
1753 /* We intentionally don't set "activity" to 1, here. */
1755 assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));
1756 assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));
1757 if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {
1758 if (bcm43xx_using_pio(bcm))
1759 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue3);
1761 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring3);
1764 assert(!(dma_reason[4] & BCM43xx_DMAIRQ_RX_DONE));
1765 assert(!(dma_reason[5] & BCM43xx_DMAIRQ_RX_DONE));
1766 bcmirq_handled(BCM43xx_IRQ_RX);
1768 if (reason & BCM43xx_IRQ_XMIT_STATUS) {
1769 handle_irq_transmit_status(bcm);
1771 //TODO: In AP mode, this also causes sending of powersave responses.
1772 bcmirq_handled(BCM43xx_IRQ_XMIT_STATUS);
1775 /* IRQ_PIO_WORKAROUND is handled in the top-half. */
1776 bcmirq_handled(BCM43xx_IRQ_PIO_WORKAROUND);
1777 #ifdef CONFIG_BCM43XX_DEBUG
1778 if (unlikely(reason & ~_handled)) {
1779 printkl(KERN_WARNING PFX
1780 "Unhandled IRQ! Reason: 0x%08x, Unhandled: 0x%08x, "
1781 "DMA: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1782 reason, (reason & ~_handled),
1783 dma_reason[0], dma_reason[1],
1784 dma_reason[2], dma_reason[3]);
1787 #undef bcmirq_handled
1789 if (!modparam_noleds)
1790 bcm43xx_leds_update(bcm, activity);
1791 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
1793 spin_unlock_irqrestore(&bcm->irq_lock, flags);
1796 static void pio_irq_workaround(struct bcm43xx_private *bcm,
1797 u16 base, int queueidx)
1801 rxctl = bcm43xx_read16(bcm, base + BCM43xx_PIO_RXCTL);
1802 if (rxctl & BCM43xx_PIO_RXCTL_DATAAVAILABLE)
1803 bcm->dma_reason[queueidx] |= BCM43xx_DMAIRQ_RX_DONE;
1805 bcm->dma_reason[queueidx] &= ~BCM43xx_DMAIRQ_RX_DONE;
1808 static void bcm43xx_interrupt_ack(struct bcm43xx_private *bcm, u32 reason)
1810 if (bcm43xx_using_pio(bcm) &&
1811 (bcm->current_core->rev < 3) &&
1812 (!(reason & BCM43xx_IRQ_PIO_WORKAROUND))) {
1813 /* Apply a PIO specific workaround to the dma_reasons */
1814 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO1_BASE, 0);
1815 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO2_BASE, 1);
1816 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO3_BASE, 2);
1817 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO4_BASE, 3);
1820 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, reason);
1822 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA0_REASON,
1823 bcm->dma_reason[0]);
1824 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_REASON,
1825 bcm->dma_reason[1]);
1826 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_REASON,
1827 bcm->dma_reason[2]);
1828 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_REASON,
1829 bcm->dma_reason[3]);
1830 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_REASON,
1831 bcm->dma_reason[4]);
1832 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA5_REASON,
1833 bcm->dma_reason[5]);
1836 /* Interrupt handler top-half */
1837 static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id, struct pt_regs *regs)
1839 irqreturn_t ret = IRQ_HANDLED;
1840 struct bcm43xx_private *bcm = dev_id;
1846 spin_lock(&bcm->irq_lock);
1848 assert(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED);
1849 assert(bcm->current_core->id == BCM43xx_COREID_80211);
1851 reason = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
1852 if (reason == 0xffffffff) {
1853 /* irq not for us (shared irq) */
1857 reason &= bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
1861 bcm->dma_reason[0] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA0_REASON)
1863 bcm->dma_reason[1] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA1_REASON)
1865 bcm->dma_reason[2] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA2_REASON)
1867 bcm->dma_reason[3] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA3_REASON)
1869 bcm->dma_reason[4] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA4_REASON)
1871 bcm->dma_reason[5] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA5_REASON)
1874 bcm43xx_interrupt_ack(bcm, reason);
1876 /* disable all IRQs. They are enabled again in the bottom half. */
1877 bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1878 /* save the reason code and call our bottom half. */
1879 bcm->irq_reason = reason;
1880 tasklet_schedule(&bcm->isr_tasklet);
1884 spin_unlock(&bcm->irq_lock);
1889 static void bcm43xx_release_firmware(struct bcm43xx_private *bcm, int force)
1891 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1893 if (bcm->firmware_norelease && !force)
1894 return; /* Suspending or controller reset. */
1895 release_firmware(phy->ucode);
1897 release_firmware(phy->pcm);
1899 release_firmware(phy->initvals0);
1900 phy->initvals0 = NULL;
1901 release_firmware(phy->initvals1);
1902 phy->initvals1 = NULL;
1905 static int bcm43xx_request_firmware(struct bcm43xx_private *bcm)
1907 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1908 u8 rev = bcm->current_core->rev;
1911 char buf[22 + sizeof(modparam_fwpostfix) - 1] = { 0 };
1914 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_microcode%d%s.fw",
1915 (rev >= 5 ? 5 : rev),
1916 modparam_fwpostfix);
1917 err = request_firmware(&phy->ucode, buf, &bcm->pci_dev->dev);
1920 "Error: Microcode \"%s\" not available or load failed.\n",
1927 snprintf(buf, ARRAY_SIZE(buf),
1928 "bcm43xx_pcm%d%s.fw",
1930 modparam_fwpostfix);
1931 err = request_firmware(&phy->pcm, buf, &bcm->pci_dev->dev);
1934 "Error: PCM \"%s\" not available or load failed.\n",
1940 if (!phy->initvals0) {
1941 if (rev == 2 || rev == 4) {
1942 switch (phy->type) {
1943 case BCM43xx_PHYTYPE_A:
1946 case BCM43xx_PHYTYPE_B:
1947 case BCM43xx_PHYTYPE_G:
1954 } else if (rev >= 5) {
1955 switch (phy->type) {
1956 case BCM43xx_PHYTYPE_A:
1959 case BCM43xx_PHYTYPE_B:
1960 case BCM43xx_PHYTYPE_G:
1968 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
1969 nr, modparam_fwpostfix);
1971 err = request_firmware(&phy->initvals0, buf, &bcm->pci_dev->dev);
1974 "Error: InitVals \"%s\" not available or load failed.\n",
1978 if (phy->initvals0->size % sizeof(struct bcm43xx_initval)) {
1979 printk(KERN_ERR PFX "InitVals fileformat error.\n");
1984 if (!phy->initvals1) {
1988 switch (phy->type) {
1989 case BCM43xx_PHYTYPE_A:
1990 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1991 if (sbtmstatehigh & 0x00010000)
1996 case BCM43xx_PHYTYPE_B:
1997 case BCM43xx_PHYTYPE_G:
2003 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
2004 nr, modparam_fwpostfix);
2006 err = request_firmware(&phy->initvals1, buf, &bcm->pci_dev->dev);
2009 "Error: InitVals \"%s\" not available or load failed.\n",
2013 if (phy->initvals1->size % sizeof(struct bcm43xx_initval)) {
2014 printk(KERN_ERR PFX "InitVals fileformat error.\n");
2023 bcm43xx_release_firmware(bcm, 1);
2026 printk(KERN_ERR PFX "Error: No InitVals available!\n");
2031 static void bcm43xx_upload_microcode(struct bcm43xx_private *bcm)
2033 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2035 unsigned int i, len;
2037 /* Upload Microcode. */
2038 data = (u32 *)(phy->ucode->data);
2039 len = phy->ucode->size / sizeof(u32);
2040 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_UCODE, 0x0000);
2041 for (i = 0; i < len; i++) {
2042 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2043 be32_to_cpu(data[i]));
2047 /* Upload PCM data. */
2048 data = (u32 *)(phy->pcm->data);
2049 len = phy->pcm->size / sizeof(u32);
2050 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01ea);
2051 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, 0x00004000);
2052 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01eb);
2053 for (i = 0; i < len; i++) {
2054 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2055 be32_to_cpu(data[i]));
2060 static int bcm43xx_write_initvals(struct bcm43xx_private *bcm,
2061 const struct bcm43xx_initval *data,
2062 const unsigned int len)
2068 for (i = 0; i < len; i++) {
2069 offset = be16_to_cpu(data[i].offset);
2070 size = be16_to_cpu(data[i].size);
2071 value = be32_to_cpu(data[i].value);
2073 if (unlikely(offset >= 0x1000))
2076 if (unlikely(value & 0xFFFF0000))
2078 bcm43xx_write16(bcm, offset, (u16)value);
2079 } else if (size == 4) {
2080 bcm43xx_write32(bcm, offset, value);
2088 printk(KERN_ERR PFX "InitVals (bcm43xx_initvalXX.fw) file-format error. "
2089 "Please fix your bcm43xx firmware files.\n");
2093 static int bcm43xx_upload_initvals(struct bcm43xx_private *bcm)
2095 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2098 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)phy->initvals0->data,
2099 phy->initvals0->size / sizeof(struct bcm43xx_initval));
2102 if (phy->initvals1) {
2103 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)phy->initvals1->data,
2104 phy->initvals1->size / sizeof(struct bcm43xx_initval));
2112 #ifdef CONFIG_BCM947XX
2113 static struct pci_device_id bcm43xx_47xx_ids[] = {
2114 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
2119 static int bcm43xx_initialize_irq(struct bcm43xx_private *bcm)
2123 bcm->irq = bcm->pci_dev->irq;
2124 #ifdef CONFIG_BCM947XX
2125 if (bcm->pci_dev->bus->number == 0) {
2127 struct pci_device_id *id;
2128 for (id = bcm43xx_47xx_ids; id->vendor; id++) {
2129 d = pci_get_device(id->vendor, id->device, NULL);
2138 err = request_irq(bcm->irq, bcm43xx_interrupt_handler,
2139 IRQF_SHARED, KBUILD_MODNAME, bcm);
2141 printk(KERN_ERR PFX "Cannot register IRQ%d\n", bcm->irq);
2146 /* Switch to the core used to write the GPIO register.
2147 * This is either the ChipCommon, or the PCI core.
2149 static int switch_to_gpio_core(struct bcm43xx_private *bcm)
2153 /* Where to find the GPIO register depends on the chipset.
2154 * If it has a ChipCommon, its register at offset 0x6c is the GPIO
2155 * control register. Otherwise the register at offset 0x6c in the
2156 * PCI core is the GPIO control register.
2158 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
2159 if (err == -ENODEV) {
2160 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2161 if (unlikely(err == -ENODEV)) {
2162 printk(KERN_ERR PFX "gpio error: "
2163 "Neither ChipCommon nor PCI core available!\n");
2170 /* Initialize the GPIOs
2171 * http://bcm-specs.sipsolutions.net/GPIO
2173 static int bcm43xx_gpio_init(struct bcm43xx_private *bcm)
2175 struct bcm43xx_coreinfo *old_core;
2179 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2180 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2183 bcm43xx_leds_switch_all(bcm, 0);
2184 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2185 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK) | 0x000F);
2189 if (bcm->chip_id == 0x4301) {
2193 if (0 /* FIXME: conditional unknown */) {
2194 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2195 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2200 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL) {
2201 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2202 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2207 if (bcm->current_core->rev >= 2)
2208 mask |= 0x0010; /* FIXME: This is redundant. */
2210 old_core = bcm->current_core;
2211 err = switch_to_gpio_core(bcm);
2214 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL,
2215 (bcm43xx_read32(bcm, BCM43xx_GPIO_CONTROL) & mask) | set);
2216 err = bcm43xx_switch_core(bcm, old_core);
2221 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2222 static int bcm43xx_gpio_cleanup(struct bcm43xx_private *bcm)
2224 struct bcm43xx_coreinfo *old_core;
2227 old_core = bcm->current_core;
2228 err = switch_to_gpio_core(bcm);
2231 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL, 0x00000000);
2232 err = bcm43xx_switch_core(bcm, old_core);
2238 /* http://bcm-specs.sipsolutions.net/EnableMac */
2239 void bcm43xx_mac_enable(struct bcm43xx_private *bcm)
2241 bcm->mac_suspended--;
2242 assert(bcm->mac_suspended >= 0);
2243 if (bcm->mac_suspended == 0) {
2244 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2245 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2246 | BCM43xx_SBF_MAC_ENABLED);
2247 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, BCM43xx_IRQ_READY);
2248 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
2249 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2250 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
2254 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2255 void bcm43xx_mac_suspend(struct bcm43xx_private *bcm)
2260 assert(bcm->mac_suspended >= 0);
2261 if (bcm->mac_suspended == 0) {
2262 bcm43xx_power_saving_ctl_bits(bcm, -1, 1);
2263 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2264 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2265 & ~BCM43xx_SBF_MAC_ENABLED);
2266 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2267 for (i = 10000; i; i--) {
2268 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2269 if (tmp & BCM43xx_IRQ_READY)
2273 printkl(KERN_ERR PFX "MAC suspend failed\n");
2276 bcm->mac_suspended++;
2279 void bcm43xx_set_iwmode(struct bcm43xx_private *bcm,
2282 unsigned long flags;
2283 struct net_device *net_dev = bcm->net_dev;
2287 spin_lock_irqsave(&bcm->ieee->lock, flags);
2288 bcm->ieee->iw_mode = iw_mode;
2289 spin_unlock_irqrestore(&bcm->ieee->lock, flags);
2290 if (iw_mode == IW_MODE_MONITOR)
2291 net_dev->type = ARPHRD_IEEE80211;
2293 net_dev->type = ARPHRD_ETHER;
2295 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2296 /* Reset status to infrastructured mode */
2297 status &= ~(BCM43xx_SBF_MODE_AP | BCM43xx_SBF_MODE_MONITOR);
2298 status &= ~BCM43xx_SBF_MODE_PROMISC;
2299 status |= BCM43xx_SBF_MODE_NOTADHOC;
2301 /* FIXME: Always enable promisc mode, until we get the MAC filters working correctly. */
2302 status |= BCM43xx_SBF_MODE_PROMISC;
2305 case IW_MODE_MONITOR:
2306 status |= BCM43xx_SBF_MODE_MONITOR;
2307 status |= BCM43xx_SBF_MODE_PROMISC;
2310 status &= ~BCM43xx_SBF_MODE_NOTADHOC;
2312 case IW_MODE_MASTER:
2313 status |= BCM43xx_SBF_MODE_AP;
2315 case IW_MODE_SECOND:
2316 case IW_MODE_REPEAT:
2320 /* nothing to be done here... */
2323 dprintk(KERN_ERR PFX "Unknown mode in set_iwmode: %d\n", iw_mode);
2325 if (net_dev->flags & IFF_PROMISC)
2326 status |= BCM43xx_SBF_MODE_PROMISC;
2327 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
2330 if (iw_mode != IW_MODE_ADHOC && iw_mode != IW_MODE_MASTER) {
2331 if (bcm->chip_id == 0x4306 && bcm->chip_rev == 3)
2336 bcm43xx_write16(bcm, 0x0612, value);
2339 /* This is the opposite of bcm43xx_chip_init() */
2340 static void bcm43xx_chip_cleanup(struct bcm43xx_private *bcm)
2342 bcm43xx_radio_turn_off(bcm);
2343 if (!modparam_noleds)
2344 bcm43xx_leds_exit(bcm);
2345 bcm43xx_gpio_cleanup(bcm);
2346 bcm43xx_release_firmware(bcm, 0);
2349 /* Initialize the chip
2350 * http://bcm-specs.sipsolutions.net/ChipInit
2352 static int bcm43xx_chip_init(struct bcm43xx_private *bcm)
2354 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2355 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2361 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2362 BCM43xx_SBF_CORE_READY
2365 err = bcm43xx_request_firmware(bcm);
2368 bcm43xx_upload_microcode(bcm);
2370 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0xFFFFFFFF);
2371 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, 0x00020402);
2374 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2375 if (value32 == BCM43xx_IRQ_READY)
2378 if (i >= BCM43xx_IRQWAIT_MAX_RETRIES) {
2379 printk(KERN_ERR PFX "IRQ_READY timeout\n");
2381 goto err_release_fw;
2385 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2387 value16 = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2388 BCM43xx_UCODE_REVISION);
2390 dprintk(KERN_INFO PFX "Microcode rev 0x%x, pl 0x%x "
2391 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", value16,
2392 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2393 BCM43xx_UCODE_PATCHLEVEL),
2394 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2395 BCM43xx_UCODE_DATE) >> 12) & 0xf,
2396 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2397 BCM43xx_UCODE_DATE) >> 8) & 0xf,
2398 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2399 BCM43xx_UCODE_DATE) & 0xff,
2400 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2401 BCM43xx_UCODE_TIME) >> 11) & 0x1f,
2402 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2403 BCM43xx_UCODE_TIME) >> 5) & 0x3f,
2404 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2405 BCM43xx_UCODE_TIME) & 0x1f);
2407 if ( value16 > 0x128 ) {
2408 dprintk(KERN_ERR PFX
2409 "Firmware: no support for microcode rev > 0x128\n");
2411 goto err_release_fw;
2414 err = bcm43xx_gpio_init(bcm);
2416 goto err_release_fw;
2418 err = bcm43xx_upload_initvals(bcm);
2420 goto err_gpio_cleanup;
2421 bcm43xx_radio_turn_on(bcm);
2423 bcm43xx_write16(bcm, 0x03E6, 0x0000);
2424 err = bcm43xx_phy_init(bcm);
2428 /* Select initial Interference Mitigation. */
2429 tmp = radio->interfmode;
2430 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2431 bcm43xx_radio_set_interference_mitigation(bcm, tmp);
2433 bcm43xx_phy_set_antenna_diversity(bcm);
2434 bcm43xx_radio_set_txantenna(bcm, BCM43xx_RADIO_TXANTENNA_DEFAULT);
2435 if (phy->type == BCM43xx_PHYTYPE_B) {
2436 value16 = bcm43xx_read16(bcm, 0x005E);
2438 bcm43xx_write16(bcm, 0x005E, value16);
2440 bcm43xx_write32(bcm, 0x0100, 0x01000000);
2441 if (bcm->current_core->rev < 5)
2442 bcm43xx_write32(bcm, 0x010C, 0x01000000);
2444 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2445 value32 &= ~ BCM43xx_SBF_MODE_NOTADHOC;
2446 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2447 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2448 value32 |= BCM43xx_SBF_MODE_NOTADHOC;
2449 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2451 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2452 value32 |= 0x100000;
2453 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2455 if (bcm43xx_using_pio(bcm)) {
2456 bcm43xx_write32(bcm, 0x0210, 0x00000100);
2457 bcm43xx_write32(bcm, 0x0230, 0x00000100);
2458 bcm43xx_write32(bcm, 0x0250, 0x00000100);
2459 bcm43xx_write32(bcm, 0x0270, 0x00000100);
2460 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0034, 0x0000);
2463 /* Probe Response Timeout value */
2464 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2465 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0074, 0x0000);
2467 /* Initially set the wireless operation mode. */
2468 bcm43xx_set_iwmode(bcm, bcm->ieee->iw_mode);
2470 if (bcm->current_core->rev < 3) {
2471 bcm43xx_write16(bcm, 0x060E, 0x0000);
2472 bcm43xx_write16(bcm, 0x0610, 0x8000);
2473 bcm43xx_write16(bcm, 0x0604, 0x0000);
2474 bcm43xx_write16(bcm, 0x0606, 0x0200);
2476 bcm43xx_write32(bcm, 0x0188, 0x80000000);
2477 bcm43xx_write32(bcm, 0x018C, 0x02000000);
2479 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);
2480 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2481 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2482 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2483 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2484 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2485 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2487 value32 = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
2488 value32 |= 0x00100000;
2489 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, value32);
2491 bcm43xx_write16(bcm, BCM43xx_MMIO_POWERUP_DELAY, bcm43xx_pctl_powerup_delay(bcm));
2494 dprintk(KERN_INFO PFX "Chip initialized\n");
2499 bcm43xx_radio_turn_off(bcm);
2501 bcm43xx_gpio_cleanup(bcm);
2503 bcm43xx_release_firmware(bcm, 1);
2507 /* Validate chip access
2508 * http://bcm-specs.sipsolutions.net/ValidateChipAccess */
2509 static int bcm43xx_validate_chip(struct bcm43xx_private *bcm)
2514 shm_backup = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000);
2515 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0xAA5555AA);
2516 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0xAA5555AA)
2518 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0x55AAAA55);
2519 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0x55AAAA55)
2521 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, shm_backup);
2523 value = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2524 if ((value | 0x80000000) != 0x80000400)
2527 value = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2528 if (value != 0x00000000)
2533 printk(KERN_ERR PFX "Failed to validate the chipaccess\n");
2537 static void bcm43xx_init_struct_phyinfo(struct bcm43xx_phyinfo *phy)
2539 /* Initialize a "phyinfo" structure. The structure is already
2541 * This is called on insmod time to initialize members.
2543 phy->savedpctlreg = 0xFFFF;
2544 spin_lock_init(&phy->lock);
2547 static void bcm43xx_init_struct_radioinfo(struct bcm43xx_radioinfo *radio)
2549 /* Initialize a "radioinfo" structure. The structure is already
2551 * This is called on insmod time to initialize members.
2553 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2554 radio->channel = 0xFF;
2555 radio->initial_channel = 0xFF;
2558 static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2562 u32 core_vendor, core_id, core_rev;
2563 u32 sb_id_hi, chip_id_32 = 0;
2564 u16 pci_device, chip_id_16;
2567 memset(&bcm->core_chipcommon, 0, sizeof(struct bcm43xx_coreinfo));
2568 memset(&bcm->core_pci, 0, sizeof(struct bcm43xx_coreinfo));
2569 memset(&bcm->core_80211, 0, sizeof(struct bcm43xx_coreinfo)
2570 * BCM43xx_MAX_80211_CORES);
2571 memset(&bcm->core_80211_ext, 0, sizeof(struct bcm43xx_coreinfo_80211)
2572 * BCM43xx_MAX_80211_CORES);
2573 bcm->nr_80211_available = 0;
2574 bcm->current_core = NULL;
2575 bcm->active_80211_core = NULL;
2578 err = _switch_core(bcm, 0);
2582 /* fetch sb_id_hi from core information registers */
2583 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2585 core_id = (sb_id_hi & 0xFFF0) >> 4;
2586 core_rev = (sb_id_hi & 0xF);
2587 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2589 /* if present, chipcommon is always core 0; read the chipid from it */
2590 if (core_id == BCM43xx_COREID_CHIPCOMMON) {
2591 chip_id_32 = bcm43xx_read32(bcm, 0);
2592 chip_id_16 = chip_id_32 & 0xFFFF;
2593 bcm->core_chipcommon.available = 1;
2594 bcm->core_chipcommon.id = core_id;
2595 bcm->core_chipcommon.rev = core_rev;
2596 bcm->core_chipcommon.index = 0;
2597 /* While we are at it, also read the capabilities. */
2598 bcm->chipcommon_capabilities = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_CAPABILITIES);
2600 /* without a chipCommon, use a hard coded table. */
2601 pci_device = bcm->pci_dev->device;
2602 if (pci_device == 0x4301)
2603 chip_id_16 = 0x4301;
2604 else if ((pci_device >= 0x4305) && (pci_device <= 0x4307))
2605 chip_id_16 = 0x4307;
2606 else if ((pci_device >= 0x4402) && (pci_device <= 0x4403))
2607 chip_id_16 = 0x4402;
2608 else if ((pci_device >= 0x4610) && (pci_device <= 0x4615))
2609 chip_id_16 = 0x4610;
2610 else if ((pci_device >= 0x4710) && (pci_device <= 0x4715))
2611 chip_id_16 = 0x4710;
2612 #ifdef CONFIG_BCM947XX
2613 else if ((pci_device >= 0x4320) && (pci_device <= 0x4325))
2614 chip_id_16 = 0x4309;
2617 printk(KERN_ERR PFX "Could not determine Chip ID\n");
2622 /* ChipCommon with Core Rev >=4 encodes number of cores,
2623 * otherwise consult hardcoded table */
2624 if ((core_id == BCM43xx_COREID_CHIPCOMMON) && (core_rev >= 4)) {
2625 core_count = (chip_id_32 & 0x0F000000) >> 24;
2627 switch (chip_id_16) {
2650 /* SOL if we get here */
2656 bcm->chip_id = chip_id_16;
2657 bcm->chip_rev = (chip_id_32 & 0x000F0000) >> 16;
2658 bcm->chip_package = (chip_id_32 & 0x00F00000) >> 20;
2660 dprintk(KERN_INFO PFX "Chip ID 0x%x, rev 0x%x\n",
2661 bcm->chip_id, bcm->chip_rev);
2662 dprintk(KERN_INFO PFX "Number of cores: %d\n", core_count);
2663 if (bcm->core_chipcommon.available) {
2664 dprintk(KERN_INFO PFX "Core 0: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2665 core_id, core_rev, core_vendor,
2666 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled");
2669 if (bcm->core_chipcommon.available)
2673 for ( ; current_core < core_count; current_core++) {
2674 struct bcm43xx_coreinfo *core;
2675 struct bcm43xx_coreinfo_80211 *ext_80211;
2677 err = _switch_core(bcm, current_core);
2680 /* Gather information */
2681 /* fetch sb_id_hi from core information registers */
2682 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2684 /* extract core_id, core_rev, core_vendor */
2685 core_id = (sb_id_hi & 0xFFF0) >> 4;
2686 core_rev = (sb_id_hi & 0xF);
2687 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2689 dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2690 current_core, core_id, core_rev, core_vendor,
2691 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled" );
2695 case BCM43xx_COREID_PCI:
2696 core = &bcm->core_pci;
2697 if (core->available) {
2698 printk(KERN_WARNING PFX "Multiple PCI cores found.\n");
2702 case BCM43xx_COREID_80211:
2703 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
2704 core = &(bcm->core_80211[i]);
2705 ext_80211 = &(bcm->core_80211_ext[i]);
2706 if (!core->available)
2711 printk(KERN_WARNING PFX "More than %d cores of type 802.11 found.\n",
2712 BCM43xx_MAX_80211_CORES);
2716 /* More than one 80211 core is only supported
2718 * There are chips with two 80211 cores, but with
2719 * dangling pins on the second core. Be careful
2720 * and ignore these cores here.
2722 if (bcm->pci_dev->device != 0x4324) {
2723 dprintk(KERN_INFO PFX "Ignoring additional 802.11 core.\n");
2736 printk(KERN_ERR PFX "Error: Unsupported 80211 core revision %u\n",
2741 bcm->nr_80211_available++;
2742 core->priv = ext_80211;
2743 bcm43xx_init_struct_phyinfo(&ext_80211->phy);
2744 bcm43xx_init_struct_radioinfo(&ext_80211->radio);
2746 case BCM43xx_COREID_CHIPCOMMON:
2747 printk(KERN_WARNING PFX "Multiple CHIPCOMMON cores found.\n");
2751 core->available = 1;
2753 core->rev = core_rev;
2754 core->index = current_core;
2758 if (!bcm->core_80211[0].available) {
2759 printk(KERN_ERR PFX "Error: No 80211 core found!\n");
2764 err = bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
2771 static void bcm43xx_gen_bssid(struct bcm43xx_private *bcm)
2773 const u8 *mac = (const u8*)(bcm->net_dev->dev_addr);
2774 u8 *bssid = bcm->ieee->bssid;
2776 switch (bcm->ieee->iw_mode) {
2778 random_ether_addr(bssid);
2780 case IW_MODE_MASTER:
2782 case IW_MODE_REPEAT:
2783 case IW_MODE_SECOND:
2784 case IW_MODE_MONITOR:
2785 memcpy(bssid, mac, ETH_ALEN);
2792 static void bcm43xx_rate_memory_write(struct bcm43xx_private *bcm,
2800 offset += (bcm43xx_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2804 offset += (bcm43xx_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2806 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, offset + 0x20,
2807 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, offset));
2810 static void bcm43xx_rate_memory_init(struct bcm43xx_private *bcm)
2812 switch (bcm43xx_current_phy(bcm)->type) {
2813 case BCM43xx_PHYTYPE_A:
2814 case BCM43xx_PHYTYPE_G:
2815 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_6MB, 1);
2816 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_12MB, 1);
2817 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_18MB, 1);
2818 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_24MB, 1);
2819 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_36MB, 1);
2820 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_48MB, 1);
2821 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_54MB, 1);
2822 case BCM43xx_PHYTYPE_B:
2823 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_1MB, 0);
2824 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_2MB, 0);
2825 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_5MB, 0);
2826 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_11MB, 0);
2833 static void bcm43xx_wireless_core_cleanup(struct bcm43xx_private *bcm)
2835 bcm43xx_chip_cleanup(bcm);
2836 bcm43xx_pio_free(bcm);
2837 bcm43xx_dma_free(bcm);
2839 bcm->current_core->initialized = 0;
2842 /* http://bcm-specs.sipsolutions.net/80211Init */
2843 static int bcm43xx_wireless_core_init(struct bcm43xx_private *bcm,
2846 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2847 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2853 if (bcm->chip_rev < 5) {
2854 sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
2855 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
2856 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
2857 if (bcm->bustype == BCM43xx_BUSTYPE_PCI)
2858 sbimconfiglow |= 0x32;
2859 else if (bcm->bustype == BCM43xx_BUSTYPE_SB)
2860 sbimconfiglow |= 0x53;
2863 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow);
2866 bcm43xx_phy_calibrate(bcm);
2867 err = bcm43xx_chip_init(bcm);
2871 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0016, bcm->current_core->rev);
2872 ucodeflags = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, BCM43xx_UCODEFLAGS_OFFSET);
2874 if (0 /*FIXME: which condition has to be used here? */)
2875 ucodeflags |= 0x00000010;
2877 /* HW decryption needs to be set now */
2878 ucodeflags |= 0x40000000;
2880 if (phy->type == BCM43xx_PHYTYPE_G) {
2881 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2883 ucodeflags |= BCM43xx_UCODEFLAG_UNKGPHY;
2884 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL)
2885 ucodeflags |= BCM43xx_UCODEFLAG_UNKPACTRL;
2886 } else if (phy->type == BCM43xx_PHYTYPE_B) {
2887 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2888 if (phy->rev >= 2 && radio->version == 0x2050)
2889 ucodeflags &= ~BCM43xx_UCODEFLAG_UNKGPHY;
2892 if (ucodeflags != bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
2893 BCM43xx_UCODEFLAGS_OFFSET)) {
2894 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
2895 BCM43xx_UCODEFLAGS_OFFSET, ucodeflags);
2898 /* Short/Long Retry Limit.
2899 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
2900 * the chip-internal counter.
2902 limit = limit_value(modparam_short_retry, 0, 0xF);
2903 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0006, limit);
2904 limit = limit_value(modparam_long_retry, 0, 0xF);
2905 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0007, limit);
2907 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0044, 3);
2908 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0046, 2);
2910 bcm43xx_rate_memory_init(bcm);
2912 /* Minimum Contention Window */
2913 if (phy->type == BCM43xx_PHYTYPE_B)
2914 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000001f);
2916 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000000f);
2917 /* Maximum Contention Window */
2918 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
2920 bcm43xx_gen_bssid(bcm);
2921 bcm43xx_write_mac_bssid_templates(bcm);
2923 if (bcm->current_core->rev >= 5)
2924 bcm43xx_write16(bcm, 0x043C, 0x000C);
2926 if (active_wlcore) {
2927 if (bcm43xx_using_pio(bcm))
2928 err = bcm43xx_pio_init(bcm);
2930 err = bcm43xx_dma_init(bcm);
2932 goto err_chip_cleanup;
2934 bcm43xx_write16(bcm, 0x0612, 0x0050);
2935 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0416, 0x0050);
2936 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0414, 0x01F4);
2938 if (active_wlcore) {
2939 if (radio->initial_channel != 0xFF)
2940 bcm43xx_radio_selectchannel(bcm, radio->initial_channel, 0);
2943 /* Don't enable MAC/IRQ here, as it will race with the IRQ handler.
2944 * We enable it later.
2946 bcm->current_core->initialized = 1;
2951 bcm43xx_chip_cleanup(bcm);
2955 static int bcm43xx_chipset_attach(struct bcm43xx_private *bcm)
2960 err = bcm43xx_pctl_set_crystal(bcm, 1);
2963 bcm43xx_pci_read_config16(bcm, PCI_STATUS, &pci_status);
2964 bcm43xx_pci_write_config16(bcm, PCI_STATUS, pci_status & ~PCI_STATUS_SIG_TARGET_ABORT);
2970 static void bcm43xx_chipset_detach(struct bcm43xx_private *bcm)
2972 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
2973 bcm43xx_pctl_set_crystal(bcm, 0);
2976 static void bcm43xx_pcicore_broadcast_value(struct bcm43xx_private *bcm,
2980 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_ADDR, address);
2981 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_DATA, data);
2984 static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm)
2987 struct bcm43xx_coreinfo *old_core;
2989 old_core = bcm->current_core;
2990 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2994 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
2996 bcm43xx_switch_core(bcm, old_core);
3002 /* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable.
3003 * To enable core 0, pass a core_mask of 1<<0
3005 static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
3008 u32 backplane_flag_nr;
3010 struct bcm43xx_coreinfo *old_core;
3013 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTPSFLAG);
3014 backplane_flag_nr = value & BCM43xx_BACKPLANE_FLAG_NR_MASK;
3016 old_core = bcm->current_core;
3017 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
3021 if (bcm->core_pci.rev < 6) {
3022 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC);
3023 value |= (1 << backplane_flag_nr);
3024 bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value);
3026 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ICR, &value);
3028 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3029 goto out_switch_back;
3031 value |= core_mask << 8;
3032 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ICR, value);
3034 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3035 goto out_switch_back;
3039 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3040 value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST;
3041 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3043 if (bcm->core_pci.rev < 5) {
3044 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
3045 value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT)
3046 & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
3047 value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT)
3048 & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
3049 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value);
3050 err = bcm43xx_pcicore_commit_settings(bcm);
3055 err = bcm43xx_switch_core(bcm, old_core);
3060 static void bcm43xx_periodic_every120sec(struct bcm43xx_private *bcm)
3062 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3064 if (phy->type != BCM43xx_PHYTYPE_G || phy->rev < 2)
3067 bcm43xx_mac_suspend(bcm);
3068 bcm43xx_phy_lo_g_measure(bcm);
3069 bcm43xx_mac_enable(bcm);
3072 static void bcm43xx_periodic_every60sec(struct bcm43xx_private *bcm)
3074 bcm43xx_phy_lo_mark_all_unused(bcm);
3075 if (bcm->sprom.boardflags & BCM43xx_BFL_RSSI) {
3076 bcm43xx_mac_suspend(bcm);
3077 bcm43xx_calc_nrssi_slope(bcm);
3078 bcm43xx_mac_enable(bcm);
3082 static void bcm43xx_periodic_every30sec(struct bcm43xx_private *bcm)
3084 /* Update device statistics. */
3085 bcm43xx_calculate_link_quality(bcm);
3088 static void bcm43xx_periodic_every15sec(struct bcm43xx_private *bcm)
3090 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3091 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
3093 if (phy->type == BCM43xx_PHYTYPE_G) {
3094 //TODO: update_aci_moving_average
3095 if (radio->aci_enable && radio->aci_wlan_automatic) {
3096 bcm43xx_mac_suspend(bcm);
3097 if (!radio->aci_enable && 1 /*TODO: not scanning? */) {
3098 if (0 /*TODO: bunch of conditions*/) {
3099 bcm43xx_radio_set_interference_mitigation(bcm,
3100 BCM43xx_RADIO_INTERFMODE_MANUALWLAN);
3102 } else if (1/*TODO*/) {
3104 if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(bcm))) {
3105 bcm43xx_radio_set_interference_mitigation(bcm,
3106 BCM43xx_RADIO_INTERFMODE_NONE);
3110 bcm43xx_mac_enable(bcm);
3111 } else if (radio->interfmode == BCM43xx_RADIO_INTERFMODE_NONWLAN &&
3113 //TODO: implement rev1 workaround
3116 bcm43xx_phy_xmitpower(bcm); //FIXME: unless scanning?
3117 //TODO for APHY (temperature?)
3120 static void do_periodic_work(struct bcm43xx_private *bcm)
3124 state = bcm->periodic_state;
3126 bcm43xx_periodic_every120sec(bcm);
3128 bcm43xx_periodic_every60sec(bcm);
3130 bcm43xx_periodic_every30sec(bcm);
3132 bcm43xx_periodic_every15sec(bcm);
3133 bcm->periodic_state = state + 1;
3135 schedule_delayed_work(&bcm->periodic_work, HZ * 15);
3138 /* Estimate a "Badness" value based on the periodic work
3139 * state-machine state. "Badness" is worse (bigger), if the
3140 * periodic work will take longer.
3142 static int estimate_periodic_work_badness(unsigned int state)
3146 if (state % 8 == 0) /* every 120 sec */
3148 if (state % 4 == 0) /* every 60 sec */
3150 if (state % 2 == 0) /* every 30 sec */
3152 if (state % 1 == 0) /* every 15 sec */
3155 #define BADNESS_LIMIT 4
3159 static void bcm43xx_periodic_work_handler(void *d)
3161 struct bcm43xx_private *bcm = d;
3162 unsigned long flags;
3166 badness = estimate_periodic_work_badness(bcm->periodic_state);
3167 mutex_lock(&bcm->mutex);
3169 /* We must fake a started transmission here, as we are going to
3170 * disable TX. If we wouldn't fake a TX, it would be possible to
3171 * trigger the netdev watchdog, if the last real TX is already
3172 * some time on the past (slightly less than 5secs)
3174 bcm->net_dev->trans_start = jiffies;
3175 netif_tx_disable(bcm->net_dev);
3177 spin_lock_irqsave(&bcm->irq_lock, flags);
3178 if (badness > BADNESS_LIMIT) {
3179 /* Periodic work will take a long time, so we want it to
3182 bcm43xx_mac_suspend(bcm);
3183 if (bcm43xx_using_pio(bcm))
3184 bcm43xx_pio_freeze_txqueues(bcm);
3185 savedirqs = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3186 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3187 bcm43xx_synchronize_irq(bcm);
3190 do_periodic_work(bcm);
3192 if (badness > BADNESS_LIMIT) {
3193 spin_lock_irqsave(&bcm->irq_lock, flags);
3194 tasklet_enable(&bcm->isr_tasklet);
3195 bcm43xx_interrupt_enable(bcm, savedirqs);
3196 if (bcm43xx_using_pio(bcm))
3197 bcm43xx_pio_thaw_txqueues(bcm);
3198 bcm43xx_mac_enable(bcm);
3201 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3202 netif_wake_queue(bcm->net_dev);
3203 mutex_unlock(&bcm->mutex);
3206 void bcm43xx_periodic_tasks_delete(struct bcm43xx_private *bcm)
3208 cancel_rearming_delayed_work(&bcm->periodic_work);
3211 void bcm43xx_periodic_tasks_setup(struct bcm43xx_private *bcm)
3213 struct work_struct *work = &(bcm->periodic_work);
3215 assert(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED);
3216 INIT_WORK(work, bcm43xx_periodic_work_handler, bcm);
3217 schedule_work(work);
3220 static void bcm43xx_security_init(struct bcm43xx_private *bcm)
3222 bcm->security_offset = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
3224 bcm43xx_clear_keys(bcm);
3227 static int bcm43xx_rng_read(struct hwrng *rng, u32 *data)
3229 struct bcm43xx_private *bcm = (struct bcm43xx_private *)rng->priv;
3230 unsigned long flags;
3232 spin_lock_irqsave(&(bcm)->irq_lock, flags);
3233 *data = bcm43xx_read16(bcm, BCM43xx_MMIO_RNG);
3234 spin_unlock_irqrestore(&(bcm)->irq_lock, flags);
3236 return (sizeof(u16));
3239 static void bcm43xx_rng_exit(struct bcm43xx_private *bcm)
3241 hwrng_unregister(&bcm->rng);
3244 static int bcm43xx_rng_init(struct bcm43xx_private *bcm)
3248 snprintf(bcm->rng_name, ARRAY_SIZE(bcm->rng_name),
3249 "%s_%s", KBUILD_MODNAME, bcm->net_dev->name);
3250 bcm->rng.name = bcm->rng_name;
3251 bcm->rng.data_read = bcm43xx_rng_read;
3252 bcm->rng.priv = (unsigned long)bcm;
3253 err = hwrng_register(&bcm->rng);
3255 printk(KERN_ERR PFX "RNG init failed (%d)\n", err);
3260 static int bcm43xx_shutdown_all_wireless_cores(struct bcm43xx_private *bcm)
3264 struct bcm43xx_coreinfo *core;
3266 bcm43xx_set_status(bcm, BCM43xx_STAT_SHUTTINGDOWN);
3267 for (i = 0; i < bcm->nr_80211_available; i++) {
3268 core = &(bcm->core_80211[i]);
3269 assert(core->available);
3270 if (!core->initialized)
3272 err = bcm43xx_switch_core(bcm, core);
3274 dprintk(KERN_ERR PFX "shutdown_all_wireless_cores "
3275 "switch_core failed (%d)\n", err);
3279 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3280 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
3281 bcm43xx_wireless_core_cleanup(bcm);
3282 if (core == bcm->active_80211_core)
3283 bcm->active_80211_core = NULL;
3285 free_irq(bcm->irq, bcm);
3286 bcm43xx_set_status(bcm, BCM43xx_STAT_UNINIT);
3291 /* This is the opposite of bcm43xx_init_board() */
3292 static void bcm43xx_free_board(struct bcm43xx_private *bcm)
3294 bcm43xx_rng_exit(bcm);
3295 bcm43xx_sysfs_unregister(bcm);
3296 bcm43xx_periodic_tasks_delete(bcm);
3298 mutex_lock(&(bcm)->mutex);
3299 bcm43xx_shutdown_all_wireless_cores(bcm);
3300 bcm43xx_pctl_set_crystal(bcm, 0);
3301 mutex_unlock(&(bcm)->mutex);
3304 static void prepare_phydata_for_init(struct bcm43xx_phyinfo *phy)
3306 phy->antenna_diversity = 0xFFFF;
3307 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3308 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3311 phy->calibrated = 0;
3314 if (phy->_lo_pairs) {
3315 memset(phy->_lo_pairs, 0,
3316 sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT);
3318 memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3321 static void prepare_radiodata_for_init(struct bcm43xx_private *bcm,
3322 struct bcm43xx_radioinfo *radio)
3326 /* Set default attenuation values. */
3327 radio->baseband_atten = bcm43xx_default_baseband_attenuation(bcm);
3328 radio->radio_atten = bcm43xx_default_radio_attenuation(bcm);
3329 radio->txctl1 = bcm43xx_default_txctl1(bcm);
3330 radio->txctl2 = 0xFFFF;
3331 radio->txpwr_offset = 0;
3334 radio->nrssislope = 0;
3335 for (i = 0; i < ARRAY_SIZE(radio->nrssi); i++)
3336 radio->nrssi[i] = -1000;
3337 for (i = 0; i < ARRAY_SIZE(radio->nrssi_lt); i++)
3338 radio->nrssi_lt[i] = i;
3340 radio->lofcal = 0xFFFF;
3341 radio->initval = 0xFFFF;
3343 radio->aci_enable = 0;
3344 radio->aci_wlan_automatic = 0;
3345 radio->aci_hw_rssi = 0;
3348 static void prepare_priv_for_init(struct bcm43xx_private *bcm)
3351 struct bcm43xx_coreinfo *core;
3352 struct bcm43xx_coreinfo_80211 *wlext;
3354 assert(!bcm->active_80211_core);
3356 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZING);
3359 bcm->was_initialized = 0;
3360 bcm->reg124_set_0x4 = 0;
3363 memset(&bcm->stats, 0, sizeof(bcm->stats));
3365 /* Wireless core data */
3366 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3367 core = &(bcm->core_80211[i]);
3370 if (!core->available)
3372 assert(wlext == &(bcm->core_80211_ext[i]));
3374 prepare_phydata_for_init(&wlext->phy);
3375 prepare_radiodata_for_init(bcm, &wlext->radio);
3378 /* IRQ related flags */
3379 bcm->irq_reason = 0;
3380 memset(bcm->dma_reason, 0, sizeof(bcm->dma_reason));
3381 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
3383 bcm->mac_suspended = 1;
3385 /* Noise calculation context */
3386 memset(&bcm->noisecalc, 0, sizeof(bcm->noisecalc));
3388 /* Periodic work context */
3389 bcm->periodic_state = 0;
3392 static int wireless_core_up(struct bcm43xx_private *bcm,
3397 if (!bcm43xx_core_enabled(bcm))
3398 bcm43xx_wireless_core_reset(bcm, 1);
3400 bcm43xx_wireless_core_mark_inactive(bcm);
3401 err = bcm43xx_wireless_core_init(bcm, active_wlcore);
3405 bcm43xx_radio_turn_off(bcm);
3410 /* Select and enable the "to be used" wireless core.
3411 * Locking: bcm->mutex must be aquired before calling this.
3412 * bcm->irq_lock must not be aquired.
3414 int bcm43xx_select_wireless_core(struct bcm43xx_private *bcm,
3418 struct bcm43xx_coreinfo *active_core = NULL;
3419 struct bcm43xx_coreinfo_80211 *active_wlext = NULL;
3420 struct bcm43xx_coreinfo *core;
3421 struct bcm43xx_coreinfo_80211 *wlext;
3422 int adjust_active_sbtmstatelow = 0;
3427 /* If no phytype is requested, select the first core. */
3428 assert(bcm->core_80211[0].available);
3429 wlext = bcm->core_80211[0].priv;
3430 phytype = wlext->phy.type;
3432 /* Find the requested core. */
3433 for (i = 0; i < bcm->nr_80211_available; i++) {
3434 core = &(bcm->core_80211[i]);
3436 if (wlext->phy.type == phytype) {
3438 active_wlext = wlext;
3443 return -ESRCH; /* No such PHYTYPE on this board. */
3445 if (bcm->active_80211_core) {
3446 /* We already selected a wl core in the past.
3447 * So first clean up everything.
3449 dprintk(KERN_INFO PFX "select_wireless_core: cleanup\n");
3450 ieee80211softmac_stop(bcm->net_dev);
3451 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZED);
3452 err = bcm43xx_disable_interrupts_sync(bcm);
3454 tasklet_enable(&bcm->isr_tasklet);
3455 err = bcm43xx_shutdown_all_wireless_cores(bcm);
3458 /* Ok, everything down, continue to re-initialize. */
3459 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZING);
3462 /* Reset all data structures. */
3463 prepare_priv_for_init(bcm);
3465 err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_FAST);
3469 /* Mark all unused cores "inactive". */
3470 for (i = 0; i < bcm->nr_80211_available; i++) {
3471 core = &(bcm->core_80211[i]);
3474 if (core == active_core)
3476 err = bcm43xx_switch_core(bcm, core);
3478 dprintk(KERN_ERR PFX "Could not switch to inactive "
3479 "802.11 core (%d)\n", err);
3482 err = wireless_core_up(bcm, 0);
3484 dprintk(KERN_ERR PFX "core_up for inactive 802.11 core "
3485 "failed (%d)\n", err);
3488 adjust_active_sbtmstatelow = 1;
3491 /* Now initialize the active 802.11 core. */
3492 err = bcm43xx_switch_core(bcm, active_core);
3494 dprintk(KERN_ERR PFX "Could not switch to active "
3495 "802.11 core (%d)\n", err);
3498 if (adjust_active_sbtmstatelow &&
3499 active_wlext->phy.type == BCM43xx_PHYTYPE_G) {
3502 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
3503 sbtmstatelow |= 0x20000000;
3504 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
3506 err = wireless_core_up(bcm, 1);
3508 dprintk(KERN_ERR PFX "core_up for active 802.11 core "
3509 "failed (%d)\n", err);
3512 err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_DYNAMIC);
3515 bcm->active_80211_core = active_core;
3517 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
3518 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_SELF, (u8 *)(bcm->net_dev->dev_addr));
3519 bcm43xx_security_init(bcm);
3520 ieee80211softmac_start(bcm->net_dev);
3522 /* Let's go! Be careful after enabling the IRQs.
3523 * Don't switch cores, for example.
3525 bcm43xx_mac_enable(bcm);
3526 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZED);
3527 err = bcm43xx_initialize_irq(bcm);
3530 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
3532 dprintk(KERN_INFO PFX "Selected 802.11 core (phytype %d)\n",
3533 active_wlext->phy.type);
3538 bcm43xx_set_status(bcm, BCM43xx_STAT_UNINIT);
3539 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
3543 static int bcm43xx_init_board(struct bcm43xx_private *bcm)
3547 mutex_lock(&(bcm)->mutex);
3549 tasklet_enable(&bcm->isr_tasklet);
3550 err = bcm43xx_pctl_set_crystal(bcm, 1);
3553 err = bcm43xx_pctl_init(bcm);
3555 goto err_crystal_off;
3556 err = bcm43xx_select_wireless_core(bcm, -1);
3558 goto err_crystal_off;
3559 err = bcm43xx_sysfs_register(bcm);
3561 goto err_wlshutdown;
3562 err = bcm43xx_rng_init(bcm);
3564 goto err_sysfs_unreg;
3565 bcm43xx_periodic_tasks_setup(bcm);
3567 /*FIXME: This should be handled by softmac instead. */
3568 schedule_work(&bcm->softmac->associnfo.work);
3571 mutex_unlock(&(bcm)->mutex);
3576 bcm43xx_sysfs_unregister(bcm);
3578 bcm43xx_shutdown_all_wireless_cores(bcm);
3580 bcm43xx_pctl_set_crystal(bcm, 0);
3582 tasklet_disable(&bcm->isr_tasklet);
3586 static void bcm43xx_detach_board(struct bcm43xx_private *bcm)
3588 struct pci_dev *pci_dev = bcm->pci_dev;
3591 bcm43xx_chipset_detach(bcm);
3592 /* Do _not_ access the chip, after it is detached. */
3593 pci_iounmap(pci_dev, bcm->mmio_addr);
3594 pci_release_regions(pci_dev);
3595 pci_disable_device(pci_dev);
3597 /* Free allocated structures/fields */
3598 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3599 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3600 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3601 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3605 static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
3607 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3615 value = bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_VER);
3617 phy_version = (value & 0xF000) >> 12;
3618 phy_type = (value & 0x0F00) >> 8;
3619 phy_rev = (value & 0x000F);
3621 dprintk(KERN_INFO PFX "Detected PHY: Version: %x, Type %x, Revision %x\n",
3622 phy_version, phy_type, phy_rev);
3625 case BCM43xx_PHYTYPE_A:
3628 /*FIXME: We need to switch the ieee->modulation, etc.. flags,
3629 * if we switch 80211 cores after init is done.
3630 * As we do not implement on the fly switching between
3631 * wireless cores, I will leave this as a future task.
3633 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION;
3634 bcm->ieee->mode = IEEE_A;
3635 bcm->ieee->freq_band = IEEE80211_52GHZ_BAND |
3636 IEEE80211_24GHZ_BAND;
3638 case BCM43xx_PHYTYPE_B:
3639 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 && phy_rev != 7)
3641 bcm->ieee->modulation = IEEE80211_CCK_MODULATION;
3642 bcm->ieee->mode = IEEE_B;
3643 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3645 case BCM43xx_PHYTYPE_G:
3648 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION |
3649 IEEE80211_CCK_MODULATION;
3650 bcm->ieee->mode = IEEE_G;
3651 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3654 printk(KERN_ERR PFX "Error: Unknown PHY Type %x\n",
3659 printk(KERN_WARNING PFX "Invalid PHY Revision %x\n",
3663 phy->version = phy_version;
3664 phy->type = phy_type;
3666 if ((phy_type == BCM43xx_PHYTYPE_B) || (phy_type == BCM43xx_PHYTYPE_G)) {
3667 p = kzalloc(sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT,
3677 static int bcm43xx_attach_board(struct bcm43xx_private *bcm)
3679 struct pci_dev *pci_dev = bcm->pci_dev;
3680 struct net_device *net_dev = bcm->net_dev;
3685 err = pci_enable_device(pci_dev);
3687 printk(KERN_ERR PFX "pci_enable_device() failed\n");
3690 err = pci_request_regions(pci_dev, KBUILD_MODNAME);
3692 printk(KERN_ERR PFX "pci_request_regions() failed\n");
3693 goto err_pci_disable;
3695 /* enable PCI bus-mastering */
3696 pci_set_master(pci_dev);
3697 bcm->mmio_addr = pci_iomap(pci_dev, 0, ~0UL);
3698 if (!bcm->mmio_addr) {
3699 printk(KERN_ERR PFX "pci_iomap() failed\n");
3701 goto err_pci_release;
3703 net_dev->base_addr = (unsigned long)bcm->mmio_addr;
3705 bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_VENDOR_ID,
3706 &bcm->board_vendor);
3707 bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_ID,
3709 bcm43xx_pci_read_config16(bcm, PCI_REVISION_ID,
3710 &bcm->board_revision);
3712 err = bcm43xx_chipset_attach(bcm);
3715 err = bcm43xx_pctl_init(bcm);
3717 goto err_chipset_detach;
3718 err = bcm43xx_probe_cores(bcm);
3720 goto err_chipset_detach;
3722 /* Attach all IO cores to the backplane. */
3724 for (i = 0; i < bcm->nr_80211_available; i++)
3725 coremask |= (1 << bcm->core_80211[i].index);
3726 //FIXME: Also attach some non80211 cores?
3727 err = bcm43xx_setup_backplane_pci_connection(bcm, coremask);
3729 printk(KERN_ERR PFX "Backplane->PCI connection failed!\n");
3730 goto err_chipset_detach;
3733 err = bcm43xx_sprom_extract(bcm);
3735 goto err_chipset_detach;
3736 err = bcm43xx_leds_init(bcm);
3738 goto err_chipset_detach;
3740 for (i = 0; i < bcm->nr_80211_available; i++) {
3741 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3742 assert(err != -ENODEV);
3744 goto err_80211_unwind;
3746 /* Enable the selected wireless core.
3747 * Connect PHY only on the first core.
3749 bcm43xx_wireless_core_reset(bcm, (i == 0));
3751 err = bcm43xx_read_phyinfo(bcm);
3752 if (err && (i == 0))
3753 goto err_80211_unwind;
3755 err = bcm43xx_read_radioinfo(bcm);
3756 if (err && (i == 0))
3757 goto err_80211_unwind;
3759 err = bcm43xx_validate_chip(bcm);
3760 if (err && (i == 0))
3761 goto err_80211_unwind;
3763 bcm43xx_radio_turn_off(bcm);
3764 err = bcm43xx_phy_init_tssi2dbm_table(bcm);
3766 goto err_80211_unwind;
3767 bcm43xx_wireless_core_disable(bcm);
3769 err = bcm43xx_geo_init(bcm);
3771 goto err_80211_unwind;
3772 bcm43xx_pctl_set_crystal(bcm, 0);
3774 /* Set the MAC address in the networking subsystem */
3775 if (is_valid_ether_addr(bcm->sprom.et1macaddr))
3776 memcpy(bcm->net_dev->dev_addr, bcm->sprom.et1macaddr, 6);
3778 memcpy(bcm->net_dev->dev_addr, bcm->sprom.il0macaddr, 6);
3780 snprintf(bcm->nick, IW_ESSID_MAX_SIZE,
3781 "Broadcom %04X", bcm->chip_id);
3788 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3789 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3790 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3791 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3794 bcm43xx_chipset_detach(bcm);
3796 pci_iounmap(pci_dev, bcm->mmio_addr);
3798 pci_release_regions(pci_dev);
3800 pci_disable_device(pci_dev);
3804 /* Do the Hardware IO operations to send the txb */
3805 static inline int bcm43xx_tx(struct bcm43xx_private *bcm,
3806 struct ieee80211_txb *txb)
3810 if (bcm43xx_using_pio(bcm))
3811 err = bcm43xx_pio_tx(bcm, txb);
3813 err = bcm43xx_dma_tx(bcm, txb);
3814 bcm->net_dev->trans_start = jiffies;
3819 static void bcm43xx_ieee80211_set_chan(struct net_device *net_dev,
3822 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3823 struct bcm43xx_radioinfo *radio;
3824 unsigned long flags;
3826 mutex_lock(&bcm->mutex);
3827 spin_lock_irqsave(&bcm->irq_lock, flags);
3828 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) {
3829 bcm43xx_mac_suspend(bcm);
3830 bcm43xx_radio_selectchannel(bcm, channel, 0);
3831 bcm43xx_mac_enable(bcm);
3833 radio = bcm43xx_current_radio(bcm);
3834 radio->initial_channel = channel;
3836 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3837 mutex_unlock(&bcm->mutex);
3840 /* set_security() callback in struct ieee80211_device */
3841 static void bcm43xx_ieee80211_set_security(struct net_device *net_dev,
3842 struct ieee80211_security *sec)
3844 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3845 struct ieee80211_security *secinfo = &bcm->ieee->sec;
3846 unsigned long flags;
3849 dprintk(KERN_INFO PFX "set security called");
3851 mutex_lock(&bcm->mutex);
3852 spin_lock_irqsave(&bcm->irq_lock, flags);
3854 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++)
3855 if (sec->flags & (1<<keyidx)) {
3856 secinfo->encode_alg[keyidx] = sec->encode_alg[keyidx];
3857 secinfo->key_sizes[keyidx] = sec->key_sizes[keyidx];
3858 memcpy(secinfo->keys[keyidx], sec->keys[keyidx], SCM_KEY_LEN);
3861 if (sec->flags & SEC_ACTIVE_KEY) {
3862 secinfo->active_key = sec->active_key;
3863 dprintk(", .active_key = %d", sec->active_key);
3865 if (sec->flags & SEC_UNICAST_GROUP) {
3866 secinfo->unicast_uses_group = sec->unicast_uses_group;
3867 dprintk(", .unicast_uses_group = %d", sec->unicast_uses_group);
3869 if (sec->flags & SEC_LEVEL) {
3870 secinfo->level = sec->level;
3871 dprintk(", .level = %d", sec->level);
3873 if (sec->flags & SEC_ENABLED) {
3874 secinfo->enabled = sec->enabled;
3875 dprintk(", .enabled = %d", sec->enabled);
3877 if (sec->flags & SEC_ENCRYPT) {
3878 secinfo->encrypt = sec->encrypt;
3879 dprintk(", .encrypt = %d", sec->encrypt);
3881 if (sec->flags & SEC_AUTH_MODE) {
3882 secinfo->auth_mode = sec->auth_mode;
3883 dprintk(", .auth_mode = %d", sec->auth_mode);
3886 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED &&
3887 !bcm->ieee->host_encrypt) {
3888 if (secinfo->enabled) {
3889 /* upload WEP keys to hardware */
3890 char null_address[6] = { 0 };
3892 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++) {
3893 if (!(sec->flags & (1<<keyidx)))
3895 switch (sec->encode_alg[keyidx]) {
3896 case SEC_ALG_NONE: algorithm = BCM43xx_SEC_ALGO_NONE; break;
3898 algorithm = BCM43xx_SEC_ALGO_WEP;
3899 if (secinfo->key_sizes[keyidx] == 13)
3900 algorithm = BCM43xx_SEC_ALGO_WEP104;
3904 algorithm = BCM43xx_SEC_ALGO_TKIP;
3908 algorithm = BCM43xx_SEC_ALGO_AES;
3914 bcm43xx_key_write(bcm, keyidx, algorithm, sec->keys[keyidx], secinfo->key_sizes[keyidx], &null_address[0]);
3915 bcm->key[keyidx].enabled = 1;
3916 bcm->key[keyidx].algorithm = algorithm;
3919 bcm43xx_clear_keys(bcm);
3921 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3922 mutex_unlock(&bcm->mutex);
3925 /* hard_start_xmit() callback in struct ieee80211_device */
3926 static int bcm43xx_ieee80211_hard_start_xmit(struct ieee80211_txb *txb,
3927 struct net_device *net_dev,
3930 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3932 unsigned long flags;
3934 spin_lock_irqsave(&bcm->irq_lock, flags);
3935 if (likely(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED))
3936 err = bcm43xx_tx(bcm, txb);
3937 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3940 return NETDEV_TX_BUSY;
3941 return NETDEV_TX_OK;
3944 static struct net_device_stats * bcm43xx_net_get_stats(struct net_device *net_dev)
3946 return &(bcm43xx_priv(net_dev)->ieee->stats);
3949 static void bcm43xx_net_tx_timeout(struct net_device *net_dev)
3951 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3952 unsigned long flags;
3954 spin_lock_irqsave(&bcm->irq_lock, flags);
3955 bcm43xx_controller_restart(bcm, "TX timeout");
3956 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3959 #ifdef CONFIG_NET_POLL_CONTROLLER
3960 static void bcm43xx_net_poll_controller(struct net_device *net_dev)
3962 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3963 unsigned long flags;
3965 local_irq_save(flags);
3966 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED)
3967 bcm43xx_interrupt_handler(bcm->irq, bcm, NULL);
3968 local_irq_restore(flags);
3970 #endif /* CONFIG_NET_POLL_CONTROLLER */
3972 static int bcm43xx_net_open(struct net_device *net_dev)
3974 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3976 return bcm43xx_init_board(bcm);
3979 static int bcm43xx_net_stop(struct net_device *net_dev)
3981 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3984 ieee80211softmac_stop(net_dev);
3985 err = bcm43xx_disable_interrupts_sync(bcm);
3987 bcm43xx_free_board(bcm);
3988 flush_scheduled_work();
3993 static int bcm43xx_init_private(struct bcm43xx_private *bcm,
3994 struct net_device *net_dev,
3995 struct pci_dev *pci_dev)
3999 bcm43xx_set_status(bcm, BCM43xx_STAT_UNINIT);
4000 bcm->ieee = netdev_priv(net_dev);
4001 bcm->softmac = ieee80211_priv(net_dev);
4002 bcm->softmac->set_channel = bcm43xx_ieee80211_set_chan;
4004 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
4005 bcm->mac_suspended = 1;
4006 bcm->pci_dev = pci_dev;
4007 bcm->net_dev = net_dev;
4008 bcm->bad_frames_preempt = modparam_bad_frames_preempt;
4009 spin_lock_init(&bcm->irq_lock);
4010 spin_lock_init(&bcm->leds_lock);
4011 mutex_init(&bcm->mutex);
4012 tasklet_init(&bcm->isr_tasklet,
4013 (void (*)(unsigned long))bcm43xx_interrupt_tasklet,
4014 (unsigned long)bcm);
4015 tasklet_disable_nosync(&bcm->isr_tasklet);
4017 bcm->__using_pio = 1;
4019 err = pci_set_dma_mask(pci_dev, DMA_30BIT_MASK);
4020 err |= pci_set_consistent_dma_mask(pci_dev, DMA_30BIT_MASK);
4022 #ifdef CONFIG_BCM43XX_PIO
4023 printk(KERN_WARNING PFX "DMA not supported. Falling back to PIO.\n");
4024 bcm->__using_pio = 1;
4026 printk(KERN_ERR PFX "FATAL: DMA not supported and PIO not configured. "
4027 "Recompile the driver with PIO support, please.\n");
4029 #endif /* CONFIG_BCM43XX_PIO */
4032 bcm->rts_threshold = BCM43xx_DEFAULT_RTS_THRESHOLD;
4034 /* default to sw encryption for now */
4035 bcm->ieee->host_build_iv = 0;
4036 bcm->ieee->host_encrypt = 1;
4037 bcm->ieee->host_decrypt = 1;
4039 bcm->ieee->iw_mode = BCM43xx_INITIAL_IWMODE;
4040 bcm->ieee->tx_headroom = sizeof(struct bcm43xx_txhdr);
4041 bcm->ieee->set_security = bcm43xx_ieee80211_set_security;
4042 bcm->ieee->hard_start_xmit = bcm43xx_ieee80211_hard_start_xmit;
4047 static int __devinit bcm43xx_init_one(struct pci_dev *pdev,
4048 const struct pci_device_id *ent)
4050 struct net_device *net_dev;
4051 struct bcm43xx_private *bcm;
4054 #ifdef CONFIG_BCM947XX
4055 if ((pdev->bus->number == 0) && (pdev->device != 0x0800))
4059 #ifdef DEBUG_SINGLE_DEVICE_ONLY
4060 if (strcmp(pci_name(pdev), DEBUG_SINGLE_DEVICE_ONLY))
4064 net_dev = alloc_ieee80211softmac(sizeof(*bcm));
4067 "could not allocate ieee80211 device %s\n",
4072 /* initialize the net_device struct */
4073 SET_MODULE_OWNER(net_dev);
4074 SET_NETDEV_DEV(net_dev, &pdev->dev);
4076 net_dev->open = bcm43xx_net_open;
4077 net_dev->stop = bcm43xx_net_stop;
4078 net_dev->get_stats = bcm43xx_net_get_stats;
4079 net_dev->tx_timeout = bcm43xx_net_tx_timeout;
4080 #ifdef CONFIG_NET_POLL_CONTROLLER
4081 net_dev->poll_controller = bcm43xx_net_poll_controller;
4083 net_dev->wireless_handlers = &bcm43xx_wx_handlers_def;
4084 net_dev->irq = pdev->irq;
4085 SET_ETHTOOL_OPS(net_dev, &bcm43xx_ethtool_ops);
4087 /* initialize the bcm43xx_private struct */
4088 bcm = bcm43xx_priv(net_dev);
4089 memset(bcm, 0, sizeof(*bcm));
4090 err = bcm43xx_init_private(bcm, net_dev, pdev);
4092 goto err_free_netdev;
4094 pci_set_drvdata(pdev, net_dev);
4096 err = bcm43xx_attach_board(bcm);
4098 goto err_free_netdev;
4100 err = register_netdev(net_dev);
4102 printk(KERN_ERR PFX "Cannot register net device, "
4105 goto err_detach_board;
4108 bcm43xx_debugfs_add_device(bcm);
4115 bcm43xx_detach_board(bcm);
4117 free_ieee80211softmac(net_dev);
4121 static void __devexit bcm43xx_remove_one(struct pci_dev *pdev)
4123 struct net_device *net_dev = pci_get_drvdata(pdev);
4124 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4126 bcm43xx_debugfs_remove_device(bcm);
4127 unregister_netdev(net_dev);
4128 bcm43xx_detach_board(bcm);
4129 free_ieee80211softmac(net_dev);
4132 /* Hard-reset the chip. Do not call this directly.
4133 * Use bcm43xx_controller_restart()
4135 static void bcm43xx_chip_reset(void *_bcm)
4137 struct bcm43xx_private *bcm = _bcm;
4138 struct bcm43xx_phyinfo *phy;
4141 mutex_lock(&(bcm)->mutex);
4142 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) {
4143 bcm43xx_periodic_tasks_delete(bcm);
4144 phy = bcm43xx_current_phy(bcm);
4145 err = bcm43xx_select_wireless_core(bcm, phy->type);
4147 bcm43xx_periodic_tasks_setup(bcm);
4149 mutex_unlock(&(bcm)->mutex);
4151 printk(KERN_ERR PFX "Controller restart%s\n",
4152 (err == 0) ? "ed" : " failed");
4155 /* Hard-reset the chip.
4156 * This can be called from interrupt or process context.
4157 * bcm->irq_lock must be locked.
4159 void bcm43xx_controller_restart(struct bcm43xx_private *bcm, const char *reason)
4161 if (bcm43xx_status(bcm) != BCM43xx_STAT_INITIALIZED)
4163 printk(KERN_ERR PFX "Controller RESET (%s) ...\n", reason);
4164 INIT_WORK(&bcm->restart_work, bcm43xx_chip_reset, bcm);
4165 schedule_work(&bcm->restart_work);
4170 static int bcm43xx_suspend(struct pci_dev *pdev, pm_message_t state)
4172 struct net_device *net_dev = pci_get_drvdata(pdev);
4173 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4176 dprintk(KERN_INFO PFX "Suspending...\n");
4178 netif_device_detach(net_dev);
4179 bcm->was_initialized = 0;
4180 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) {
4181 bcm->was_initialized = 1;
4182 ieee80211softmac_stop(net_dev);
4183 err = bcm43xx_disable_interrupts_sync(bcm);
4184 if (unlikely(err)) {
4185 dprintk(KERN_ERR PFX "Suspend failed.\n");
4188 bcm->firmware_norelease = 1;
4189 bcm43xx_free_board(bcm);
4190 bcm->firmware_norelease = 0;
4192 bcm43xx_chipset_detach(bcm);
4194 pci_save_state(pdev);
4195 pci_disable_device(pdev);
4196 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4198 dprintk(KERN_INFO PFX "Device suspended.\n");
4203 static int bcm43xx_resume(struct pci_dev *pdev)
4205 struct net_device *net_dev = pci_get_drvdata(pdev);
4206 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4209 dprintk(KERN_INFO PFX "Resuming...\n");
4211 pci_set_power_state(pdev, 0);
4212 pci_enable_device(pdev);
4213 pci_restore_state(pdev);
4215 bcm43xx_chipset_attach(bcm);
4216 if (bcm->was_initialized)
4217 err = bcm43xx_init_board(bcm);
4219 printk(KERN_ERR PFX "Resume failed!\n");
4222 netif_device_attach(net_dev);
4224 dprintk(KERN_INFO PFX "Device resumed.\n");
4229 #endif /* CONFIG_PM */
4231 static struct pci_driver bcm43xx_pci_driver = {
4232 .name = KBUILD_MODNAME,
4233 .id_table = bcm43xx_pci_tbl,
4234 .probe = bcm43xx_init_one,
4235 .remove = __devexit_p(bcm43xx_remove_one),
4237 .suspend = bcm43xx_suspend,
4238 .resume = bcm43xx_resume,
4239 #endif /* CONFIG_PM */
4242 static int __init bcm43xx_init(void)
4244 printk(KERN_INFO KBUILD_MODNAME " driver\n");
4245 bcm43xx_debugfs_init();
4246 return pci_register_driver(&bcm43xx_pci_driver);
4249 static void __exit bcm43xx_exit(void)
4251 pci_unregister_driver(&bcm43xx_pci_driver);
4252 bcm43xx_debugfs_exit();
4255 module_init(bcm43xx_init)
4256 module_exit(bcm43xx_exit)