2 * eisa.c - provide support for EISA adapters in PA-RISC machines
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
9 * Copyright (c) 2001 Matthew Wilcox for Hewlett Packard
10 * Copyright (c) 2001 Daniel Engstrom <5116@telia.com>
12 * There are two distinct EISA adapters. Mongoose is found in machines
13 * before the 712; then the Wax ASIC is used. To complicate matters, the
14 * Wax ASIC also includes a PS/2 and RS-232 controller, but those are
15 * dealt with elsewhere; this file is concerned only with the EISA portions
21 * To allow an ISA card to work properly in the EISA slot you need to
22 * set an edge trigger level. This may be done on the palo command line
23 * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with
24 * n and n2 as the irq levels you want to use.
26 * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at
27 * irq levels 10 and 11.
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/irq.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/sched.h>
37 #include <linux/spinlock.h>
38 #include <linux/eisa.h>
40 #include <asm/byteorder.h>
42 #include <asm/hardware.h>
43 #include <asm/processor.h>
44 #include <asm/parisc-device.h>
45 #include <asm/delay.h>
46 #include <asm/eisa_bus.h>
49 #define EISA_DBG(msg, arg... ) printk(KERN_DEBUG "eisa: " msg , ## arg )
51 #define EISA_DBG(msg, arg... )
54 #define SNAKES_EEPROM_BASE_ADDR 0xF0810400
55 #define MIRAGE_EEPROM_BASE_ADDR 0xF00C0400
57 static spinlock_t eisa_irq_lock = SPIN_LOCK_UNLOCKED;
59 /* We can only have one EISA adapter in the system because neither
60 * implementation can be flexed.
62 static struct eisa_ba {
63 struct pci_hba_data hba;
64 unsigned long eeprom_addr;
65 struct eisa_root_device root;
70 static inline unsigned long eisa_permute(unsigned short port)
73 return 0xfc000000 | ((port & 0xfc00) >> 6)
74 | ((port & 0x3f8) << 9) | (port & 7);
76 return 0xfc000000 | port;
80 unsigned char eisa_in8(unsigned short port)
83 return gsc_readb(eisa_permute(port));
87 unsigned short eisa_in16(unsigned short port)
90 return le16_to_cpu(gsc_readw(eisa_permute(port)));
94 unsigned int eisa_in32(unsigned short port)
97 return le32_to_cpu(gsc_readl(eisa_permute(port)));
101 void eisa_out8(unsigned char data, unsigned short port)
104 gsc_writeb(data, eisa_permute(port));
107 void eisa_out16(unsigned short data, unsigned short port)
110 gsc_writew(cpu_to_le16(data), eisa_permute(port));
113 void eisa_out32(unsigned int data, unsigned short port)
116 gsc_writel(cpu_to_le32(data), eisa_permute(port));
120 /* We call these directly without PCI. See asm/io.h. */
121 EXPORT_SYMBOL(eisa_in8);
122 EXPORT_SYMBOL(eisa_in16);
123 EXPORT_SYMBOL(eisa_in32);
124 EXPORT_SYMBOL(eisa_out8);
125 EXPORT_SYMBOL(eisa_out16);
126 EXPORT_SYMBOL(eisa_out32);
129 /* Interrupt handling */
131 /* cached interrupt mask registers */
132 static int master_mask;
133 static int slave_mask;
135 /* the trig level can be set with the
136 * eisa_irq_edge=n,n,n commandline parameter
137 * We should really read this from the EEPROM
140 /* irq 13,8,2,1,0 must be edge */
141 static unsigned int eisa_irq_level; /* default to edge triggered */
144 /* called by free irq */
145 static void eisa_disable_irq(void *irq_dev, int irq)
149 EISA_DBG("disable irq %d\n", irq);
150 /* just mask for now */
151 spin_lock_irqsave(&eisa_irq_lock, flags);
153 slave_mask |= (1 << (irq&7));
154 eisa_out8(slave_mask, 0xa1);
156 master_mask |= (1 << (irq&7));
157 eisa_out8(master_mask, 0x21);
159 spin_unlock_irqrestore(&eisa_irq_lock, flags);
160 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
161 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
164 /* called by request irq */
165 static void eisa_enable_irq(void *irq_dev, int irq)
168 EISA_DBG("enable irq %d\n", irq);
170 spin_lock_irqsave(&eisa_irq_lock, flags);
172 slave_mask &= ~(1 << (irq&7));
173 eisa_out8(slave_mask, 0xa1);
175 master_mask &= ~(1 << (irq&7));
176 eisa_out8(master_mask, 0x21);
178 spin_unlock_irqrestore(&eisa_irq_lock, flags);
179 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
180 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
183 static void eisa_mask_irq(void *irq_dev, int irq)
186 EISA_DBG("mask irq %d\n", irq);
189 spin_lock_irqsave(&eisa_irq_lock, flags);
191 slave_mask |= (1 << (irq&7));
192 eisa_out8(slave_mask, 0xa1);
194 master_mask |= (1 << (irq&7));
195 eisa_out8(master_mask, 0x21);
197 spin_unlock_irqrestore(&eisa_irq_lock, flags);
200 static void eisa_unmask_irq(void *irq_dev, int irq)
203 EISA_DBG("unmask irq %d\n", irq);
206 spin_lock_irqsave(&eisa_irq_lock, flags);
208 slave_mask &= ~(1 << (irq&7));
209 eisa_out8(slave_mask, 0xa1);
211 master_mask &= ~(1 << (irq&7));
212 eisa_out8(master_mask, 0x21);
214 spin_unlock_irqrestore(&eisa_irq_lock, flags);
217 static struct irqaction action[IRQ_PER_REGION];
219 /* EISA needs to be fixed at IRQ region #0 (EISA_IRQ_REGION) */
220 static struct irq_region eisa_irq_region = {
221 .ops = { eisa_disable_irq, eisa_enable_irq, eisa_mask_irq, eisa_unmask_irq },
222 .data = { .name = "EISA", .irqbase = 0 },
226 static irqreturn_t eisa_irq(int _, void *intr_dev, struct pt_regs *regs)
228 extern void do_irq(struct irqaction *a, int i, struct pt_regs *p);
229 int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */
232 spin_lock_irqsave(&eisa_irq_lock, flags);
233 /* read IRR command */
234 eisa_out8(0x0a, 0x20);
235 eisa_out8(0x0a, 0xa0);
237 EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n",
238 irq, eisa_in8(0x20), eisa_in8(0xa0));
240 /* read ISR command */
241 eisa_out8(0x0a, 0x20);
242 eisa_out8(0x0a, 0xa0);
243 EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n",
244 eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1));
248 /* mask irq and write eoi */
250 slave_mask |= (1 << (irq&7));
251 eisa_out8(slave_mask, 0xa1);
252 eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */
253 eisa_out8(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
256 master_mask |= (1 << (irq&7));
257 eisa_out8(master_mask, 0x21);
258 eisa_out8(0x60|irq,0x20); /* 'Specific EOI' to master */
260 spin_unlock_irqrestore(&eisa_irq_lock, flags);
263 do_irq(&eisa_irq_region.action[irq], EISA_IRQ_REGION + irq, regs);
265 spin_lock_irqsave(&eisa_irq_lock, flags);
268 slave_mask &= ~(1 << (irq&7));
269 eisa_out8(slave_mask, 0xa1);
271 master_mask &= ~(1 << (irq&7));
272 eisa_out8(master_mask, 0x21);
274 spin_unlock_irqrestore(&eisa_irq_lock, flags);
278 static irqreturn_t dummy_irq2_handler(int _, void *dev, struct pt_regs *regs)
280 printk(KERN_ALERT "eisa: uhh, irq2?\n");
284 static void init_eisa_pic(void)
288 spin_lock_irqsave(&eisa_irq_lock, flags);
290 eisa_out8(0xff, 0x21); /* mask during init */
291 eisa_out8(0xff, 0xa1); /* mask during init */
294 eisa_out8(0x11,0x20); /* ICW1 */
295 eisa_out8(0x00,0x21); /* ICW2 */
296 eisa_out8(0x04,0x21); /* ICW3 */
297 eisa_out8(0x01,0x21); /* ICW4 */
298 eisa_out8(0x40,0x20); /* OCW2 */
301 eisa_out8(0x11,0xa0); /* ICW1 */
302 eisa_out8(0x08,0xa1); /* ICW2 */
303 eisa_out8(0x02,0xa1); /* ICW3 */
304 eisa_out8(0x01,0xa1); /* ICW4 */
305 eisa_out8(0x40,0xa0); /* OCW2 */
311 eisa_out8(slave_mask, 0xa1); /* OCW1 */
312 eisa_out8(master_mask, 0x21); /* OCW1 */
314 /* setup trig level */
315 EISA_DBG("EISA edge/level %04x\n", eisa_irq_level);
317 eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge */
318 eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1);
320 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
321 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
322 EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0));
323 EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1));
325 spin_unlock_irqrestore(&eisa_irq_lock, flags);
328 /* Device initialisation */
330 #define is_mongoose(dev) (dev->id.sversion == 0x00076)
332 static int __devinit eisa_probe(struct parisc_device *dev)
336 char *name = is_mongoose(dev) ? "Mongoose" : "Wax";
338 printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n",
341 eisa_dev.hba.dev = dev;
342 eisa_dev.hba.iommu = ccio_get_iommu(dev);
344 eisa_dev.hba.lmmio_space.name = "EISA";
345 eisa_dev.hba.lmmio_space.start = F_EXTEND(0xfc000000);
346 eisa_dev.hba.lmmio_space.end = F_EXTEND(0xffbfffff);
347 eisa_dev.hba.lmmio_space.flags = IORESOURCE_MEM;
348 result = ccio_request_resource(dev, &eisa_dev.hba.lmmio_space);
350 printk(KERN_ERR "EISA: failed to claim EISA Bus address space!\n");
353 eisa_dev.hba.io_space.name = "EISA";
354 eisa_dev.hba.io_space.start = 0;
355 eisa_dev.hba.io_space.end = 0xffff;
356 eisa_dev.hba.lmmio_space.flags = IORESOURCE_IO;
357 result = request_resource(&ioport_resource, &eisa_dev.hba.io_space);
359 printk(KERN_ERR "EISA: failed to claim EISA Bus port space!\n");
362 pcibios_register_hba(&eisa_dev.hba);
364 result = request_irq(dev->irq, eisa_irq, SA_SHIRQ, "EISA", NULL);
366 printk(KERN_ERR "EISA: request_irq failed!\n");
371 action[2].handler = dummy_irq2_handler;
372 action[2].name = "cascade";
374 eisa_irq_region.data.dev = dev;
375 irq_region[0] = &eisa_irq_region;
378 if (dev->num_addrs) {
379 /* newer firmware hand out the eeprom address */
380 eisa_dev.eeprom_addr = dev->addr[0];
382 /* old firmware, need to figure out the box */
383 if (is_mongoose(dev)) {
384 eisa_dev.eeprom_addr = SNAKES_EEPROM_BASE_ADDR;
386 eisa_dev.eeprom_addr = MIRAGE_EEPROM_BASE_ADDR;
389 eisa_eeprom_init(eisa_dev.eeprom_addr);
390 result = eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space, &eisa_dev.hba.lmmio_space);
394 /* FIXME : Don't enumerate the bus twice. */
395 eisa_dev.root.dev = &dev->dev;
396 dev->dev.driver_data = &eisa_dev.root;
397 eisa_dev.root.bus_base_addr = 0;
398 eisa_dev.root.res = &eisa_dev.hba.io_space;
399 eisa_dev.root.slots = result;
400 eisa_dev.root.dma_mask = 0xffffffff; /* wild guess */
401 if (eisa_root_register (&eisa_dev.root)) {
402 printk(KERN_ERR "EISA: Failed to register EISA root\n");
410 static struct parisc_device_id eisa_tbl[] = {
411 { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00076 }, /* Mongoose */
412 { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00090 }, /* Wax EISA */
416 MODULE_DEVICE_TABLE(parisc, eisa_tbl);
418 static struct parisc_driver eisa_driver = {
419 .name = "EISA Bus Adapter",
420 .id_table = eisa_tbl,
424 void __init eisa_init(void)
426 register_parisc_driver(&eisa_driver);
430 static unsigned int eisa_irq_configured;
431 void eisa_make_irq_level(int num)
433 if (eisa_irq_configured& (1<<num)) {
435 "IRQ %d polarity configured twice (last to level)\n",
438 eisa_irq_level |= (1<<num); /* set the corresponding bit */
439 eisa_irq_configured |= (1<<num); /* set the corresponding bit */
442 void eisa_make_irq_edge(int num)
444 if (eisa_irq_configured& (1<<num)) {
446 "IRQ %d polarity configured twice (last to edge)\n",
449 eisa_irq_level &= ~(1<<num); /* clear the corresponding bit */
450 eisa_irq_configured |= (1<<num); /* set the corresponding bit */
453 static int __init eisa_irq_setup(char *str)
458 EISA_DBG("IRQ setup\n");
459 while (cur != NULL) {
462 val = (int) simple_strtoul(cur, &pe, 0);
463 if (val > 15 || val < 0) {
464 printk(KERN_ERR "eisa: EISA irq value are 0-15\n");
470 eisa_make_irq_edge(val); /* clear the corresponding bit */
471 EISA_DBG("setting IRQ %d to edge-triggered mode\n", val);
473 if ((cur = strchr(cur, ','))) {
482 __setup("eisa_irq_edge=", eisa_irq_setup);