2 ** I/O Sapic Driver - PCI interrupt line support
4 ** (c) Copyright 1999 Grant Grundler
5 ** (c) Copyright 1999 Hewlett-Packard Company
7 ** This program is free software; you can redistribute it and/or modify
8 ** it under the terms of the GNU General Public License as published by
9 ** the Free Software Foundation; either version 2 of the License, or
10 ** (at your option) any later version.
12 ** The I/O sapic driver manages the Interrupt Redirection Table which is
13 ** the control logic to convert PCI line based interrupts into a Message
14 ** Signaled Interrupt (aka Transaction Based Interrupt, TBI).
18 ** HPA Hard Physical Address (aka MMIO address)
19 ** IRQ Interrupt ReQuest. Implies Line based interrupt.
20 ** IRT Interrupt Routing Table (provided by PAT firmware)
21 ** IRdT Interrupt Redirection Table. IRQ line to TXN ADDR/DATA
22 ** table which is implemented in I/O SAPIC.
23 ** ISR Interrupt Service Routine. aka Interrupt handler.
24 ** MSI Message Signaled Interrupt. PCI 2.2 functionality.
25 ** aka Transaction Based Interrupt (or TBI).
26 ** PA Precision Architecture. HP's RISC architecture.
27 ** RISC Reduced Instruction Set Computer.
30 ** What's a Message Signalled Interrupt?
31 ** -------------------------------------
32 ** MSI is a write transaction which targets a processor and is similar
33 ** to a processor write to memory or MMIO. MSIs can be generated by I/O
34 ** devices as well as processors and require *architecture* to work.
36 ** PA only supports MSI. So I/O subsystems must either natively generate
37 ** MSIs (e.g. GSC or HP-PB) or convert line based interrupts into MSIs
38 ** (e.g. PCI and EISA). IA64 supports MSIs via a "local SAPIC" which
39 ** acts on behalf of a processor.
41 ** MSI allows any I/O device to interrupt any processor. This makes
42 ** load balancing of the interrupt processing possible on an SMP platform.
43 ** Interrupts are also ordered WRT to DMA data. It's possible on I/O
44 ** coherent systems to completely eliminate PIO reads from the interrupt
45 ** path. The device and driver must be designed and implemented to
46 ** guarantee all DMA has been issued (issues about atomicity here)
47 ** before the MSI is issued. I/O status can then safely be read from
48 ** DMA'd data by the ISR.
53 ** PA-RISC platforms have two fundementally different types of firmware.
54 ** For PCI devices, "Legacy" PDC initializes the "INTERRUPT_LINE" register
55 ** and BARs similar to a traditional PC BIOS.
56 ** The newer "PAT" firmware supports PDC calls which return tables.
57 ** PAT firmware only initializes PCI Console and Boot interface.
58 ** With these tables, the OS can progam all other PCI devices.
60 ** One such PAT PDC call returns the "Interrupt Routing Table" (IRT).
61 ** The IRT maps each PCI slot's INTA-D "output" line to an I/O SAPIC
62 ** input line. If the IRT is not available, this driver assumes
63 ** INTERRUPT_LINE register has been programmed by firmware. The latter
64 ** case also means online addition of PCI cards can NOT be supported
65 ** even if HW support is present.
67 ** All platforms with PAT firmware to date (Oct 1999) use one Interrupt
68 ** Routing Table for the entire platform.
70 ** Where's the iosapic?
71 ** --------------------
72 ** I/O sapic is part of the "Core Electronics Complex". And on HP platforms
73 ** it's integrated as part of the PCI bus adapter, "lba". So no bus walk
74 ** will discover I/O Sapic. I/O Sapic driver learns about each device
75 ** when lba driver advertises the presence of the I/O sapic by calling
76 ** iosapic_register().
81 ** The IO-SAPIC can indicate to the CPU which interrupt was asserted.
82 ** So, unlike the GSC-ASIC and Dino, we allocate one CPU interrupt per
83 ** IO-SAPIC interrupt and call the device driver's handler directly.
84 ** The IO-SAPIC driver hijacks the CPU interrupt handler so it can
85 ** issue the End Of Interrupt command to the IO-SAPIC.
87 ** Overview of exported iosapic functions
88 ** --------------------------------------
89 ** (caveat: code isn't finished yet - this is just the plan)
92 ** o initialize globals (lock, etc)
93 ** o try to read IRT. Presence of IRT determines if this is
94 ** a PAT platform or not.
96 ** iosapic_register():
97 ** o create iosapic_info instance data structure
98 ** o allocate vector_info array for this iosapic
99 ** o initialize vector_info - read corresponding IRdT?
101 ** iosapic_xlate_pin: (only called by fixup_irq for PAT platform)
102 ** o intr_pin = read cfg (INTERRUPT_PIN);
103 ** o if (device under PCI-PCI bridge)
104 ** translate slot/pin
106 ** iosapic_fixup_irq:
107 ** o if PAT platform (IRT present)
108 ** intr_pin = iosapic_xlate_pin(isi,pcidev):
109 ** intr_line = find IRT entry(isi, PCI_SLOT(pcidev), intr_pin)
110 ** save IRT entry into vector_info later
111 ** write cfg INTERRUPT_LINE (with intr_line)?
113 ** intr_line = pcidev->irq
114 ** IRT pointer = NULL
116 ** o locate vector_info (needs: isi, intr_line)
117 ** o allocate processor "irq" and get txn_addr/data
118 ** o request_irq(processor_irq, iosapic_interrupt, vector_info,...)
120 ** iosapic_enable_irq:
121 ** o clear any pending IRQ on that line
122 ** o enable IRdT - call enable_irq(vector[line]->processor_irq)
123 ** o write EOI in case line is already asserted.
125 ** iosapic_disable_irq:
126 ** o disable IRdT - call disable_irq(vector[line]->processor_irq)
130 /* FIXME: determine which include files are really needed */
131 #include <linux/types.h>
132 #include <linux/kernel.h>
133 #include <linux/spinlock.h>
134 #include <linux/pci.h>
135 #include <linux/init.h>
136 #include <linux/slab.h>
137 #include <linux/interrupt.h>
139 #include <asm/byteorder.h> /* get in-line asm for swab */
141 #include <asm/pdcpat.h>
142 #include <asm/page.h>
143 #include <asm/system.h>
144 #include <asm/io.h> /* read/write functions */
145 #ifdef CONFIG_SUPERIO
146 #include <asm/superio.h>
149 #include <asm/iosapic.h>
150 #include "./iosapic_private.h"
152 #define MODULE_NAME "iosapic"
154 /* "local" compile flags */
155 #undef PCI_BRIDGE_FUNCS
157 #undef DEBUG_IOSAPIC_IRT
161 static char assert_buf[128];
164 assert_failed (char *a, char *f, int l)
167 "ASSERT(%s) failed!\nline %d in %s\n",
168 a, /* assertion text */
176 #define ASSERT(EX) { if (!(EX)) assert_failed(# EX, __FILE__, __LINE__); }
178 #define DBG(x...) printk(x)
180 #else /* DEBUG_IOSAPIC */
186 #endif /* DEBUG_IOSAPIC */
188 #ifdef DEBUG_IOSAPIC_IRT
189 #define DBG_IRT(x...) printk(x)
191 #define DBG_IRT(x...)
195 #define IOSAPIC_REG_SELECT 0x00
196 #define IOSAPIC_REG_WINDOW 0x10
197 #define IOSAPIC_REG_EOI 0x40
199 #define IOSAPIC_REG_VERSION 0x1
201 #define IOSAPIC_IRDT_ENTRY(idx) (0x10+(idx)*2)
202 #define IOSAPIC_IRDT_ENTRY_HI(idx) (0x11+(idx)*2)
204 static inline unsigned int iosapic_read(unsigned long iosapic, unsigned int reg)
206 writel(reg, iosapic + IOSAPIC_REG_SELECT);
207 return readl(iosapic + IOSAPIC_REG_WINDOW);
210 static inline void iosapic_write(unsigned long iosapic, unsigned int reg, u32 val)
212 writel(reg, iosapic + IOSAPIC_REG_SELECT);
213 writel(val, iosapic + IOSAPIC_REG_WINDOW);
217 ** GFP_KERNEL includes __GFP_WAIT flag and that may not
218 ** be acceptable. Since this is boot time, we shouldn't have
219 ** to wait ever and this code should (will?) never get called
220 ** from the interrrupt context.
222 #define IOSAPIC_KALLOC(a_type, cnt) \
223 (a_type *) kmalloc(sizeof(a_type)*(cnt), GFP_KERNEL)
224 #define IOSAPIC_FREE(addr, f_type, cnt) kfree((void *)addr)
227 #define IOSAPIC_LOCK(lck) spin_lock_irqsave(lck, irqflags)
228 #define IOSAPIC_UNLOCK(lck) spin_unlock_irqrestore(lck, irqflags)
231 #define IOSAPIC_VERSION_MASK 0x000000ff
232 #define IOSAPIC_VERSION(ver) ((int) (ver & IOSAPIC_VERSION_MASK))
234 #define IOSAPIC_MAX_ENTRY_MASK 0x00ff0000
235 #define IOSAPIC_MAX_ENTRY_SHIFT 0x10
236 #define IOSAPIC_IRDT_MAX_ENTRY(ver) \
237 (int) (((ver) & IOSAPIC_MAX_ENTRY_MASK) >> IOSAPIC_MAX_ENTRY_SHIFT)
239 /* bits in the "low" I/O Sapic IRdT entry */
240 #define IOSAPIC_IRDT_ENABLE 0x10000
241 #define IOSAPIC_IRDT_PO_LOW 0x02000
242 #define IOSAPIC_IRDT_LEVEL_TRIG 0x08000
243 #define IOSAPIC_IRDT_MODE_LPRI 0x00100
245 /* bits in the "high" I/O Sapic IRdT entry */
246 #define IOSAPIC_IRDT_ID_EID_SHIFT 0x10
249 static spinlock_t iosapic_lock = SPIN_LOCK_UNLOCKED;
251 static inline void iosapic_eoi(void __iomem *addr, unsigned int data)
253 __raw_writel(data, addr);
257 ** REVISIT: future platforms may have more than one IRT.
258 ** If so, the following three fields form a structure which
259 ** then be linked into a list. Names are chosen to make searching
260 ** for them easy - not necessarily accurate (eg "cell").
262 ** Alternative: iosapic_info could point to the IRT it's in.
263 ** iosapic_register() could search a list of IRT's.
265 static struct irt_entry *irt_cell;
266 static size_t irt_num_entry;
273 ** The "Get PCI INT Routing Table Size" option returns the number of
274 ** entries in the PCI interrupt routing table for the cell specified
275 ** in the cell_number argument. The cell number must be for a cell
276 ** within the caller's protection domain.
278 ** The "Get PCI INT Routing Table" option returns, for the cell
279 ** specified in the cell_number argument, the PCI interrupt routing
280 ** table in the caller allocated memory pointed to by mem_addr.
281 ** We assume the IRT only contains entries for I/O SAPIC and
282 ** calculate the size based on the size of I/O sapic entries.
284 ** The PCI interrupt routing table entry format is derived from the
285 ** IA64 SAL Specification 2.4. The PCI interrupt routing table defines
286 ** the routing of PCI interrupt signals between the PCI device output
287 ** "pins" and the IO SAPICs' input "lines" (including core I/O PCI
288 ** devices). This table does NOT include information for devices/slots
289 ** behind PCI to PCI bridges. See PCI to PCI Bridge Architecture Spec.
290 ** for the architected method of routing of IRQ's behind PPB's.
294 static int __init /* return number of entries as success/fail flag */
295 iosapic_load_irt(unsigned long cell_num, struct irt_entry **irt)
297 long status; /* PDC return value status */
298 struct irt_entry *table; /* start of interrupt routing tbl */
299 unsigned long num_entries = 0UL;
305 /* Use pat pdc routine to get interrupt routing table size */
306 DBG("calling get_irt_size (cell %ld)\n", cell_num);
307 status = pdc_pat_get_irt_size(&num_entries, cell_num);
308 DBG("get_irt_size: %ld\n", status);
310 ASSERT(status == PDC_OK);
312 /* save the number of entries in the table */
313 ASSERT(0UL != num_entries);
316 ** allocate memory for interrupt routing table
317 ** This interface isn't really right. We are assuming
318 ** the contents of the table are exclusively
319 ** for I/O sapic devices.
321 table = IOSAPIC_KALLOC(struct irt_entry, num_entries);
323 printk(KERN_WARNING MODULE_NAME ": read_irt : can not alloc mem for IRT\n");
327 /* get PCI INT routing table */
328 status = pdc_pat_get_irt(table, cell_num);
329 DBG("pdc_pat_get_irt: %ld\n", status);
330 ASSERT(status == PDC_OK);
333 ** C3000/J5000 (and similar) platforms with Sprockets PDC
334 ** will return exactly one IRT for all iosapics.
335 ** So if we have one, don't need to get it again.
337 if (NULL != irt_cell)
340 /* Should be using the Elroy's HPA, but it's ignored anyway */
341 status = pdc_pci_irt_size(&num_entries, 0);
342 DBG("pdc_pci_irt_size: %ld\n", status);
344 if (PDC_OK != status) {
345 /* Not a "legacy" system with I/O SAPIC either */
349 ASSERT(0UL != num_entries);
351 table = IOSAPIC_KALLOC(struct irt_entry, num_entries);
353 printk(KERN_WARNING MODULE_NAME ": read_irt : can not alloc mem for IRT\n");
357 /* HPA ignored by this call too. */
358 status = pdc_pci_irt(num_entries, 0, table);
359 ASSERT(PDC_OK == status);
362 /* return interrupt table address */
365 #ifdef DEBUG_IOSAPIC_IRT
367 struct irt_entry *p = table;
370 printk(MODULE_NAME " Interrupt Routing Table (cell %ld)\n", cell_num);
371 printk(MODULE_NAME " start = 0x%p num_entries %ld entry_size %d\n",
374 (int) sizeof(struct irt_entry));
376 for (i = 0 ; i < num_entries ; i++, p++) {
377 printk(MODULE_NAME " %02x %02x %02x %02x %02x %02x %02x %02x %08x%08x\n",
378 p->entry_type, p->entry_length, p->interrupt_type,
379 p->polarity_trigger, p->src_bus_irq_devno, p->src_bus_id,
380 p->src_seg_id, p->dest_iosapic_intin,
386 #endif /* DEBUG_IOSAPIC_IRT */
396 unsigned long cell = 0;
398 /* init global data */
399 spin_lock_init(&iosapic_lock);
400 iosapic_list = (struct iosapic_info *) NULL;
403 DBG("iosapic_init()\n");
408 struct pdc_pat_cell_num cell_info;
410 status = pdc_pat_cell_get_number(&cell_info);
411 if (status == PDC_OK) {
412 cell = cell_info.cell_num;
418 ** get IRT for this cell.
420 irt_num_entry = iosapic_load_irt(cell, &irt_cell);
421 if (0 == irt_num_entry)
422 irt_cell = NULL; /* old PDC w/o iosapic */
427 ** Return the IRT entry in case we need to look something else up.
429 static struct irt_entry *
430 irt_find_irqline(struct iosapic_info *isi, u8 slot, u8 intr_pin)
432 struct irt_entry *i = irt_cell;
433 int cnt; /* track how many entries we've looked at */
434 u8 irq_devno = (slot << IRT_DEV_SHIFT) | (intr_pin-1);
436 DBG_IRT("irt_find_irqline() SLOT %d pin %d\n", slot, intr_pin);
438 for (cnt=0; cnt < irt_num_entry; cnt++, i++) {
441 ** Validate: entry_type, entry_length, interrupt_type
443 ** Difference between validate vs compare is the former
444 ** should print debug info and is not expected to "fail"
445 ** on current platforms.
447 if (i->entry_type != IRT_IOSAPIC_TYPE) {
448 DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d type %d\n", i, cnt, i->entry_type);
452 if (i->entry_length != IRT_IOSAPIC_LENGTH) {
453 DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d length %d\n", i, cnt, i->entry_length);
457 if (i->interrupt_type != IRT_VECTORED_INTR) {
458 DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d interrupt_type %d\n", i, cnt, i->interrupt_type);
463 ** Compare: dest_iosapic_addr, src_bus_irq_devno
465 if (i->dest_iosapic_addr != (u64) ((long) isi->isi_hpa))
468 if ((i->src_bus_irq_devno & IRT_IRQ_DEVNO_MASK) != irq_devno)
472 ** Ignore: src_bus_id and rc_seg_id correlate with
473 ** iosapic_info->isi_hpa on HP platforms.
474 ** If needed, pass in "PFA" (aka config space addr)
482 printk(KERN_WARNING MODULE_NAME ": 0x%lx : no IRT entry for slot %d, pin %d\n",
483 isi->isi_hpa, slot, intr_pin);
489 ** xlate_pin() supports the skewing of IRQ lines done by subsidiary bridges.
490 ** Legacy PDC already does this translation for us and stores it in INTR_LINE.
492 ** PAT PDC needs to basically do what legacy PDC does:
494 ** o adjust PIN in case device is "behind" a PPB
495 ** (eg 4-port 100BT and SCSI/LAN "Combo Card")
496 ** o convert slot/pin to I/O SAPIC input line.
498 ** HP platforms only support:
499 ** o one level of skewing for any number of PPBs
500 ** o only support PCI-PCI Bridges.
502 static struct irt_entry *
503 iosapic_xlate_pin(struct iosapic_info *isi, struct pci_dev *pcidev)
505 u8 intr_pin, intr_slot;
507 pci_read_config_byte(pcidev, PCI_INTERRUPT_PIN, &intr_pin);
509 DBG_IRT("iosapic_xlate_pin() SLOT %d pin %d\n",
510 PCI_SLOT(pcidev->devfn), intr_pin);
513 /* The device does NOT support/use IRQ lines. */
517 /* Check if pcidev behind a PPB */
518 if (NULL != pcidev->bus->self) {
519 /* Convert pcidev INTR_PIN into something we
520 ** can lookup in the IRT.
522 #ifdef PCI_BRIDGE_FUNCS
526 ** call implementation specific translation function
527 ** This is architecturally "cleaner". HP-UX doesn't
528 ** support other secondary bus types (eg. E/ISA) directly.
529 ** May be needed for other processor (eg IA64) architectures
530 ** or by some ambitous soul who wants to watch TV.
532 if (pci_bridge_funcs->xlate_intr_line) {
533 intr_pin = pci_bridge_funcs->xlate_intr_line(pcidev);
535 #else /* PCI_BRIDGE_FUNCS */
536 struct pci_bus *p = pcidev->bus;
539 ** The "pin" is skewed ((pin + dev - 1) % 4).
541 ** This isn't very clean since I/O SAPIC must assume:
542 ** - all platforms only have PCI busses.
543 ** - only PCI-PCI bridge (eg not PCI-EISA, PCI-PCMCIA)
544 ** - IRQ routing is only skewed once regardless of
545 ** the number of PPB's between iosapic and device.
546 ** (Bit3 expansion chassis follows this rule)
548 ** Advantage is it's really easy to implement.
550 intr_pin = ((intr_pin-1)+PCI_SLOT(pcidev->devfn)) % 4;
551 intr_pin++; /* convert back to INTA-D (1-4) */
552 #endif /* PCI_BRIDGE_FUNCS */
555 ** Locate the host slot the PPB nearest the Host bus
558 while (NULL != p->parent->self)
561 intr_slot = PCI_SLOT(p->self->devfn);
563 intr_slot = PCI_SLOT(pcidev->devfn);
565 DBG_IRT("iosapic_xlate_pin: bus %d slot %d pin %d\n",
566 pcidev->bus->secondary, intr_slot, intr_pin);
568 return irt_find_irqline(isi, intr_slot, intr_pin);
571 static void iosapic_rd_irt_entry(struct vector_info *vi , u32 *dp0, u32 *dp1)
573 struct iosapic_info *isp = vi->iosapic;
574 u8 idx = vi->irqline;
576 *dp0 = iosapic_read(isp->addr, IOSAPIC_IRDT_ENTRY(idx));
577 *dp1 = iosapic_read(isp->addr, IOSAPIC_IRDT_ENTRY_HI(idx));
581 static void iosapic_wr_irt_entry(struct vector_info *vi, u32 dp0, u32 dp1)
583 struct iosapic_info *isp = vi->iosapic;
585 DBG_IRT("iosapic_wr_irt_entry(): irq %d hpa %lx 0x%x 0x%x\n",
586 vi->irqline, isp->isi_hpa, dp0, dp1);
588 iosapic_write(isp->addr, IOSAPIC_IRDT_ENTRY(vi->irqline), dp0);
590 /* Read the window register to flush the writes down to HW */
591 dp0 = readl(isp->addr+IOSAPIC_REG_WINDOW);
593 iosapic_write(isp->addr, IOSAPIC_IRDT_ENTRY_HI(vi->irqline), dp1);
595 /* Read the window register to flush the writes down to HW */
596 dp1 = readl(isp->addr+IOSAPIC_REG_WINDOW);
600 ** set_irt prepares the data (dp0, dp1) according to the vector_info
601 ** and target cpu (id_eid). dp0/dp1 are then used to program I/O SAPIC
602 ** IRdT for the given "vector" (aka IRQ line).
605 iosapic_set_irt_data( struct vector_info *vi, u32 *dp0, u32 *dp1)
608 struct irt_entry *p = vi->irte;
609 ASSERT(NULL != vi->irte);
611 if ((p->polarity_trigger & IRT_PO_MASK) == IRT_ACTIVE_LO)
612 mode |= IOSAPIC_IRDT_PO_LOW;
614 if (((p->polarity_trigger >> IRT_EL_SHIFT) & IRT_EL_MASK) == IRT_LEVEL_TRIG)
615 mode |= IOSAPIC_IRDT_LEVEL_TRIG;
619 ** PA doesn't support EXTINT or LPRIO bits.
622 ASSERT(vi->txn_data);
623 *dp0 = mode | (u32) vi->txn_data;
626 ** Extracting id_eid isn't a real clean way of getting it.
627 ** But the encoding is the same for both PA and IA64 platforms.
631 ** PAT PDC just hands it to us "right".
632 ** txn_addr comes from cpu_data[x].txn_addr.
634 *dp1 = (u32) (vi->txn_addr);
637 ** eg if base_addr == 0xfffa0000),
638 ** we want to get 0xa0ff0000.
640 ** eid 0x0ff00000 -> 0x00ff0000
641 ** id 0x000ff000 -> 0xff000000
643 *dp1 = (((u32)vi->txn_addr & 0x0ff00000) >> 4) |
644 (((u32)vi->txn_addr & 0x000ff000) << 12);
646 DBG_IRT("iosapic_set_irt_data(): 0x%x 0x%x\n", *dp0, *dp1);
650 static struct vector_info *iosapic_get_vector(unsigned int irq)
652 return irq_desc[irq].handler_data;
655 static void iosapic_disable_irq(unsigned int irq)
658 struct vector_info *vi = iosapic_get_vector(irq);
661 spin_lock_irqsave(&iosapic_lock, flags);
662 iosapic_rd_irt_entry(vi, &d0, &d1);
663 d0 |= IOSAPIC_IRDT_ENABLE;
664 iosapic_wr_irt_entry(vi, d0, d1);
665 spin_unlock_irqrestore(&iosapic_lock, flags);
668 static void iosapic_enable_irq(unsigned int irq)
670 struct vector_info *vi = iosapic_get_vector(irq);
673 /* data is initialized by fixup_irq */
674 WARN_ON(vi->txn_irq == 0);
676 iosapic_set_irt_data(vi, &d0, &d1);
677 iosapic_wr_irt_entry(vi, d0, d1);
679 #ifdef DEBUG_IOSAPIC_IRT
681 u32 *t = (u32 *) ((ulong) vi->eoi_addr & ~0xffUL);
682 printk("iosapic_enable_irq(): regs %p", vi->eoi_addr);
683 for ( ; t < vi->eoi_addr; t++)
684 printk(" %x", readl(t));
688 printk("iosapic_enable_irq(): sel ");
690 struct iosapic_info *isp = vi->iosapic;
692 for (d0=0x10; d0<0x1e; d0++) {
693 d1 = iosapic_read(isp->addr, d0);
701 * Issuing I/O SAPIC an EOI causes an interrupt IFF IRQ line is
702 * asserted. IRQ generally should not be asserted when a driver
703 * enables their IRQ. It can lead to "interesting" race conditions
704 * in the driver initialization sequence.
706 DBG(KERN_DEBUG "enable_irq(%d): eoi(%p, 0x%x)\n", irq,
707 vi->eoi_addr, vi->eoi_data);
708 iosapic_eoi(vi->eoi_addr, vi->eoi_data);
712 * PARISC only supports PCI devices below I/O SAPIC.
713 * PCI only supports level triggered in order to share IRQ lines.
714 * ergo I/O SAPIC must always issue EOI on parisc.
716 * i386/ia64 support ISA devices and have to deal with
717 * edge-triggered interrupts too.
719 static void iosapic_end_irq(unsigned int irq)
721 struct vector_info *vi = iosapic_get_vector(irq);
722 DBG(KERN_DEBUG "end_irq(%d): eoi(%p, 0x%x)\n", irq,
723 vi->eoi_addr, vi->eoi_data);
724 iosapic_eoi(vi->eoi_addr, vi->eoi_data);
727 static unsigned int iosapic_startup_irq(unsigned int irq)
729 iosapic_enable_irq(irq);
733 static struct hw_interrupt_type iosapic_interrupt_type = {
734 .typename = "IO-SAPIC-level",
735 .startup = iosapic_startup_irq,
736 .shutdown = iosapic_disable_irq,
737 .enable = iosapic_enable_irq,
738 .disable = iosapic_disable_irq,
740 .end = iosapic_end_irq,
741 // .set_affinity = iosapic_set_affinity_irq,
744 int iosapic_fixup_irq(void *isi_obj, struct pci_dev *pcidev)
746 struct iosapic_info *isi = isi_obj;
747 struct irt_entry *irte = NULL; /* only used if PAT PDC */
748 struct vector_info *vi;
749 int isi_line; /* line used by device */
752 printk(KERN_WARNING MODULE_NAME ": hpa not registered for %s\n",
757 #ifdef CONFIG_SUPERIO
759 * HACK ALERT! (non-compliant PCI device support)
761 * All SuckyIO interrupts are routed through the PIC's on function 1.
762 * But SuckyIO OHCI USB controller gets an IRT entry anyway because
763 * it advertises INT D for INT_PIN. Use that IRT entry to get the
764 * SuckyIO interrupt routing for PICs on function 1 (*BLEECCHH*).
766 if (is_superio_device(pcidev)) {
767 /* We must call superio_fixup_irq() to register the pdev */
768 pcidev->irq = superio_fixup_irq(pcidev);
770 /* Don't return if need to program the IOSAPIC's IRT... */
771 if (PCI_FUNC(pcidev->devfn) != SUPERIO_USB_FN)
774 #endif /* CONFIG_SUPERIO */
776 /* lookup IRT entry for isi/slot/pin set */
777 irte = iosapic_xlate_pin(isi, pcidev);
779 printk("iosapic: no IRTE for %s (IRQ not connected?)\n",
783 DBG_IRT("iosapic_fixup_irq(): irte %p %x %x %x %x %x %x %x %x\n",
787 irte->polarity_trigger,
788 irte->src_bus_irq_devno,
791 irte->dest_iosapic_intin,
792 (u32) irte->dest_iosapic_addr);
793 isi_line = irte->dest_iosapic_intin;
795 /* get vector info for this input line */
796 vi = isi->isi_vector + isi_line;
797 DBG_IRT("iosapic_fixup_irq: line %d vi 0x%p\n", isi_line, vi);
799 /* If this IRQ line has already been setup, skip it */
805 /* Allocate processor IRQ */
806 vi->txn_irq = txn_alloc_irq();
809 * XXX/FIXME The txn_alloc_irq() code and related code should be
810 * moved to enable_irq(). That way we only allocate processor IRQ
811 * bits for devices that actually have drivers claiming them.
812 * Right now we assign an IRQ to every PCI device present,
813 * regardless of whether it's used or not.
816 panic("I/O sapic: couldn't get TXN IRQ\n");
818 /* enable_irq() will use txn_* to program IRdT */
819 vi->txn_addr = txn_alloc_addr(vi->txn_irq);
820 vi->txn_data = txn_alloc_data(vi->txn_irq, 8);
822 vi->eoi_addr = isi->addr + IOSAPIC_REG_EOI;
823 vi->eoi_data = cpu_to_le32(vi->txn_data);
825 cpu_claim_irq(vi->txn_irq, &iosapic_interrupt_type, vi);
828 pcidev->irq = vi->txn_irq;
830 DBG_IRT("iosapic_fixup_irq() %d:%d %x %x line %d irq %d\n",
831 PCI_SLOT(pcidev->devfn), PCI_FUNC(pcidev->devfn),
832 pcidev->vendor, pcidev->device, isi_line, pcidev->irq);
839 ** squirrel away the I/O Sapic Version
842 iosapic_rd_version(struct iosapic_info *isi)
845 ASSERT(isi->isi_hpa);
847 return iosapic_read(isi->isi_hpa, IOSAPIC_REG_VERSION);
852 ** iosapic_register() is called by "drivers" with an integrated I/O SAPIC.
853 ** Caller must be certain they have an I/O SAPIC and know its MMIO address.
855 ** o allocate iosapic_info and add it to the list
856 ** o read iosapic version and squirrel that away
857 ** o read size of IRdT.
858 ** o allocate and initialize isi_vector[]
859 ** o allocate irq region
861 void *iosapic_register(unsigned long hpa)
863 struct iosapic_info *isi = NULL;
864 struct irt_entry *irte = irt_cell;
865 struct vector_info *vip;
866 int cnt; /* track how many entries we've looked at */
869 ** Astro based platforms can't support PCI OLARD if they
870 ** implement the legacy PDC (not PAT). Though Legacy PDC
871 ** supports an IRT, LBA's with no device under them
872 ** are *not* listed in the IRT.
873 ** Search the IRT and ignore iosapic's which aren't
876 ASSERT(NULL != irte); /* always have built-in devices */
877 for (cnt=0; cnt < irt_num_entry; cnt++, irte++) {
878 ASSERT(IRT_IOSAPIC_TYPE == irte->entry_type);
880 ** We need sign extension of the hpa on 32-bit kernels.
881 ** The address in the IRT is *always* 64 bit and really
882 ** is an unsigned quantity (like all physical addresses).
884 if (irte->dest_iosapic_addr == (s64) ((long) hpa))
888 if (cnt >= irt_num_entry)
891 if ((isi = IOSAPIC_KALLOC(struct iosapic_info, 1)) == NULL) {
896 memset(isi, 0, sizeof(struct iosapic_info));
899 isi->isi_version = iosapic_rd_version(isi);
900 isi->isi_num_vectors = IOSAPIC_IRDT_MAX_ENTRY(isi->isi_version) + 1;
902 vip = isi->isi_vector =
903 IOSAPIC_KALLOC(struct vector_info, isi->isi_num_vectors);
906 IOSAPIC_FREE(isi, struct iosapic_info, 1);
910 memset(vip, 0, sizeof(struct vector_info) * isi->isi_num_vectors);
912 for (cnt=0; cnt < isi->isi_num_vectors; cnt++, vip++) {
913 vip->irqline = (unsigned char) cnt;
923 iosapic_prt_irt(void *irt, long num_entry)
925 unsigned int i, *irp = (unsigned int *) irt;
929 printk(KERN_DEBUG MODULE_NAME ": Interrupt Routing Table (%lx entries)\n", num_entry);
931 for (i=0; i<num_entry; i++, irp += 4) {
932 printk(KERN_DEBUG "%p : %2d %.8x %.8x %.8x %.8x\n",
933 irp, i, irp[0], irp[1], irp[2], irp[3]);
939 iosapic_prt_vi(struct vector_info *vi)
943 printk(KERN_DEBUG MODULE_NAME ": vector_info[%d] is at %p\n", vi->irqline, vi);
944 printk(KERN_DEBUG "\t\tstatus: %.4x\n", vi->status);
945 printk(KERN_DEBUG "\t\ttxn_irq: %d\n", vi->txn_irq);
946 printk(KERN_DEBUG "\t\ttxn_addr: %lx\n", vi->txn_addr);
947 printk(KERN_DEBUG "\t\ttxn_data: %lx\n", vi->txn_data);
948 printk(KERN_DEBUG "\t\teoi_addr: %p\n", vi->eoi_addr);
949 printk(KERN_DEBUG "\t\teoi_data: %x\n", vi->eoi_data);
954 iosapic_prt_isi(struct iosapic_info *isi)
957 printk(KERN_DEBUG MODULE_NAME ": io_sapic_info at %p\n", isi);
958 printk(KERN_DEBUG "\t\tisi_hpa: %lx\n", isi->isi_hpa);
959 printk(KERN_DEBUG "\t\tisi_status: %x\n", isi->isi_status);
960 printk(KERN_DEBUG "\t\tisi_version: %x\n", isi->isi_version);
961 printk(KERN_DEBUG "\t\tisi_vector: %p\n", isi->isi_vector);
963 #endif /* DEBUG_IOSAPIC */