2 ** PCI Lower Bus Adapter (LBA) manager
4 ** (c) Copyright 1999,2000 Grant Grundler
5 ** (c) Copyright 1999,2000 Hewlett-Packard Company
7 ** This program is free software; you can redistribute it and/or modify
8 ** it under the terms of the GNU General Public License as published by
9 ** the Free Software Foundation; either version 2 of the License, or
10 ** (at your option) any later version.
13 ** This module primarily provides access to PCI bus (config/IOport
14 ** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class
15 ** with 4 digit model numbers - eg C3000 (and A400...sigh).
17 ** LBA driver isn't as simple as the Dino driver because:
18 ** (a) this chip has substantial bug fixes between revisions
19 ** (Only one Dino bug has a software workaround :^( )
20 ** (b) has more options which we don't (yet) support (DMA hints, OLARD)
21 ** (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver)
22 ** (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC).
23 ** (dino only deals with "Legacy" PDC)
25 ** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver.
26 ** (I/O SAPIC is integratd in the LBA chip).
28 ** FIXME: Add support to SBA and LBA drivers for DMA hint sets
29 ** FIXME: Add support for PCI card hot-plug (OLARD).
32 #include <linux/delay.h>
33 #include <linux/types.h>
34 #include <linux/kernel.h>
35 #include <linux/spinlock.h>
36 #include <linux/init.h> /* for __init and __devinit */
37 /* #define PCI_DEBUG enable ASSERT */
38 #include <linux/pci.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
41 #include <linux/smp_lock.h>
43 #include <asm/byteorder.h>
44 #include <asm/irq.h> /* for struct irq_region support */
47 #include <asm/segment.h>
48 #include <asm/system.h>
50 #include <asm/hardware.h> /* for register_parisc_driver() stuff */
51 #include <asm/parisc-device.h>
52 #include <asm/iosapic.h> /* for iosapic_register() */
53 #include <asm/io.h> /* read/write stuff */
57 #define FALSE (1 == 0)
60 #undef DEBUG_LBA /* general stuff */
61 #undef DEBUG_LBA_PORT /* debug I/O Port access */
62 #undef DEBUG_LBA_CFG /* debug Config Space Access (ie PCI Bus walk) */
63 #undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */
65 #undef FBB_SUPPORT /* Fast Back-Back xfers - NOT READY YET */
69 #define DBG(x...) printk(x)
75 #define DBG_PORT(x...) printk(x)
77 #define DBG_PORT(x...)
81 #define DBG_CFG(x...) printk(x)
87 #define DBG_PAT(x...) printk(x)
93 ** Config accessor functions only pass in the 8-bit bus number and not
94 ** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
95 ** number based on what firmware wrote into the scratch register.
97 ** The "secondary" bus number is set to this before calling
98 ** pci_register_ops(). If any PPB's are present, the scan will
99 ** discover them and update the "secondary" and "subordinate"
100 ** fields in the pci_bus structure.
102 ** Changes in the configuration *may* result in a different
103 ** bus number for each LBA depending on what firmware does.
106 #define MODULE_NAME "lba"
108 #define LBA_FUNC_ID 0x0000 /* function id */
109 #define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */
110 #define LBA_CAPABLE 0x0030 /* capabilities register */
112 #define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */
113 #define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */
115 #define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */
116 #define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */
117 #define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */
119 #define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */
120 #define LBA_ARB_PRI 0x0088 /* firmware sets this. */
121 #define LBA_ARB_MODE 0x0090 /* firmware sets this. */
122 #define LBA_ARB_MTLT 0x0098 /* firmware sets this. */
124 #define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */
126 #define LBA_STAT_CTL 0x0108 /* Status & Control */
127 #define LBA_BUS_RESET 0x01 /* Deassert PCI Bus Reset Signal */
128 #define CLEAR_ERRLOG 0x10 /* "Clear Error Log" cmd */
129 #define CLEAR_ERRLOG_ENABLE 0x20 /* "Clear Error Log" Enable */
130 #define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */
132 #define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */
133 #define LBA_LMMIO_MASK 0x0208
135 #define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */
136 #define LBA_GMMIO_MASK 0x0218
138 #define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */
139 #define LBA_WLMMIO_MASK 0x0228
141 #define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */
142 #define LBA_WGMMIO_MASK 0x0238
144 #define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */
145 #define LBA_IOS_MASK 0x0248
147 #define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */
148 #define LBA_ELMMIO_MASK 0x0258
150 #define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */
151 #define LBA_EIOS_MASK 0x0268
153 #define LBA_DMA_CTL 0x0278 /* firmware sets this */
155 #define LBA_IBASE 0x0300 /* SBA DMA support */
156 #define LBA_IMASK 0x0308
158 /* FIXME: ignore DMA Hint stuff until we can measure performance */
159 #define LBA_HINT_CFG 0x0310
160 #define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */
162 /* ERROR regs are needed for config cycle kluges */
163 #define LBA_ERROR_CONFIG 0x0680
164 #define LBA_SMART_MODE 0x20
165 #define LBA_ERROR_STATUS 0x0688
166 #define LBA_ROPE_CTL 0x06A0
168 #define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */
170 /* non-postable I/O port space, densely packed */
172 #define LBA_ASTRO_PORT_BASE (0xfffffffffee00000UL)
174 #define LBA_ASTRO_PORT_BASE (0xfee00000UL)
179 ** lba_device: Per instance Elroy data structure
182 struct pci_hba_data hba;
188 unsigned long iop_base; /* PA_VIEW - for IO port accessor funcs */
191 int flags; /* state/functionality enabled */
192 int hw_rev; /* HW revision of chip */
201 #define LBA_FLAG_NO_DMA_DURING_CFG 0x01
202 #define LBA_FLAG_SKIP_PROBE 0x10
204 /* Tape Release 4 == hw_rev 5 */
205 #define LBA_TR4PLUS(d) ((d)->hw_rev > 0x4)
206 #define LBA_DMA_DURING_CFG_DISABLED(d) ((d)->flags & LBA_FLAG_NO_DMA_DURING_CFG)
207 #define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)
210 /* Looks nice and keeps the compiler happy */
211 #define LBA_DEV(d) ((struct lba_device *) (d))
215 ** Only allow 8 subsidiary busses per LBA
216 ** Problem is the PCI bus numbering is globally shared.
218 #define LBA_MAX_NUM_BUSES 8
220 /************************************
221 * LBA register read and write support
223 * BE WARNED: register writes are posted.
224 * (ie follow writes which must reach HW with a read)
226 #define READ_U8(addr) __raw_readb(addr)
227 #define READ_U16(addr) __raw_readw(addr)
228 #define READ_U32(addr) __raw_readl(addr)
229 #define WRITE_U8(value, addr) __raw_writeb(value, addr)
230 #define WRITE_U16(value, addr) __raw_writew(value, addr)
231 #define WRITE_U32(value, addr) __raw_writel(value, addr)
233 #define READ_REG8(addr) readb(addr)
234 #define READ_REG16(addr) readw(addr)
235 #define READ_REG32(addr) readl(addr)
236 #define READ_REG64(addr) readq(addr)
237 #define WRITE_REG8(value, addr) writeb(value, addr)
238 #define WRITE_REG16(value, addr) writew(value, addr)
239 #define WRITE_REG32(value, addr) writel(value, addr)
242 #define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8))
243 #define LBA_CFG_BUS(tok) ((u8) ((tok)>>16))
244 #define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f)
245 #define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)
249 ** Extract LBA (Rope) number from HPA
250 ** REVISIT: 16 ropes for Stretch/Ike?
252 #define ROPES_PER_SBA 8
253 #define LBA_NUM(x) ((((unsigned long) x) >> 13) & (ROPES_PER_SBA-1))
257 lba_dump_res(struct resource *r, int d)
264 printk(KERN_DEBUG "(%p)", r->parent);
265 for (i = d; i ; --i) printk(" ");
266 printk(KERN_DEBUG "%p [%lx,%lx]/%x\n", r, r->start, r->end, (int) r->flags);
267 lba_dump_res(r->child, d+2);
268 lba_dump_res(r->sibling, d);
273 ** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex
274 ** workaround for cfg cycles:
275 ** -- preserve LBA state
276 ** -- LBA_FLAG_NO_DMA_DURING_CFG workaround
277 ** -- turn on smart mode
278 ** -- probe with config writes before doing config reads
279 ** -- check ERROR_STATUS
280 ** -- clear ERROR_STATUS
281 ** -- restore LBA state
283 ** The workaround is only used for device discovery.
287 lba_device_present( u8 bus, u8 dfn, struct lba_device *d)
289 u8 first_bus = d->hba.hba_bus->secondary;
290 u8 last_sub_bus = d->hba.hba_bus->subordinate;
292 /* FIXME - see below in this function */
293 u8 dev = PCI_SLOT(dfn);
294 u8 func = PCI_FUNC(dfn);
297 ASSERT(bus >= first_bus);
298 ASSERT(bus <= last_sub_bus);
299 ASSERT((bus - first_bus) < LBA_MAX_NUM_BUSES);
301 if ((bus < first_bus) ||
302 (bus > last_sub_bus) ||
303 ((bus - first_bus) >= LBA_MAX_NUM_BUSES))
305 /* devices that fall into any of these cases won't get claimed */
311 ** FIXME: Need to implement code to fill the devices bitmap based
312 ** on contents of the local pci_bus tree "data base".
313 ** pci_register_ops() walks the bus for us and builds the tree.
314 ** For now, always do the config cycle.
318 return (((d->devices[bus][dev]) >> func) & 0x1);
326 #define LBA_CFG_SETUP(d, tok) { \
327 /* Save contents of error config register. */ \
328 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
330 /* Save contents of status control register. */ \
331 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
333 /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA \
334 ** arbitration for full bus walks. \
336 if (LBA_DMA_DURING_CFG_DISABLED(d)) { \
337 /* Save contents of arb mask register. */ \
338 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
341 * Turn off all device arbitration bits (i.e. everything \
342 * except arbitration enable bit). \
344 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
348 * Set the smart mode bit so that master aborts don't cause \
349 * LBA to go into PCI fatal mode (required). \
351 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
355 #define LBA_CFG_PROBE(d, tok) { \
357 * Setup Vendor ID write and read back the address register \
358 * to make sure that LBA is the bus master. \
360 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
362 * Read address register to ensure that LBA is the bus master, \
363 * which implies that DMA traffic has stopped when DMA arb is off. \
365 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
367 * Generate a cfg write cycle (will have no affect on \
368 * Vendor ID register since read-only). \
370 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
372 * Make sure write has completed before proceeding further, \
373 * i.e. before setting clear enable. \
375 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
381 * -- Can't tell if config cycle got the error.
383 * OV bit is broken until rev 4.0, so can't use OV bit and
384 * LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle.
386 * As of rev 4.0, no longer need the error check.
388 * -- Even if we could tell, we still want to return -1
389 * for **ANY** error (not just master abort).
391 * -- Only clear non-fatal errors (we don't want to bring
392 * LBA out of pci-fatal mode).
394 * Actually, there is still a race in which
395 * we could be clearing a fatal error. We will
396 * live with this during our initial bus walk
397 * until rev 4.0 (no driver activity during
398 * initial bus walk). The initial bus walk
399 * has race conditions concerning the use of
400 * smart mode as well.
403 #define LBA_MASTER_ABORT_ERROR 0xc
404 #define LBA_FATAL_ERROR 0x10
406 #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \
407 u32 error_status = 0; \
409 * Set clear enable (CE) bit. Unset by HW when new \
410 * errors are logged -- LBA HW ERS section 14.3.3). \
412 WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \
413 error_status = READ_REG32(base + LBA_ERROR_STATUS); \
414 if ((error_status & 0x1f) != 0) { \
416 * Fail the config read request. \
419 if ((error_status & LBA_FATAL_ERROR) == 0) { \
421 * Clear error status (if fatal bit not set) by setting \
422 * clear error log bit (CL). \
424 WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \
429 #define LBA_CFG_TR4_ADDR_SETUP(d, addr) \
430 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR)
432 #define LBA_CFG_ADDR_SETUP(d, addr) { \
433 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
436 * -- Potentially could skip this once DMA bug fixed. \
438 * Read address register to ensure that LBA is the bus master, \
439 * which implies that DMA traffic has stopped when DMA arb is off. \
441 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
445 #define LBA_CFG_RESTORE(d, base) { \
447 * Restore status control register (turn off clear enable). \
449 WRITE_REG32(status_control, base + LBA_STAT_CTL); \
451 * Restore error config register (turn off smart mode). \
453 WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \
454 if (LBA_DMA_DURING_CFG_DISABLED(d)) { \
456 * Restore arb mask register (reenables DMA arbitration). \
458 WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \
465 lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size)
469 u32 arb_mask = 0; /* used by LBA_CFG_SETUP/RESTORE */
470 u32 error_config = 0; /* used by LBA_CFG_SETUP/RESTORE */
471 u32 status_control = 0; /* used by LBA_CFG_SETUP/RESTORE */
473 ASSERT((size == sizeof(u8)) ||
474 (size == sizeof(u16)) ||
475 (size == sizeof(u32)));
477 if ((size != sizeof(u8)) &&
478 (size != sizeof(u16)) &&
479 (size != sizeof(u32))) {
483 LBA_CFG_SETUP(d, tok);
484 LBA_CFG_PROBE(d, tok);
485 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
487 LBA_CFG_ADDR_SETUP(d, tok | reg);
490 data = (u32) READ_REG8(d->hba.base_addr + LBA_PCI_CFG_DATA + (reg & 3));
493 data = (u32) READ_REG16(d->hba.base_addr + LBA_PCI_CFG_DATA + (reg & 2));
496 data = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_DATA);
499 break; /* leave data as -1 */
502 LBA_CFG_RESTORE(d, d->hba.base_addr);
507 static int lba_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
509 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
510 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
511 u32 tok = LBA_CFG_TOK(local_bus, devfn);
513 /* FIXME: B2K/C3600 workaround is always use old method... */
514 /* if (!LBA_TR4PLUS(d) && !LBA_SKIP_PROBE(d)) */ {
515 /* original - Generate config cycle on broken elroy
516 with risk we will miss PCI bus errors. */
517 *data = lba_rd_cfg(d, tok, pos, size);
518 DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __FUNCTION__, tok, pos, *data);
519 return(*data == ~0U);
522 if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d)))
524 DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __FUNCTION__, tok, pos);
525 /* either don't want to look or know device isn't present. */
531 ** Should only get here on fully working LBA rev.
532 ** This is how simple the code should have been.
534 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
536 case 1: *(u8 *) data = READ_REG8(d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
538 case 2: *(u16 *) data = READ_REG16(d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
540 case 4: *(u32 *) data = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_DATA);
543 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__, tok, pos, *data);
544 return(*data == ~0U);
549 lba_wr_cfg( struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size)
553 u32 error_config = 0;
554 u32 status_control = 0;
556 ASSERT((size == sizeof(u8)) ||
557 (size == sizeof(u16)) ||
558 (size == sizeof(u32)));
560 if ((size != sizeof(u8)) &&
561 (size != sizeof(u16)) &&
562 (size != sizeof(u32))) {
566 LBA_CFG_SETUP(d, tok);
567 LBA_CFG_ADDR_SETUP(d, tok | reg);
570 WRITE_REG8((u8) data, d->hba.base_addr + LBA_PCI_CFG_DATA + (reg&3));
573 WRITE_REG16((u8) data, d->hba.base_addr + LBA_PCI_CFG_DATA +(reg&2));
576 WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
581 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
582 LBA_CFG_RESTORE(d, d->hba.base_addr);
587 * LBA 4.0 config write code implements non-postable semantics
588 * by doing a read of CONFIG ADDR after the write.
591 static int lba_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
593 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
594 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
595 u32 tok = LBA_CFG_TOK(local_bus,devfn);
597 ASSERT((tok & 0xff) == 0);
600 if (!LBA_TR4PLUS(d) && !LBA_SKIP_PROBE(d)) {
601 /* Original Workaround */
602 lba_wr_cfg(d, tok, pos, (u32) data, size);
603 DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __FUNCTION__, tok, pos,data);
607 if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d))) {
608 DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __FUNCTION__, tok, pos,data);
609 return 1; /* New Workaround */
612 DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __FUNCTION__, tok, pos, data);
613 /* Basic Algorithm */
614 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
616 case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
618 case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
620 case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
623 /* flush posted write */
624 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
629 static struct pci_ops lba_cfg_ops = {
630 .read = lba_cfg_read,
631 .write = lba_cfg_write,
638 DBG(MODULE_NAME ": lba_bios_init\n");
645 ** Determine if a device is already configured.
646 ** If so, reserve it resources.
648 ** Read PCI cfg command register and see if I/O or MMIO is enabled.
649 ** PAT has to enable the devices it's using.
651 ** Note: resources are fixed up before we try to claim them.
654 lba_claim_dev_resources(struct pci_dev *dev)
659 (void) pci_read_config_word(dev, PCI_COMMAND, &cmd);
661 srch_flags = (cmd & PCI_COMMAND_IO) ? IORESOURCE_IO : 0;
662 if (cmd & PCI_COMMAND_MEMORY)
663 srch_flags |= IORESOURCE_MEM;
668 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
669 if (dev->resource[i].flags & srch_flags) {
670 pci_claim_resource(dev, i);
671 DBG(" claimed %s %d [%lx,%lx]/%x\n",
673 dev->resource[i].start,
674 dev->resource[i].end,
675 (int) dev->resource[i].flags
684 ** The algorithm is generic code.
685 ** But it needs to access local data structures to get the IRQ base.
686 ** Could make this a "pci_fixup_irq(bus, region)" but not sure
689 ** Called by do_pci_scan_bus() immediately after each PCI bus is walked.
690 ** Resources aren't allocated until recursive buswalk below HBA is completed.
693 lba_fixup_bus(struct pci_bus *bus)
695 struct list_head *ln;
699 struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge));
700 int lba_portbase = HBA_PORT_BASE(ldev->hba.hba_num);
702 DBG("lba_fixup_bus(0x%p) bus %d sysdata 0x%p\n",
703 bus, bus->secondary, bus->bridge->platform_data);
706 ** Properly Setup MMIO resources for this bus.
707 ** pci_alloc_primary_bus() mangles this.
711 pci_read_bridge_bases(bus);
713 /* Host-PCI Bridge */
716 DBG("lba_fixup_bus() %s [%lx/%lx]/%x\n",
717 ldev->hba.io_space.name,
718 ldev->hba.io_space.start, ldev->hba.io_space.end,
719 (int) ldev->hba.io_space.flags);
720 DBG("lba_fixup_bus() %s [%lx/%lx]/%x\n",
721 ldev->hba.lmmio_space.name,
722 ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end,
723 (int) ldev->hba.lmmio_space.flags);
725 err = request_resource(&ioport_resource, &(ldev->hba.io_space));
728 lba_dump_res(&ioport_resource, 2);
731 err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space));
734 lba_dump_res(&iomem_resource, 2);
738 if (ldev->hba.gmmio_space.flags) {
739 err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space));
742 lba_dump_res(&iomem_resource, 2);
744 bus->resource[2] = &(ldev->hba.gmmio_space);
748 /* advertize Host bridge resources to PCI bus */
749 bus->resource[0] = &(ldev->hba.io_space);
750 bus->resource[1] = &(ldev->hba.lmmio_space);
753 list_for_each(ln, &bus->devices) {
755 struct pci_dev *dev = pci_dev_b(ln);
757 DBG("lba_fixup_bus() %s\n", pci_name(dev));
759 /* Virtualize Device/Bridge Resources. */
760 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
761 struct resource *res = &dev->resource[i];
763 /* If resource not allocated - skip it */
767 if (res->flags & IORESOURCE_IO) {
768 DBG("lba_fixup_bus() I/O Ports [%lx/%lx] -> ",
769 res->start, res->end);
770 res->start |= lba_portbase;
771 res->end |= lba_portbase;
772 DBG("[%lx/%lx]\n", res->start, res->end);
773 } else if (res->flags & IORESOURCE_MEM) {
775 ** Convert PCI (IO_VIEW) addresses to
776 ** processor (PA_VIEW) addresses
778 DBG("lba_fixup_bus() MMIO [%lx/%lx] -> ",
779 res->start, res->end);
780 res->start = PCI_HOST_ADDR(HBA_DATA(ldev), res->start);
781 res->end = PCI_HOST_ADDR(HBA_DATA(ldev), res->end);
782 DBG("[%lx/%lx]\n", res->start, res->end);
788 ** If one device does not support FBB transfers,
789 ** No one on the bus can be allowed to use them.
791 (void) pci_read_config_word(dev, PCI_STATUS, &status);
792 bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK);
797 /* Claim resources for PDC's devices */
798 lba_claim_dev_resources(dev);
803 ** P2PB's have no IRQs. ignore them.
805 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
808 /* Adjust INTERRUPT_LINE for this dev */
809 iosapic_fixup_irq(ldev->iosapic_obj, dev);
813 /* FIXME/REVISIT - finish figuring out to set FBB on both
814 ** pci_setup_bridge() clobbers PCI_BRIDGE_CONTROL.
815 ** Can't fixup here anyway....garr...
821 (void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control);
822 (void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK);
827 fbb_enable = PCI_COMMAND_FAST_BACK;
830 /* Lastly enable FBB/PERR/SERR on all devices too */
831 list_for_each(ln, &bus->devices) {
832 (void) pci_read_config_word(dev, PCI_COMMAND, &status);
833 status |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | fbb_enable;
834 (void) pci_write_config_word(dev, PCI_COMMAND, status);
840 struct pci_bios_ops lba_bios_ops = {
841 .init = lba_bios_init,
842 .fixup_bus = lba_fixup_bus,
848 /*******************************************************
850 ** LBA Sprockets "I/O Port" Space Accessor Functions
852 ** This set of accessor functions is intended for use with
853 ** "legacy firmware" (ie Sprockets on Allegro/Forte boxes).
855 ** Many PCI devices don't require use of I/O port space (eg Tulip,
856 ** NCR720) since they export the same registers to both MMIO and
857 ** I/O port space. In general I/O port space is slower than
858 ** MMIO since drivers are designed so PIO writes can be posted.
860 ********************************************************/
862 #define LBA_PORT_IN(size, mask) \
863 static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
866 t = READ_REG##size(LBA_ASTRO_PORT_BASE + addr); \
867 DBG_PORT(" 0x%x\n", t); \
878 ** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR
880 ** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is
881 ** guarantee non-postable completion semantics - not avoid X4107.
882 ** The READ_U32 only guarantees the write data gets to elroy but
883 ** out to the PCI bus. We can't read stuff from I/O port space
884 ** since we don't know what has side-effects. Attempting to read
885 ** from configuration space would be suicidal given the number of
886 ** bugs in that elroy functionality.
889 ** DMA read results can improperly pass PIO writes (X4107). The
890 ** result of this bug is that if a processor modifies a location in
891 ** memory after having issued PIO writes, the PIO writes are not
892 ** guaranteed to be completed before a PCI device is allowed to see
893 ** the modified data in a DMA read.
895 ** Note that IKE bug X3719 in TR1 IKEs will result in the same
899 ** The workaround for this bug is to always follow a PIO write with
900 ** a PIO read to the same bus before starting DMA on that PCI bus.
903 #define LBA_PORT_OUT(size, mask) \
904 static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
907 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, d, addr, val); \
908 WRITE_REG##size(val, LBA_ASTRO_PORT_BASE + addr); \
909 if (LBA_DEV(d)->hw_rev < 3) \
910 lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
918 static struct pci_port_ops lba_astro_port_ops = {
919 .inb = lba_astro_in8,
920 .inw = lba_astro_in16,
921 .inl = lba_astro_in32,
922 .outb = lba_astro_out8,
923 .outw = lba_astro_out16,
924 .outl = lba_astro_out32
929 #define PIOP_TO_GMMIO(lba, addr) \
930 ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
932 /*******************************************************
934 ** LBA PAT "I/O Port" Space Accessor Functions
936 ** This set of accessor functions is intended for use with
937 ** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes).
939 ** This uses the PIOP space located in the first 64MB of GMMIO.
940 ** Each rope gets a full 64*KB* (ie 4 bytes per page) this way.
941 ** bits 1:0 stay the same. bits 15:2 become 25:12.
942 ** Then add the base and we can generate an I/O Port cycle.
943 ********************************************************/
945 #define LBA_PORT_IN(size, mask) \
946 static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \
949 ASSERT(bus != NULL); \
950 DBG_PORT("%s(0x%p, 0x%x) ->", __FUNCTION__, l, addr); \
951 t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
952 DBG_PORT(" 0x%x\n", t); \
962 #define LBA_PORT_OUT(size, mask) \
963 static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \
965 void *where = (void *) PIOP_TO_GMMIO(LBA_DEV(l), addr); \
966 ASSERT(bus != NULL); \
967 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, l, addr, val); \
968 WRITE_REG##size(val, where); \
969 /* flush the I/O down to the elroy at least */ \
970 lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
978 static struct pci_port_ops lba_pat_port_ops = {
982 .outb = lba_pat_out8,
983 .outw = lba_pat_out16,
984 .outl = lba_pat_out32
990 ** make range information from PDC available to PCI subsystem.
991 ** We make the PDC call here in order to get the PCI bus range
992 ** numbers. The rest will get forwarded in pcibios_fixup_bus().
993 ** We don't have a struct pci_bus assigned to us yet.
996 lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
998 unsigned long bytecnt;
999 pdc_pat_cell_mod_maddr_block_t pa_pdc_cell; /* PA_VIEW */
1000 pdc_pat_cell_mod_maddr_block_t io_pdc_cell; /* IO_VIEW */
1002 long status; /* PDC return status */
1006 /* return cell module (IO view) */
1007 status = pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
1008 PA_VIEW, & pa_pdc_cell);
1009 pa_count = pa_pdc_cell.mod[1];
1011 status |= pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
1012 IO_VIEW, &io_pdc_cell);
1013 io_count = io_pdc_cell.mod[1];
1015 /* We've already done this once for device discovery...*/
1016 if (status != PDC_OK) {
1017 panic("pdc_pat_cell_module() call failed for LBA!\n");
1020 if (PAT_GET_ENTITY(pa_pdc_cell.mod_info) != PAT_ENTITY_LBA) {
1021 panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n");
1025 ** Inspect the resources PAT tells us about
1027 for (i = 0; i < pa_count; i++) {
1030 unsigned long start;
1031 unsigned long end; /* aka finish */
1035 p = (void *) &(pa_pdc_cell.mod[2+i*3]);
1036 io = (void *) &(io_pdc_cell.mod[2+i*3]);
1038 /* Convert the PAT range data to PCI "struct resource" */
1039 switch(p->type & 0xff) {
1041 lba_dev->hba.bus_num.start = p->start;
1042 lba_dev->hba.bus_num.end = p->end;
1046 /* used to fix up pre-initialized MEM BARs */
1047 lba_dev->hba.lmmio_space_offset = p->start - io->start;
1049 r = &(lba_dev->hba.lmmio_space);
1050 r->name = "LBA LMMIO";
1051 r->start = p->start;
1053 r->flags = IORESOURCE_MEM;
1054 r->parent = r->sibling = r->child = NULL;
1058 /* MMIO space > 4GB phys addr; for 64-bit BAR */
1059 r = &(lba_dev->hba.gmmio_space);
1060 r->name = "LBA GMMIO";
1061 r->start = p->start;
1063 r->flags = IORESOURCE_MEM;
1064 r->parent = r->sibling = r->child = NULL;
1068 printk(KERN_WARNING MODULE_NAME
1069 " range[%d] : ignoring NPIOP (0x%lx)\n",
1075 ** Postable I/O port space is per PCI host adapter.
1076 ** base of 64MB PIOP region
1078 lba_dev->iop_base = p->start;
1080 r = &(lba_dev->hba.io_space);
1081 r->name = "LBA I/O Port";
1082 r->start = HBA_PORT_BASE(lba_dev->hba.hba_num);
1083 r->end = r->start + HBA_PORT_SPACE_SIZE - 1;
1084 r->flags = IORESOURCE_IO;
1085 r->parent = r->sibling = r->child = NULL;
1089 printk(KERN_WARNING MODULE_NAME
1090 " range[%d] : unknown pat range type (0x%lx)\n",
1096 #endif /* __LP64__ */
1100 lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
1103 unsigned long rsize;
1108 ** Sign extend all BAR values on "legacy" platforms.
1109 ** "Sprockets" PDC (Forte/Allegro) initializes everything
1110 ** for "legacy" 32-bit OS (HPUX 10.20).
1111 ** Upper 32-bits of 64-bit BAR will be zero too.
1113 lba_dev->hba.lmmio_space_offset = 0xffffffff00000000UL;
1115 lba_dev->hba.lmmio_space_offset = 0UL;
1119 ** With "legacy" firmware, the lowest byte of FW_SCRATCH
1120 ** represents bus->secondary and the second byte represents
1121 ** bus->subsidiary (i.e. highest PPB programmed by firmware).
1122 ** PCI bus walk *should* end up with the same result.
1123 ** FIXME: But we don't have sanity checks in PCI or LBA.
1125 lba_num = READ_REG32(pa_dev->hpa + LBA_FW_SCRATCH);
1126 r = &(lba_dev->hba.bus_num);
1127 r->name = "LBA PCI Busses";
1128 r->start = lba_num & 0xff;
1129 r->end = (lba_num>>8) & 0xff;
1131 /* Set up local PCI Bus resources - we don't really need
1132 ** them for Legacy boxes but it's nice to see in /proc.
1134 r = &(lba_dev->hba.lmmio_space);
1135 r->name = "LBA PCI LMMIO";
1136 r->flags = IORESOURCE_MEM;
1137 /* Ignore "Range Enable" bit in the BASE register */
1138 r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev),
1139 ((long) READ_REG32(pa_dev->hpa + LBA_LMMIO_BASE)) & ~1UL);
1140 rsize = ~READ_REG32(pa_dev->hpa + LBA_LMMIO_MASK) + 1;
1143 ** Each rope only gets part of the distributed range.
1144 ** Adjust "window" for this rope
1146 rsize /= ROPES_PER_SBA;
1147 r->start += rsize * LBA_NUM(pa_dev->hpa);
1148 r->end = r->start + rsize - 1 ;
1151 ** XXX FIXME - ignore LBA_ELMMIO_BASE for now
1152 ** "Directed" ranges are used when the "distributed range" isn't
1153 ** sufficient for all devices below a given LBA. Typically devices
1154 ** like graphics cards or X25 may need a directed range when the
1155 ** bus has multiple slots (ie multiple devices) or the device
1156 ** needs more than the typical 4 or 8MB a distributed range offers.
1158 ** The main reason for ignoring it now frigging complications.
1159 ** Directed ranges may overlap (and have precedence) over
1160 ** distributed ranges. Ie a distributed range assigned to a unused
1161 ** rope may be used by a directed range on a different rope.
1162 ** Support for graphics devices may require fixing this
1163 ** since they may be assigned a directed range which overlaps
1164 ** an existing (but unused portion of) distributed range.
1166 r = &(lba_dev->hba.elmmio_space);
1167 r->name = "extra LBA PCI LMMIO";
1168 r->flags = IORESOURCE_MEM;
1169 r->start = READ_REG32(pa_dev->hpa + LBA_ELMMIO_BASE);
1172 /* check Range Enable bit */
1174 /* First baby step to getting Direct Ranges listed in /proc.
1175 ** AFAIK, only Sprockets PDC will setup a directed Range.
1180 r->end += ~READ_REG32(pa_dev->hpa + LBA_ELMMIO_MASK);
1181 printk(KERN_DEBUG "WARNING: Ignoring enabled ELMMIO BASE 0x%0lx SIZE 0x%lx\n",
1187 r = &(lba_dev->hba.io_space);
1188 r->name = "LBA PCI I/O Ports";
1189 r->flags = IORESOURCE_IO;
1190 r->start = READ_REG32(pa_dev->hpa + LBA_IOS_BASE) & ~1L;
1191 r->end = r->start + (READ_REG32(pa_dev->hpa + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1));
1193 /* Virtualize the I/O Port space ranges */
1194 lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num);
1195 r->start |= lba_num;
1200 /**************************************************************************
1202 ** LBA initialization code (HW and SW)
1204 ** o identify LBA chip itself
1205 ** o initialize LBA chip modes (HardFail)
1206 ** o FIXME: initialize DMA hints for reasonable defaults
1207 ** o enable configuration functions
1208 ** o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked)
1210 **************************************************************************/
1213 lba_hw_init(struct lba_device *d)
1216 u32 bus_reset; /* PDC_PAT_BUG */
1219 printk(KERN_DEBUG "LBA %lx STAT_CTL %Lx ERROR_CFG %Lx STATUS %Lx DMA_CTL %Lx\n",
1221 READ_REG64(d->hba.base_addr + LBA_STAT_CTL),
1222 READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG),
1223 READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS),
1224 READ_REG64(d->hba.base_addr + LBA_DMA_CTL) );
1225 printk(KERN_DEBUG " ARB mask %Lx pri %Lx mode %Lx mtlt %Lx\n",
1226 READ_REG64(d->hba.base_addr + LBA_ARB_MASK),
1227 READ_REG64(d->hba.base_addr + LBA_ARB_PRI),
1228 READ_REG64(d->hba.base_addr + LBA_ARB_MODE),
1229 READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) );
1230 printk(KERN_DEBUG " HINT cfg 0x%Lx\n",
1231 READ_REG64(d->hba.base_addr + LBA_HINT_CFG));
1232 printk(KERN_DEBUG " HINT reg ");
1234 for (i=LBA_HINT_BASE; i< (14*8 + LBA_HINT_BASE); i+=8)
1235 printk(" %Lx", READ_REG64(d->hba.base_addr + i));
1238 #endif /* DEBUG_LBA_PAT */
1242 * FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support
1243 * Only N-Class and up can really make use of Get slot status.
1244 * maybe L-class too but I've never played with it there.
1248 /* PDC_PAT_BUG: exhibited in rev 40.48 on L2000 */
1249 bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1;
1251 printk(KERN_DEBUG "NOTICE: PCI bus reset still asserted! (clearing)\n");
1254 stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);
1255 if (stat & LBA_SMART_MODE) {
1256 printk(KERN_DEBUG "NOTICE: LBA in SMART mode! (cleared)\n");
1257 stat &= ~LBA_SMART_MODE;
1258 WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG);
1261 /* Set HF mode as the default (vs. -1 mode). */
1262 stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);
1263 WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
1266 ** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal
1267 ** if it's not already set. If we just cleared the PCI Bus Reset
1268 ** signal, wait a bit for the PCI devices to recover and setup.
1271 mdelay(pci_post_reset_delay);
1273 if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) {
1275 ** PDC_PAT_BUG: PDC rev 40.48 on L2000.
1276 ** B2000/C3600/J6000 also have this problem?
1278 ** Elroys with hot pluggable slots don't get configured
1279 ** correctly if the slot is empty. ARB_MASK is set to 0
1280 ** and we can't master transactions on the bus if it's
1281 ** not at least one. 0x3 enables elroy and first slot.
1283 printk(KERN_DEBUG "NOTICE: Enabling PCI Arbitration\n");
1284 WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK);
1288 ** FIXME: Hint registers are programmed with default hint
1289 ** values by firmware. Hints should be sane even if we
1290 ** can't reprogram them the way drivers want.
1298 lba_common_init(struct lba_device *lba_dev)
1300 pci_bios = &lba_bios_ops;
1301 pcibios_register_hba(HBA_DATA(lba_dev));
1302 lba_dev->lba_lock = SPIN_LOCK_UNLOCKED;
1305 ** Set flags which depend on hw_rev
1307 if (!LBA_TR4PLUS(lba_dev)) {
1308 lba_dev->flags |= LBA_FLAG_NO_DMA_DURING_CFG;
1315 ** Determine if lba should claim this chip (return 0) or not (return 1).
1316 ** If so, initialize the chip and tell other partners in crime they
1320 lba_driver_callback(struct parisc_device *dev)
1322 struct lba_device *lba_dev;
1323 struct pci_bus *lba_bus;
1328 /* Read HW Rev First */
1329 func_class = READ_REG32(dev->hpa + LBA_FCLASS);
1332 switch (func_class) {
1333 case 0: version = "TR1.0"; break;
1334 case 1: version = "TR2.0"; break;
1335 case 2: version = "TR2.1"; break;
1336 case 3: version = "TR2.2"; break;
1337 case 4: version = "TR3.0"; break;
1338 case 5: version = "TR4.0"; break;
1339 default: version = "TR4+";
1342 printk(KERN_INFO "%s version %s (0x%x) found at 0x%lx\n",
1343 MODULE_NAME, version, func_class & 0xf, dev->hpa);
1345 /* Just in case we find some prototypes... */
1346 if (func_class < 2) {
1347 printk(KERN_WARNING "Can't support LBA older than TR2.1 "
1348 "- continuing under adversity.\n");
1352 ** Tell I/O SAPIC driver we have a IRQ handler/region.
1354 tmp_obj = iosapic_register(dev->hpa + LBA_IOSAPIC_BASE);
1356 /* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't
1357 ** have an IRT entry will get NULL back from iosapic code.
1360 lba_dev = kmalloc(sizeof(struct lba_device), GFP_KERNEL);
1361 if (NULL == lba_dev)
1363 printk(KERN_ERR "lba_init_chip - couldn't alloc lba_device\n");
1367 memset(lba_dev, 0, sizeof(struct lba_device));
1370 /* ---------- First : initialize data we already have --------- */
1373 ** Need hw_rev to adjust configuration space behavior.
1374 ** LBA_TR4PLUS macro uses hw_rev field.
1376 lba_dev->hw_rev = func_class;
1378 lba_dev->hba.base_addr = dev->hpa; /* faster access */
1379 lba_dev->hba.dev = dev;
1380 lba_dev->iosapic_obj = tmp_obj; /* save interrupt handle */
1381 lba_dev->hba.iommu = sba_get_iommu(dev); /* get iommu data */
1383 /* ------------ Second : initialize common stuff ---------- */
1384 lba_common_init(lba_dev);
1386 if (lba_hw_init(lba_dev))
1389 /* ---------- Third : setup I/O Port and MMIO resources --------- */
1393 /* PDC PAT firmware uses PIOP region of GMMIO space. */
1394 pci_port = &lba_pat_port_ops;
1396 /* Go ask PDC PAT what resources this LBA has */
1397 lba_pat_resources(dev, lba_dev);
1401 /* Sprockets PDC uses NPIOP region */
1402 pci_port = &lba_astro_port_ops;
1404 /* Poke the chip a bit for /proc output */
1405 lba_legacy_resources(dev, lba_dev);
1409 ** Tell PCI support another PCI bus was found.
1410 ** Walks PCI bus for us too.
1412 dev->dev.platform_data = lba_dev;
1413 lba_bus = lba_dev->hba.hba_bus =
1414 pci_scan_bus_parented(&dev->dev, lba_dev->hba.bus_num.start,
1415 &lba_cfg_ops, NULL);
1419 /* assign resources to un-initialized devices */
1420 DBG_PAT("LBA pci_bus_assign_resources()\n");
1421 pci_bus_assign_resources(lba_bus);
1423 #ifdef DEBUG_LBA_PAT
1424 DBG_PAT("\nLBA PIOP resource tree\n");
1425 lba_dump_res(&lba_dev->hba.io_space, 2);
1426 DBG_PAT("\nLBA LMMIO resource tree\n");
1427 lba_dump_res(&lba_dev->hba.lmmio_space, 2);
1433 ** Once PCI register ops has walked the bus, access to config
1434 ** space is restricted. Avoids master aborts on config cycles.
1435 ** Early LBA revs go fatal on *any* master abort.
1437 if (!LBA_TR4PLUS(lba_dev)) {
1438 lba_dev->flags |= LBA_FLAG_SKIP_PROBE;
1441 /* Whew! Finally done! Tell services we got this one covered. */
1445 static struct parisc_device_id lba_tbl[] = {
1446 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x782, 0xa },
1450 static struct parisc_driver lba_driver = {
1451 .name = MODULE_NAME,
1452 .id_table = lba_tbl,
1453 .probe = lba_driver_callback,
1457 ** One time initialization to let the world know the LBA was found.
1458 ** Must be called exactly once before pci_init().
1460 void __init lba_init(void)
1462 register_parisc_driver(&lba_driver);
1466 ** Initialize the IBASE/IMASK registers for LBA (Elroy).
1467 ** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA).
1468 ** sba_iommu is responsible for locking (none needed at init time).
1471 lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask)
1473 unsigned long base_addr = lba->hpa;
1475 imask <<= 2; /* adjust for hints - 2 more bits */
1477 ASSERT((ibase & 0x003fffff) == 0);
1478 ASSERT((imask & 0x003fffff) == 0);
1480 DBG("%s() ibase 0x%x imask 0x%x\n", __FUNCTION__, ibase, imask);
1481 WRITE_REG32( imask, base_addr + LBA_IMASK);
1482 WRITE_REG32( ibase, base_addr + LBA_IBASE);