2 ** PCI Lower Bus Adapter (LBA) manager
4 ** (c) Copyright 1999,2000 Grant Grundler
5 ** (c) Copyright 1999,2000 Hewlett-Packard Company
7 ** This program is free software; you can redistribute it and/or modify
8 ** it under the terms of the GNU General Public License as published by
9 ** the Free Software Foundation; either version 2 of the License, or
10 ** (at your option) any later version.
13 ** This module primarily provides access to PCI bus (config/IOport
14 ** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class
15 ** with 4 digit model numbers - eg C3000 (and A400...sigh).
17 ** LBA driver isn't as simple as the Dino driver because:
18 ** (a) this chip has substantial bug fixes between revisions
19 ** (Only one Dino bug has a software workaround :^( )
20 ** (b) has more options which we don't (yet) support (DMA hints, OLARD)
21 ** (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver)
22 ** (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC).
23 ** (dino only deals with "Legacy" PDC)
25 ** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver.
26 ** (I/O SAPIC is integratd in the LBA chip).
28 ** FIXME: Add support to SBA and LBA drivers for DMA hint sets
29 ** FIXME: Add support for PCI card hot-plug (OLARD).
32 #include <linux/delay.h>
33 #include <linux/types.h>
34 #include <linux/kernel.h>
35 #include <linux/spinlock.h>
36 #include <linux/init.h> /* for __init and __devinit */
37 #include <linux/pci.h>
38 #include <linux/ioport.h>
39 #include <linux/slab.h>
40 #include <linux/smp_lock.h>
42 #include <asm/byteorder.h>
43 #include <asm/irq.h> /* for struct irq_region support */
45 #include <asm/pdcpat.h>
47 #include <asm/segment.h>
48 #include <asm/system.h>
50 #include <asm/hardware.h> /* for register_parisc_driver() stuff */
51 #include <asm/parisc-device.h>
52 #include <asm/iosapic.h> /* for iosapic_register() */
53 #include <asm/io.h> /* read/write stuff */
57 #define FALSE (1 == 0)
60 #undef DEBUG_LBA /* general stuff */
61 #undef DEBUG_LBA_PORT /* debug I/O Port access */
62 #undef DEBUG_LBA_CFG /* debug Config Space Access (ie PCI Bus walk) */
63 #undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */
65 #undef FBB_SUPPORT /* Fast Back-Back xfers - NOT READY YET */
69 #define DBG(x...) printk(x)
75 #define DBG_PORT(x...) printk(x)
77 #define DBG_PORT(x...)
81 #define DBG_CFG(x...) printk(x)
87 #define DBG_PAT(x...) printk(x)
94 #define ASSERT(expr) \
96 printk("\n%s:%d: Assertion " #expr " failed!\n", \
97 __FILE__, __LINE__); \
106 ** Config accessor functions only pass in the 8-bit bus number and not
107 ** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
108 ** number based on what firmware wrote into the scratch register.
110 ** The "secondary" bus number is set to this before calling
111 ** pci_register_ops(). If any PPB's are present, the scan will
112 ** discover them and update the "secondary" and "subordinate"
113 ** fields in the pci_bus structure.
115 ** Changes in the configuration *may* result in a different
116 ** bus number for each LBA depending on what firmware does.
119 #define MODULE_NAME "lba"
121 #define LBA_FUNC_ID 0x0000 /* function id */
122 #define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */
123 #define LBA_CAPABLE 0x0030 /* capabilities register */
125 #define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */
126 #define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */
128 #define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */
129 #define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */
130 #define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */
132 #define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */
133 #define LBA_ARB_PRI 0x0088 /* firmware sets this. */
134 #define LBA_ARB_MODE 0x0090 /* firmware sets this. */
135 #define LBA_ARB_MTLT 0x0098 /* firmware sets this. */
137 #define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */
139 #define LBA_STAT_CTL 0x0108 /* Status & Control */
140 #define LBA_BUS_RESET 0x01 /* Deassert PCI Bus Reset Signal */
141 #define CLEAR_ERRLOG 0x10 /* "Clear Error Log" cmd */
142 #define CLEAR_ERRLOG_ENABLE 0x20 /* "Clear Error Log" Enable */
143 #define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */
145 #define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */
146 #define LBA_LMMIO_MASK 0x0208
148 #define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */
149 #define LBA_GMMIO_MASK 0x0218
151 #define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */
152 #define LBA_WLMMIO_MASK 0x0228
154 #define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */
155 #define LBA_WGMMIO_MASK 0x0238
157 #define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */
158 #define LBA_IOS_MASK 0x0248
160 #define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */
161 #define LBA_ELMMIO_MASK 0x0258
163 #define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */
164 #define LBA_EIOS_MASK 0x0268
166 #define LBA_DMA_CTL 0x0278 /* firmware sets this */
168 #define LBA_IBASE 0x0300 /* SBA DMA support */
169 #define LBA_IMASK 0x0308
171 /* FIXME: ignore DMA Hint stuff until we can measure performance */
172 #define LBA_HINT_CFG 0x0310
173 #define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */
175 #define LBA_BUS_MODE 0x0620
177 /* ERROR regs are needed for config cycle kluges */
178 #define LBA_ERROR_CONFIG 0x0680
179 #define LBA_SMART_MODE 0x20
180 #define LBA_ERROR_STATUS 0x0688
181 #define LBA_ROPE_CTL 0x06A0
183 #define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */
185 /* non-postable I/O port space, densely packed */
186 #ifdef CONFIG_PARISC64
187 #define LBA_ASTRO_PORT_BASE (0xfffffffffee00000UL)
189 #define LBA_ASTRO_PORT_BASE (0xfee00000UL)
192 #define ELROY_HVERS 0x782
193 #define MERCURY_HVERS 0x783
194 #define QUICKSILVER_HVERS 0x784
196 static inline int IS_ELROY(struct parisc_device *d)
198 return (d->id.hversion == ELROY_HVERS);
201 static inline int IS_MERCURY(struct parisc_device *d)
203 return (d->id.hversion == MERCURY_HVERS);
206 static inline int IS_QUICKSILVER(struct parisc_device *d)
208 return (d->id.hversion == QUICKSILVER_HVERS);
213 ** lba_device: Per instance Elroy data structure
216 struct pci_hba_data hba;
221 #ifdef CONFIG_PARISC64
222 unsigned long iop_base; /* PA_VIEW - for IO port accessor funcs */
225 int flags; /* state/functionality enabled */
226 int hw_rev; /* HW revision of chip */
235 #define LBA_FLAG_NO_DMA_DURING_CFG 0x01
236 #define LBA_FLAG_SKIP_PROBE 0x10
238 /* Tape Release 4 == hw_rev 5 */
239 #define LBA_TR4PLUS(d) ((d)->hw_rev > 0x4)
240 #define LBA_DMA_DURING_CFG_DISABLED(d) ((d)->flags & LBA_FLAG_NO_DMA_DURING_CFG)
241 #define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)
244 /* Looks nice and keeps the compiler happy */
245 #define LBA_DEV(d) ((struct lba_device *) (d))
249 ** Only allow 8 subsidiary busses per LBA
250 ** Problem is the PCI bus numbering is globally shared.
252 #define LBA_MAX_NUM_BUSES 8
254 /************************************
255 * LBA register read and write support
257 * BE WARNED: register writes are posted.
258 * (ie follow writes which must reach HW with a read)
260 #define READ_U8(addr) __raw_readb(addr)
261 #define READ_U16(addr) __raw_readw(addr)
262 #define READ_U32(addr) __raw_readl(addr)
263 #define WRITE_U8(value, addr) __raw_writeb(value, addr)
264 #define WRITE_U16(value, addr) __raw_writew(value, addr)
265 #define WRITE_U32(value, addr) __raw_writel(value, addr)
267 #define READ_REG8(addr) readb(addr)
268 #define READ_REG16(addr) readw(addr)
269 #define READ_REG32(addr) readl(addr)
270 #define READ_REG64(addr) readq(addr)
271 #define WRITE_REG8(value, addr) writeb(value, addr)
272 #define WRITE_REG16(value, addr) writew(value, addr)
273 #define WRITE_REG32(value, addr) writel(value, addr)
276 #define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8))
277 #define LBA_CFG_BUS(tok) ((u8) ((tok)>>16))
278 #define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f)
279 #define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)
283 ** Extract LBA (Rope) number from HPA
284 ** REVISIT: 16 ropes for Stretch/Ike?
286 #define ROPES_PER_SBA 8
287 #define LBA_NUM(x) ((((unsigned long) x) >> 13) & (ROPES_PER_SBA-1))
291 lba_dump_res(struct resource *r, int d)
298 printk(KERN_DEBUG "(%p)", r->parent);
299 for (i = d; i ; --i) printk(" ");
300 printk(KERN_DEBUG "%p [%lx,%lx]/%x\n", r, r->start, r->end, (int) r->flags);
301 lba_dump_res(r->child, d+2);
302 lba_dump_res(r->sibling, d);
307 ** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex
308 ** workaround for cfg cycles:
309 ** -- preserve LBA state
310 ** -- LBA_FLAG_NO_DMA_DURING_CFG workaround
311 ** -- turn on smart mode
312 ** -- probe with config writes before doing config reads
313 ** -- check ERROR_STATUS
314 ** -- clear ERROR_STATUS
315 ** -- restore LBA state
317 ** The workaround is only used for device discovery.
321 lba_device_present( u8 bus, u8 dfn, struct lba_device *d)
323 u8 first_bus = d->hba.hba_bus->secondary;
324 u8 last_sub_bus = d->hba.hba_bus->subordinate;
326 ASSERT(bus >= first_bus);
327 ASSERT(bus <= last_sub_bus);
328 ASSERT((bus - first_bus) < LBA_MAX_NUM_BUSES);
330 if ((bus < first_bus) ||
331 (bus > last_sub_bus) ||
332 ((bus - first_bus) >= LBA_MAX_NUM_BUSES))
334 /* devices that fall into any of these cases won't get claimed */
343 #define LBA_CFG_SETUP(d, tok) { \
344 /* Save contents of error config register. */ \
345 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
347 /* Save contents of status control register. */ \
348 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
350 /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA \
351 ** arbitration for full bus walks. \
353 if (LBA_DMA_DURING_CFG_DISABLED(d)) { \
354 /* Save contents of arb mask register. */ \
355 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
358 * Turn off all device arbitration bits (i.e. everything \
359 * except arbitration enable bit). \
361 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
365 * Set the smart mode bit so that master aborts don't cause \
366 * LBA to go into PCI fatal mode (required). \
368 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
372 #define LBA_CFG_PROBE(d, tok) { \
374 * Setup Vendor ID write and read back the address register \
375 * to make sure that LBA is the bus master. \
377 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
379 * Read address register to ensure that LBA is the bus master, \
380 * which implies that DMA traffic has stopped when DMA arb is off. \
382 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
384 * Generate a cfg write cycle (will have no affect on \
385 * Vendor ID register since read-only). \
387 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
389 * Make sure write has completed before proceeding further, \
390 * i.e. before setting clear enable. \
392 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
398 * -- Can't tell if config cycle got the error.
400 * OV bit is broken until rev 4.0, so can't use OV bit and
401 * LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle.
403 * As of rev 4.0, no longer need the error check.
405 * -- Even if we could tell, we still want to return -1
406 * for **ANY** error (not just master abort).
408 * -- Only clear non-fatal errors (we don't want to bring
409 * LBA out of pci-fatal mode).
411 * Actually, there is still a race in which
412 * we could be clearing a fatal error. We will
413 * live with this during our initial bus walk
414 * until rev 4.0 (no driver activity during
415 * initial bus walk). The initial bus walk
416 * has race conditions concerning the use of
417 * smart mode as well.
420 #define LBA_MASTER_ABORT_ERROR 0xc
421 #define LBA_FATAL_ERROR 0x10
423 #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \
424 u32 error_status = 0; \
426 * Set clear enable (CE) bit. Unset by HW when new \
427 * errors are logged -- LBA HW ERS section 14.3.3). \
429 WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \
430 error_status = READ_REG32(base + LBA_ERROR_STATUS); \
431 if ((error_status & 0x1f) != 0) { \
433 * Fail the config read request. \
436 if ((error_status & LBA_FATAL_ERROR) == 0) { \
438 * Clear error status (if fatal bit not set) by setting \
439 * clear error log bit (CL). \
441 WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \
446 #define LBA_CFG_TR4_ADDR_SETUP(d, addr) \
447 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR)
449 #define LBA_CFG_ADDR_SETUP(d, addr) { \
450 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
453 * -- Potentially could skip this once DMA bug fixed. \
455 * Read address register to ensure that LBA is the bus master, \
456 * which implies that DMA traffic has stopped when DMA arb is off. \
458 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
462 #define LBA_CFG_RESTORE(d, base) { \
464 * Restore status control register (turn off clear enable). \
466 WRITE_REG32(status_control, base + LBA_STAT_CTL); \
468 * Restore error config register (turn off smart mode). \
470 WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \
471 if (LBA_DMA_DURING_CFG_DISABLED(d)) { \
473 * Restore arb mask register (reenables DMA arbitration). \
475 WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \
482 lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size)
486 u32 arb_mask = 0; /* used by LBA_CFG_SETUP/RESTORE */
487 u32 error_config = 0; /* used by LBA_CFG_SETUP/RESTORE */
488 u32 status_control = 0; /* used by LBA_CFG_SETUP/RESTORE */
490 ASSERT((size == sizeof(u8)) ||
491 (size == sizeof(u16)) ||
492 (size == sizeof(u32)));
494 if ((size != sizeof(u8)) &&
495 (size != sizeof(u16)) &&
496 (size != sizeof(u32))) {
500 LBA_CFG_SETUP(d, tok);
501 LBA_CFG_PROBE(d, tok);
502 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
504 LBA_CFG_ADDR_SETUP(d, tok | reg);
507 data = (u32) READ_REG8(d->hba.base_addr + LBA_PCI_CFG_DATA + (reg & 3));
510 data = (u32) READ_REG16(d->hba.base_addr + LBA_PCI_CFG_DATA + (reg & 2));
513 data = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_DATA);
516 break; /* leave data as -1 */
519 LBA_CFG_RESTORE(d, d->hba.base_addr);
523 #ifdef CONFIG_PARISC64
524 #define pat_cfg_addr(bus, devfn, addr) (((bus) << 16) | ((devfn) << 8) | (addr))
526 static int pat_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
528 int tok = pat_cfg_addr(bus->number, devfn, pos);
530 int ret = pdc_pat_io_pci_cfg_read(tok, size, &tmp);
532 DBG_CFG("%s(%d:%d.%d+0x%02x) -> 0x%x %d\n", __FUNCTION__, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), pos, tmp, ret);
535 case 1: *data = (u8) tmp; return (tmp == (u8) ~0);
536 case 2: *data = (u16) tmp; return (tmp == (u16) ~0);
537 case 4: *data = (u32) tmp; return (tmp == (u32) ~0);
543 static int pat_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
545 int tok = pat_cfg_addr(bus->number, devfn, pos);
546 int ret = pdc_pat_io_pci_cfg_write(tok, size, data);
548 DBG_CFG("%s(%d:%d.%d+0x%02x, 0x%lx/%d)\n", __FUNCTION__, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), pos, data, size);
552 static struct pci_ops pat_cfg_ops = {
553 .read = pat_cfg_read,
554 .write = pat_cfg_write,
557 /* keep the compiler from complaining about undeclared variables */
558 #define pat_cfg_ops lba_cfg_ops
561 static int lba_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
563 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
564 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
565 u32 tok = LBA_CFG_TOK(local_bus, devfn);
567 /* FIXME: B2K/C3600 workaround is always use old method... */
568 /* if (!LBA_TR4PLUS(d) && !LBA_SKIP_PROBE(d)) */ {
569 /* original - Generate config cycle on broken elroy
570 with risk we will miss PCI bus errors. */
571 *data = lba_rd_cfg(d, tok, pos, size);
572 DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __FUNCTION__, tok, pos, *data);
573 return(*data == ~0U);
576 if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d)))
578 DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __FUNCTION__, tok, pos);
579 /* either don't want to look or know device isn't present. */
585 ** Should only get here on fully working LBA rev.
586 ** This is how simple the code should have been.
588 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
590 case 1: *(u8 *) data = READ_REG8(d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
592 case 2: *(u16 *) data = READ_REG16(d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
594 case 4: *(u32 *) data = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_DATA);
597 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__, tok, pos, *data);
598 return(*data == ~0U);
603 lba_wr_cfg( struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size)
607 u32 error_config = 0;
608 u32 status_control = 0;
610 ASSERT((size == sizeof(u8)) ||
611 (size == sizeof(u16)) ||
612 (size == sizeof(u32)));
614 if ((size != sizeof(u8)) &&
615 (size != sizeof(u16)) &&
616 (size != sizeof(u32))) {
620 LBA_CFG_SETUP(d, tok);
621 LBA_CFG_ADDR_SETUP(d, tok | reg);
624 WRITE_REG8((u8) data, d->hba.base_addr + LBA_PCI_CFG_DATA + (reg&3));
627 WRITE_REG16((u8) data, d->hba.base_addr + LBA_PCI_CFG_DATA +(reg&2));
630 WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
635 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
636 LBA_CFG_RESTORE(d, d->hba.base_addr);
641 * LBA 4.0 config write code implements non-postable semantics
642 * by doing a read of CONFIG ADDR after the write.
645 static int lba_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
647 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
648 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
649 u32 tok = LBA_CFG_TOK(local_bus,devfn);
651 ASSERT((tok & 0xff) == 0);
654 if (!LBA_TR4PLUS(d) && !LBA_SKIP_PROBE(d)) {
655 /* Original Workaround */
656 lba_wr_cfg(d, tok, pos, (u32) data, size);
657 DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __FUNCTION__, tok, pos,data);
661 if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d))) {
662 DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __FUNCTION__, tok, pos,data);
663 return 1; /* New Workaround */
666 DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __FUNCTION__, tok, pos, data);
668 /* Basic Algorithm */
669 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
671 case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
673 case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
675 case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
678 /* flush posted write */
679 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
684 static struct pci_ops lba_cfg_ops = {
685 .read = lba_cfg_read,
686 .write = lba_cfg_write,
693 DBG(MODULE_NAME ": lba_bios_init\n");
697 #ifdef CONFIG_PARISC64
700 ** Determine if a device is already configured.
701 ** If so, reserve it resources.
703 ** Read PCI cfg command register and see if I/O or MMIO is enabled.
704 ** PAT has to enable the devices it's using.
706 ** Note: resources are fixed up before we try to claim them.
709 lba_claim_dev_resources(struct pci_dev *dev)
714 (void) pci_read_config_word(dev, PCI_COMMAND, &cmd);
716 srch_flags = (cmd & PCI_COMMAND_IO) ? IORESOURCE_IO : 0;
717 if (cmd & PCI_COMMAND_MEMORY)
718 srch_flags |= IORESOURCE_MEM;
723 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
724 if (dev->resource[i].flags & srch_flags) {
725 pci_claim_resource(dev, i);
726 DBG(" claimed %s %d [%lx,%lx]/%x\n",
728 dev->resource[i].start,
729 dev->resource[i].end,
730 (int) dev->resource[i].flags
736 #define lba_claim_dev_resources(dev)
741 ** The algorithm is generic code.
742 ** But it needs to access local data structures to get the IRQ base.
743 ** Could make this a "pci_fixup_irq(bus, region)" but not sure
746 ** Called by do_pci_scan_bus() immediately after each PCI bus is walked.
747 ** Resources aren't allocated until recursive buswalk below HBA is completed.
750 lba_fixup_bus(struct pci_bus *bus)
752 struct list_head *ln;
756 struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge));
757 int lba_portbase = HBA_PORT_BASE(ldev->hba.hba_num);
759 DBG("lba_fixup_bus(0x%p) bus %d sysdata 0x%p\n",
760 bus, bus->secondary, bus->bridge->platform_data);
763 ** Properly Setup MMIO resources for this bus.
764 ** pci_alloc_primary_bus() mangles this.
768 pci_read_bridge_bases(bus);
770 /* Host-PCI Bridge */
773 DBG("lba_fixup_bus() %s [%lx/%lx]/%x\n",
774 ldev->hba.io_space.name,
775 ldev->hba.io_space.start, ldev->hba.io_space.end,
776 (int) ldev->hba.io_space.flags);
777 DBG("lba_fixup_bus() %s [%lx/%lx]/%x\n",
778 ldev->hba.lmmio_space.name,
779 ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end,
780 (int) ldev->hba.lmmio_space.flags);
782 err = request_resource(&ioport_resource, &(ldev->hba.io_space));
785 lba_dump_res(&ioport_resource, 2);
788 err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space));
791 lba_dump_res(&iomem_resource, 2);
794 #ifdef CONFIG_PARISC64
795 if (ldev->hba.gmmio_space.flags) {
796 err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space));
799 lba_dump_res(&iomem_resource, 2);
801 bus->resource[2] = &(ldev->hba.gmmio_space);
805 /* advertize Host bridge resources to PCI bus */
806 bus->resource[0] = &(ldev->hba.io_space);
807 bus->resource[1] = &(ldev->hba.lmmio_space);
810 list_for_each(ln, &bus->devices) {
812 struct pci_dev *dev = pci_dev_b(ln);
814 DBG("lba_fixup_bus() %s\n", pci_name(dev));
816 /* Virtualize Device/Bridge Resources. */
817 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
818 struct resource *res = &dev->resource[i];
820 /* If resource not allocated - skip it */
824 if (res->flags & IORESOURCE_IO) {
825 DBG("lba_fixup_bus() I/O Ports [%lx/%lx] -> ",
826 res->start, res->end);
827 res->start |= lba_portbase;
828 res->end |= lba_portbase;
829 DBG("[%lx/%lx]\n", res->start, res->end);
830 } else if (res->flags & IORESOURCE_MEM) {
832 ** Convert PCI (IO_VIEW) addresses to
833 ** processor (PA_VIEW) addresses
835 DBG("lba_fixup_bus() MMIO [%lx/%lx] -> ",
836 res->start, res->end);
837 res->start = PCI_HOST_ADDR(HBA_DATA(ldev), res->start);
838 res->end = PCI_HOST_ADDR(HBA_DATA(ldev), res->end);
839 DBG("[%lx/%lx]\n", res->start, res->end);
845 ** If one device does not support FBB transfers,
846 ** No one on the bus can be allowed to use them.
848 (void) pci_read_config_word(dev, PCI_STATUS, &status);
849 bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK);
853 /* Claim resources for PDC's devices */
854 lba_claim_dev_resources(dev);
858 ** P2PB's have no IRQs. ignore them.
860 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
863 /* Adjust INTERRUPT_LINE for this dev */
864 iosapic_fixup_irq(ldev->iosapic_obj, dev);
868 /* FIXME/REVISIT - finish figuring out to set FBB on both
869 ** pci_setup_bridge() clobbers PCI_BRIDGE_CONTROL.
870 ** Can't fixup here anyway....garr...
876 (void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control);
877 (void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK);
882 fbb_enable = PCI_COMMAND_FAST_BACK;
885 /* Lastly enable FBB/PERR/SERR on all devices too */
886 list_for_each(ln, &bus->devices) {
887 (void) pci_read_config_word(dev, PCI_COMMAND, &status);
888 status |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | fbb_enable;
889 (void) pci_write_config_word(dev, PCI_COMMAND, status);
895 struct pci_bios_ops lba_bios_ops = {
896 .init = lba_bios_init,
897 .fixup_bus = lba_fixup_bus,
903 /*******************************************************
905 ** LBA Sprockets "I/O Port" Space Accessor Functions
907 ** This set of accessor functions is intended for use with
908 ** "legacy firmware" (ie Sprockets on Allegro/Forte boxes).
910 ** Many PCI devices don't require use of I/O port space (eg Tulip,
911 ** NCR720) since they export the same registers to both MMIO and
912 ** I/O port space. In general I/O port space is slower than
913 ** MMIO since drivers are designed so PIO writes can be posted.
915 ********************************************************/
917 #define LBA_PORT_IN(size, mask) \
918 static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
921 t = READ_REG##size(LBA_ASTRO_PORT_BASE + addr); \
922 DBG_PORT(" 0x%x\n", t); \
933 ** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR
935 ** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is
936 ** guarantee non-postable completion semantics - not avoid X4107.
937 ** The READ_U32 only guarantees the write data gets to elroy but
938 ** out to the PCI bus. We can't read stuff from I/O port space
939 ** since we don't know what has side-effects. Attempting to read
940 ** from configuration space would be suicidal given the number of
941 ** bugs in that elroy functionality.
944 ** DMA read results can improperly pass PIO writes (X4107). The
945 ** result of this bug is that if a processor modifies a location in
946 ** memory after having issued PIO writes, the PIO writes are not
947 ** guaranteed to be completed before a PCI device is allowed to see
948 ** the modified data in a DMA read.
950 ** Note that IKE bug X3719 in TR1 IKEs will result in the same
954 ** The workaround for this bug is to always follow a PIO write with
955 ** a PIO read to the same bus before starting DMA on that PCI bus.
958 #define LBA_PORT_OUT(size, mask) \
959 static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
962 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, d, addr, val); \
963 WRITE_REG##size(val, LBA_ASTRO_PORT_BASE + addr); \
964 if (LBA_DEV(d)->hw_rev < 3) \
965 lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
973 static struct pci_port_ops lba_astro_port_ops = {
974 .inb = lba_astro_in8,
975 .inw = lba_astro_in16,
976 .inl = lba_astro_in32,
977 .outb = lba_astro_out8,
978 .outw = lba_astro_out16,
979 .outl = lba_astro_out32
983 #ifdef CONFIG_PARISC64
984 #define PIOP_TO_GMMIO(lba, addr) \
985 ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
987 /*******************************************************
989 ** LBA PAT "I/O Port" Space Accessor Functions
991 ** This set of accessor functions is intended for use with
992 ** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes).
994 ** This uses the PIOP space located in the first 64MB of GMMIO.
995 ** Each rope gets a full 64*KB* (ie 4 bytes per page) this way.
996 ** bits 1:0 stay the same. bits 15:2 become 25:12.
997 ** Then add the base and we can generate an I/O Port cycle.
998 ********************************************************/
1000 #define LBA_PORT_IN(size, mask) \
1001 static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \
1004 ASSERT(bus != NULL); \
1005 DBG_PORT("%s(0x%p, 0x%x) ->", __FUNCTION__, l, addr); \
1006 t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
1007 DBG_PORT(" 0x%x\n", t); \
1017 #define LBA_PORT_OUT(size, mask) \
1018 static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \
1020 void *where = (void *) PIOP_TO_GMMIO(LBA_DEV(l), addr); \
1021 ASSERT(bus != NULL); \
1022 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, l, addr, val); \
1023 WRITE_REG##size(val, where); \
1024 /* flush the I/O down to the elroy at least */ \
1025 lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
1033 static struct pci_port_ops lba_pat_port_ops = {
1035 .inw = lba_pat_in16,
1036 .inl = lba_pat_in32,
1037 .outb = lba_pat_out8,
1038 .outw = lba_pat_out16,
1039 .outl = lba_pat_out32
1045 ** make range information from PDC available to PCI subsystem.
1046 ** We make the PDC call here in order to get the PCI bus range
1047 ** numbers. The rest will get forwarded in pcibios_fixup_bus().
1048 ** We don't have a struct pci_bus assigned to us yet.
1051 lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
1053 unsigned long bytecnt;
1054 pdc_pat_cell_mod_maddr_block_t pa_pdc_cell; /* PA_VIEW */
1055 pdc_pat_cell_mod_maddr_block_t io_pdc_cell; /* IO_VIEW */
1057 long status; /* PDC return status */
1061 /* return cell module (IO view) */
1062 status = pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
1063 PA_VIEW, & pa_pdc_cell);
1064 pa_count = pa_pdc_cell.mod[1];
1066 status |= pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
1067 IO_VIEW, &io_pdc_cell);
1068 io_count = io_pdc_cell.mod[1];
1070 /* We've already done this once for device discovery...*/
1071 if (status != PDC_OK) {
1072 panic("pdc_pat_cell_module() call failed for LBA!\n");
1075 if (PAT_GET_ENTITY(pa_pdc_cell.mod_info) != PAT_ENTITY_LBA) {
1076 panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n");
1080 ** Inspect the resources PAT tells us about
1082 for (i = 0; i < pa_count; i++) {
1085 unsigned long start;
1086 unsigned long end; /* aka finish */
1090 p = (void *) &(pa_pdc_cell.mod[2+i*3]);
1091 io = (void *) &(io_pdc_cell.mod[2+i*3]);
1093 /* Convert the PAT range data to PCI "struct resource" */
1094 switch(p->type & 0xff) {
1096 lba_dev->hba.bus_num.start = p->start;
1097 lba_dev->hba.bus_num.end = p->end;
1101 /* used to fix up pre-initialized MEM BARs */
1102 lba_dev->hba.lmmio_space_offset = p->start - io->start;
1104 r = &(lba_dev->hba.lmmio_space);
1105 r->name = "LBA LMMIO";
1106 r->start = p->start;
1108 r->flags = IORESOURCE_MEM;
1109 r->parent = r->sibling = r->child = NULL;
1113 /* MMIO space > 4GB phys addr; for 64-bit BAR */
1114 r = &(lba_dev->hba.gmmio_space);
1115 r->name = "LBA GMMIO";
1116 r->start = p->start;
1118 r->flags = IORESOURCE_MEM;
1119 r->parent = r->sibling = r->child = NULL;
1123 printk(KERN_WARNING MODULE_NAME
1124 " range[%d] : ignoring NPIOP (0x%lx)\n",
1130 ** Postable I/O port space is per PCI host adapter.
1131 ** base of 64MB PIOP region
1133 lba_dev->iop_base = p->start;
1135 r = &(lba_dev->hba.io_space);
1136 r->name = "LBA I/O Port";
1137 r->start = HBA_PORT_BASE(lba_dev->hba.hba_num);
1138 r->end = r->start + HBA_PORT_SPACE_SIZE - 1;
1139 r->flags = IORESOURCE_IO;
1140 r->parent = r->sibling = r->child = NULL;
1144 printk(KERN_WARNING MODULE_NAME
1145 " range[%d] : unknown pat range type (0x%lx)\n",
1152 /* keep compiler from complaining about missing declarations */
1153 #define lba_pat_port_ops lba_astro_port_ops
1154 #define lba_pat_resources(pa_dev, lba_dev)
1155 #endif /* CONFIG_PARISC64 */
1159 lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
1162 unsigned long rsize;
1165 #ifdef CONFIG_PARISC64
1167 ** Sign extend all BAR values on "legacy" platforms.
1168 ** "Sprockets" PDC (Forte/Allegro) initializes everything
1169 ** for "legacy" 32-bit OS (HPUX 10.20).
1170 ** Upper 32-bits of 64-bit BAR will be zero too.
1172 lba_dev->hba.lmmio_space_offset = 0xffffffff00000000UL;
1174 lba_dev->hba.lmmio_space_offset = 0UL;
1178 ** With "legacy" firmware, the lowest byte of FW_SCRATCH
1179 ** represents bus->secondary and the second byte represents
1180 ** bus->subsidiary (i.e. highest PPB programmed by firmware).
1181 ** PCI bus walk *should* end up with the same result.
1182 ** FIXME: But we don't have sanity checks in PCI or LBA.
1184 lba_num = READ_REG32(pa_dev->hpa + LBA_FW_SCRATCH);
1185 r = &(lba_dev->hba.bus_num);
1186 r->name = "LBA PCI Busses";
1187 r->start = lba_num & 0xff;
1188 r->end = (lba_num>>8) & 0xff;
1190 /* Set up local PCI Bus resources - we don't really need
1191 ** them for Legacy boxes but it's nice to see in /proc.
1193 r = &(lba_dev->hba.lmmio_space);
1194 r->name = "LBA PCI LMMIO";
1195 r->flags = IORESOURCE_MEM;
1196 /* Ignore "Range Enable" bit in the BASE register */
1197 r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev),
1198 ((long) READ_REG32(pa_dev->hpa + LBA_LMMIO_BASE)) & ~1UL);
1199 rsize = ~READ_REG32(pa_dev->hpa + LBA_LMMIO_MASK) + 1;
1202 ** Each rope only gets part of the distributed range.
1203 ** Adjust "window" for this rope
1205 rsize /= ROPES_PER_SBA;
1206 r->start += rsize * LBA_NUM(pa_dev->hpa);
1207 r->end = r->start + rsize - 1 ;
1210 ** XXX FIXME - ignore LBA_ELMMIO_BASE for now
1211 ** "Directed" ranges are used when the "distributed range" isn't
1212 ** sufficient for all devices below a given LBA. Typically devices
1213 ** like graphics cards or X25 may need a directed range when the
1214 ** bus has multiple slots (ie multiple devices) or the device
1215 ** needs more than the typical 4 or 8MB a distributed range offers.
1217 ** The main reason for ignoring it now frigging complications.
1218 ** Directed ranges may overlap (and have precedence) over
1219 ** distributed ranges. Ie a distributed range assigned to a unused
1220 ** rope may be used by a directed range on a different rope.
1221 ** Support for graphics devices may require fixing this
1222 ** since they may be assigned a directed range which overlaps
1223 ** an existing (but unused portion of) distributed range.
1225 r = &(lba_dev->hba.elmmio_space);
1226 r->name = "extra LBA PCI LMMIO";
1227 r->flags = IORESOURCE_MEM;
1228 r->start = READ_REG32(pa_dev->hpa + LBA_ELMMIO_BASE);
1231 /* check Range Enable bit */
1233 /* First baby step to getting Direct Ranges listed in /proc.
1234 ** AFAIK, only Sprockets PDC will setup a directed Range.
1239 r->end += ~READ_REG32(pa_dev->hpa + LBA_ELMMIO_MASK);
1240 printk(KERN_DEBUG "WARNING: Ignoring enabled ELMMIO BASE 0x%0lx SIZE 0x%lx\n",
1246 r = &(lba_dev->hba.io_space);
1247 r->name = "LBA PCI I/O Ports";
1248 r->flags = IORESOURCE_IO;
1249 r->start = READ_REG32(pa_dev->hpa + LBA_IOS_BASE) & ~1L;
1250 r->end = r->start + (READ_REG32(pa_dev->hpa + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1));
1252 /* Virtualize the I/O Port space ranges */
1253 lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num);
1254 r->start |= lba_num;
1259 /**************************************************************************
1261 ** LBA initialization code (HW and SW)
1263 ** o identify LBA chip itself
1264 ** o initialize LBA chip modes (HardFail)
1265 ** o FIXME: initialize DMA hints for reasonable defaults
1266 ** o enable configuration functions
1267 ** o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked)
1269 **************************************************************************/
1272 lba_hw_init(struct lba_device *d)
1275 u32 bus_reset; /* PDC_PAT_BUG */
1278 printk(KERN_DEBUG "LBA %lx STAT_CTL %Lx ERROR_CFG %Lx STATUS %Lx DMA_CTL %Lx\n",
1280 READ_REG64(d->hba.base_addr + LBA_STAT_CTL),
1281 READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG),
1282 READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS),
1283 READ_REG64(d->hba.base_addr + LBA_DMA_CTL) );
1284 printk(KERN_DEBUG " ARB mask %Lx pri %Lx mode %Lx mtlt %Lx\n",
1285 READ_REG64(d->hba.base_addr + LBA_ARB_MASK),
1286 READ_REG64(d->hba.base_addr + LBA_ARB_PRI),
1287 READ_REG64(d->hba.base_addr + LBA_ARB_MODE),
1288 READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) );
1289 printk(KERN_DEBUG " HINT cfg 0x%Lx\n",
1290 READ_REG64(d->hba.base_addr + LBA_HINT_CFG));
1291 printk(KERN_DEBUG " HINT reg ");
1293 for (i=LBA_HINT_BASE; i< (14*8 + LBA_HINT_BASE); i+=8)
1294 printk(" %Lx", READ_REG64(d->hba.base_addr + i));
1297 #endif /* DEBUG_LBA_PAT */
1299 #ifdef CONFIG_PARISC64
1301 * FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support
1302 * Only N-Class and up can really make use of Get slot status.
1303 * maybe L-class too but I've never played with it there.
1307 /* PDC_PAT_BUG: exhibited in rev 40.48 on L2000 */
1308 bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1;
1310 printk(KERN_DEBUG "NOTICE: PCI bus reset still asserted! (clearing)\n");
1313 stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);
1314 if (stat & LBA_SMART_MODE) {
1315 printk(KERN_DEBUG "NOTICE: LBA in SMART mode! (cleared)\n");
1316 stat &= ~LBA_SMART_MODE;
1317 WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG);
1320 /* Set HF mode as the default (vs. -1 mode). */
1321 stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);
1322 WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
1325 ** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal
1326 ** if it's not already set. If we just cleared the PCI Bus Reset
1327 ** signal, wait a bit for the PCI devices to recover and setup.
1330 mdelay(pci_post_reset_delay);
1332 if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) {
1334 ** PDC_PAT_BUG: PDC rev 40.48 on L2000.
1335 ** B2000/C3600/J6000 also have this problem?
1337 ** Elroys with hot pluggable slots don't get configured
1338 ** correctly if the slot is empty. ARB_MASK is set to 0
1339 ** and we can't master transactions on the bus if it's
1340 ** not at least one. 0x3 enables elroy and first slot.
1342 printk(KERN_DEBUG "NOTICE: Enabling PCI Arbitration\n");
1343 WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK);
1347 ** FIXME: Hint registers are programmed with default hint
1348 ** values by firmware. Hints should be sane even if we
1349 ** can't reprogram them the way drivers want.
1357 lba_common_init(struct lba_device *lba_dev)
1359 pci_bios = &lba_bios_ops;
1360 pcibios_register_hba(HBA_DATA(lba_dev));
1361 lba_dev->lba_lock = SPIN_LOCK_UNLOCKED;
1364 ** Set flags which depend on hw_rev
1366 if (!LBA_TR4PLUS(lba_dev)) {
1367 lba_dev->flags |= LBA_FLAG_NO_DMA_DURING_CFG;
1374 ** Determine if lba should claim this chip (return 0) or not (return 1).
1375 ** If so, initialize the chip and tell other partners in crime they
1379 lba_driver_probe(struct parisc_device *dev)
1381 struct lba_device *lba_dev;
1382 struct pci_bus *lba_bus;
1387 /* Read HW Rev First */
1388 func_class = READ_REG32(dev->hpa + LBA_FCLASS);
1390 if (IS_ELROY(dev)) {
1392 switch (func_class) {
1393 case 0: version = "TR1.0"; break;
1394 case 1: version = "TR2.0"; break;
1395 case 2: version = "TR2.1"; break;
1396 case 3: version = "TR2.2"; break;
1397 case 4: version = "TR3.0"; break;
1398 case 5: version = "TR4.0"; break;
1399 default: version = "TR4+";
1401 printk(KERN_INFO "%s version %s (0x%x) found at 0x%lx\n",
1402 MODULE_NAME, version, func_class & 0xf, dev->hpa);
1404 /* Just in case we find some prototypes... */
1405 } else if (IS_MERCURY(dev) || IS_QUICKSILVER(dev)) {
1407 version = kmalloc(6, GFP_KERNEL);
1408 sprintf(version,"TR%d.%d",(func_class >> 4),(func_class & 0xf));
1409 /* We could use one printk for both and have it outside,
1410 * but for the mask for func_class.
1412 printk(KERN_INFO "%s version %s (0x%x) found at 0x%lx\n",
1413 MODULE_NAME, version, func_class & 0xff, dev->hpa);
1416 if (func_class < 2) {
1417 printk(KERN_WARNING "Can't support LBA older than TR2.1"
1418 " - continuing under adversity.\n");
1422 ** Tell I/O SAPIC driver we have a IRQ handler/region.
1424 tmp_obj = iosapic_register(dev->hpa + LBA_IOSAPIC_BASE);
1426 /* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't
1427 ** have an IRT entry will get NULL back from iosapic code.
1430 lba_dev = kmalloc(sizeof(struct lba_device), GFP_KERNEL);
1431 if (NULL == lba_dev)
1433 printk(KERN_ERR "lba_init_chip - couldn't alloc lba_device\n");
1437 memset(lba_dev, 0, sizeof(struct lba_device));
1440 /* ---------- First : initialize data we already have --------- */
1443 ** Need hw_rev to adjust configuration space behavior.
1444 ** LBA_TR4PLUS macro uses hw_rev field.
1446 lba_dev->hw_rev = func_class;
1448 lba_dev->hba.base_addr = dev->hpa; /* faster access */
1449 lba_dev->hba.dev = dev;
1450 lba_dev->iosapic_obj = tmp_obj; /* save interrupt handle */
1451 lba_dev->hba.iommu = sba_get_iommu(dev); /* get iommu data */
1453 /* ------------ Second : initialize common stuff ---------- */
1454 lba_common_init(lba_dev);
1456 if (lba_hw_init(lba_dev))
1459 /* ---------- Third : setup I/O Port and MMIO resources --------- */
1462 /* PDC PAT firmware uses PIOP region of GMMIO space. */
1463 pci_port = &lba_pat_port_ops;
1464 /* Go ask PDC PAT what resources this LBA has */
1465 lba_pat_resources(dev, lba_dev);
1467 /* Sprockets PDC uses NPIOP region */
1468 pci_port = &lba_astro_port_ops;
1470 /* Poke the chip a bit for /proc output */
1471 lba_legacy_resources(dev, lba_dev);
1475 ** Tell PCI support another PCI bus was found.
1476 ** Walks PCI bus for us too.
1478 dev->dev.platform_data = lba_dev;
1479 lba_bus = lba_dev->hba.hba_bus =
1480 pci_scan_bus_parented(&dev->dev, lba_dev->hba.bus_num.start,
1481 is_pdc_pat() ? &pat_cfg_ops : &lba_cfg_ops,
1485 /* assign resources to un-initialized devices */
1486 DBG_PAT("LBA pci_bus_assign_resources()\n");
1487 pci_bus_assign_resources(lba_bus);
1489 #ifdef DEBUG_LBA_PAT
1490 DBG_PAT("\nLBA PIOP resource tree\n");
1491 lba_dump_res(&lba_dev->hba.io_space, 2);
1492 DBG_PAT("\nLBA LMMIO resource tree\n");
1493 lba_dump_res(&lba_dev->hba.lmmio_space, 2);
1498 ** Once PCI register ops has walked the bus, access to config
1499 ** space is restricted. Avoids master aborts on config cycles.
1500 ** Early LBA revs go fatal on *any* master abort.
1502 if (!LBA_TR4PLUS(lba_dev)) {
1503 lba_dev->flags |= LBA_FLAG_SKIP_PROBE;
1506 /* Whew! Finally done! Tell services we got this one covered. */
1510 static struct parisc_device_id lba_tbl[] = {
1511 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, ELROY_HVERS, 0xa },
1512 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, MERCURY_HVERS, 0xa },
1513 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, QUICKSILVER_HVERS, 0xa },
1517 static struct parisc_driver lba_driver = {
1518 .name = MODULE_NAME,
1519 .id_table = lba_tbl,
1520 .probe = lba_driver_probe,
1524 ** One time initialization to let the world know the LBA was found.
1525 ** Must be called exactly once before pci_init().
1527 void __init lba_init(void)
1529 register_parisc_driver(&lba_driver);
1533 ** Initialize the IBASE/IMASK registers for LBA (Elroy).
1534 ** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA).
1535 ** sba_iommu is responsible for locking (none needed at init time).
1538 lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask)
1540 unsigned long base_addr = lba->hpa;
1542 imask <<= 2; /* adjust for hints - 2 more bits */
1544 ASSERT((ibase & 0x003fffff) == 0);
1545 ASSERT((imask & 0x003fffff) == 0);
1547 DBG("%s() ibase 0x%x imask 0x%x\n", __FUNCTION__, ibase, imask);
1548 WRITE_REG32( imask, base_addr + LBA_IMASK);
1549 WRITE_REG32( ibase, base_addr + LBA_IBASE);