3 ** PCI Lower Bus Adapter (LBA) manager
5 ** (c) Copyright 1999,2000 Grant Grundler
6 ** (c) Copyright 1999,2000 Hewlett-Packard Company
8 ** This program is free software; you can redistribute it and/or modify
9 ** it under the terms of the GNU General Public License as published by
10 ** the Free Software Foundation; either version 2 of the License, or
11 ** (at your option) any later version.
14 ** This module primarily provides access to PCI bus (config/IOport
15 ** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class
16 ** with 4 digit model numbers - eg C3000 (and A400...sigh).
18 ** LBA driver isn't as simple as the Dino driver because:
19 ** (a) this chip has substantial bug fixes between revisions
20 ** (Only one Dino bug has a software workaround :^( )
21 ** (b) has more options which we don't (yet) support (DMA hints, OLARD)
22 ** (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver)
23 ** (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC).
24 ** (dino only deals with "Legacy" PDC)
26 ** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver.
27 ** (I/O SAPIC is integratd in the LBA chip).
29 ** FIXME: Add support to SBA and LBA drivers for DMA hint sets
30 ** FIXME: Add support for PCI card hot-plug (OLARD).
33 #include <linux/delay.h>
34 #include <linux/types.h>
35 #include <linux/kernel.h>
36 #include <linux/spinlock.h>
37 #include <linux/init.h> /* for __init and __devinit */
38 #include <linux/pci.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
41 #include <linux/smp_lock.h>
43 #include <asm/byteorder.h>
45 #include <asm/pdcpat.h>
47 #include <asm/system.h>
49 #include <asm/hardware.h> /* for register_parisc_driver() stuff */
50 #include <asm/parisc-device.h>
51 #include <asm/iosapic.h> /* for iosapic_register() */
52 #include <asm/io.h> /* read/write stuff */
56 #define FALSE (1 == 0)
59 #undef DEBUG_LBA /* general stuff */
60 #undef DEBUG_LBA_PORT /* debug I/O Port access */
61 #undef DEBUG_LBA_CFG /* debug Config Space Access (ie PCI Bus walk) */
62 #undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */
64 #undef FBB_SUPPORT /* Fast Back-Back xfers - NOT READY YET */
68 #define DBG(x...) printk(x)
74 #define DBG_PORT(x...) printk(x)
76 #define DBG_PORT(x...)
80 #define DBG_CFG(x...) printk(x)
86 #define DBG_PAT(x...) printk(x)
93 #define ASSERT(expr) \
95 printk("\n%s:%d: Assertion " #expr " failed!\n", \
96 __FILE__, __LINE__); \
105 ** Config accessor functions only pass in the 8-bit bus number and not
106 ** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
107 ** number based on what firmware wrote into the scratch register.
109 ** The "secondary" bus number is set to this before calling
110 ** pci_register_ops(). If any PPB's are present, the scan will
111 ** discover them and update the "secondary" and "subordinate"
112 ** fields in the pci_bus structure.
114 ** Changes in the configuration *may* result in a different
115 ** bus number for each LBA depending on what firmware does.
118 #define MODULE_NAME "LBA"
120 #define LBA_FUNC_ID 0x0000 /* function id */
121 #define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */
122 #define LBA_CAPABLE 0x0030 /* capabilities register */
124 #define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */
125 #define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */
127 #define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */
128 #define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */
129 #define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */
131 #define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */
132 #define LBA_ARB_PRI 0x0088 /* firmware sets this. */
133 #define LBA_ARB_MODE 0x0090 /* firmware sets this. */
134 #define LBA_ARB_MTLT 0x0098 /* firmware sets this. */
136 #define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */
138 #define LBA_STAT_CTL 0x0108 /* Status & Control */
139 #define LBA_BUS_RESET 0x01 /* Deassert PCI Bus Reset Signal */
140 #define CLEAR_ERRLOG 0x10 /* "Clear Error Log" cmd */
141 #define CLEAR_ERRLOG_ENABLE 0x20 /* "Clear Error Log" Enable */
142 #define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */
144 #define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */
145 #define LBA_LMMIO_MASK 0x0208
147 #define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */
148 #define LBA_GMMIO_MASK 0x0218
150 #define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */
151 #define LBA_WLMMIO_MASK 0x0228
153 #define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */
154 #define LBA_WGMMIO_MASK 0x0238
156 #define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */
157 #define LBA_IOS_MASK 0x0248
159 #define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */
160 #define LBA_ELMMIO_MASK 0x0258
162 #define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */
163 #define LBA_EIOS_MASK 0x0268
165 #define LBA_GLOBAL_MASK 0x0270 /* Mercury only: Global Address Mask */
166 #define LBA_DMA_CTL 0x0278 /* firmware sets this */
168 #define LBA_IBASE 0x0300 /* SBA DMA support */
169 #define LBA_IMASK 0x0308
171 /* FIXME: ignore DMA Hint stuff until we can measure performance */
172 #define LBA_HINT_CFG 0x0310
173 #define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */
175 #define LBA_BUS_MODE 0x0620
177 /* ERROR regs are needed for config cycle kluges */
178 #define LBA_ERROR_CONFIG 0x0680
179 #define LBA_SMART_MODE 0x20
180 #define LBA_ERROR_STATUS 0x0688
181 #define LBA_ROPE_CTL 0x06A0
183 #define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */
185 /* non-postable I/O port space, densely packed */
186 #define LBA_PORT_BASE (PCI_F_EXTEND | 0xfee00000UL)
188 #define ELROY_HVERS 0x782
189 #define MERCURY_HVERS 0x783
190 #define QUICKSILVER_HVERS 0x784
192 static inline int IS_ELROY(struct parisc_device *d)
194 return (d->id.hversion == ELROY_HVERS);
197 static inline int IS_MERCURY(struct parisc_device *d)
199 return (d->id.hversion == MERCURY_HVERS);
202 static inline int IS_QUICKSILVER(struct parisc_device *d)
204 return (d->id.hversion == QUICKSILVER_HVERS);
209 ** lba_device: Per instance Elroy data structure
212 struct pci_hba_data hba;
217 #ifdef CONFIG_PARISC64
218 unsigned long iop_base; /* PA_VIEW - for IO port accessor funcs */
221 int flags; /* state/functionality enabled */
222 int hw_rev; /* HW revision of chip */
231 #define LBA_FLAG_NO_DMA_DURING_CFG 0x01
232 #define LBA_FLAG_SKIP_PROBE 0x10
234 /* Tape Release 4 == hw_rev 5 */
235 #define LBA_TR4PLUS(d) ((d)->hw_rev > 0x4)
236 #define LBA_DMA_DURING_CFG_DISABLED(d) ((d)->flags & LBA_FLAG_NO_DMA_DURING_CFG)
237 #define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)
240 /* Looks nice and keeps the compiler happy */
241 #define LBA_DEV(d) ((struct lba_device *) (d))
245 ** Only allow 8 subsidiary busses per LBA
246 ** Problem is the PCI bus numbering is globally shared.
248 #define LBA_MAX_NUM_BUSES 8
250 /************************************
251 * LBA register read and write support
253 * BE WARNED: register writes are posted.
254 * (ie follow writes which must reach HW with a read)
256 #define READ_U8(addr) __raw_readb(addr)
257 #define READ_U16(addr) __raw_readw(addr)
258 #define READ_U32(addr) __raw_readl(addr)
259 #define WRITE_U8(value, addr) __raw_writeb(value, addr)
260 #define WRITE_U16(value, addr) __raw_writew(value, addr)
261 #define WRITE_U32(value, addr) __raw_writel(value, addr)
263 #define READ_REG8(addr) readb(addr)
264 #define READ_REG16(addr) readw(addr)
265 #define READ_REG32(addr) readl(addr)
266 #define READ_REG64(addr) readq(addr)
267 #define WRITE_REG8(value, addr) writeb(value, addr)
268 #define WRITE_REG16(value, addr) writew(value, addr)
269 #define WRITE_REG32(value, addr) writel(value, addr)
272 #define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8))
273 #define LBA_CFG_BUS(tok) ((u8) ((tok)>>16))
274 #define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f)
275 #define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)
279 ** Extract LBA (Rope) number from HPA
280 ** REVISIT: 16 ropes for Stretch/Ike?
282 #define ROPES_PER_IOC 8
283 #define LBA_NUM(x) ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1))
287 lba_dump_res(struct resource *r, int d)
294 printk(KERN_DEBUG "(%p)", r->parent);
295 for (i = d; i ; --i) printk(" ");
296 printk(KERN_DEBUG "%p [%lx,%lx]/%x\n", r, r->start, r->end, (int) r->flags);
297 lba_dump_res(r->child, d+2);
298 lba_dump_res(r->sibling, d);
303 ** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex
304 ** workaround for cfg cycles:
305 ** -- preserve LBA state
306 ** -- LBA_FLAG_NO_DMA_DURING_CFG workaround
307 ** -- turn on smart mode
308 ** -- probe with config writes before doing config reads
309 ** -- check ERROR_STATUS
310 ** -- clear ERROR_STATUS
311 ** -- restore LBA state
313 ** The workaround is only used for device discovery.
317 lba_device_present( u8 bus, u8 dfn, struct lba_device *d)
319 u8 first_bus = d->hba.hba_bus->secondary;
320 u8 last_sub_bus = d->hba.hba_bus->subordinate;
322 ASSERT(bus >= first_bus);
323 ASSERT(bus <= last_sub_bus);
324 ASSERT((bus - first_bus) < LBA_MAX_NUM_BUSES);
326 if ((bus < first_bus) ||
327 (bus > last_sub_bus) ||
328 ((bus - first_bus) >= LBA_MAX_NUM_BUSES))
330 /* devices that fall into any of these cases won't get claimed */
339 #define LBA_CFG_SETUP(d, tok) { \
340 /* Save contents of error config register. */ \
341 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
343 /* Save contents of status control register. */ \
344 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
346 /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA \
347 ** arbitration for full bus walks. \
349 if (LBA_DMA_DURING_CFG_DISABLED(d)) { \
350 /* Save contents of arb mask register. */ \
351 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
354 * Turn off all device arbitration bits (i.e. everything \
355 * except arbitration enable bit). \
357 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
361 * Set the smart mode bit so that master aborts don't cause \
362 * LBA to go into PCI fatal mode (required). \
364 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
368 #define LBA_CFG_PROBE(d, tok) { \
370 * Setup Vendor ID write and read back the address register \
371 * to make sure that LBA is the bus master. \
373 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
375 * Read address register to ensure that LBA is the bus master, \
376 * which implies that DMA traffic has stopped when DMA arb is off. \
378 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
380 * Generate a cfg write cycle (will have no affect on \
381 * Vendor ID register since read-only). \
383 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
385 * Make sure write has completed before proceeding further, \
386 * i.e. before setting clear enable. \
388 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
394 * -- Can't tell if config cycle got the error.
396 * OV bit is broken until rev 4.0, so can't use OV bit and
397 * LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle.
399 * As of rev 4.0, no longer need the error check.
401 * -- Even if we could tell, we still want to return -1
402 * for **ANY** error (not just master abort).
404 * -- Only clear non-fatal errors (we don't want to bring
405 * LBA out of pci-fatal mode).
407 * Actually, there is still a race in which
408 * we could be clearing a fatal error. We will
409 * live with this during our initial bus walk
410 * until rev 4.0 (no driver activity during
411 * initial bus walk). The initial bus walk
412 * has race conditions concerning the use of
413 * smart mode as well.
416 #define LBA_MASTER_ABORT_ERROR 0xc
417 #define LBA_FATAL_ERROR 0x10
419 #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \
420 u32 error_status = 0; \
422 * Set clear enable (CE) bit. Unset by HW when new \
423 * errors are logged -- LBA HW ERS section 14.3.3). \
425 WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \
426 error_status = READ_REG32(base + LBA_ERROR_STATUS); \
427 if ((error_status & 0x1f) != 0) { \
429 * Fail the config read request. \
432 if ((error_status & LBA_FATAL_ERROR) == 0) { \
434 * Clear error status (if fatal bit not set) by setting \
435 * clear error log bit (CL). \
437 WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \
442 #define LBA_CFG_TR4_ADDR_SETUP(d, addr) \
443 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
444 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR)
446 #define LBA_CFG_ADDR_SETUP(d, addr) { \
447 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
450 * -- Potentially could skip this once DMA bug fixed. \
452 * Read address register to ensure that LBA is the bus master, \
453 * which implies that DMA traffic has stopped when DMA arb is off. \
455 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
459 #define LBA_CFG_RESTORE(d, base) { \
461 * Restore status control register (turn off clear enable). \
463 WRITE_REG32(status_control, base + LBA_STAT_CTL); \
465 * Restore error config register (turn off smart mode). \
467 WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \
468 if (LBA_DMA_DURING_CFG_DISABLED(d)) { \
470 * Restore arb mask register (reenables DMA arbitration). \
472 WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \
479 lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size)
483 u32 arb_mask = 0; /* used by LBA_CFG_SETUP/RESTORE */
484 u32 error_config = 0; /* used by LBA_CFG_SETUP/RESTORE */
485 u32 status_control = 0; /* used by LBA_CFG_SETUP/RESTORE */
487 ASSERT((size == sizeof(u8)) ||
488 (size == sizeof(u16)) ||
489 (size == sizeof(u32)));
491 if ((size != sizeof(u8)) &&
492 (size != sizeof(u16)) &&
493 (size != sizeof(u32))) {
497 LBA_CFG_SETUP(d, tok);
498 LBA_CFG_PROBE(d, tok);
499 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
501 LBA_CFG_ADDR_SETUP(d, tok | reg);
504 data = (u32) READ_REG8(d->hba.base_addr + LBA_PCI_CFG_DATA + (reg & 3));
507 data = (u32) READ_REG16(d->hba.base_addr + LBA_PCI_CFG_DATA + (reg & 2));
510 data = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_DATA);
513 break; /* leave data as -1 */
516 LBA_CFG_RESTORE(d, d->hba.base_addr);
523 /* PAT PDC needs to be relocated in order to perform properly.
524 * tg3 driver does about 1600 PCI Cfg writes to initialize the card.
525 * On 440Mhz A500, PDC takes ~20ms/write, or ~30 seconds per card.
526 * On PA8800, that takes about 5ms/write (8 seconds).
527 * But relocating PDC will burn at least 4MB of RAM.
528 * Easier/Cheaper to just maintain our own mercury cfg ops.
530 #define pat_cfg_addr(bus, devfn, addr) (((bus) << 16) | ((devfn) << 8) | (addr))
532 static int pat_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
534 int tok = pat_cfg_addr(bus->number, devfn, pos);
536 int ret = pdc_pat_io_pci_cfg_read(tok, size, &tmp);
538 DBG_CFG("%s(%d:%d.%d+0x%02x) -> 0x%x %d\n", __FUNCTION__, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), pos, tmp, ret);
541 case 1: *data = (u8) tmp; return (tmp == (u8) ~0);
542 case 2: *data = (u16) tmp; return (tmp == (u16) ~0);
543 case 4: *data = (u32) tmp; return (tmp == (u32) ~0);
549 static int pat_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
551 int tok = pat_cfg_addr(bus->number, devfn, pos);
552 int ret = pdc_pat_io_pci_cfg_write(tok, size, data);
554 DBG_CFG("%s(%d:%d.%d+0x%02x, 0x%lx/%d)\n", __FUNCTION__, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), pos, data, size);
558 static struct pci_ops pat_cfg_ops = {
559 .read = pat_cfg_read,
560 .write = pat_cfg_write,
565 #ifdef CONFIG_PARISC64
566 static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
568 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
569 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
570 u32 tok = LBA_CFG_TOK(local_bus, devfn);
573 ** Should only get here on fully working LBA rev.
574 ** This is how simple the original LBA code should have been.
576 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
578 case 1: *(u8 *) data = READ_REG8(d->hba.base_addr + LBA_PCI_CFG_DATA
580 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__, tok, pos,
582 return(*(u8 *)data == (u8) ~0U);
583 case 2: *(u16 *) data = READ_REG16(d->hba.base_addr + LBA_PCI_CFG_DATA
585 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__, tok, pos,
587 return(*(u16 *)data == (u16) ~0U);
588 case 4: *(u32 *) data = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_DATA);
589 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__, tok, pos, *data);
590 return(*data == ~0U);
592 DBG_CFG("%s(%x+%2x) -> bad size (%d)\n", __FUNCTION__, tok, pos, size);
594 return(!PCIBIOS_SUCCESSFUL); /* failed */
598 * LBA 4.0 config write code implements non-postable semantics
599 * by doing a read of CONFIG ADDR after the write.
602 static int mercury_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
604 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
605 unsigned long data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
606 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
607 u32 tok = LBA_CFG_TOK(local_bus,devfn);
609 ASSERT((tok & 0xff) == 0);
612 DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __FUNCTION__, tok, pos, data);
614 /* Basic Algorithm */
615 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
617 case 1: WRITE_REG8 (data, data_reg + (pos & 3)); break;
618 case 2: WRITE_REG16(data, data_reg + (pos & 2)); break;
619 case 4: WRITE_REG32(data, data_reg); break;
621 DBG_CFG("%s(%x+%2x) WTF! size %d\n", __FUNCTION__, tok, pos,
625 /* flush posted write */
626 lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
627 return PCIBIOS_SUCCESSFUL;
631 static struct pci_ops mercury_cfg_ops = {
632 .read = mercury_cfg_read,
633 .write = mercury_cfg_write,
636 #define mercury_cfg_ops lba_cfg_ops
637 #endif /* CONFIG_PARISC64 */
640 static int lba_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
642 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
643 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
644 u32 tok = LBA_CFG_TOK(local_bus, devfn);
646 /* FIXME: B2K/C3600 workaround is always use old method... */
647 /* if (!LBA_TR4PLUS(d) && !LBA_SKIP_PROBE(d)) */ {
648 /* original - Generate config cycle on broken elroy
649 with risk we will miss PCI bus errors. */
650 *data = lba_rd_cfg(d, tok, pos, size);
651 DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __FUNCTION__, tok, pos, *data);
652 return(*data == ~0U);
655 if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d)))
657 DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __FUNCTION__, tok, pos);
658 /* either don't want to look or know device isn't present. */
664 ** Should only get here on fully working LBA rev.
665 ** This is how simple the code should have been.
667 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
669 case 1: *(u8 *) data = READ_REG8(d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
671 case 2: *(u16 *) data = READ_REG16(d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
673 case 4: *(u32 *) data = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_DATA);
676 DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__, tok, pos, *data);
677 return(*data == ~0U);
682 lba_wr_cfg( struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size)
686 u32 error_config = 0;
687 u32 status_control = 0;
689 ASSERT((size == sizeof(u8)) ||
690 (size == sizeof(u16)) ||
691 (size == sizeof(u32)));
693 if ((size != sizeof(u8)) &&
694 (size != sizeof(u16)) &&
695 (size != sizeof(u32))) {
699 LBA_CFG_SETUP(d, tok);
700 LBA_CFG_ADDR_SETUP(d, tok | reg);
703 WRITE_REG8((u8) data, d->hba.base_addr + LBA_PCI_CFG_DATA + (reg&3));
706 WRITE_REG16((u8) data, d->hba.base_addr + LBA_PCI_CFG_DATA +(reg&2));
709 WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
714 LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
715 LBA_CFG_RESTORE(d, d->hba.base_addr);
720 * LBA 4.0 config write code implements non-postable semantics
721 * by doing a read of CONFIG ADDR after the write.
724 static int lba_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
726 struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
727 u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary;
728 u32 tok = LBA_CFG_TOK(local_bus,devfn);
730 ASSERT((tok & 0xff) == 0);
733 if (!LBA_TR4PLUS(d) && !LBA_SKIP_PROBE(d)) {
734 /* Original Workaround */
735 lba_wr_cfg(d, tok, pos, (u32) data, size);
736 DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __FUNCTION__, tok, pos,data);
740 if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d))) {
741 DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __FUNCTION__, tok, pos,data);
742 return 1; /* New Workaround */
745 DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __FUNCTION__, tok, pos, data);
747 /* Basic Algorithm */
748 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
750 case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
752 case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
754 case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
757 /* flush posted write */
758 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
763 static struct pci_ops lba_cfg_ops = {
764 .read = lba_cfg_read,
765 .write = lba_cfg_write,
772 DBG(MODULE_NAME ": lba_bios_init\n");
776 #ifdef CONFIG_PARISC64
779 ** Determine if a device is already configured.
780 ** If so, reserve it resources.
782 ** Read PCI cfg command register and see if I/O or MMIO is enabled.
783 ** PAT has to enable the devices it's using.
785 ** Note: resources are fixed up before we try to claim them.
788 lba_claim_dev_resources(struct pci_dev *dev)
793 (void) pci_read_config_word(dev, PCI_COMMAND, &cmd);
795 srch_flags = (cmd & PCI_COMMAND_IO) ? IORESOURCE_IO : 0;
796 if (cmd & PCI_COMMAND_MEMORY)
797 srch_flags |= IORESOURCE_MEM;
802 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
803 if (dev->resource[i].flags & srch_flags) {
804 pci_claim_resource(dev, i);
805 DBG(" claimed %s %d [%lx,%lx]/%x\n",
807 dev->resource[i].start,
808 dev->resource[i].end,
809 (int) dev->resource[i].flags
815 #define lba_claim_dev_resources(dev)
820 ** The algorithm is generic code.
821 ** But it needs to access local data structures to get the IRQ base.
822 ** Could make this a "pci_fixup_irq(bus, region)" but not sure
825 ** Called by do_pci_scan_bus() immediately after each PCI bus is walked.
826 ** Resources aren't allocated until recursive buswalk below HBA is completed.
829 lba_fixup_bus(struct pci_bus *bus)
831 struct list_head *ln;
835 struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge));
836 int lba_portbase = HBA_PORT_BASE(ldev->hba.hba_num);
838 DBG("lba_fixup_bus(0x%p) bus %d sysdata 0x%p\n",
839 bus, bus->secondary, bus->bridge->platform_data);
842 ** Properly Setup MMIO resources for this bus.
843 ** pci_alloc_primary_bus() mangles this.
847 pci_read_bridge_bases(bus);
849 /* Host-PCI Bridge */
852 DBG("lba_fixup_bus() %s [%lx/%lx]/%x\n",
853 ldev->hba.io_space.name,
854 ldev->hba.io_space.start, ldev->hba.io_space.end,
855 (int) ldev->hba.io_space.flags);
856 DBG("lba_fixup_bus() %s [%lx/%lx]/%x\n",
857 ldev->hba.lmmio_space.name,
858 ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end,
859 (int) ldev->hba.lmmio_space.flags);
861 err = request_resource(&ioport_resource, &(ldev->hba.io_space));
863 lba_dump_res(&ioport_resource, 2);
867 if (ldev->hba.elmmio_space.start) {
868 err = request_resource(&iomem_resource,
869 &(ldev->hba.elmmio_space));
872 printk("FAILED: lba_fixup_bus() request for "
873 "elmmio_space [%lx/%lx]\n",
874 ldev->hba.elmmio_space.start,
875 ldev->hba.elmmio_space.end);
877 /* lba_dump_res(&iomem_resource, 2); */
882 err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space));
884 /* FIXME overlaps with elmmio will fail here.
885 * Need to prune (or disable) the distributed range.
887 * BEWARE: conflicts with this lmmio range may be
888 * elmmio range which is pointing down another rope.
891 printk("FAILED: lba_fixup_bus() request for "
892 "lmmio_space [%lx/%lx]\n",
893 ldev->hba.lmmio_space.start,
894 ldev->hba.lmmio_space.end);
895 /* lba_dump_res(&iomem_resource, 2); */
898 #ifdef CONFIG_PARISC64
899 /* GMMIO is distributed range. Every LBA/Rope gets part it. */
900 if (ldev->hba.gmmio_space.flags) {
901 err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space));
903 printk("FAILED: lba_fixup_bus() request for "
904 "gmmio_space [%lx/%lx]\n",
905 ldev->hba.gmmio_space.start,
906 ldev->hba.gmmio_space.end);
907 lba_dump_res(&iomem_resource, 2);
913 /* advertize Host bridge resources to PCI bus */
914 bus->resource[0] = &(ldev->hba.io_space);
915 bus->resource[1] = &(ldev->hba.lmmio_space);
917 if (ldev->hba.elmmio_space.start)
918 bus->resource[i++] = &(ldev->hba.elmmio_space);
919 if (ldev->hba.gmmio_space.start)
920 bus->resource[i++] = &(ldev->hba.gmmio_space);
924 list_for_each(ln, &bus->devices) {
926 struct pci_dev *dev = pci_dev_b(ln);
928 DBG("lba_fixup_bus() %s\n", pci_name(dev));
930 /* Virtualize Device/Bridge Resources. */
931 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
932 struct resource *res = &dev->resource[i];
934 /* If resource not allocated - skip it */
938 if (res->flags & IORESOURCE_IO) {
939 DBG("lba_fixup_bus() I/O Ports [%lx/%lx] -> ",
940 res->start, res->end);
941 res->start |= lba_portbase;
942 res->end |= lba_portbase;
943 DBG("[%lx/%lx]\n", res->start, res->end);
944 } else if (res->flags & IORESOURCE_MEM) {
946 ** Convert PCI (IO_VIEW) addresses to
947 ** processor (PA_VIEW) addresses
949 DBG("lba_fixup_bus() MMIO [%lx/%lx] -> ",
950 res->start, res->end);
951 res->start = PCI_HOST_ADDR(HBA_DATA(ldev), res->start);
952 res->end = PCI_HOST_ADDR(HBA_DATA(ldev), res->end);
953 DBG("[%lx/%lx]\n", res->start, res->end);
955 DBG("lba_fixup_bus() WTF? 0x%lx [%lx/%lx] XXX",
956 res->flags, res->start, res->end);
962 ** If one device does not support FBB transfers,
963 ** No one on the bus can be allowed to use them.
965 (void) pci_read_config_word(dev, PCI_STATUS, &status);
966 bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK);
970 /* Claim resources for PDC's devices */
971 lba_claim_dev_resources(dev);
975 ** P2PB's have no IRQs. ignore them.
977 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
980 /* Adjust INTERRUPT_LINE for this dev */
981 iosapic_fixup_irq(ldev->iosapic_obj, dev);
985 /* FIXME/REVISIT - finish figuring out to set FBB on both
986 ** pci_setup_bridge() clobbers PCI_BRIDGE_CONTROL.
987 ** Can't fixup here anyway....garr...
993 (void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control);
994 (void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK);
999 fbb_enable = PCI_COMMAND_FAST_BACK;
1002 /* Lastly enable FBB/PERR/SERR on all devices too */
1003 list_for_each(ln, &bus->devices) {
1004 (void) pci_read_config_word(dev, PCI_COMMAND, &status);
1005 status |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | fbb_enable;
1006 (void) pci_write_config_word(dev, PCI_COMMAND, status);
1012 struct pci_bios_ops lba_bios_ops = {
1013 .init = lba_bios_init,
1014 .fixup_bus = lba_fixup_bus,
1020 /*******************************************************
1022 ** LBA Sprockets "I/O Port" Space Accessor Functions
1024 ** This set of accessor functions is intended for use with
1025 ** "legacy firmware" (ie Sprockets on Allegro/Forte boxes).
1027 ** Many PCI devices don't require use of I/O port space (eg Tulip,
1028 ** NCR720) since they export the same registers to both MMIO and
1029 ** I/O port space. In general I/O port space is slower than
1030 ** MMIO since drivers are designed so PIO writes can be posted.
1032 ********************************************************/
1034 #define LBA_PORT_IN(size, mask) \
1035 static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
1038 t = READ_REG##size(LBA_PORT_BASE + addr); \
1039 DBG_PORT(" 0x%x\n", t); \
1050 ** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR
1052 ** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is
1053 ** guarantee non-postable completion semantics - not avoid X4107.
1054 ** The READ_U32 only guarantees the write data gets to elroy but
1055 ** out to the PCI bus. We can't read stuff from I/O port space
1056 ** since we don't know what has side-effects. Attempting to read
1057 ** from configuration space would be suicidal given the number of
1058 ** bugs in that elroy functionality.
1061 ** DMA read results can improperly pass PIO writes (X4107). The
1062 ** result of this bug is that if a processor modifies a location in
1063 ** memory after having issued PIO writes, the PIO writes are not
1064 ** guaranteed to be completed before a PCI device is allowed to see
1065 ** the modified data in a DMA read.
1067 ** Note that IKE bug X3719 in TR1 IKEs will result in the same
1071 ** The workaround for this bug is to always follow a PIO write with
1072 ** a PIO read to the same bus before starting DMA on that PCI bus.
1075 #define LBA_PORT_OUT(size, mask) \
1076 static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
1078 ASSERT(d != NULL); \
1079 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, d, addr, val); \
1080 WRITE_REG##size(val, LBA_PORT_BASE + addr); \
1081 if (LBA_DEV(d)->hw_rev < 3) \
1082 lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
1090 static struct pci_port_ops lba_astro_port_ops = {
1091 .inb = lba_astro_in8,
1092 .inw = lba_astro_in16,
1093 .inl = lba_astro_in32,
1094 .outb = lba_astro_out8,
1095 .outw = lba_astro_out16,
1096 .outl = lba_astro_out32
1100 #ifdef CONFIG_PARISC64
1101 #define PIOP_TO_GMMIO(lba, addr) \
1102 ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
1104 /*******************************************************
1106 ** LBA PAT "I/O Port" Space Accessor Functions
1108 ** This set of accessor functions is intended for use with
1109 ** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes).
1111 ** This uses the PIOP space located in the first 64MB of GMMIO.
1112 ** Each rope gets a full 64*KB* (ie 4 bytes per page) this way.
1113 ** bits 1:0 stay the same. bits 15:2 become 25:12.
1114 ** Then add the base and we can generate an I/O Port cycle.
1115 ********************************************************/
1117 #define LBA_PORT_IN(size, mask) \
1118 static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \
1121 DBG_PORT("%s(0x%p, 0x%x) ->", __FUNCTION__, l, addr); \
1122 t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
1123 DBG_PORT(" 0x%x\n", t); \
1133 #define LBA_PORT_OUT(size, mask) \
1134 static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \
1136 void *where = (void *) PIOP_TO_GMMIO(LBA_DEV(l), addr); \
1137 DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, l, addr, val); \
1138 WRITE_REG##size(val, where); \
1139 /* flush the I/O down to the elroy at least */ \
1140 lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
1148 static struct pci_port_ops lba_pat_port_ops = {
1150 .inw = lba_pat_in16,
1151 .inl = lba_pat_in32,
1152 .outb = lba_pat_out8,
1153 .outw = lba_pat_out16,
1154 .outl = lba_pat_out32
1160 ** make range information from PDC available to PCI subsystem.
1161 ** We make the PDC call here in order to get the PCI bus range
1162 ** numbers. The rest will get forwarded in pcibios_fixup_bus().
1163 ** We don't have a struct pci_bus assigned to us yet.
1166 lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
1168 unsigned long bytecnt;
1169 pdc_pat_cell_mod_maddr_block_t pa_pdc_cell; /* PA_VIEW */
1170 pdc_pat_cell_mod_maddr_block_t io_pdc_cell; /* IO_VIEW */
1172 long status; /* PDC return status */
1176 /* return cell module (IO view) */
1177 status = pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
1178 PA_VIEW, & pa_pdc_cell);
1179 pa_count = pa_pdc_cell.mod[1];
1181 status |= pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
1182 IO_VIEW, &io_pdc_cell);
1183 io_count = io_pdc_cell.mod[1];
1185 /* We've already done this once for device discovery...*/
1186 if (status != PDC_OK) {
1187 panic("pdc_pat_cell_module() call failed for LBA!\n");
1190 if (PAT_GET_ENTITY(pa_pdc_cell.mod_info) != PAT_ENTITY_LBA) {
1191 panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n");
1195 ** Inspect the resources PAT tells us about
1197 for (i = 0; i < pa_count; i++) {
1200 unsigned long start;
1201 unsigned long end; /* aka finish */
1205 p = (void *) &(pa_pdc_cell.mod[2+i*3]);
1206 io = (void *) &(io_pdc_cell.mod[2+i*3]);
1208 /* Convert the PAT range data to PCI "struct resource" */
1209 switch(p->type & 0xff) {
1211 lba_dev->hba.bus_num.start = p->start;
1212 lba_dev->hba.bus_num.end = p->end;
1216 /* used to fix up pre-initialized MEM BARs */
1217 if (!lba_dev->hba.lmmio_space.start) {
1218 sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO",
1219 (int) lba_dev->hba.bus_num.start);
1220 lba_dev->hba.lmmio_space_offset = p->start - io->start;
1221 r = &(lba_dev->hba.lmmio_space);
1222 r->name = lba_dev->hba.lmmio_name;
1223 } else if (!lba_dev->hba.elmmio_space.start) {
1224 sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO",
1225 (int) lba_dev->hba.bus_num.start);
1226 r = &(lba_dev->hba.elmmio_space);
1227 r->name = lba_dev->hba.elmmio_name;
1229 printk(KERN_WARNING MODULE_NAME
1230 " only supports 2 LMMIO resources!\n");
1234 r->start = p->start;
1236 r->flags = IORESOURCE_MEM;
1237 r->parent = r->sibling = r->child = NULL;
1241 /* MMIO space > 4GB phys addr; for 64-bit BAR */
1242 sprintf(lba_dev->hba.gmmio_name, "PCI%02x GMMIO",
1243 (int) lba_dev->hba.bus_num.start);
1244 r = &(lba_dev->hba.gmmio_space);
1245 r->name = lba_dev->hba.gmmio_name;
1246 r->start = p->start;
1248 r->flags = IORESOURCE_MEM;
1249 r->parent = r->sibling = r->child = NULL;
1253 printk(KERN_WARNING MODULE_NAME
1254 " range[%d] : ignoring NPIOP (0x%lx)\n",
1260 ** Postable I/O port space is per PCI host adapter.
1261 ** base of 64MB PIOP region
1263 lba_dev->iop_base = p->start;
1265 sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
1266 (int) lba_dev->hba.bus_num.start);
1267 r = &(lba_dev->hba.io_space);
1268 r->name = lba_dev->hba.io_name;
1269 r->start = HBA_PORT_BASE(lba_dev->hba.hba_num);
1270 r->end = r->start + HBA_PORT_SPACE_SIZE - 1;
1271 r->flags = IORESOURCE_IO;
1272 r->parent = r->sibling = r->child = NULL;
1276 printk(KERN_WARNING MODULE_NAME
1277 " range[%d] : unknown pat range type (0x%lx)\n",
1284 /* keep compiler from complaining about missing declarations */
1285 #define lba_pat_port_ops lba_astro_port_ops
1286 #define lba_pat_resources(pa_dev, lba_dev)
1287 #endif /* CONFIG_PARISC64 */
1290 extern void sba_distributed_lmmio(struct parisc_device *, struct resource *);
1291 extern void sba_directed_lmmio(struct parisc_device *, struct resource *);
1295 lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
1300 lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND;
1303 ** With "legacy" firmware, the lowest byte of FW_SCRATCH
1304 ** represents bus->secondary and the second byte represents
1305 ** bus->subsidiary (i.e. highest PPB programmed by firmware).
1306 ** PCI bus walk *should* end up with the same result.
1307 ** FIXME: But we don't have sanity checks in PCI or LBA.
1309 lba_num = READ_REG32(pa_dev->hpa + LBA_FW_SCRATCH);
1310 r = &(lba_dev->hba.bus_num);
1311 r->name = "LBA PCI Busses";
1312 r->start = lba_num & 0xff;
1313 r->end = (lba_num>>8) & 0xff;
1315 /* Set up local PCI Bus resources - we don't need them for
1316 ** Legacy boxes but it's nice to see in /proc/iomem.
1318 r = &(lba_dev->hba.lmmio_space);
1319 sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO",
1320 (int) lba_dev->hba.bus_num.start);
1321 r->name = lba_dev->hba.lmmio_name;
1324 /* We want the CPU -> IO routing of addresses.
1325 * The SBA BASE/MASK registers control CPU -> IO routing.
1326 * Ask SBA what is routed to this rope/LBA.
1328 sba_distributed_lmmio(pa_dev, r);
1331 * The LBA BASE/MASK registers control IO -> System routing.
1333 * The following code works but doesn't get us what we want.
1334 * Well, only because firmware (v5.0) on C3000 doesn't program
1335 * the LBA BASE/MASE registers to be the exact inverse of
1336 * the corresponding SBA registers. Other Astro/Pluto
1337 * based platform firmware may do it right.
1339 * Should someone want to mess with MSI, they may need to
1340 * reprogram LBA BASE/MASK registers. Thus preserve the code
1341 * below until MSI is known to work on C3000/A500/N4000/RP3440.
1343 * Using the code below, /proc/iomem shows:
1345 * f0000000-f0ffffff : PCI00 LMMIO
1346 * f05d0000-f05d0000 : lcd_data
1347 * f05d0008-f05d0008 : lcd_cmd
1348 * f1000000-f1ffffff : PCI01 LMMIO
1349 * f4000000-f4ffffff : PCI02 LMMIO
1350 * f4000000-f4001fff : sym53c8xx
1351 * f4002000-f4003fff : sym53c8xx
1352 * f4004000-f40043ff : sym53c8xx
1353 * f4005000-f40053ff : sym53c8xx
1354 * f4007000-f4007fff : ohci_hcd
1355 * f4008000-f40083ff : tulip
1356 * f6000000-f6ffffff : PCI03 LMMIO
1357 * f8000000-fbffffff : PCI00 ELMMIO
1358 * fa100000-fa4fffff : stifb mmio
1359 * fb000000-fb1fffff : stifb fb
1361 * But everything listed under PCI02 actually lives under PCI00.
1362 * This is clearly wrong.
1364 * Asking SBA how things are routed tells the correct story:
1365 * LMMIO_BASE/MASK/ROUTE f4000001 fc000000 00000000
1366 * DIR0_BASE/MASK/ROUTE fa000001 fe000000 00000006
1367 * DIR1_BASE/MASK/ROUTE f9000001 ff000000 00000004
1368 * DIR2_BASE/MASK/ROUTE f0000000 fc000000 00000000
1369 * DIR3_BASE/MASK/ROUTE f0000000 fc000000 00000000
1371 * Which looks like this in /proc/iomem:
1372 * f4000000-f47fffff : PCI00 LMMIO
1373 * f4000000-f4001fff : sym53c8xx
1374 * ...[deteled core devices - same as above]...
1375 * f4008000-f40083ff : tulip
1376 * f4800000-f4ffffff : PCI01 LMMIO
1377 * f6000000-f67fffff : PCI02 LMMIO
1378 * f7000000-f77fffff : PCI03 LMMIO
1379 * f9000000-f9ffffff : PCI02 ELMMIO
1380 * fa000000-fbffffff : PCI03 ELMMIO
1381 * fa100000-fa4fffff : stifb mmio
1382 * fb000000-fb1fffff : stifb fb
1384 * ie all Built-in core are under now correctly under PCI00.
1385 * The "PCI02 ELMMIO" directed range is for:
1386 * +-[02]---03.0 3Dfx Interactive, Inc. Voodoo 2
1390 r->start = (long) READ_REG32(pa_dev->hpa + LBA_LMMIO_BASE);
1392 unsigned long rsize;
1394 r->flags = IORESOURCE_MEM;
1395 /* mmio_mask also clears Enable bit */
1396 r->start &= mmio_mask;
1397 r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev), r->start);
1398 rsize = ~ READ_REG32(pa_dev->hpa + LBA_LMMIO_MASK);
1401 ** Each rope only gets part of the distributed range.
1402 ** Adjust "window" for this rope.
1404 rsize /= ROPES_PER_IOC;
1405 r->start += (rsize + 1) * LBA_NUM(pa_dev->hpa);
1406 r->end = r->start + rsize;
1408 r->end = r->start = 0; /* Not enabled. */
1413 ** "Directed" ranges are used when the "distributed range" isn't
1414 ** sufficient for all devices below a given LBA. Typically devices
1415 ** like graphics cards or X25 may need a directed range when the
1416 ** bus has multiple slots (ie multiple devices) or the device
1417 ** needs more than the typical 4 or 8MB a distributed range offers.
1419 ** The main reason for ignoring it now frigging complications.
1420 ** Directed ranges may overlap (and have precedence) over
1421 ** distributed ranges. Or a distributed range assigned to a unused
1422 ** rope may be used by a directed range on a different rope.
1423 ** Support for graphics devices may require fixing this
1424 ** since they may be assigned a directed range which overlaps
1425 ** an existing (but unused portion of) distributed range.
1427 r = &(lba_dev->hba.elmmio_space);
1428 sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO",
1429 (int) lba_dev->hba.bus_num.start);
1430 r->name = lba_dev->hba.elmmio_name;
1433 /* See comment which precedes call to sba_directed_lmmio() */
1434 sba_directed_lmmio(pa_dev, r);
1436 r->start = READ_REG32(pa_dev->hpa + LBA_ELMMIO_BASE);
1439 unsigned long rsize;
1440 r->flags = IORESOURCE_MEM;
1441 /* mmio_mask also clears Enable bit */
1442 r->start &= mmio_mask;
1443 r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev), r->start);
1444 rsize = READ_REG32(pa_dev->hpa + LBA_ELMMIO_MASK);
1445 r->end = r->start + ~rsize;
1449 r = &(lba_dev->hba.io_space);
1450 sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
1451 (int) lba_dev->hba.bus_num.start);
1452 r->name = lba_dev->hba.io_name;
1453 r->flags = IORESOURCE_IO;
1454 r->start = READ_REG32(pa_dev->hpa + LBA_IOS_BASE) & ~1L;
1455 r->end = r->start + (READ_REG32(pa_dev->hpa + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1));
1457 /* Virtualize the I/O Port space ranges */
1458 lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num);
1459 r->start |= lba_num;
1464 /**************************************************************************
1466 ** LBA initialization code (HW and SW)
1468 ** o identify LBA chip itself
1469 ** o initialize LBA chip modes (HardFail)
1470 ** o FIXME: initialize DMA hints for reasonable defaults
1471 ** o enable configuration functions
1472 ** o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked)
1474 **************************************************************************/
1477 lba_hw_init(struct lba_device *d)
1480 u32 bus_reset; /* PDC_PAT_BUG */
1483 printk(KERN_DEBUG "LBA %lx STAT_CTL %Lx ERROR_CFG %Lx STATUS %Lx DMA_CTL %Lx\n",
1485 READ_REG64(d->hba.base_addr + LBA_STAT_CTL),
1486 READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG),
1487 READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS),
1488 READ_REG64(d->hba.base_addr + LBA_DMA_CTL) );
1489 printk(KERN_DEBUG " ARB mask %Lx pri %Lx mode %Lx mtlt %Lx\n",
1490 READ_REG64(d->hba.base_addr + LBA_ARB_MASK),
1491 READ_REG64(d->hba.base_addr + LBA_ARB_PRI),
1492 READ_REG64(d->hba.base_addr + LBA_ARB_MODE),
1493 READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) );
1494 printk(KERN_DEBUG " HINT cfg 0x%Lx\n",
1495 READ_REG64(d->hba.base_addr + LBA_HINT_CFG));
1496 printk(KERN_DEBUG " HINT reg ");
1498 for (i=LBA_HINT_BASE; i< (14*8 + LBA_HINT_BASE); i+=8)
1499 printk(" %Lx", READ_REG64(d->hba.base_addr + i));
1502 #endif /* DEBUG_LBA_PAT */
1504 #ifdef CONFIG_PARISC64
1506 * FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support
1507 * Only N-Class and up can really make use of Get slot status.
1508 * maybe L-class too but I've never played with it there.
1512 /* PDC_PAT_BUG: exhibited in rev 40.48 on L2000 */
1513 bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1;
1515 printk(KERN_DEBUG "NOTICE: PCI bus reset still asserted! (clearing)\n");
1518 stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);
1519 if (stat & LBA_SMART_MODE) {
1520 printk(KERN_DEBUG "NOTICE: LBA in SMART mode! (cleared)\n");
1521 stat &= ~LBA_SMART_MODE;
1522 WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG);
1525 /* Set HF mode as the default (vs. -1 mode). */
1526 stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);
1527 WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
1530 ** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal
1531 ** if it's not already set. If we just cleared the PCI Bus Reset
1532 ** signal, wait a bit for the PCI devices to recover and setup.
1535 mdelay(pci_post_reset_delay);
1537 if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) {
1539 ** PDC_PAT_BUG: PDC rev 40.48 on L2000.
1540 ** B2000/C3600/J6000 also have this problem?
1542 ** Elroys with hot pluggable slots don't get configured
1543 ** correctly if the slot is empty. ARB_MASK is set to 0
1544 ** and we can't master transactions on the bus if it's
1545 ** not at least one. 0x3 enables elroy and first slot.
1547 printk(KERN_DEBUG "NOTICE: Enabling PCI Arbitration\n");
1548 WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK);
1552 ** FIXME: Hint registers are programmed with default hint
1553 ** values by firmware. Hints should be sane even if we
1554 ** can't reprogram them the way drivers want.
1562 lba_common_init(struct lba_device *lba_dev)
1564 pci_bios = &lba_bios_ops;
1565 pcibios_register_hba(HBA_DATA(lba_dev));
1566 spin_lock_init(&lba_dev->lba_lock);
1569 ** Set flags which depend on hw_rev
1571 if (!LBA_TR4PLUS(lba_dev)) {
1572 lba_dev->flags |= LBA_FLAG_NO_DMA_DURING_CFG;
1579 ** Determine if lba should claim this chip (return 0) or not (return 1).
1580 ** If so, initialize the chip and tell other partners in crime they
1584 lba_driver_probe(struct parisc_device *dev)
1586 struct lba_device *lba_dev;
1587 struct pci_bus *lba_bus;
1592 /* Read HW Rev First */
1593 func_class = READ_REG32(dev->hpa + LBA_FCLASS);
1595 if (IS_ELROY(dev)) {
1597 switch (func_class) {
1598 case 0: version = "TR1.0"; break;
1599 case 1: version = "TR2.0"; break;
1600 case 2: version = "TR2.1"; break;
1601 case 3: version = "TR2.2"; break;
1602 case 4: version = "TR3.0"; break;
1603 case 5: version = "TR4.0"; break;
1604 default: version = "TR4+";
1606 printk(KERN_INFO "%s version %s (0x%x) found at 0x%lx\n",
1607 MODULE_NAME, version, func_class & 0xf, dev->hpa);
1609 /* Just in case we find some prototypes... */
1610 } else if (IS_MERCURY(dev) || IS_QUICKSILVER(dev)) {
1612 version = kmalloc(6, GFP_KERNEL);
1613 sprintf(version,"TR%d.%d",(func_class >> 4),(func_class & 0xf));
1614 /* We could use one printk for both and have it outside,
1615 * but for the mask for func_class.
1617 printk(KERN_INFO "%s version %s (0x%x) found at 0x%lx\n",
1618 MODULE_NAME, version, func_class & 0xff, dev->hpa);
1621 if (func_class < 2) {
1622 printk(KERN_WARNING "Can't support LBA older than TR2.1"
1623 " - continuing under adversity.\n");
1627 ** Tell I/O SAPIC driver we have a IRQ handler/region.
1629 tmp_obj = iosapic_register(dev->hpa + LBA_IOSAPIC_BASE);
1631 /* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't
1632 ** have an IRT entry will get NULL back from iosapic code.
1635 lba_dev = kmalloc(sizeof(struct lba_device), GFP_KERNEL);
1636 if (NULL == lba_dev)
1638 printk(KERN_ERR "lba_init_chip - couldn't alloc lba_device\n");
1642 memset(lba_dev, 0, sizeof(struct lba_device));
1645 /* ---------- First : initialize data we already have --------- */
1648 ** Need hw_rev to adjust configuration space behavior.
1649 ** LBA_TR4PLUS macro uses hw_rev field.
1651 lba_dev->hw_rev = func_class;
1653 lba_dev->hba.base_addr = dev->hpa; /* faster access */
1654 lba_dev->hba.dev = dev;
1655 lba_dev->iosapic_obj = tmp_obj; /* save interrupt handle */
1656 lba_dev->hba.iommu = sba_get_iommu(dev); /* get iommu data */
1658 /* ------------ Second : initialize common stuff ---------- */
1659 lba_common_init(lba_dev);
1661 if (lba_hw_init(lba_dev))
1664 /* ---------- Third : setup I/O Port and MMIO resources --------- */
1667 /* PDC PAT firmware uses PIOP region of GMMIO space. */
1668 pci_port = &lba_pat_port_ops;
1669 /* Go ask PDC PAT what resources this LBA has */
1670 lba_pat_resources(dev, lba_dev);
1672 /* Sprockets PDC uses NPIOP region */
1673 pci_port = &lba_astro_port_ops;
1675 /* Poke the chip a bit for /proc output */
1676 lba_legacy_resources(dev, lba_dev);
1680 ** Tell PCI support another PCI bus was found.
1681 ** Walks PCI bus for us too.
1683 dev->dev.platform_data = lba_dev;
1684 lba_bus = lba_dev->hba.hba_bus =
1685 pci_scan_bus_parented(&dev->dev, lba_dev->hba.bus_num.start,
1686 IS_ELROY(dev) ? &lba_cfg_ops : &mercury_cfg_ops,
1689 /* This is in lieu of calling pci_assign_unassigned_resources() */
1691 /* assign resources to un-initialized devices */
1693 DBG_PAT("LBA pci_bus_size_bridges()\n");
1694 pci_bus_size_bridges(lba_bus);
1696 DBG_PAT("LBA pci_bus_assign_resources()\n");
1697 pci_bus_assign_resources(lba_bus);
1699 #ifdef DEBUG_LBA_PAT
1700 DBG_PAT("\nLBA PIOP resource tree\n");
1701 lba_dump_res(&lba_dev->hba.io_space, 2);
1702 DBG_PAT("\nLBA LMMIO resource tree\n");
1703 lba_dump_res(&lba_dev->hba.lmmio_space, 2);
1706 pci_enable_bridges(lba_bus);
1710 ** Once PCI register ops has walked the bus, access to config
1711 ** space is restricted. Avoids master aborts on config cycles.
1712 ** Early LBA revs go fatal on *any* master abort.
1714 if (!LBA_TR4PLUS(lba_dev)) {
1715 lba_dev->flags |= LBA_FLAG_SKIP_PROBE;
1718 /* Whew! Finally done! Tell services we got this one covered. */
1722 static struct parisc_device_id lba_tbl[] = {
1723 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, ELROY_HVERS, 0xa },
1724 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, MERCURY_HVERS, 0xa },
1725 { HPHW_BRIDGE, HVERSION_REV_ANY_ID, QUICKSILVER_HVERS, 0xa },
1729 static struct parisc_driver lba_driver = {
1730 .name = MODULE_NAME,
1731 .id_table = lba_tbl,
1732 .probe = lba_driver_probe,
1736 ** One time initialization to let the world know the LBA was found.
1737 ** Must be called exactly once before pci_init().
1739 void __init lba_init(void)
1741 register_parisc_driver(&lba_driver);
1745 ** Initialize the IBASE/IMASK registers for LBA (Elroy).
1746 ** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA).
1747 ** sba_iommu is responsible for locking (none needed at init time).
1750 lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask)
1752 unsigned long base_addr = lba->hpa;
1754 imask <<= 2; /* adjust for hints - 2 more bits */
1756 ASSERT((ibase & 0x003fffff) == 0);
1757 ASSERT((imask & 0x003fffff) == 0);
1759 DBG("%s() ibase 0x%x imask 0x%x\n", __FUNCTION__, ibase, imask);
1760 WRITE_REG32( imask, base_addr + LBA_IMASK);
1761 WRITE_REG32( ibase, base_addr + LBA_IBASE);