2 ** System Bus Adapter (SBA) I/O MMU manager
4 ** (c) Copyright 2000 Grant Grundler
5 ** (c) Copyright 2000 Hewlett-Packard Company
7 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
9 ** This program is free software; you can redistribute it and/or modify
10 ** it under the terms of the GNU General Public License as published by
11 ** the Free Software Foundation; either version 2 of the License, or
12 ** (at your option) any later version.
15 ** This module initializes the IOC (I/O Controller) found on B1000/C3000/
16 ** J5000/J7000/N-class/L-class machines and their successors.
18 ** FIXME: add DMA hint support programming in both sba and lba modules.
21 #include <linux/config.h>
22 #include <linux/types.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/slab.h>
26 #include <linux/init.h>
29 #include <linux/string.h>
30 #undef PCI_DEBUG /* for ASSERT */
31 #include <linux/pci.h>
34 #include <asm/byteorder.h>
36 #include <asm/dma.h> /* for DMA_CHUNK_SIZE */
38 #include <asm/hardware.h> /* for register_parisc_driver() stuff */
40 #include <linux/proc_fs.h>
41 #include <asm/runway.h> /* for proc_runway_root */
42 #include <asm/pdc.h> /* for PDC_MODEL_* */
43 #include <asm/parisc-device.h>
45 #define MODULE_NAME "SBA"
48 /* depends on proc fs support. But costs CPU performance */
49 #undef SBA_COLLECT_STATS
53 ** The number of debug flags is a clue - this code is fragile.
54 ** Don't even think about messing with it unless you have
55 ** plenty of 710's to sacrifice to the computer gods. :^)
59 #undef DEBUG_SBA_RUN_SG
60 #undef DEBUG_SBA_RESOURCE
61 #undef ASSERT_PDIR_SANITY
62 #undef DEBUG_LARGE_SG_ENTRIES
65 #define SBA_INLINE __inline__
68 #define DBG_INIT(x...) printk(x)
70 #define DBG_INIT(x...)
74 #define DBG_RUN(x...) printk(x)
79 #ifdef DEBUG_SBA_RUN_SG
80 #define DBG_RUN_SG(x...) printk(x)
82 #define DBG_RUN_SG(x...)
86 #ifdef DEBUG_SBA_RESOURCE
87 #define DBG_RES(x...) printk(x)
93 ** The number of pdir entries to "free" before issueing
94 ** a read to PCOM register to flush out PCOM writes.
95 ** Interacts with allocation granularity (ie 4 or 8 entries
96 ** allocated and free'd/purged at a time might make this
99 #define DELAYED_RESOURCE_CNT 16
101 #define DEFAULT_DMA_HINT_REG 0
103 #define ASTRO_RUNWAY_PORT 0x582
104 #define ASTRO_ROPES_PORT 0x780
106 #define IKE_MERCED_PORT 0x803
107 #define IKE_ROPES_PORT 0x781
109 #define REO_MERCED_PORT 0x804
110 #define REO_ROPES_PORT 0x782
112 #define REOG_MERCED_PORT 0x805
113 #define REOG_ROPES_PORT 0x783
115 #define SBA_FUNC_ID 0x0000 /* function id */
116 #define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
118 #define IS_ASTRO(id) \
119 (((id)->hversion == ASTRO_RUNWAY_PORT) || ((id)->hversion == ASTRO_ROPES_PORT))
122 (((id)->hversion == IKE_MERCED_PORT) || ((id)->hversion == IKE_ROPES_PORT))
124 #define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
126 #define ASTRO_IOC_OFFSET 0x20000
127 /* Ike's IOC's occupy functions 2 and 3 (not 0 and 1) */
128 #define IKE_IOC_OFFSET(p) ((p+2)*SBA_FUNC_SIZE)
130 #define IOC_CTRL 0x8 /* IOC_CTRL offset */
131 #define IOC_CTRL_TC (1 << 0) /* TOC Enable */
132 #define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */
133 #define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
134 #define IOC_CTRL_RM (1 << 8) /* Real Mode */
135 #define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
137 #define MAX_IOC 2 /* per Ike. Astro only has 1 */
141 ** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
142 ** Firmware programs this stuff. Don't touch it.
144 #define IOS_DIST_BASE 0x390
145 #define IOS_DIST_MASK 0x398
146 #define IOS_DIST_ROUTE 0x3A0
148 #define IOS_DIRECT_BASE 0x3C0
149 #define IOS_DIRECT_MASK 0x3C8
150 #define IOS_DIRECT_ROUTE 0x3D0
153 ** Offsets into I/O TLB (Function 2 and 3 on Ike)
155 #define ROPE0_CTL 0x200 /* "regbus pci0" */
156 #define ROPE1_CTL 0x208
157 #define ROPE2_CTL 0x210
158 #define ROPE3_CTL 0x218
159 #define ROPE4_CTL 0x220
160 #define ROPE5_CTL 0x228
161 #define ROPE6_CTL 0x230
162 #define ROPE7_CTL 0x238
164 #define HF_ENABLE 0x40
167 #define IOC_IBASE 0x300 /* IO TLB */
168 #define IOC_IMASK 0x308
169 #define IOC_PCOM 0x310
170 #define IOC_TCNFG 0x318
171 #define IOC_PDIR_BASE 0x320
173 #define IOC_IOVA_SPACE_BASE 0 /* IOVA ranges start at 0 */
176 ** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
177 ** It's safer (avoid memory corruption) to keep DMA page mappings
178 ** equivalently sized to VM PAGE_SIZE.
180 ** We really can't avoid generating a new mapping for each
181 ** page since the Virtual Coherence Index has to be generated
182 ** and updated for each page.
184 ** IOVP_SIZE could only be greater than PAGE_SIZE if we are
185 ** confident the drivers really only touch the next physical
186 ** page iff that driver instance owns it.
188 #define IOVP_SIZE PAGE_SIZE
189 #define IOVP_SHIFT PAGE_SHIFT
190 #define IOVP_MASK PAGE_MASK
192 #define SBA_PERF_CFG 0x708 /* Performance Counter stuff */
193 #define SBA_PERF_MASK1 0x718
194 #define SBA_PERF_MASK2 0x730
198 ** Offsets into PCI Performance Counters (functions 12 and 13)
199 ** Controlled by PERF registers in function 2 & 3 respectively.
201 #define SBA_PERF_CNT1 0x200
202 #define SBA_PERF_CNT2 0x208
203 #define SBA_PERF_CNT3 0x210
207 unsigned long ioc_hpa; /* I/O MMU base address */
208 char *res_map; /* resource map, bit == pdir entry */
209 u64 *pdir_base; /* physical base address */
211 unsigned long *res_hint; /* next avail IOVP - circular search */
213 unsigned long hint_mask_pdir; /* bits used for DMA hints */
214 unsigned int res_bitshift; /* from the LEFT! */
215 unsigned int res_size; /* size of resource map in bytes */
216 unsigned int hint_shift_pdir;
217 #if DELAYED_RESOURCE_CNT > 0
219 struct sba_dma_pair {
222 } saved[DELAYED_RESOURCE_CNT];
225 #ifdef SBA_COLLECT_STATS
226 #define SBA_SEARCH_SAMPLE 0x100
227 unsigned long avg_search[SBA_SEARCH_SAMPLE];
228 unsigned long avg_idx; /* current index into avg_search */
229 unsigned long used_pages;
230 unsigned long msingle_calls;
231 unsigned long msingle_pages;
232 unsigned long msg_calls;
233 unsigned long msg_pages;
234 unsigned long usingle_calls;
235 unsigned long usingle_pages;
236 unsigned long usg_calls;
237 unsigned long usg_pages;
240 /* STUFF We don't need in performance path */
241 unsigned int pdir_size; /* in bytes, determined by IOV Space size */
242 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
243 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
247 struct sba_device *next; /* list of SBA's in system */
248 struct parisc_device *dev; /* dev found in bus walk */
249 struct parisc_device_id *iodc; /* data about dev from firmware */
251 unsigned long sba_hpa; /* base address */
253 unsigned int flags; /* state/functionality enabled */
254 unsigned int hw_rev; /* HW revision of chip */
256 unsigned int num_ioc; /* number of on-board IOC's */
257 struct ioc ioc[MAX_IOC];
261 static struct sba_device *sba_list;
263 static unsigned long ioc_needs_fdc = 0;
265 /* Ratio of Host MEM to IOV Space size */
266 static unsigned long sba_mem_ratio = 8;
268 /* global count of IOMMUs in the system */
269 static unsigned int global_ioc_cnt = 0;
271 /* PA8700 (Piranha 2.2) bug workaround */
272 static unsigned long piranha_bad_128k = 0;
274 /* Looks nice and keeps the compiler happy */
275 #define SBA_DEV(d) ((struct sba_device *) (d))
278 #define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1))
281 /************************************
282 ** SBA register read and write support
284 ** BE WARNED: register writes are posted.
285 ** (ie follow writes which must reach HW with a read)
287 ** Superdome (in particular, REO) allows only 64-bit CSR accesses.
289 #define READ_REG32(addr) le32_to_cpu(__raw_readl(addr))
290 #define READ_REG64(addr) le64_to_cpu(__raw_readq(addr))
291 #define WRITE_REG32(val, addr) __raw_writel(cpu_to_le32(val), addr)
292 #define WRITE_REG64(val, addr) __raw_writeq(cpu_to_le64(val), addr)
295 #define READ_REG(addr) READ_REG64(addr)
296 #define WRITE_REG(value, addr) WRITE_REG64(value, addr)
298 #define READ_REG(addr) READ_REG32(addr)
299 #define WRITE_REG(value, addr) WRITE_REG32(value, addr)
302 #ifdef DEBUG_SBA_INIT
304 /* NOTE: When __LP64__ isn't defined, READ_REG64() is two 32-bit reads */
307 * sba_dump_ranges - debugging only - print ranges assigned to this IOA
308 * @hpa: base address of the sba
310 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
311 * IO Adapter (aka Bus Converter).
314 sba_dump_ranges(unsigned long hpa)
316 DBG_INIT("SBA at 0x%lx\n", hpa);
317 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
318 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
319 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
321 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
322 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
323 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
327 * sba_dump_tlb - debugging only - print IOMMU operating parameters
328 * @hpa: base address of the IOMMU
330 * Print the size/location of the IO MMU PDIR.
333 sba_dump_tlb(unsigned long hpa)
335 DBG_INIT("IO TLB at 0x%lx\n", hpa);
336 DBG_INIT("IOC_IBASE : %Lx\n", READ_REG64(hpa+IOC_IBASE));
337 DBG_INIT("IOC_IMASK : %Lx\n", READ_REG64(hpa+IOC_IMASK));
338 DBG_INIT("IOC_TCNFG : %Lx\n", READ_REG64(hpa+IOC_TCNFG));
339 DBG_INIT("IOC_PDIR_BASE: %Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
345 #ifdef ASSERT_PDIR_SANITY
348 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
349 * @ioc: IO MMU structure which owns the pdir we are interested in.
350 * @msg: text to print ont the output line.
353 * Print one entry of the IO MMU PDIR in human readable form.
356 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
358 /* start printing from lowest pde in rval */
359 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
360 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
363 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
365 rptr, pide & (BITS_PER_LONG - 1), *rptr);
368 while (rcnt < BITS_PER_LONG) {
369 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
370 (rcnt == (pide & (BITS_PER_LONG - 1)))
376 printk(KERN_DEBUG "%s", msg);
381 * sba_check_pdir - debugging only - consistency checker
382 * @ioc: IO MMU structure which owns the pdir we are interested in.
383 * @msg: text to print ont the output line.
385 * Verify the resource map and pdir state is consistent
388 sba_check_pdir(struct ioc *ioc, char *msg)
390 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
391 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */
392 u64 *pptr = ioc->pdir_base; /* pdir ptr */
395 while (rptr < rptr_end) {
397 int rcnt = 32; /* number of bits we might check */
400 /* Get last byte and highest bit from that */
401 u32 pde = ((u32) (((char *)pptr)[7])) << 24;
402 if ((rval ^ pde) & 0x80000000)
405 ** BUMMER! -- res_map != pdir --
406 ** Dump rval and matching pdir entries
408 sba_dump_pdir_entry(ioc, msg, pide);
412 rval <<= 1; /* try the next bit */
416 rptr++; /* look at next word of res_map */
418 /* It'd be nice if we always got here :^) */
424 * sba_dump_sg - debugging only - print Scatter-Gather list
425 * @ioc: IO MMU structure which owns the pdir we are interested in.
426 * @startsg: head of the SG list
427 * @nents: number of entries in SG list
429 * print the SG list so we can verify it's correct by hand.
432 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
434 while (nents-- > 0) {
435 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
437 (unsigned long) sg_dma_address(startsg),
439 sg_virt_addr(startsg), startsg->length);
444 #endif /* ASSERT_PDIR_SANITY */
449 /**************************************************************
451 * I/O Pdir Resource Management
453 * Bits set in the resource map are in use.
454 * Each bit can represent a number of pages.
455 * LSbs represent lower addresses (IOVA's).
457 ***************************************************************/
458 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
460 /* Convert from IOVP to IOVA and vice versa. */
461 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset) | ((hint_reg)<<(ioc->hint_shift_pdir)))
462 #define SBA_IOVP(ioc,iova) ((iova) & ioc->hint_mask_pdir)
464 /* FIXME : review these macros to verify correctness and usage */
465 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
466 #define MKIOVP(dma_hint,pide) (dma_addr_t)((long)(dma_hint) | ((long)(pide) << IOVP_SHIFT))
467 #define MKIOVA(iovp,offset) (dma_addr_t)((long)iovp | (long)offset)
469 #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
470 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
474 * sba_search_bitmap - find free space in IO PDIR resource bitmap
475 * @ioc: IO MMU structure which owns the pdir we are interested in.
476 * @bits_wanted: number of entries we need.
478 * Find consecutive free bits in resource bitmap.
479 * Each bit represents one entry in the IO Pdir.
480 * Cool perf optimization: search for log2(size) bits at a time.
482 static SBA_INLINE unsigned long
483 sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted)
485 unsigned long *res_ptr = ioc->res_hint;
486 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
487 unsigned long pide = ~0UL;
489 ASSERT(((unsigned long) ioc->res_hint & (sizeof(unsigned long) - 1UL)) == 0);
490 ASSERT(res_ptr < res_end);
491 if (bits_wanted > (BITS_PER_LONG/2)) {
492 /* Search word at a time - no mask needed */
493 for(; res_ptr < res_end; ++res_ptr) {
495 *res_ptr = RESMAP_MASK(bits_wanted);
496 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
497 pide <<= 3; /* convert to bit address */
501 /* point to the next word on next pass */
503 ioc->res_bitshift = 0;
506 ** Search the resource bit map on well-aligned values.
507 ** "o" is the alignment.
508 ** We need the alignment to invalidate I/O TLB using
509 ** SBA HW features in the unmap path.
511 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
512 uint bitshiftcnt = ROUNDUP(ioc->res_bitshift, o);
515 if (bitshiftcnt >= BITS_PER_LONG) {
519 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
521 DBG_RES("%s() o %ld %p", __FUNCTION__, o, res_ptr);
522 while(res_ptr < res_end)
524 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
526 if(0 == ((*res_ptr) & mask)) {
527 *res_ptr |= mask; /* mark resources busy! */
528 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
529 pide <<= 3; /* convert to bit address */
536 mask = RESMAP_MASK(bits_wanted);
541 /* look in the same word on the next pass */
542 ioc->res_bitshift = bitshiftcnt + bits_wanted;
546 if (res_end <= res_ptr) {
547 ioc->res_hint = (unsigned long *) ioc->res_map;
548 ioc->res_bitshift = 0;
550 ioc->res_hint = res_ptr;
557 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
558 * @ioc: IO MMU structure which owns the pdir we are interested in.
559 * @size: number of bytes to create a mapping for
561 * Given a size, find consecutive unmarked and then mark those bits in the
565 sba_alloc_range(struct ioc *ioc, size_t size)
567 unsigned int pages_needed = size >> IOVP_SHIFT;
568 #ifdef SBA_COLLECT_STATS
569 unsigned long cr_start = mfctl(16);
573 ASSERT(pages_needed);
574 ASSERT((pages_needed * IOVP_SIZE) <= DMA_CHUNK_SIZE);
575 ASSERT(pages_needed <= BITS_PER_LONG);
576 ASSERT(0 == (size & ~IOVP_MASK));
579 ** "seek and ye shall find"...praying never hurts either...
580 ** ggg sacrifices another 710 to the computer gods.
583 pide = sba_search_bitmap(ioc, pages_needed);
584 if (pide >= (ioc->res_size << 3)) {
585 pide = sba_search_bitmap(ioc, pages_needed);
586 if (pide >= (ioc->res_size << 3))
587 panic("%s: I/O MMU @ %lx is out of mapping resources\n",
588 __FILE__, ioc->ioc_hpa);
591 #ifdef ASSERT_PDIR_SANITY
592 /* verify the first enable bit is clear */
593 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
594 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
598 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
599 __FUNCTION__, size, pages_needed, pide,
600 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
603 #ifdef SBA_COLLECT_STATS
605 unsigned long cr_end = mfctl(16);
606 unsigned long tmp = cr_end - cr_start;
607 /* check for roll over */
608 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
610 ioc->avg_search[ioc->avg_idx++] = cr_start;
611 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
613 ioc->used_pages += pages_needed;
621 * sba_free_range - unmark bits in IO PDIR resource bitmap
622 * @ioc: IO MMU structure which owns the pdir we are interested in.
623 * @iova: IO virtual address which was previously allocated.
624 * @size: number of bytes to create a mapping for
626 * clear bits in the ioc's resource map
628 static SBA_INLINE void
629 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
631 unsigned long iovp = SBA_IOVP(ioc, iova);
632 unsigned int pide = PDIR_INDEX(iovp);
633 unsigned int ridx = pide >> 3; /* convert bit to byte address */
634 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
636 int bits_not_wanted = size >> IOVP_SHIFT;
638 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
639 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
641 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
642 __FUNCTION__, (uint) iova, size,
643 bits_not_wanted, m, pide, res_ptr, *res_ptr);
645 #ifdef SBA_COLLECT_STATS
646 ioc->used_pages -= bits_not_wanted;
650 ASSERT(bits_not_wanted);
651 ASSERT((bits_not_wanted * IOVP_SIZE) <= DMA_CHUNK_SIZE);
652 ASSERT(bits_not_wanted <= BITS_PER_LONG);
653 ASSERT((*res_ptr & m) == m); /* verify same bits are set */
658 /**************************************************************
660 * "Dynamic DMA Mapping" support (aka "Coherent I/O")
662 ***************************************************************/
664 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
667 typedef unsigned long space_t;
668 #define KERNEL_SPACE 0
671 * sba_io_pdir_entry - fill in one IO PDIR entry
672 * @pdir_ptr: pointer to IO PDIR entry
673 * @sid: process Space ID
674 * @vba: Virtual CPU address of buffer to map
676 * SBA Mapping Routine
678 * Given a virtual address (vba, arg2) and space id, (sid, arg1)
679 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
680 * pdir_ptr (arg0). Each IO Pdir entry consists of 8 bytes as
681 * shown below (MSB == bit 0):
684 * +-+---------------------+----------------------------------+----+--------+
685 * |V| U | PPN[43:12] | U | VI |
686 * +-+---------------------+----------------------------------+----+--------+
690 * PPN == Physical Page Number
691 * VI == Virtual Index (aka Coherent Index)
693 * The physical address fields are filled with the results of the LPA
694 * instruction. The virtual index field is filled with the results of
695 * of the LCI (Load Coherence Index) instruction. The 8 bits used for
696 * the virtual index are bits 12:19 of the value returned by LCI.
698 * We need to pre-swap the bytes since PCX-W is Big Endian.
703 sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
706 u64 pa; /* physical address */
707 register unsigned ci; /* coherent index */
709 /* We currently only support kernel addresses.
710 * fdc instr below will need to reload sr1 with KERNEL_SPACE
711 * once we try to support direct DMA to user space.
713 ASSERT(sid == KERNEL_SPACE);
715 pa = virt_to_phys(vba);
716 pa &= ~4095ULL; /* clear out offset bits */
719 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
720 pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */
722 pa |= 0x8000000000000000ULL; /* set "valid" bit */
723 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
726 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
727 * (bit #61, big endian), we have to flush and sync every time
728 * IO-PDIR is changed in Ike/Astro.
731 asm volatile("fdc 0(%%sr1,%0)\n\tsync" : : "r" (pdir_ptr));
737 * sba_mark_invalid - invalidate one or more IO PDIR entries
738 * @ioc: IO MMU structure which owns the pdir we are interested in.
739 * @iova: IO Virtual Address mapped earlier
740 * @byte_cnt: number of bytes this mapping covers.
742 * Marking the IO PDIR entry(ies) as Invalid and invalidate
743 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
744 * is to purge stale entries in the IO TLB when unmapping entries.
746 * The PCOM register supports purging of multiple pages, with a minium
747 * of 1 page and a maximum of 2GB. Hardware requires the address be
748 * aligned to the size of the range being purged. The size of the range
749 * must be a power of 2. The "Cool perf optimization" in the
750 * allocation routine helps keep that true.
752 static SBA_INLINE void
753 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
755 u32 iovp = (u32) SBA_IOVP(ioc,iova);
757 /* Even though this is a big-endian machine, the entries
758 ** in the iopdir are little endian. That's why we clear the byte
759 ** at +7 instead of at +0.
761 int off = PDIR_INDEX(iovp)*sizeof(u64)+7;
763 /* Must be non-zero and rounded up */
764 ASSERT(byte_cnt > 0);
765 ASSERT(0 == (byte_cnt & ~IOVP_MASK));
767 #ifdef ASSERT_PDIR_SANITY
768 /* Assert first pdir entry is set */
769 if (0x80 != (((u8 *) ioc->pdir_base)[off])) {
770 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
774 if (byte_cnt <= IOVP_SIZE)
776 ASSERT( off < ioc->pdir_size);
778 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
781 ** clear I/O PDIR entry "valid" bit
782 ** Do NOT clear the rest - save it for debugging.
783 ** We should only clear bits that have previously
786 ((u8 *)(ioc->pdir_base))[off] = 0;
788 u32 t = get_order(byte_cnt) + PAGE_SHIFT;
791 ASSERT(t <= 31); /* 2GB! Max value of "size" field */
794 /* verify this pdir entry is enabled */
795 ASSERT(0x80 == (((u8 *) ioc->pdir_base)[off] & 0x80));
796 /* clear I/O Pdir entry "valid" bit first */
797 ((u8 *)(ioc->pdir_base))[off] = 0;
799 byte_cnt -= IOVP_SIZE;
800 } while (byte_cnt > 0);
803 WRITE_REG(iovp, ioc->ioc_hpa+IOC_PCOM);
807 * sba_dma_supported - PCI driver can query DMA support
808 * @dev: instance of PCI owned by the driver that's asking
809 * @mask: number of address bits this PCI device can handle
811 * See Documentation/DMA-mapping.txt
814 sba_dma_supported( struct device *dev, u64 mask)
817 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
822 /* only support 32-bit PCI devices - no DAC support (yet) */
823 return((int) (mask == 0xffffffffUL));
828 * sba_map_single - map one buffer and return IOVA for DMA
829 * @dev: instance of PCI owned by the driver that's asking.
830 * @addr: driver buffer to map.
831 * @size: number of bytes to map in driver buffer.
832 * @direction: R/W or both.
834 * See Documentation/DMA-mapping.txt
837 sba_map_single(struct device *dev, void *addr, size_t size,
838 enum dma_data_direction direction)
848 ASSERT(size <= DMA_CHUNK_SIZE);
853 /* save offset bits */
854 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
856 /* round up to nearest IOVP_SIZE */
857 size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
859 spin_lock_irqsave(&ioc->res_lock, flags);
860 #ifdef ASSERT_PDIR_SANITY
861 sba_check_pdir(ioc,"Check before sba_map_single()");
864 #ifdef SBA_COLLECT_STATS
865 ioc->msingle_calls++;
866 ioc->msingle_pages += size >> IOVP_SHIFT;
868 pide = sba_alloc_range(ioc, size);
869 iovp = (dma_addr_t) pide << IOVP_SHIFT;
871 DBG_RUN("%s() 0x%p -> 0x%lx",
872 __FUNCTION__, addr, (long) iovp | offset);
874 pdir_start = &(ioc->pdir_base[pide]);
877 ASSERT(((u8 *)pdir_start)[7] == 0); /* verify availability */
878 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
880 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
882 (u8) (((u8 *) pdir_start)[7]),
883 (u8) (((u8 *) pdir_start)[6]),
884 (u8) (((u8 *) pdir_start)[5]),
885 (u8) (((u8 *) pdir_start)[4]),
886 (u8) (((u8 *) pdir_start)[3]),
887 (u8) (((u8 *) pdir_start)[2]),
888 (u8) (((u8 *) pdir_start)[1]),
889 (u8) (((u8 *) pdir_start)[0])
896 /* form complete address */
897 #ifdef ASSERT_PDIR_SANITY
898 sba_check_pdir(ioc,"Check after sba_map_single()");
900 spin_unlock_irqrestore(&ioc->res_lock, flags);
901 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
906 * sba_unmap_single - unmap one IOVA and free resources
907 * @dev: instance of PCI owned by the driver that's asking.
908 * @iova: IOVA of driver buffer previously mapped.
909 * @size: number of bytes mapped in driver buffer.
910 * @direction: R/W or both.
912 * See Documentation/DMA-mapping.txt
915 sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size,
916 enum dma_data_direction direction)
919 #if DELAYED_RESOURCE_CNT > 0
920 struct sba_dma_pair *d;
928 offset = iova & ~IOVP_MASK;
930 DBG_RUN("%s() iovp 0x%lx/%x\n",
931 __FUNCTION__, (long) iova, size);
933 iova ^= offset; /* clear offset bits */
935 size = ROUNDUP(size, IOVP_SIZE);
937 spin_lock_irqsave(&ioc->res_lock, flags);
939 #ifdef SBA_COLLECT_STATS
940 ioc->usingle_calls++;
941 ioc->usingle_pages += size >> IOVP_SHIFT;
944 #if DELAYED_RESOURCE_CNT > 0
945 d = &(ioc->saved[ioc->saved_cnt]);
948 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
949 int cnt = ioc->saved_cnt;
951 sba_mark_invalid(ioc, d->iova, d->size);
952 sba_free_range(ioc, d->iova, d->size);
956 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
958 #else /* DELAYED_RESOURCE_CNT == 0 */
959 sba_mark_invalid(ioc, iova, size);
960 sba_free_range(ioc, iova, size);
961 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
962 #endif /* DELAYED_RESOURCE_CNT == 0 */
963 spin_unlock_irqrestore(&ioc->res_lock, flags);
965 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
966 ** For Astro based systems this isn't a big deal WRT performance.
967 ** As long as 2.4 kernels copyin/copyout data from/to userspace,
968 ** we don't need the syncdma. The issue here is I/O MMU cachelines
969 ** are *not* coherent in all cases. May be hwrev dependent.
970 ** Need to investigate more.
971 asm volatile("syncdma");
977 * sba_alloc_consistent - allocate/map shared mem for DMA
978 * @hwdev: instance of PCI owned by the driver that's asking.
979 * @size: number of bytes mapped in driver buffer.
980 * @dma_handle: IOVA of new buffer.
982 * See Documentation/DMA-mapping.txt
984 static void *sba_alloc_consistent(struct device *hwdev, size_t size,
985 dma_addr_t *dma_handle, int gfp)
990 /* only support PCI */
995 ret = (void *) __get_free_pages(gfp, get_order(size));
998 memset(ret, 0, size);
999 *dma_handle = sba_map_single(hwdev, ret, size, 0);
1007 * sba_free_consistent - free/unmap shared mem for DMA
1008 * @hwdev: instance of PCI owned by the driver that's asking.
1009 * @size: number of bytes mapped in driver buffer.
1010 * @vaddr: virtual address IOVA of "consistent" buffer.
1011 * @dma_handler: IO virtual address of "consistent" buffer.
1013 * See Documentation/DMA-mapping.txt
1016 sba_free_consistent(struct device *hwdev, size_t size, void *vaddr,
1017 dma_addr_t dma_handle)
1019 sba_unmap_single(hwdev, dma_handle, size, 0);
1020 free_pages((unsigned long) vaddr, get_order(size));
1025 ** Since 0 is a valid pdir_base index value, can't use that
1026 ** to determine if a value is valid or not. Use a flag to indicate
1027 ** the SG list entry contains a valid pdir index.
1029 #define PIDE_FLAG 0x80000000UL
1031 #ifdef SBA_COLLECT_STATS
1032 #define IOMMU_MAP_STATS
1034 #include "iommu-helpers.h"
1036 #ifdef DEBUG_LARGE_SG_ENTRIES
1037 int dump_run_sg = 0;
1042 * sba_map_sg - map Scatter/Gather list
1043 * @dev: instance of PCI owned by the driver that's asking.
1044 * @sglist: array of buffer/length pairs
1045 * @nents: number of entries in list
1046 * @direction: R/W or both.
1048 * See Documentation/DMA-mapping.txt
1051 sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
1052 enum dma_data_direction direction)
1055 int coalesced, filled = 0;
1056 unsigned long flags;
1058 DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);
1063 /* Fast path single entry scatterlists. */
1065 sg_dma_address(sglist) = sba_map_single(dev,
1066 (void *)sg_virt_addr(sglist),
1067 sglist->length, direction);
1068 sg_dma_len(sglist) = sglist->length;
1072 spin_lock_irqsave(&ioc->res_lock, flags);
1074 #ifdef ASSERT_PDIR_SANITY
1075 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
1077 sba_dump_sg(ioc, sglist, nents);
1078 panic("Check before sba_map_sg()");
1082 #ifdef SBA_COLLECT_STATS
1087 ** First coalesce the chunks and allocate I/O pdir space
1089 ** If this is one DMA stream, we can properly map using the
1090 ** correct virtual address associated with each DMA page.
1091 ** w/o this association, we wouldn't have coherent DMA!
1092 ** Access to the virtual address is what forces a two pass algorithm.
1094 coalesced = iommu_coalesce_chunks(ioc, sglist, nents, sba_alloc_range);
1097 ** Program the I/O Pdir
1099 ** map the virtual addresses to the I/O Pdir
1100 ** o dma_address will contain the pdir index
1101 ** o dma_len will contain the number of bytes to map
1102 ** o address contains the virtual address.
1104 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
1106 #ifdef ASSERT_PDIR_SANITY
1107 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
1109 sba_dump_sg(ioc, sglist, nents);
1110 panic("Check after sba_map_sg()\n");
1114 spin_unlock_irqrestore(&ioc->res_lock, flags);
1116 ASSERT(coalesced == filled);
1117 DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);
1124 * sba_unmap_sg - unmap Scatter/Gather list
1125 * @dev: instance of PCI owned by the driver that's asking.
1126 * @sglist: array of buffer/length pairs
1127 * @nents: number of entries in list
1128 * @direction: R/W or both.
1130 * See Documentation/DMA-mapping.txt
1133 sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
1134 enum dma_data_direction direction)
1137 #ifdef ASSERT_PDIR_SANITY
1138 unsigned long flags;
1141 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1142 __FUNCTION__, nents, sg_virt_addr(sglist), sglist->length);
1147 #ifdef SBA_COLLECT_STATS
1151 #ifdef ASSERT_PDIR_SANITY
1152 spin_lock_irqsave(&ioc->res_lock, flags);
1153 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1154 spin_unlock_irqrestore(&ioc->res_lock, flags);
1157 while (sg_dma_len(sglist) && nents--) {
1159 sba_unmap_single(dev, sg_dma_address(sglist), sg_dma_len(sglist), direction);
1160 #ifdef SBA_COLLECT_STATS
1161 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
1162 ioc->usingle_calls--; /* kluge since call is unmap_sg() */
1167 DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents);
1169 #ifdef ASSERT_PDIR_SANITY
1170 spin_lock_irqsave(&ioc->res_lock, flags);
1171 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1172 spin_unlock_irqrestore(&ioc->res_lock, flags);
1177 static struct hppa_dma_ops sba_ops = {
1178 .dma_supported = sba_dma_supported,
1179 .alloc_consistent = sba_alloc_consistent,
1180 .alloc_noncoherent = sba_alloc_consistent,
1181 .free_consistent = sba_free_consistent,
1182 .map_single = sba_map_single,
1183 .unmap_single = sba_unmap_single,
1184 .map_sg = sba_map_sg,
1185 .unmap_sg = sba_unmap_sg,
1186 .dma_sync_single_for_cpu = NULL,
1187 .dma_sync_single_for_device = NULL,
1188 .dma_sync_sg_for_cpu = NULL,
1189 .dma_sync_sg_for_device = NULL,
1193 /**************************************************************************
1195 ** SBA PAT PDC support
1197 ** o call pdc_pat_cell_module()
1198 ** o store ranges in PCI "resource" structures
1200 **************************************************************************/
1203 sba_get_pat_resources(struct sba_device *sba_dev)
1207 ** TODO/REVISIT/FIXME: support for directed ranges requires calls to
1208 ** PAT PDC to program the SBA/LBA directed range registers...this
1209 ** burden may fall on the LBA code since it directly supports the
1210 ** PCI subsystem. It's not clear yet. - ggg
1212 PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
1214 PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
1215 Tells where the dvi bits are located in the address.
1216 PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
1222 /**************************************************************
1224 * Initialization and claim
1226 ***************************************************************/
1227 #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
1228 #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
1230 sba_alloc_pdir(unsigned int pdir_size)
1232 unsigned long pdir_base;
1233 unsigned long pdir_order = get_order(pdir_size);
1235 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
1236 if (NULL == (void *) pdir_base)
1237 panic("sba_ioc_init() could not allocate I/O Page Table\n");
1239 /* If this is not PA8700 (PCX-W2)
1240 ** OR newer than ver 2.2
1241 ** OR in a system that doesn't need VINDEX bits from SBA,
1243 ** then we aren't exposed to the HW bug.
1245 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
1246 || (boot_cpu_data.pdc.versions > 0x202)
1247 || (boot_cpu_data.pdc.capabilities & 0x08L) )
1248 return (void *) pdir_base;
1251 * PA8700 (PCX-W2, aka piranha) silent data corruption fix
1253 * An interaction between PA8700 CPU (Ver 2.2 or older) and
1254 * Ike/Astro can cause silent data corruption. This is only
1255 * a problem if the I/O PDIR is located in memory such that
1256 * (little-endian) bits 17 and 18 are on and bit 20 is off.
1258 * Since the max IO Pdir size is 2MB, by cleverly allocating the
1259 * right physical address, we can either avoid (IOPDIR <= 1MB)
1260 * or minimize (2MB IO Pdir) the problem if we restrict the
1261 * IO Pdir to a maximum size of 2MB-128K (1902K).
1263 * Because we always allocate 2^N sized IO pdirs, either of the
1264 * "bad" regions will be the last 128K if at all. That's easy
1268 if (pdir_order <= (19-12)) {
1269 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
1270 /* allocate a new one on 512k alignment */
1271 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
1272 /* release original */
1273 free_pages(pdir_base, pdir_order);
1275 pdir_base = new_pdir;
1277 /* release excess */
1278 while (pdir_order < (19-12)) {
1279 new_pdir += pdir_size;
1280 free_pages(new_pdir, pdir_order);
1288 ** Needs to be aligned on an "odd" 1MB boundary.
1290 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */
1292 /* release original */
1293 free_pages( pdir_base, pdir_order);
1295 /* release first 1MB */
1296 free_pages(new_pdir, 20-12);
1298 pdir_base = new_pdir + 1024*1024;
1300 if (pdir_order > (20-12)) {
1304 ** Flag tells init_bitmap() to mark bad 128k as used
1305 ** and to reduce the size by 128k.
1307 piranha_bad_128k = 1;
1309 new_pdir += 3*1024*1024;
1310 /* release last 1MB */
1311 free_pages(new_pdir, 20-12);
1313 /* release unusable 128KB */
1314 free_pages(new_pdir - 128*1024 , 17-12);
1316 pdir_size -= 128*1024;
1320 memset((void *) pdir_base, 0, pdir_size);
1321 return (void *) pdir_base;
1326 sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1328 /* lba_set_iregs() is in arch/parisc/kernel/lba_pci.c */
1329 extern void lba_set_iregs(struct parisc_device *, u32, u32);
1331 u32 iova_space_size, iova_space_mask;
1332 int pdir_size, iov_order;
1333 unsigned long physmem;
1334 struct parisc_device *lba;
1337 ** Determine IOVA Space size from memory size.
1339 ** Ideally, PCI drivers would register the maximum number
1340 ** of DMA they can have outstanding for each device they
1341 ** own. Next best thing would be to guess how much DMA
1342 ** can be outstanding based on PCI Class/sub-class. Both
1343 ** methods still require some "extra" to support PCI
1344 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
1346 ** While we have 32-bits "IOVA" space, top two 2 bits are used
1347 ** for DMA hints - ergo only 30 bits max.
1350 physmem = num_physpages << PAGE_SHIFT;
1351 iova_space_size = (u32) (physmem/(sba_mem_ratio*global_ioc_cnt));
1353 /* limit IOVA space size to 1MB-1GB */
1354 if (iova_space_size < 1024*1024) {
1355 iova_space_size = 1024*1024;
1358 else if (iova_space_size > 512*1024*1024) {
1359 iova_space_size = 512*1024*1024;
1364 ** iova space must be log2() in size.
1365 ** thus, pdir/res_map will also be log2().
1366 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
1368 iov_order = get_order(iova_space_size >> (IOVP_SHIFT-PAGE_SHIFT));
1369 ASSERT(iov_order <= (30 - IOVP_SHIFT)); /* iova_space_size <= 1GB */
1370 ASSERT(iov_order >= (20 - IOVP_SHIFT)); /* iova_space_size >= 1MB */
1371 iova_space_size = 1 << (iov_order + IOVP_SHIFT);
1373 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
1375 ASSERT(pdir_size < 4*1024*1024); /* max pdir size == 2MB */
1377 /* Verify it's a power of two */
1378 ASSERT((1 << get_order(pdir_size)) == (pdir_size >> PAGE_SHIFT));
1380 DBG_INIT("%s() hpa 0x%lx mem %dMB IOV %dMB (%d bits) PDIR size 0x%0x\n",
1381 __FUNCTION__, ioc->ioc_hpa, (int) (physmem>>20),
1382 iova_space_size>>20, iov_order + PAGE_SHIFT, pdir_size);
1384 /* FIXME : DMA HINTs not used */
1385 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1386 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1388 ioc->pdir_base = sba_alloc_pdir(pdir_size);
1390 DBG_INIT("%s() pdir %p size %x hint_shift_pdir %x hint_mask_pdir %lx\n",
1391 __FUNCTION__, ioc->pdir_base, pdir_size,
1392 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1394 ASSERT((((unsigned long) ioc->pdir_base) & PAGE_MASK) == (unsigned long) ioc->pdir_base);
1395 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1397 /* build IMASK for IOC and Elroy */
1398 iova_space_mask = 0xffffffff;
1399 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1402 ** On C3000 w/512MB mem, HP-UX 10.20 reports:
1403 ** ibase=0, imask=0xFE000000, size=0x2000000.
1405 ioc->ibase = IOC_IOVA_SPACE_BASE | 1; /* bit 0 == enable bit */
1406 ioc->imask = iova_space_mask; /* save it */
1408 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
1409 __FUNCTION__, ioc->ibase, ioc->imask);
1412 ** FIXME: Hint registers are programmed with default hint
1413 ** values during boot, so hints should be sane even if we
1414 ** can't reprogram them the way drivers want.
1418 ** setup Elroy IBASE/IMASK registers as well.
1420 for (lba = sba->child; lba; lba = lba->sibling) {
1421 int rope_num = (lba->hpa >> 13) & 0xf;
1422 if (rope_num >> 3 == ioc_num)
1423 lba_set_iregs(lba, ioc->ibase, ioc->imask);
1427 ** Program the IOC's ibase and enable IOVA translation
1429 WRITE_REG(ioc->ibase, ioc->ioc_hpa+IOC_IBASE);
1430 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
1432 /* Set I/O PDIR Page size to 4K */
1433 WRITE_REG(0, ioc->ioc_hpa+IOC_TCNFG);
1436 ** Clear I/O TLB of any possible entries.
1437 ** (Yes. This is a bit paranoid...but so what)
1439 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
1441 DBG_INIT("%s() DONE\n", __FUNCTION__);
1446 /**************************************************************************
1448 ** SBA initialization code (HW and SW)
1450 ** o identify SBA chip itself
1451 ** o initialize SBA chip modes (HardFail)
1452 ** o initialize SBA chip modes (HardFail)
1453 ** o FIXME: initialize DMA hints for reasonable defaults
1455 **************************************************************************/
1458 sba_hw_init(struct sba_device *sba_dev)
1464 if (!is_pdc_pat()) {
1465 /* Shutdown the USB controller on Astro-based workstations.
1466 ** Once we reprogram the IOMMU, the next DMA performed by
1467 ** USB will HPMC the box.
1469 pdc_io_reset_devices();
1472 ** XXX May need something more sophisticated to deal
1473 ** with DMA from LAN. Maybe use page zero boot device
1474 ** as a handle to talk to PDC about which device to
1475 ** shutdown. This also needs to work for is_pdc_pat().
1479 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
1480 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
1481 __FUNCTION__, sba_dev->sba_hpa, ioc_ctl);
1482 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
1483 ioc_ctl |= IOC_CTRL_TC; /* Astro: firmware enables this */
1485 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
1487 #ifdef DEBUG_SBA_INIT
1488 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
1489 DBG_INIT(" 0x%Lx\n", ioc_ctl);
1492 if (IS_ASTRO(sba_dev->iodc)) {
1493 /* PAT_PDC (L-class) also reports the same goofy base */
1494 sba_dev->ioc[0].ioc_hpa = ASTRO_IOC_OFFSET;
1497 sba_dev->ioc[0].ioc_hpa = sba_dev->ioc[1].ioc_hpa = 0;
1501 sba_dev->num_ioc = num_ioc;
1502 for (i = 0; i < num_ioc; i++) {
1503 sba_dev->ioc[i].ioc_hpa += sba_dev->sba_hpa + IKE_IOC_OFFSET(i);
1506 ** Make sure the box crashes if we get any errors on a rope.
1508 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE0_CTL);
1509 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE1_CTL);
1510 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE2_CTL);
1511 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE3_CTL);
1512 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE4_CTL);
1513 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE5_CTL);
1514 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE6_CTL);
1515 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1517 /* flush out the writes */
1518 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1520 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
1525 sba_common_init(struct sba_device *sba_dev)
1529 /* add this one to the head of the list (order doesn't matter)
1530 ** This will be useful for debugging - especially if we get coredumps
1532 sba_dev->next = sba_list;
1535 for(i=0; i< sba_dev->num_ioc; i++) {
1537 #ifdef DEBUG_DMB_TRAP
1538 extern void iterate_pages(unsigned long , unsigned long ,
1539 void (*)(pte_t * , unsigned long),
1541 void set_data_memory_break(pte_t * , unsigned long);
1543 /* resource map size dictated by pdir_size */
1544 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */
1546 /* Second part of PIRANHA BUG */
1547 if (piranha_bad_128k) {
1548 res_size -= (128*1024)/sizeof(u64);
1551 res_size >>= 3; /* convert bit count to byte count */
1552 DBG_INIT("%s() res_size 0x%x\n",
1553 __FUNCTION__, res_size);
1555 sba_dev->ioc[i].res_size = res_size;
1556 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
1558 #ifdef DEBUG_DMB_TRAP
1559 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1560 set_data_memory_break, 0);
1563 if (NULL == sba_dev->ioc[i].res_map)
1565 panic("%s:%s() could not allocate resource map\n",
1566 __FILE__, __FUNCTION__ );
1569 memset(sba_dev->ioc[i].res_map, 0, res_size);
1570 /* next available IOVP - circular search */
1571 sba_dev->ioc[i].res_hint = (unsigned long *)
1572 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
1574 #ifdef ASSERT_PDIR_SANITY
1575 /* Mark first bit busy - ie no IOVA 0 */
1576 sba_dev->ioc[i].res_map[0] = 0x80;
1577 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
1580 /* Third (and last) part of PIRANHA BUG */
1581 if (piranha_bad_128k) {
1582 /* region from +1408K to +1536 is un-usable. */
1584 int idx_start = (1408*1024/sizeof(u64)) >> 3;
1585 int idx_end = (1536*1024/sizeof(u64)) >> 3;
1586 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
1587 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
1589 /* mark that part of the io pdir busy */
1590 while (p_start < p_end)
1595 #ifdef DEBUG_DMB_TRAP
1596 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1597 set_data_memory_break, 0);
1598 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
1599 set_data_memory_break, 0);
1602 DBG_INIT("%s() %d res_map %x %p\n",
1603 __FUNCTION__, i, res_size, sba_dev->ioc[i].res_map);
1606 sba_dev->sba_lock = SPIN_LOCK_UNLOCKED;
1607 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
1609 #ifdef DEBUG_SBA_INIT
1611 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
1612 * (bit #61, big endian), we have to flush and sync every time
1613 * IO-PDIR is changed in Ike/Astro.
1615 if (boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC) {
1616 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
1618 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
1623 #ifdef CONFIG_PROC_FS
1624 static int sba_proc_info(char *buf, char **start, off_t offset, int len)
1626 struct sba_device *sba_dev = sba_list;
1627 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1628 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
1629 #ifdef SBA_COLLECT_STATS
1630 unsigned long i = 0, avg = 0, min, max;
1633 sprintf(buf, "%s rev %d.%d\n",
1635 (sba_dev->hw_rev & 0x7) + 1,
1636 (sba_dev->hw_rev & 0x18) >> 3
1638 sprintf(buf, "%sIO PDIR size : %d bytes (%d entries)\n",
1640 (int) ((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
1643 sprintf(buf, "%sResource bitmap : %d bytes (%d pages)\n",
1644 buf, ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
1646 #ifdef SBA_COLLECT_STATS
1647 sprintf(buf, "%sIO PDIR entries : %ld free %ld used (%d%%)\n", buf,
1648 total_pages - ioc->used_pages, ioc->used_pages,
1649 (int) (ioc->used_pages * 100 / total_pages));
1651 min = max = ioc->avg_search[0];
1652 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1653 avg += ioc->avg_search[i];
1654 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1655 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1657 avg /= SBA_SEARCH_SAMPLE;
1658 sprintf(buf, "%s Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1659 buf, min, avg, max);
1661 sprintf(buf, "%spci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
1662 buf, ioc->msingle_calls, ioc->msingle_pages,
1663 (int) ((ioc->msingle_pages * 1000)/ioc->msingle_calls));
1665 /* KLUGE - unmap_sg calls unmap_single for each mapped page */
1666 min = ioc->usingle_calls;
1667 max = ioc->usingle_pages - ioc->usg_pages;
1668 sprintf(buf, "%spci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
1670 (int) ((max * 1000)/min));
1672 sprintf(buf, "%spci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1673 buf, ioc->msg_calls, ioc->msg_pages,
1674 (int) ((ioc->msg_pages * 1000)/ioc->msg_calls));
1676 sprintf(buf, "%spci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1677 buf, ioc->usg_calls, ioc->usg_pages,
1678 (int) ((ioc->usg_pages * 1000)/ioc->usg_calls));
1685 /* XXX too much output - exceeds 4k limit and needs to be re-written */
1687 sba_resource_map(char *buf, char **start, off_t offset, int len)
1689 struct sba_device *sba_dev = sba_list;
1690 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Mutli-IOC suppoer! */
1691 unsigned int *res_ptr = (unsigned int *)ioc->res_map;
1695 for(i = 0; i < (ioc->res_size / sizeof(unsigned int)); ++i, ++res_ptr) {
1698 sprintf(buf, "%s %08x", buf, *res_ptr);
1705 #endif /* CONFIG_PROC_FS */
1707 static struct parisc_device_id sba_tbl[] = {
1708 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
1709 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
1710 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
1711 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
1712 /* These two entries commented out because we don't find them in a
1713 * buswalk yet. If/when we do, they would cause us to think we had
1714 * many more SBAs then we really do.
1715 * { HPHW_BCPORT, HVERSION_REV_ANY_ID, ASTRO_ROPES_PORT, 0xc },
1716 * { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_ROPES_PORT, 0xc },
1721 int sba_driver_callback(struct parisc_device *);
1723 static struct parisc_driver sba_driver = {
1724 .name = MODULE_NAME,
1725 .id_table = sba_tbl,
1726 .probe = sba_driver_callback,
1730 ** Determine if lba should claim this chip (return 0) or not (return 1).
1731 ** If so, initialize the chip and tell other partners in crime they
1735 sba_driver_callback(struct parisc_device *dev)
1737 struct sba_device *sba_dev;
1742 #ifdef DEBUG_SBA_INIT
1743 sba_dump_ranges(dev->hpa);
1746 /* Read HW Rev First */
1747 func_class = READ_REG(dev->hpa + SBA_FCLASS);
1749 if (IS_ASTRO(&dev->id)) {
1750 unsigned long fclass;
1751 static char astro_rev[]="Astro ?.?";
1753 /* Astro is broken...Read HW Rev First */
1754 fclass = READ_REG(dev->hpa);
1756 astro_rev[6] = '1' + (char) (fclass & 0x7);
1757 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
1758 version = astro_rev;
1760 } else if (IS_IKE(&dev->id)) {
1761 static char ike_rev[]="Ike rev ?";
1763 ike_rev[8] = '0' + (char) (func_class & 0xff);
1766 static char reo_rev[]="REO rev ?";
1768 reo_rev[8] = '0' + (char) (func_class & 0xff);
1772 if (!global_ioc_cnt) {
1773 global_ioc_cnt = count_parisc_driver(&sba_driver);
1775 /* Only Astro has one IOC per SBA */
1776 if (!IS_ASTRO(&dev->id))
1777 global_ioc_cnt *= 2;
1780 printk(KERN_INFO "%s found %s at 0x%lx\n",
1781 MODULE_NAME, version, dev->hpa);
1783 #ifdef DEBUG_SBA_INIT
1784 sba_dump_tlb(dev->hpa);
1787 sba_dev = kmalloc(sizeof(struct sba_device), GFP_KERNEL);
1788 if (NULL == sba_dev) {
1789 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
1793 dev->sysdata = (void *) sba_dev;
1794 memset(sba_dev, 0, sizeof(struct sba_device));
1796 for(i=0; i<MAX_IOC; i++)
1797 spin_lock_init(&(sba_dev->ioc[i].res_lock));
1800 sba_dev->hw_rev = func_class;
1801 sba_dev->iodc = &dev->id;
1802 sba_dev->name = dev->name;
1803 sba_dev->sba_hpa = dev->hpa; /* faster access */
1805 sba_get_pat_resources(sba_dev);
1806 sba_hw_init(sba_dev);
1807 sba_common_init(sba_dev);
1809 hppa_dma_ops = &sba_ops;
1811 #ifdef CONFIG_PROC_FS
1812 if (IS_ASTRO(&dev->id)) {
1813 create_proc_info_entry("Astro", 0, proc_runway_root, sba_proc_info);
1814 } else if (IS_IKE(&dev->id)) {
1815 create_proc_info_entry("Ike", 0, proc_runway_root, sba_proc_info);
1817 create_proc_info_entry("Reo", 0, proc_runway_root, sba_proc_info);
1820 create_proc_info_entry("bitmap", 0, proc_runway_root, sba_resource_map);
1823 parisc_vmerge_boundary = IOVP_SIZE;
1824 parisc_vmerge_max_size = IOVP_SIZE * BITS_PER_LONG;
1830 ** One time initialization to let the world know the SBA was found.
1831 ** This is the only routine which is NOT static.
1832 ** Must be called exactly once before pci_init().
1834 void __init sba_init(void)
1836 register_parisc_driver(&sba_driver);
1841 * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
1842 * @dev: The parisc device.
1844 * This function searches through the registerd IOMMU's and returns the
1845 * appropriate IOMMU data for the given parisc PCI controller.
1847 void * sba_get_iommu(struct parisc_device *pci_hba)
1849 struct sba_device *sba = (struct sba_device *) pci_hba->parent->sysdata;
1850 char t = pci_hba->parent->id.hw_type;
1851 int iocnum = (pci_hba->hw_path >> 3); /* rope # */
1853 if ((t!=HPHW_IOA) && (t!=HPHW_BCPORT))
1856 return &(sba->ioc[iocnum]);