1 /* Low-level parallel-port routines for 8255-based PC-style hardware.
3 * Authors: Phil Blundell <Philip.Blundell@pobox.com>
4 * Tim Waugh <tim@cyberelk.demon.co.uk>
5 * Jose Renau <renau@acm.org>
6 * David Campbell <campbell@torque.net>
9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12 * DMA support - Bert De Jonghe <bert@sophis.be>
13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
15 * Various hacks, Fred Barnes, 04/2001
16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
19 /* This driver should work with any hardware that is broadly compatible
20 * with that in the IBM PC. This applies to the majority of integrated
21 * I/O chipsets that are commonly available. The expected register
28 * In addition, there are some optional registers:
32 * base+0x400 ECP config A
33 * base+0x401 ECP config B
34 * base+0x402 ECP control
36 * All registers are 8 bits wide and read/write. If your hardware differs
37 * only in register addresses (eg because your registers are on 32-bit
38 * word boundaries) then you can alter the constants in parport_pc.h to
41 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
42 * but rather will start at port->base_hi.
45 #include <linux/config.h>
46 #include <linux/module.h>
47 #include <linux/init.h>
48 #include <linux/sched.h>
49 #include <linux/delay.h>
50 #include <linux/errno.h>
51 #include <linux/interrupt.h>
52 #include <linux/ioport.h>
53 #include <linux/kernel.h>
54 #include <linux/slab.h>
55 #include <linux/pci.h>
56 #include <linux/pnp.h>
57 #include <linux/sysctl.h>
61 #include <asm/uaccess.h>
63 #include <linux/parport.h>
64 #include <linux/parport_pc.h>
65 #include <asm/parport.h>
67 #define PARPORT_PC_MAX_PORTS PARPORT_MAX
78 #define ECR_MODE_MASK 0xe0
79 #define ECR_WRITE(p,v) frob_econtrol((p),0xff,(v))
84 #define DPRINTK printk
86 #define DPRINTK(stuff...)
91 static struct superio_struct { /* For Super-IO chips autodetection */
95 } superios[NR_SUPERIOS] __devinitdata = { {0,},};
97 static int user_specified;
98 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
99 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
100 static int verbose_probing;
102 static int pci_registered_parport;
103 static int pnp_registered_parport;
105 /* frob_control, but for ECR */
106 static void frob_econtrol (struct parport *pb, unsigned char m,
109 unsigned char ectr = 0;
112 ectr = inb (ECONTROL (pb));
114 DPRINTK (KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
115 m, v, ectr, (ectr & ~m) ^ v);
117 outb ((ectr & ~m) ^ v, ECONTROL (pb));
120 static __inline__ void frob_set_mode (struct parport *p, int mode)
122 frob_econtrol (p, ECR_MODE_MASK, mode << 5);
125 #ifdef CONFIG_PARPORT_PC_FIFO
126 /* Safely change the mode bits in the ECR
129 -EBUSY: Could not drain FIFO in some finite amount of time,
132 static int change_mode(struct parport *p, int m)
134 const struct parport_pc_private *priv = p->physport->private_data;
138 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n",m);
141 printk (KERN_DEBUG "change_mode: but there's no ECR!\n");
145 /* Bits <7:5> contain the mode. */
146 oecr = inb (ECONTROL (p));
147 mode = (oecr >> 5) & 0x7;
148 if (mode == m) return 0;
150 if (mode >= 2 && !(priv->ctr & 0x20)) {
151 /* This mode resets the FIFO, so we may
152 * have to wait for it to drain first. */
153 unsigned long expire = jiffies + p->physport->cad->timeout;
156 case ECR_PPF: /* Parallel Port FIFO mode */
157 case ECR_ECP: /* ECP Parallel Port mode */
158 /* Busy wait for 200us */
159 for (counter = 0; counter < 40; counter++) {
160 if (inb (ECONTROL (p)) & 0x01)
162 if (signal_pending (current)) break;
167 while (!(inb (ECONTROL (p)) & 0x01)) {
168 if (time_after_eq (jiffies, expire))
169 /* The FIFO is stuck. */
171 __set_current_state (TASK_INTERRUPTIBLE);
172 schedule_timeout ((HZ + 99) / 100);
173 if (signal_pending (current))
179 if (mode >= 2 && m >= 2) {
180 /* We have to go through mode 001 */
182 oecr |= ECR_PS2 << 5;
193 #ifdef CONFIG_PARPORT_1284
194 /* Find FIFO lossage; FIFO is reset */
195 static int get_fifo_residue (struct parport *p)
199 const struct parport_pc_private *priv = p->physport->private_data;
201 /* Adjust for the contents of the FIFO. */
202 for (residue = priv->fifo_depth; ; residue--) {
203 if (inb (ECONTROL (p)) & 0x2)
210 printk (KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name,
213 /* Reset the FIFO. */
214 frob_set_mode (p, ECR_PS2);
216 /* Now change to config mode and clean up. FIXME */
217 frob_set_mode (p, ECR_CNF);
218 cnfga = inb (CONFIGA (p));
219 printk (KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga);
221 if (!(cnfga & (1<<2))) {
222 printk (KERN_DEBUG "%s: Accounting for extra byte\n", p->name);
226 /* Don't care about partial PWords until support is added for
227 * PWord != 1 byte. */
229 /* Back to PS2 mode. */
230 frob_set_mode (p, ECR_PS2);
232 DPRINTK (KERN_DEBUG "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n", inb (ECONTROL (p)));
235 #endif /* IEEE 1284 support */
236 #endif /* FIFO support */
239 * Clear TIMEOUT BIT in EPP MODE
241 * This is also used in SPP detection.
243 static int clear_epp_timeout(struct parport *pb)
247 if (!(parport_pc_read_status(pb) & 0x01))
250 /* To clear timeout some chips require double read */
251 parport_pc_read_status(pb);
252 r = parport_pc_read_status(pb);
253 outb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */
254 outb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */
255 r = parport_pc_read_status(pb);
263 * Most of these aren't static because they may be used by the
264 * parport_xxx_yyy macros. extern __inline__ versions of several
265 * of these are in parport_pc.h.
268 static irqreturn_t parport_pc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
270 parport_generic_irq(irq, (struct parport *) dev_id, regs);
271 /* FIXME! Was it really ours? */
275 void parport_pc_init_state(struct pardevice *dev, struct parport_state *s)
279 dev->port->irq != PARPORT_IRQ_NONE)
283 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
287 void parport_pc_save_state(struct parport *p, struct parport_state *s)
289 const struct parport_pc_private *priv = p->physport->private_data;
290 s->u.pc.ctr = priv->ctr;
292 s->u.pc.ecr = inb (ECONTROL (p));
295 void parport_pc_restore_state(struct parport *p, struct parport_state *s)
297 struct parport_pc_private *priv = p->physport->private_data;
298 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
299 outb (c, CONTROL (p));
302 ECR_WRITE (p, s->u.pc.ecr);
305 #ifdef CONFIG_PARPORT_1284
306 static size_t parport_pc_epp_read_data (struct parport *port, void *buf,
307 size_t length, int flags)
311 if (flags & PARPORT_W91284PIC) {
312 unsigned char status;
313 size_t left = length;
315 /* use knowledge about data lines..:
316 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
317 * pError is 1 if there are 16 bytes in the Warp's FIFO
319 status = inb (STATUS (port));
321 while (!(status & 0x08) && (got < length)) {
322 if ((left >= 16) && (status & 0x20) && !(status & 0x08)) {
323 /* can grab 16 bytes from warp fifo */
324 if (!((long)buf & 0x03)) {
325 insl (EPPDATA (port), buf, 4);
327 insb (EPPDATA (port), buf, 16);
333 /* grab single byte from the warp fifo */
334 *((char *)buf) = inb (EPPDATA (port));
339 status = inb (STATUS (port));
341 /* EPP timeout should never occur... */
342 printk (KERN_DEBUG "%s: EPP timeout occurred while talking to "
343 "w91284pic (should not have done)\n", port->name);
344 clear_epp_timeout (port);
349 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
350 if (!(((long)buf | length) & 0x03)) {
351 insl (EPPDATA (port), buf, (length >> 2));
353 insb (EPPDATA (port), buf, length);
355 if (inb (STATUS (port)) & 0x01) {
356 clear_epp_timeout (port);
361 for (; got < length; got++) {
362 *((char*)buf) = inb (EPPDATA(port));
364 if (inb (STATUS (port)) & 0x01) {
366 clear_epp_timeout (port);
374 static size_t parport_pc_epp_write_data (struct parport *port, const void *buf,
375 size_t length, int flags)
379 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
380 if (!(((long)buf | length) & 0x03)) {
381 outsl (EPPDATA (port), buf, (length >> 2));
383 outsb (EPPDATA (port), buf, length);
385 if (inb (STATUS (port)) & 0x01) {
386 clear_epp_timeout (port);
391 for (; written < length; written++) {
392 outb (*((char*)buf), EPPDATA(port));
394 if (inb (STATUS(port)) & 0x01) {
395 clear_epp_timeout (port);
403 static size_t parport_pc_epp_read_addr (struct parport *port, void *buf,
404 size_t length, int flags)
408 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
409 insb (EPPADDR (port), buf, length);
410 if (inb (STATUS (port)) & 0x01) {
411 clear_epp_timeout (port);
416 for (; got < length; got++) {
417 *((char*)buf) = inb (EPPADDR (port));
419 if (inb (STATUS (port)) & 0x01) {
420 clear_epp_timeout (port);
428 static size_t parport_pc_epp_write_addr (struct parport *port,
429 const void *buf, size_t length,
434 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
435 outsb (EPPADDR (port), buf, length);
436 if (inb (STATUS (port)) & 0x01) {
437 clear_epp_timeout (port);
442 for (; written < length; written++) {
443 outb (*((char*)buf), EPPADDR (port));
445 if (inb (STATUS (port)) & 0x01) {
446 clear_epp_timeout (port);
454 static size_t parport_pc_ecpepp_read_data (struct parport *port, void *buf,
455 size_t length, int flags)
459 frob_set_mode (port, ECR_EPP);
460 parport_pc_data_reverse (port);
461 parport_pc_write_control (port, 0x4);
462 got = parport_pc_epp_read_data (port, buf, length, flags);
463 frob_set_mode (port, ECR_PS2);
468 static size_t parport_pc_ecpepp_write_data (struct parport *port,
469 const void *buf, size_t length,
474 frob_set_mode (port, ECR_EPP);
475 parport_pc_write_control (port, 0x4);
476 parport_pc_data_forward (port);
477 written = parport_pc_epp_write_data (port, buf, length, flags);
478 frob_set_mode (port, ECR_PS2);
483 static size_t parport_pc_ecpepp_read_addr (struct parport *port, void *buf,
484 size_t length, int flags)
488 frob_set_mode (port, ECR_EPP);
489 parport_pc_data_reverse (port);
490 parport_pc_write_control (port, 0x4);
491 got = parport_pc_epp_read_addr (port, buf, length, flags);
492 frob_set_mode (port, ECR_PS2);
497 static size_t parport_pc_ecpepp_write_addr (struct parport *port,
498 const void *buf, size_t length,
503 frob_set_mode (port, ECR_EPP);
504 parport_pc_write_control (port, 0x4);
505 parport_pc_data_forward (port);
506 written = parport_pc_epp_write_addr (port, buf, length, flags);
507 frob_set_mode (port, ECR_PS2);
511 #endif /* IEEE 1284 support */
513 #ifdef CONFIG_PARPORT_PC_FIFO
514 static size_t parport_pc_fifo_write_block_pio (struct parport *port,
515 const void *buf, size_t length)
518 const unsigned char *bufp = buf;
519 size_t left = length;
520 unsigned long expire = jiffies + port->physport->cad->timeout;
521 const int fifo = FIFO (port);
522 int poll_for = 8; /* 80 usecs */
523 const struct parport_pc_private *priv = port->physport->private_data;
524 const int fifo_depth = priv->fifo_depth;
526 port = port->physport;
528 /* We don't want to be interrupted every character. */
529 parport_pc_disable_irq (port);
530 /* set nErrIntrEn and serviceIntr */
531 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
534 parport_pc_data_forward (port); /* Must be in PS2 mode */
538 unsigned char ecrval = inb (ECONTROL (port));
541 if (need_resched() && time_before (jiffies, expire))
542 /* Can't yield the port. */
545 /* Anyone else waiting for the port? */
546 if (port->waithead) {
547 printk (KERN_DEBUG "Somebody wants the port\n");
552 /* FIFO is full. Wait for interrupt. */
554 /* Clear serviceIntr */
555 ECR_WRITE (port, ecrval & ~(1<<2));
557 ret = parport_wait_event (port, HZ);
560 if (!time_before (jiffies, expire)) {
562 printk (KERN_DEBUG "FIFO write timed out\n");
565 ecrval = inb (ECONTROL (port));
566 if (!(ecrval & (1<<2))) {
567 if (need_resched() &&
568 time_before (jiffies, expire))
577 /* Can't fail now. */
578 expire = jiffies + port->cad->timeout;
581 if (signal_pending (current))
585 /* FIFO is empty. Blast it full. */
586 const int n = left < fifo_depth ? left : fifo_depth;
587 outsb (fifo, bufp, n);
591 /* Adjust the poll time. */
592 if (i < (poll_for - 2)) poll_for--;
594 } else if (i++ < poll_for) {
596 ecrval = inb (ECONTROL (port));
600 /* Half-full (call me an optimist) */
606 dump_parport_state ("leave fifo_write_block_pio", port);
607 return length - left;
610 static size_t parport_pc_fifo_write_block_dma (struct parport *port,
611 const void *buf, size_t length)
614 unsigned long dmaflag;
615 size_t left = length;
616 const struct parport_pc_private *priv = port->physport->private_data;
617 dma_addr_t dma_addr, dma_handle;
618 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
619 unsigned long start = (unsigned long) buf;
620 unsigned long end = (unsigned long) buf + length - 1;
622 dump_parport_state ("enter fifo_write_block_dma", port);
623 if (end < MAX_DMA_ADDRESS) {
624 /* If it would cross a 64k boundary, cap it at the end. */
625 if ((start ^ end) & ~0xffffUL)
626 maxlen = 0x10000 - (start & 0xffff);
628 dma_addr = dma_handle = pci_map_single(priv->dev, (void *)buf, length,
631 /* above 16 MB we use a bounce buffer as ISA-DMA is not possible */
632 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
633 dma_addr = priv->dma_handle;
637 port = port->physport;
639 /* We don't want to be interrupted every character. */
640 parport_pc_disable_irq (port);
641 /* set nErrIntrEn and serviceIntr */
642 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
645 parport_pc_data_forward (port); /* Must be in PS2 mode */
648 unsigned long expire = jiffies + port->physport->cad->timeout;
655 if (!dma_handle) /* bounce buffer ! */
656 memcpy(priv->dma_buf, buf, count);
658 dmaflag = claim_dma_lock();
659 disable_dma(port->dma);
660 clear_dma_ff(port->dma);
661 set_dma_mode(port->dma, DMA_MODE_WRITE);
662 set_dma_addr(port->dma, dma_addr);
663 set_dma_count(port->dma, count);
666 frob_econtrol (port, 1<<3, 1<<3);
668 /* Clear serviceIntr */
669 frob_econtrol (port, 1<<2, 0);
671 enable_dma(port->dma);
672 release_dma_lock(dmaflag);
674 /* assume DMA will be successful */
677 if (dma_handle) dma_addr += count;
679 /* Wait for interrupt. */
681 ret = parport_wait_event (port, HZ);
684 if (!time_before (jiffies, expire)) {
686 printk (KERN_DEBUG "DMA write timed out\n");
689 /* Is serviceIntr set? */
690 if (!(inb (ECONTROL (port)) & (1<<2))) {
696 dmaflag = claim_dma_lock();
697 disable_dma(port->dma);
698 clear_dma_ff(port->dma);
699 count = get_dma_residue(port->dma);
700 release_dma_lock(dmaflag);
702 cond_resched(); /* Can't yield the port. */
704 /* Anyone else waiting for the port? */
705 if (port->waithead) {
706 printk (KERN_DEBUG "Somebody wants the port\n");
710 /* update for possible DMA residue ! */
713 if (dma_handle) dma_addr -= count;
716 /* Maybe got here through break, so adjust for DMA residue! */
717 dmaflag = claim_dma_lock();
718 disable_dma(port->dma);
719 clear_dma_ff(port->dma);
720 left += get_dma_residue(port->dma);
721 release_dma_lock(dmaflag);
723 /* Turn off DMA mode */
724 frob_econtrol (port, 1<<3, 0);
727 pci_unmap_single(priv->dev, dma_handle, length, PCI_DMA_TODEVICE);
729 dump_parport_state ("leave fifo_write_block_dma", port);
730 return length - left;
733 /* Parallel Port FIFO mode (ECP chipsets) */
734 size_t parport_pc_compat_write_block_pio (struct parport *port,
735 const void *buf, size_t length,
740 unsigned long expire;
741 const struct parport_pc_private *priv = port->physport->private_data;
743 /* Special case: a timeout of zero means we cannot call schedule().
744 * Also if O_NONBLOCK is set then use the default implementation. */
745 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
746 return parport_ieee1284_write_compat (port, buf,
749 /* Set up parallel port FIFO mode.*/
750 parport_pc_data_forward (port); /* Must be in PS2 mode */
751 parport_pc_frob_control (port, PARPORT_CONTROL_STROBE, 0);
752 r = change_mode (port, ECR_PPF); /* Parallel port FIFO */
753 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", port->name);
755 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
757 /* Write the data to the FIFO. */
758 if (port->dma != PARPORT_DMA_NONE)
759 written = parport_pc_fifo_write_block_dma (port, buf, length);
761 written = parport_pc_fifo_write_block_pio (port, buf, length);
764 /* For some hardware we don't want to touch the mode until
765 * the FIFO is empty, so allow 4 seconds for each position
768 expire = jiffies + (priv->fifo_depth * HZ * 4);
770 /* Wait for the FIFO to empty */
771 r = change_mode (port, ECR_PS2);
775 } while (time_before (jiffies, expire));
778 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
780 /* Prevent further data transfer. */
781 frob_set_mode (port, ECR_TST);
783 /* Adjust for the contents of the FIFO. */
784 for (written -= priv->fifo_depth; ; written++) {
785 if (inb (ECONTROL (port)) & 0x2) {
789 outb (0, FIFO (port));
792 /* Reset the FIFO and return to PS2 mode. */
793 frob_set_mode (port, ECR_PS2);
796 r = parport_wait_peripheral (port,
798 PARPORT_STATUS_BUSY);
801 "%s: BUSY timeout (%d) in compat_write_block_pio\n",
804 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
810 #ifdef CONFIG_PARPORT_1284
811 size_t parport_pc_ecp_write_block_pio (struct parport *port,
812 const void *buf, size_t length,
817 unsigned long expire;
818 const struct parport_pc_private *priv = port->physport->private_data;
820 /* Special case: a timeout of zero means we cannot call schedule().
821 * Also if O_NONBLOCK is set then use the default implementation. */
822 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
823 return parport_ieee1284_ecp_write_data (port, buf,
826 /* Switch to forward mode if necessary. */
827 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
828 /* Event 47: Set nInit high. */
829 parport_frob_control (port,
831 | PARPORT_CONTROL_AUTOFD,
833 | PARPORT_CONTROL_AUTOFD);
835 /* Event 49: PError goes high. */
836 r = parport_wait_peripheral (port,
837 PARPORT_STATUS_PAPEROUT,
838 PARPORT_STATUS_PAPEROUT);
840 printk (KERN_DEBUG "%s: PError timeout (%d) "
841 "in ecp_write_block_pio\n", port->name, r);
845 /* Set up ECP parallel port mode.*/
846 parport_pc_data_forward (port); /* Must be in PS2 mode */
847 parport_pc_frob_control (port,
848 PARPORT_CONTROL_STROBE |
849 PARPORT_CONTROL_AUTOFD,
851 r = change_mode (port, ECR_ECP); /* ECP FIFO */
852 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
853 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
855 /* Write the data to the FIFO. */
856 if (port->dma != PARPORT_DMA_NONE)
857 written = parport_pc_fifo_write_block_dma (port, buf, length);
859 written = parport_pc_fifo_write_block_pio (port, buf, length);
862 /* For some hardware we don't want to touch the mode until
863 * the FIFO is empty, so allow 4 seconds for each position
866 expire = jiffies + (priv->fifo_depth * (HZ * 4));
868 /* Wait for the FIFO to empty */
869 r = change_mode (port, ECR_PS2);
873 } while (time_before (jiffies, expire));
876 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
878 /* Prevent further data transfer. */
879 frob_set_mode (port, ECR_TST);
881 /* Adjust for the contents of the FIFO. */
882 for (written -= priv->fifo_depth; ; written++) {
883 if (inb (ECONTROL (port)) & 0x2) {
887 outb (0, FIFO (port));
890 /* Reset the FIFO and return to PS2 mode. */
891 frob_set_mode (port, ECR_PS2);
893 /* Host transfer recovery. */
894 parport_pc_data_reverse (port); /* Must be in PS2 mode */
896 parport_frob_control (port, PARPORT_CONTROL_INIT, 0);
897 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
899 printk (KERN_DEBUG "%s: PE,1 timeout (%d) "
900 "in ecp_write_block_pio\n", port->name, r);
902 parport_frob_control (port,
903 PARPORT_CONTROL_INIT,
904 PARPORT_CONTROL_INIT);
905 r = parport_wait_peripheral (port,
906 PARPORT_STATUS_PAPEROUT,
907 PARPORT_STATUS_PAPEROUT);
909 printk (KERN_DEBUG "%s: PE,2 timeout (%d) "
910 "in ecp_write_block_pio\n", port->name, r);
913 r = parport_wait_peripheral (port,
915 PARPORT_STATUS_BUSY);
918 "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
921 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
926 size_t parport_pc_ecp_read_block_pio (struct parport *port,
927 void *buf, size_t length, int flags)
929 size_t left = length;
932 const int fifo = FIFO(port);
933 const struct parport_pc_private *priv = port->physport->private_data;
934 const int fifo_depth = priv->fifo_depth;
937 port = port->physport;
938 DPRINTK (KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n");
939 dump_parport_state ("enter fcn", port);
941 /* Special case: a timeout of zero means we cannot call schedule().
942 * Also if O_NONBLOCK is set then use the default implementation. */
943 if (port->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
944 return parport_ieee1284_ecp_read_data (port, buf,
947 if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) {
948 /* If the peripheral is allowed to send RLE compressed
949 * data, it is possible for a byte to expand to 128
950 * bytes in the FIFO. */
953 fifofull = fifo_depth;
956 /* If the caller wants less than a full FIFO's worth of data,
957 * go through software emulation. Otherwise we may have to throw
959 if (length < fifofull)
960 return parport_ieee1284_ecp_read_data (port, buf,
963 if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) {
964 /* change to reverse-idle phase (must be in forward-idle) */
966 /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */
967 parport_frob_control (port,
968 PARPORT_CONTROL_AUTOFD
969 | PARPORT_CONTROL_STROBE,
970 PARPORT_CONTROL_AUTOFD);
971 parport_pc_data_reverse (port); /* Must be in PS2 mode */
973 /* Event 39: Set nInit low to initiate bus reversal */
974 parport_frob_control (port,
975 PARPORT_CONTROL_INIT,
977 /* Event 40: Wait for nAckReverse (PError) to go low */
978 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
980 printk (KERN_DEBUG "%s: PE timeout Event 40 (%d) "
981 "in ecp_read_block_pio\n", port->name, r);
986 /* Set up ECP FIFO mode.*/
987 /* parport_pc_frob_control (port,
988 PARPORT_CONTROL_STROBE |
989 PARPORT_CONTROL_AUTOFD,
990 PARPORT_CONTROL_AUTOFD); */
991 r = change_mode (port, ECR_ECP); /* ECP FIFO */
992 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
994 port->ieee1284.phase = IEEE1284_PH_REV_DATA;
996 /* the first byte must be collected manually */
997 dump_parport_state ("pre 43", port);
998 /* Event 43: Wait for nAck to go low */
999 r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0);
1001 /* timed out while reading -- no data */
1002 printk (KERN_DEBUG "PIO read timed out (initial byte)\n");
1006 *bufp++ = inb (DATA (port));
1008 dump_parport_state ("43-44", port);
1009 /* Event 44: nAutoFd (HostAck) goes high to acknowledge */
1010 parport_pc_frob_control (port,
1011 PARPORT_CONTROL_AUTOFD,
1013 dump_parport_state ("pre 45", port);
1014 /* Event 45: Wait for nAck to go high */
1015 /* r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK); */
1016 dump_parport_state ("post 45", port);
1019 /* timed out while waiting for peripheral to respond to ack */
1020 printk (KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n");
1022 /* keep hold of the byte we've got already */
1025 /* Event 46: nAutoFd (HostAck) goes low to accept more data */
1026 parport_pc_frob_control (port,
1027 PARPORT_CONTROL_AUTOFD,
1028 PARPORT_CONTROL_AUTOFD);
1031 dump_parport_state ("rev idle", port);
1032 /* Do the transfer. */
1033 while (left > fifofull) {
1035 unsigned long expire = jiffies + port->cad->timeout;
1036 unsigned char ecrval = inb (ECONTROL (port));
1038 if (need_resched() && time_before (jiffies, expire))
1039 /* Can't yield the port. */
1042 /* At this point, the FIFO may already be full. In
1043 * that case ECP is already holding back the
1044 * peripheral (assuming proper design) with a delayed
1045 * handshake. Work fast to avoid a peripheral
1048 if (ecrval & 0x01) {
1049 /* FIFO is empty. Wait for interrupt. */
1050 dump_parport_state ("FIFO empty", port);
1052 /* Anyone else waiting for the port? */
1053 if (port->waithead) {
1054 printk (KERN_DEBUG "Somebody wants the port\n");
1058 /* Clear serviceIntr */
1059 ECR_WRITE (port, ecrval & ~(1<<2));
1061 dump_parport_state ("waiting", port);
1062 ret = parport_wait_event (port, HZ);
1063 DPRINTK (KERN_DEBUG "parport_wait_event returned %d\n", ret);
1067 if (!time_before (jiffies, expire)) {
1069 dump_parport_state ("timeout", port);
1070 printk (KERN_DEBUG "PIO read timed out\n");
1073 ecrval = inb (ECONTROL (port));
1074 if (!(ecrval & (1<<2))) {
1075 if (need_resched() &&
1076 time_before (jiffies, expire)) {
1082 /* Depending on how the FIFO threshold was
1083 * set, how long interrupt service took, and
1084 * how fast the peripheral is, we might be
1085 * lucky and have a just filled FIFO. */
1089 if (ecrval & 0x02) {
1091 dump_parport_state ("FIFO full", port);
1092 insb (fifo, bufp, fifo_depth);
1098 DPRINTK (KERN_DEBUG "*** ecp_read_block_pio: reading one byte from the FIFO\n");
1100 /* FIFO not filled. We will cycle this loop for a while
1101 * and either the peripheral will fill it faster,
1102 * tripping a fast empty with insb, or we empty it. */
1103 *bufp++ = inb (fifo);
1107 /* scoop up anything left in the FIFO */
1108 while (left && !(inb (ECONTROL (port) & 0x01))) {
1109 *bufp++ = inb (fifo);
1113 port->ieee1284.phase = IEEE1284_PH_REV_IDLE;
1114 dump_parport_state ("rev idle2", port);
1118 /* Go to forward idle mode to shut the peripheral up (event 47). */
1119 parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT);
1121 /* event 49: PError goes high */
1122 r = parport_wait_peripheral (port,
1123 PARPORT_STATUS_PAPEROUT,
1124 PARPORT_STATUS_PAPEROUT);
1127 "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n",
1131 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1135 int lost = get_fifo_residue (port);
1137 /* Shouldn't happen with compliant peripherals. */
1138 printk (KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n",
1142 dump_parport_state ("fwd idle", port);
1143 return length - left;
1146 #endif /* IEEE 1284 support */
1147 #endif /* Allowed to use FIFO/DMA */
1151 * ******************************************
1152 * INITIALISATION AND MODULE STUFF BELOW HERE
1153 * ******************************************
1156 /* GCC is not inlining extern inline function later overwriten to non-inline,
1157 so we use outlined_ variants here. */
1158 struct parport_operations parport_pc_ops =
1160 .write_data = parport_pc_write_data,
1161 .read_data = parport_pc_read_data,
1163 .write_control = parport_pc_write_control,
1164 .read_control = parport_pc_read_control,
1165 .frob_control = parport_pc_frob_control,
1167 .read_status = parport_pc_read_status,
1169 .enable_irq = parport_pc_enable_irq,
1170 .disable_irq = parport_pc_disable_irq,
1172 .data_forward = parport_pc_data_forward,
1173 .data_reverse = parport_pc_data_reverse,
1175 .init_state = parport_pc_init_state,
1176 .save_state = parport_pc_save_state,
1177 .restore_state = parport_pc_restore_state,
1179 .epp_write_data = parport_ieee1284_epp_write_data,
1180 .epp_read_data = parport_ieee1284_epp_read_data,
1181 .epp_write_addr = parport_ieee1284_epp_write_addr,
1182 .epp_read_addr = parport_ieee1284_epp_read_addr,
1184 .ecp_write_data = parport_ieee1284_ecp_write_data,
1185 .ecp_read_data = parport_ieee1284_ecp_read_data,
1186 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
1188 .compat_write_data = parport_ieee1284_write_compat,
1189 .nibble_read_data = parport_ieee1284_read_nibble,
1190 .byte_read_data = parport_ieee1284_read_byte,
1192 .owner = THIS_MODULE,
1195 #ifdef CONFIG_PARPORT_PC_SUPERIO
1196 /* Super-IO chipset detection, Winbond, SMSC */
1197 static void __devinit show_parconfig_smsc37c669(int io, int key)
1199 int cr1,cr4,cra,cr23,cr26,cr27,i=0;
1200 static const char *modes[]={ "SPP and Bidirectional (PS/2)",
1221 if (verbose_probing) {
1222 printk (KERN_INFO "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
1223 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
1224 cr1,cr4,cra,cr23,cr26,cr27);
1226 /* The documentation calls DMA and IRQ-Lines by letters, so
1227 the board maker can/will wire them
1228 appropriately/randomly... G=reserved H=IDE-irq, */
1229 printk (KERN_INFO "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, "
1230 "fifo threshold=%d\n", cr23*4,
1231 (cr27 &0x0f) ? 'A'-1+(cr27 &0x0f): '-',
1232 (cr26 &0x0f) ? 'A'-1+(cr26 &0x0f): '-', cra & 0x0f);
1233 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
1234 (cr23*4 >=0x100) ?"yes":"no", (cr1 & 4) ? "yes" : "no");
1235 printk(KERN_INFO "SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1236 (cr1 & 0x08 ) ? "Standard mode only (SPP)" : modes[cr4 & 0x03],
1237 (cr4 & 0x40) ? "1.7" : "1.9");
1240 /* Heuristics ! BIOS setup for this mainboard device limits
1241 the choices to standard settings, i.e. io-address and IRQ
1242 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1243 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1244 if(cr23*4 >=0x100) { /* if active */
1245 while((superios[i].io!= 0) && (i<NR_SUPERIOS))
1248 printk(KERN_INFO "Super-IO: too many chips!\n");
1253 superios[i].io = 0x3bc;
1254 superios[i].irq = 7;
1257 superios[i].io = 0x378;
1258 superios[i].irq = 7;
1261 superios[i].io = 0x278;
1262 superios[i].irq = 5;
1265 if((d==1) || (d==3))
1268 superios[i].dma= PARPORT_DMA_NONE;
1274 static void __devinit show_parconfig_winbond(int io, int key)
1276 int cr30,cr60,cr61,cr70,cr74,crf0,i=0;
1277 static const char *modes[] = {
1278 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1283 "EPP-1.7 and SPP", /* 5 */
1285 "ECP and EPP-1.7" };
1286 static char *irqtypes[] = { "pulsed low, high-Z", "follows nACK" };
1288 /* The registers are called compatible-PnP because the
1289 register layout is modelled after ISA-PnP, the access
1290 method is just another ... */
1293 outb(0x07,io); /* Register 7: Select Logical Device */
1294 outb(0x01,io+1); /* LD1 is Parallel Port */
1309 if (verbose_probing) {
1310 printk(KERN_INFO "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x "
1311 "70=%02x 74=%02x, f0=%02x\n", cr30,cr60,cr61,cr70,cr74,crf0);
1312 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1313 (cr30 & 0x01) ? "yes":"no", cr60,cr61,cr70&0x0f );
1314 if ((cr74 & 0x07) > 3)
1315 printk("dma=none\n");
1317 printk("dma=%d\n",cr74 & 0x07);
1318 printk(KERN_INFO "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1319 irqtypes[crf0>>7], (crf0>>3)&0x0f);
1320 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", modes[crf0 & 0x07]);
1323 if(cr30 & 0x01) { /* the settings can be interrogated later ... */
1324 while((superios[i].io!= 0) && (i<NR_SUPERIOS))
1327 printk(KERN_INFO "Super-IO: too many chips!\n");
1329 superios[i].io = (cr60<<8)|cr61;
1330 superios[i].irq = cr70&0x0f;
1331 superios[i].dma = (((cr74 & 0x07) > 3) ?
1332 PARPORT_DMA_NONE : (cr74 & 0x07));
1337 static void __devinit decode_winbond(int efer, int key, int devid, int devrev, int oldid)
1339 const char *type = "unknown";
1342 if (devid == devrev)
1343 /* simple heuristics, we happened to read some
1344 non-winbond register */
1347 id=(devid<<8) | devrev;
1349 /* Values are from public data sheets pdf files, I can just
1350 confirm 83977TF is correct :-) */
1351 if (id == 0x9771) type="83977F/AF";
1352 else if (id == 0x9773) type="83977TF / SMSC 97w33x/97w34x";
1353 else if (id == 0x9774) type="83977ATF";
1354 else if ((id & ~0x0f) == 0x5270) type="83977CTF / SMSC 97w36x";
1355 else if ((id & ~0x0f) == 0x52f0) type="83977EF / SMSC 97w35x";
1356 else if ((id & ~0x0f) == 0x5210) type="83627";
1357 else if ((id & ~0x0f) == 0x6010) type="83697HF";
1358 else if ((oldid &0x0f ) == 0x0a) { type="83877F"; progif=1;}
1359 else if ((oldid &0x0f ) == 0x0b) { type="83877AF"; progif=1;}
1360 else if ((oldid &0x0f ) == 0x0c) { type="83877TF"; progif=1;}
1361 else if ((oldid &0x0f ) == 0x0d) { type="83877ATF"; progif=1;}
1364 if (verbose_probing)
1365 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x "
1366 "devid=%02x devrev=%02x oldid=%02x type=%s\n",
1367 efer, key, devid, devrev, oldid, type);
1370 show_parconfig_winbond(efer,key);
1373 static void __devinit decode_smsc(int efer, int key, int devid, int devrev)
1375 const char *type = "unknown";
1376 void (*func)(int io, int key);
1379 if (devid == devrev)
1380 /* simple heuristics, we happened to read some
1381 non-smsc register */
1385 id=(devid<<8) | devrev;
1387 if (id==0x0302) {type="37c669"; func=show_parconfig_smsc37c669;}
1388 else if (id==0x6582) type="37c665IR";
1389 else if (devid==0x65) type="37c665GT";
1390 else if (devid==0x66) type="37c666GT";
1392 if (verbose_probing)
1393 printk(KERN_INFO "SMSC chip at EFER=0x%x "
1394 "key=0x%02x devid=%02x devrev=%02x type=%s\n",
1395 efer, key, devid, devrev, type);
1402 static void __devinit winbond_check(int io, int key)
1404 int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
1406 /* First probe without key */
1415 outb(key,io); /* Write Magic Sequence to EFER, extended
1416 funtion enable register */
1417 outb(0x20,io); /* Write EFIR, extended function index register */
1418 devid=inb(io+1); /* Read EFDR, extended function data register */
1423 outb(0xaa,io); /* Magic Seal */
1425 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1426 return; /* protection against false positives */
1428 decode_winbond(io,key,devid,devrev,oldid);
1431 static void __devinit winbond_check2(int io,int key)
1433 int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
1435 /* First probe without the key */
1443 outb(key,io); /* Write Magic Byte to EFER, extended
1444 funtion enable register */
1445 outb(0x20,io+2); /* Write EFIR, extended function index register */
1446 devid=inb(io+2); /* Read EFDR, extended function data register */
1451 outb(0xaa,io); /* Magic Seal */
1453 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1454 return; /* protection against false positives */
1456 decode_winbond(io,key,devid,devrev,oldid);
1459 static void __devinit smsc_check(int io, int key)
1461 int id,rev,oldid,oldrev,x_id,x_rev,x_oldid,x_oldrev;
1463 /* First probe without the key */
1474 outb(key,io); /* Write Magic Sequence to EFER, extended
1475 funtion enable register */
1476 outb(0x0d,io); /* Write EFIR, extended function index register */
1477 oldid=inb(io+1); /* Read EFDR, extended function data register */
1484 outb(0xaa,io); /* Magic Seal */
1486 if ((x_id == id) && (x_oldrev == oldrev) &&
1487 (x_oldid == oldid) && (x_rev == rev))
1488 return; /* protection against false positives */
1490 decode_smsc(io,key,oldid,oldrev);
1494 static void __devinit detect_and_report_winbond (void)
1496 if (verbose_probing)
1497 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1498 winbond_check(0x3f0,0x87);
1499 winbond_check(0x370,0x87);
1500 winbond_check(0x2e ,0x87);
1501 winbond_check(0x4e ,0x87);
1502 winbond_check(0x3f0,0x86);
1503 winbond_check2(0x250,0x88);
1504 winbond_check2(0x250,0x89);
1507 static void __devinit detect_and_report_smsc (void)
1509 if (verbose_probing)
1510 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1511 smsc_check(0x3f0,0x55);
1512 smsc_check(0x370,0x55);
1513 smsc_check(0x3f0,0x44);
1514 smsc_check(0x370,0x44);
1516 #endif /* CONFIG_PARPORT_PC_SUPERIO */
1518 static int __devinit get_superio_dma (struct parport *p)
1521 while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
1524 return superios[i].dma;
1525 return PARPORT_DMA_NONE;
1528 static int __devinit get_superio_irq (struct parport *p)
1531 while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
1534 return superios[i].irq;
1535 return PARPORT_IRQ_NONE;
1539 /* --- Mode detection ------------------------------------- */
1542 * Checks for port existence, all ports support SPP MODE
1544 * 0 : No parallel port at this address
1545 * PARPORT_MODE_PCSPP : SPP port detected
1546 * (if the user specified an ioport himself,
1547 * this shall always be the case!)
1550 static int __devinit parport_SPP_supported(struct parport *pb)
1555 * first clear an eventually pending EPP timeout
1556 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1557 * that does not even respond to SPP cycles if an EPP
1558 * timeout is pending
1560 clear_epp_timeout(pb);
1562 /* Do a simple read-write test to make sure the port exists. */
1564 outb (w, CONTROL (pb));
1566 /* Is there a control register that we can read from? Some
1567 * ports don't allow reads, so read_control just returns a
1568 * software copy. Some ports _do_ allow reads, so bypass the
1569 * software copy here. In addition, some bits aren't
1571 r = inb (CONTROL (pb));
1572 if ((r & 0xf) == w) {
1574 outb (w, CONTROL (pb));
1575 r = inb (CONTROL (pb));
1576 outb (0xc, CONTROL (pb));
1578 return PARPORT_MODE_PCSPP;
1582 /* That didn't work, but the user thinks there's a
1584 printk (KERN_INFO "parport 0x%lx (WARNING): CTR: "
1585 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1587 /* Try the data register. The data lines aren't tri-stated at
1588 * this stage, so we expect back what we wrote. */
1590 parport_pc_write_data (pb, w);
1591 r = parport_pc_read_data (pb);
1594 parport_pc_write_data (pb, w);
1595 r = parport_pc_read_data (pb);
1597 return PARPORT_MODE_PCSPP;
1600 if (user_specified) {
1601 /* Didn't work, but the user is convinced this is the
1603 printk (KERN_INFO "parport 0x%lx (WARNING): DATA: "
1604 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1605 printk (KERN_INFO "parport 0x%lx: You gave this address, "
1606 "but there is probably no parallel port there!\n",
1610 /* It's possible that we can't read the control register or
1611 * the data register. In that case just believe the user. */
1613 return PARPORT_MODE_PCSPP;
1620 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1621 * on these cards actually accesses the CTR.
1623 * Modern cards don't do this but reading from ECR will return 0xff
1624 * regardless of what is written here if the card does NOT support
1627 * We first check to see if ECR is the same as CTR. If not, the low
1628 * two bits of ECR aren't writable, so we check by writing ECR and
1629 * reading it back to see if it's what we expect.
1631 static int __devinit parport_ECR_present(struct parport *pb)
1633 struct parport_pc_private *priv = pb->private_data;
1634 unsigned char r = 0xc;
1636 outb (r, CONTROL (pb));
1637 if ((inb (ECONTROL (pb)) & 0x3) == (r & 0x3)) {
1638 outb (r ^ 0x2, CONTROL (pb)); /* Toggle bit 1 */
1640 r = inb (CONTROL (pb));
1641 if ((inb (ECONTROL (pb)) & 0x2) == (r & 0x2))
1642 goto no_reg; /* Sure that no ECR register exists */
1645 if ((inb (ECONTROL (pb)) & 0x3 ) != 0x1)
1648 ECR_WRITE (pb, 0x34);
1649 if (inb (ECONTROL (pb)) != 0x35)
1653 outb (0xc, CONTROL (pb));
1655 /* Go to mode 000 */
1656 frob_set_mode (pb, ECR_SPP);
1661 outb (0xc, CONTROL (pb));
1665 #ifdef CONFIG_PARPORT_1284
1666 /* Detect PS/2 support.
1668 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1669 * allows us to read data from the data lines. In theory we would get back
1670 * 0xff but any peripheral attached to the port may drag some or all of the
1671 * lines down to zero. So if we get back anything that isn't the contents
1672 * of the data register we deem PS/2 support to be present.
1674 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1675 * drivers, but an external peripheral with sufficiently beefy drivers of
1676 * its own can overpower them and assert its own levels onto the bus, from
1677 * where they can then be read back as normal. Ports with this property
1678 * and the right type of device attached are likely to fail the SPP test,
1679 * (as they will appear to have stuck bits) and so the fact that they might
1680 * be misdetected here is rather academic.
1683 static int __devinit parport_PS2_supported(struct parport *pb)
1687 clear_epp_timeout(pb);
1689 /* try to tri-state the buffer */
1690 parport_pc_data_reverse (pb);
1692 parport_pc_write_data(pb, 0x55);
1693 if (parport_pc_read_data(pb) != 0x55) ok++;
1695 parport_pc_write_data(pb, 0xaa);
1696 if (parport_pc_read_data(pb) != 0xaa) ok++;
1698 /* cancel input mode */
1699 parport_pc_data_forward (pb);
1702 pb->modes |= PARPORT_MODE_TRISTATE;
1704 struct parport_pc_private *priv = pb->private_data;
1705 priv->ctr_writable &= ~0x20;
1711 #ifdef CONFIG_PARPORT_PC_FIFO
1712 static int __devinit parport_ECP_supported(struct parport *pb)
1715 int config, configb;
1717 struct parport_pc_private *priv = pb->private_data;
1718 /* Translate ECP intrLine to ISA irq value */
1719 static const int intrline[]= { 0, 7, 9, 10, 11, 14, 15, 5 };
1721 /* If there is no ECR, we have no hope of supporting ECP. */
1725 /* Find out FIFO depth */
1726 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1727 ECR_WRITE (pb, ECR_TST << 5); /* TEST FIFO */
1728 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02); i++)
1729 outb (0xaa, FIFO (pb));
1732 * Using LGS chipset it uses ECR register, but
1733 * it doesn't support ECP or FIFO MODE
1736 ECR_WRITE (pb, ECR_SPP << 5);
1740 priv->fifo_depth = i;
1741 if (verbose_probing)
1742 printk (KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1744 /* Find out writeIntrThreshold */
1745 frob_econtrol (pb, 1<<2, 1<<2);
1746 frob_econtrol (pb, 1<<2, 0);
1747 for (i = 1; i <= priv->fifo_depth; i++) {
1750 if (inb (ECONTROL (pb)) & (1<<2))
1754 if (i <= priv->fifo_depth) {
1755 if (verbose_probing)
1756 printk (KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1759 /* Number of bytes we know we can write if we get an
1763 priv->writeIntrThreshold = i;
1765 /* Find out readIntrThreshold */
1766 frob_set_mode (pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1767 parport_pc_data_reverse (pb); /* Must be in PS2 mode */
1768 frob_set_mode (pb, ECR_TST); /* Test FIFO */
1769 frob_econtrol (pb, 1<<2, 1<<2);
1770 frob_econtrol (pb, 1<<2, 0);
1771 for (i = 1; i <= priv->fifo_depth; i++) {
1772 outb (0xaa, FIFO (pb));
1773 if (inb (ECONTROL (pb)) & (1<<2))
1777 if (i <= priv->fifo_depth) {
1778 if (verbose_probing)
1779 printk (KERN_INFO "0x%lx: readIntrThreshold is %d\n",
1782 /* Number of bytes we can read if we get an interrupt. */
1785 priv->readIntrThreshold = i;
1787 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1788 ECR_WRITE (pb, 0xf4); /* Configuration mode */
1789 config = inb (CONFIGA (pb));
1790 pword = (config >> 4) & 0x7;
1794 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
1799 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
1803 printk (KERN_WARNING "0x%lx: Unknown implementation ID\n",
1809 priv->pword = pword;
1811 if (verbose_probing) {
1812 printk (KERN_DEBUG "0x%lx: PWord is %d bits\n", pb->base, 8 * pword);
1814 printk (KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
1815 config & 0x80 ? "Level" : "Pulses");
1817 configb = inb (CONFIGB (pb));
1818 printk (KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1819 pb->base, config, configb);
1820 printk (KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1821 if ((configb >>3) & 0x07)
1822 printk("%d",intrline[(configb >>3) & 0x07]);
1824 printk("<none or set by other means>");
1826 if( (configb & 0x03 ) == 0x00)
1827 printk("<none or set by other means>\n");
1829 printk("%d\n",configb & 0x07);
1832 /* Go back to mode 000 */
1833 frob_set_mode (pb, ECR_SPP);
1839 static int __devinit parport_ECPPS2_supported(struct parport *pb)
1841 const struct parport_pc_private *priv = pb->private_data;
1848 oecr = inb (ECONTROL (pb));
1849 ECR_WRITE (pb, ECR_PS2 << 5);
1850 result = parport_PS2_supported(pb);
1851 ECR_WRITE (pb, oecr);
1855 /* EPP mode detection */
1857 static int __devinit parport_EPP_supported(struct parport *pb)
1859 const struct parport_pc_private *priv = pb->private_data;
1863 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1864 * when EPP is possible and is set high when an EPP timeout
1865 * occurs (EPP uses the HALT line to stop the CPU while it does
1866 * the byte transfer, an EPP timeout occurs if the attached
1867 * device fails to respond after 10 micro seconds).
1869 * This bit is cleared by either reading it (National Semi)
1870 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1871 * This bit is always high in non EPP modes.
1874 /* If EPP timeout bit clear then EPP available */
1875 if (!clear_epp_timeout(pb)) {
1876 return 0; /* No way to clear timeout */
1879 /* Check for Intel bug. */
1882 for (i = 0x00; i < 0x80; i += 0x20) {
1884 if (clear_epp_timeout (pb)) {
1885 /* Phony EPP in ECP. */
1891 pb->modes |= PARPORT_MODE_EPP;
1893 /* Set up access functions to use EPP hardware. */
1894 pb->ops->epp_read_data = parport_pc_epp_read_data;
1895 pb->ops->epp_write_data = parport_pc_epp_write_data;
1896 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1897 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1902 static int __devinit parport_ECPEPP_supported(struct parport *pb)
1904 struct parport_pc_private *priv = pb->private_data;
1912 oecr = inb (ECONTROL (pb));
1913 /* Search for SMC style EPP+ECP mode */
1914 ECR_WRITE (pb, 0x80);
1915 outb (0x04, CONTROL (pb));
1916 result = parport_EPP_supported(pb);
1918 ECR_WRITE (pb, oecr);
1921 /* Set up access functions to use ECP+EPP hardware. */
1922 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
1923 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
1924 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
1925 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
1931 #else /* No IEEE 1284 support */
1933 /* Don't bother probing for modes we know we won't use. */
1934 static int __devinit parport_PS2_supported(struct parport *pb) { return 0; }
1935 #ifdef CONFIG_PARPORT_PC_FIFO
1936 static int __devinit parport_ECP_supported(struct parport *pb) { return 0; }
1938 static int __devinit parport_EPP_supported(struct parport *pb) { return 0; }
1939 static int __devinit parport_ECPEPP_supported(struct parport *pb){return 0;}
1940 static int __devinit parport_ECPPS2_supported(struct parport *pb){return 0;}
1942 #endif /* No IEEE 1284 support */
1944 /* --- IRQ detection -------------------------------------- */
1946 /* Only if supports ECP mode */
1947 static int __devinit programmable_irq_support(struct parport *pb)
1950 unsigned char oecr = inb (ECONTROL (pb));
1951 static const int lookup[8] = {
1952 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
1955 ECR_WRITE (pb, ECR_CNF << 5); /* Configuration MODE */
1957 intrLine = (inb (CONFIGB (pb)) >> 3) & 0x07;
1958 irq = lookup[intrLine];
1960 ECR_WRITE (pb, oecr);
1964 static int __devinit irq_probe_ECP(struct parport *pb)
1969 irqs = probe_irq_on();
1971 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1972 ECR_WRITE (pb, (ECR_TST << 5) | 0x04);
1973 ECR_WRITE (pb, ECR_TST << 5);
1975 /* If Full FIFO sure that writeIntrThreshold is generated */
1976 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02) ; i++)
1977 outb (0xaa, FIFO (pb));
1979 pb->irq = probe_irq_off(irqs);
1980 ECR_WRITE (pb, ECR_SPP << 5);
1983 pb->irq = PARPORT_IRQ_NONE;
1989 * This detection seems that only works in National Semiconductors
1990 * This doesn't work in SMC, LGS, and Winbond
1992 static int __devinit irq_probe_EPP(struct parport *pb)
1994 #ifndef ADVANCED_DETECT
1995 return PARPORT_IRQ_NONE;
2000 if (pb->modes & PARPORT_MODE_PCECR)
2001 oecr = inb (ECONTROL (pb));
2003 irqs = probe_irq_on();
2005 if (pb->modes & PARPORT_MODE_PCECR)
2006 frob_econtrol (pb, 0x10, 0x10);
2008 clear_epp_timeout(pb);
2009 parport_pc_frob_control (pb, 0x20, 0x20);
2010 parport_pc_frob_control (pb, 0x10, 0x10);
2011 clear_epp_timeout(pb);
2013 /* Device isn't expecting an EPP read
2014 * and generates an IRQ.
2016 parport_pc_read_epp(pb);
2019 pb->irq = probe_irq_off (irqs);
2020 if (pb->modes & PARPORT_MODE_PCECR)
2021 ECR_WRITE (pb, oecr);
2022 parport_pc_write_control(pb, 0xc);
2025 pb->irq = PARPORT_IRQ_NONE;
2028 #endif /* Advanced detection */
2031 static int __devinit irq_probe_SPP(struct parport *pb)
2033 /* Don't even try to do this. */
2034 return PARPORT_IRQ_NONE;
2037 /* We will attempt to share interrupt requests since other devices
2038 * such as sound cards and network cards seem to like using the
2041 * When ECP is available we can autoprobe for IRQs.
2042 * NOTE: If we can autoprobe it, we can register the IRQ.
2044 static int __devinit parport_irq_probe(struct parport *pb)
2046 struct parport_pc_private *priv = pb->private_data;
2049 pb->irq = programmable_irq_support(pb);
2051 if (pb->irq == PARPORT_IRQ_NONE)
2052 pb->irq = irq_probe_ECP(pb);
2055 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
2056 (pb->modes & PARPORT_MODE_EPP))
2057 pb->irq = irq_probe_EPP(pb);
2059 clear_epp_timeout(pb);
2061 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
2062 pb->irq = irq_probe_EPP(pb);
2064 clear_epp_timeout(pb);
2066 if (pb->irq == PARPORT_IRQ_NONE)
2067 pb->irq = irq_probe_SPP(pb);
2069 if (pb->irq == PARPORT_IRQ_NONE)
2070 pb->irq = get_superio_irq(pb);
2075 /* --- DMA detection -------------------------------------- */
2077 /* Only if chipset conforms to ECP ISA Interface Standard */
2078 static int __devinit programmable_dma_support (struct parport *p)
2080 unsigned char oecr = inb (ECONTROL (p));
2083 frob_set_mode (p, ECR_CNF);
2085 dma = inb (CONFIGB(p)) & 0x07;
2086 /* 000: Indicates jumpered 8-bit DMA if read-only.
2087 100: Indicates jumpered 16-bit DMA if read-only. */
2088 if ((dma & 0x03) == 0)
2089 dma = PARPORT_DMA_NONE;
2091 ECR_WRITE (p, oecr);
2095 static int __devinit parport_dma_probe (struct parport *p)
2097 const struct parport_pc_private *priv = p->private_data;
2099 p->dma = programmable_dma_support(p); /* ask ECP chipset first */
2100 if (p->dma == PARPORT_DMA_NONE) {
2101 /* ask known Super-IO chips proper, although these
2102 claim ECP compatible, some don't report their DMA
2103 conforming to ECP standards */
2104 p->dma = get_superio_dma(p);
2110 /* --- Initialisation code -------------------------------- */
2112 static LIST_HEAD(ports_list);
2113 static spinlock_t ports_lock = SPIN_LOCK_UNLOCKED;
2115 struct parport *parport_pc_probe_port (unsigned long int base,
2116 unsigned long int base_hi,
2118 struct pci_dev *dev)
2120 struct parport_pc_private *priv;
2121 struct parport_operations *ops;
2123 int probedirq = PARPORT_IRQ_NONE;
2124 struct resource *base_res;
2125 struct resource *ECR_res = NULL;
2126 struct resource *EPP_res = NULL;
2128 ops = kmalloc(sizeof (struct parport_operations), GFP_KERNEL);
2132 priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
2136 /* a misnomer, actually - it's allocate and reserve parport number */
2137 p = parport_register_port(base, irq, dma, ops);
2141 base_res = request_region(base, 3, p->name);
2145 memcpy(ops, &parport_pc_ops, sizeof (struct parport_operations));
2147 priv->ctr_writable = ~0x10;
2149 priv->fifo_depth = 0;
2151 priv->dma_handle = 0;
2153 INIT_LIST_HEAD(&priv->list);
2155 p->base_hi = base_hi;
2156 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2157 p->private_data = priv;
2160 ECR_res = request_region(base_hi, 3, p->name);
2162 parport_ECR_present(p);
2165 if (base != 0x3bc) {
2166 EPP_res = request_region(base+0x3, 5, p->name);
2168 if (!parport_EPP_supported(p))
2169 parport_ECPEPP_supported(p);
2171 if (!parport_SPP_supported (p))
2175 parport_ECPPS2_supported(p);
2177 parport_PS2_supported(p);
2179 p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
2181 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
2182 if (p->base_hi && priv->ecr)
2183 printk(" (0x%lx)", p->base_hi);
2184 if (p->irq == PARPORT_IRQ_AUTO) {
2185 p->irq = PARPORT_IRQ_NONE;
2186 parport_irq_probe(p);
2187 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2188 p->irq = PARPORT_IRQ_NONE;
2189 parport_irq_probe(p);
2191 p->irq = PARPORT_IRQ_NONE;
2193 if (p->irq != PARPORT_IRQ_NONE) {
2194 printk(", irq %d", p->irq);
2195 priv->ctr_writable |= 0x10;
2197 if (p->dma == PARPORT_DMA_AUTO) {
2198 p->dma = PARPORT_DMA_NONE;
2199 parport_dma_probe(p);
2202 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2203 is mandatory (see above) */
2204 p->dma = PARPORT_DMA_NONE;
2206 #ifdef CONFIG_PARPORT_PC_FIFO
2207 if (parport_ECP_supported(p) &&
2208 p->dma != PARPORT_DMA_NOFIFO &&
2209 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2210 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2211 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2212 #ifdef CONFIG_PARPORT_1284
2213 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2214 /* currently broken, but working on it.. (FB) */
2215 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2216 #endif /* IEEE 1284 support */
2217 if (p->dma != PARPORT_DMA_NONE) {
2218 printk(", dma %d", p->dma);
2219 p->modes |= PARPORT_MODE_DMA;
2221 else printk(", using FIFO");
2224 /* We can't use the DMA channel after all. */
2225 p->dma = PARPORT_DMA_NONE;
2226 #endif /* Allowed to use FIFO/DMA */
2229 #define printmode(x) {if(p->modes&PARPORT_MODE_##x){printk("%s%s",f?",":"",#x);f++;}}
2233 printmode(TRISTATE);
2240 #ifndef CONFIG_PARPORT_1284
2242 #endif /* CONFIG_PARPORT_1284 */
2244 if (probedirq != PARPORT_IRQ_NONE)
2245 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
2247 /* If No ECP release the ports grabbed above. */
2248 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2249 release_region(base_hi, 3);
2252 /* Likewise for EEP ports */
2253 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2254 release_region(base+3, 5);
2257 if (p->irq != PARPORT_IRQ_NONE) {
2258 if (request_irq (p->irq, parport_pc_interrupt,
2260 printk (KERN_WARNING "%s: irq %d in use, "
2261 "resorting to polled operation\n",
2263 p->irq = PARPORT_IRQ_NONE;
2264 p->dma = PARPORT_DMA_NONE;
2267 #ifdef CONFIG_PARPORT_PC_FIFO
2268 if (p->dma != PARPORT_DMA_NONE) {
2269 if (request_dma (p->dma, p->name)) {
2270 printk (KERN_WARNING "%s: dma %d in use, "
2271 "resorting to PIO operation\n",
2273 p->dma = PARPORT_DMA_NONE;
2276 pci_alloc_consistent(priv->dev,
2279 if (! priv->dma_buf) {
2280 printk (KERN_WARNING "%s: "
2281 "cannot get buffer for DMA, "
2282 "resorting to PIO operation\n",
2285 p->dma = PARPORT_DMA_NONE;
2289 #endif /* CONFIG_PARPORT_PC_FIFO */
2292 /* Done probing. Now put the port into a sensible start-up state. */
2295 * Put the ECP detected port in PS2 mode.
2296 * Do this also for ports that have ECR but don't do ECP.
2298 ECR_WRITE (p, 0x34);
2300 parport_pc_write_data(p, 0);
2301 parport_pc_data_forward (p);
2303 /* Now that we've told the sharing engine about the port, and
2304 found out its characteristics, let the high-level drivers
2306 spin_lock(&ports_lock);
2307 list_add(&priv->list, &ports_list);
2308 spin_unlock(&ports_lock);
2309 parport_announce_port (p);
2315 release_region(base_hi, 3);
2317 release_region(base+0x3, 5);
2318 release_region(base, 3);
2320 parport_put_port(p);
2329 EXPORT_SYMBOL (parport_pc_probe_port);
2331 void parport_pc_unregister_port (struct parport *p)
2333 struct parport_pc_private *priv = p->private_data;
2334 struct parport_operations *ops = p->ops;
2336 parport_remove_port(p);
2337 spin_lock(&ports_lock);
2338 list_del_init(&priv->list);
2339 spin_unlock(&ports_lock);
2340 if (p->dma != PARPORT_DMA_NONE)
2342 if (p->irq != PARPORT_IRQ_NONE)
2343 free_irq(p->irq, p);
2344 release_region(p->base, 3);
2346 release_region(p->base + 3, p->size - 3);
2347 if (p->modes & PARPORT_MODE_ECP)
2348 release_region(p->base_hi, 3);
2349 #ifdef CONFIG_PARPORT_PC_FIFO
2351 pci_free_consistent(priv->dev, PAGE_SIZE,
2354 #endif /* CONFIG_PARPORT_PC_FIFO */
2355 kfree (p->private_data);
2356 parport_put_port(p);
2357 kfree (ops); /* hope no-one cached it */
2360 EXPORT_SYMBOL (parport_pc_unregister_port);
2364 /* ITE support maintained by Rich Liu <richliu@poorman.org> */
2365 static int __devinit sio_ite_8872_probe (struct pci_dev *pdev, int autoirq,
2368 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2369 struct resource *base_res;
2371 u32 ite8872_lpt, ite8872_lpthi;
2372 u8 ite8872_irq, type;
2373 char *fake_name = "parport probe";
2377 DPRINTK (KERN_DEBUG "sio_ite_8872_probe()\n");
2379 // make sure which one chip
2380 for(i = 0; i < 5; i++) {
2381 base_res = request_region(inta_addr[i], 0x8, fake_name);
2384 pci_write_config_dword (pdev, 0x60,
2385 0xe7000000 | inta_addr[i]);
2386 pci_write_config_dword (pdev, 0x78,
2387 0x00000000 | inta_addr[i]);
2388 test = inb (inta_addr[i]);
2389 if (test != 0xff) break;
2390 release_region(inta_addr[i], 0x8);
2394 printk (KERN_INFO "parport_pc: cannot find ITE8872 INTA\n");
2398 type = inb (inta_addr[i] + 0x18);
2403 printk (KERN_INFO "parport_pc: ITE8871 found (1P)\n");
2404 ite8872set = 0x64200000;
2407 printk (KERN_INFO "parport_pc: ITE8875 found (1P)\n");
2408 ite8872set = 0x64200000;
2411 printk (KERN_INFO "parport_pc: ITE8872 found (2S1P)\n");
2412 ite8872set = 0x64e00000;
2415 printk (KERN_INFO "parport_pc: ITE8873 found (1S)\n");
2418 DPRINTK (KERN_DEBUG "parport_pc: ITE8874 found (2S)\n");
2421 printk (KERN_INFO "parport_pc: unknown ITE887x\n");
2422 printk (KERN_INFO "parport_pc: please mail 'lspci -nvv' "
2423 "output to Rich.Liu@ite.com.tw\n");
2427 pci_read_config_byte (pdev, 0x3c, &ite8872_irq);
2428 pci_read_config_dword (pdev, 0x1c, &ite8872_lpt);
2429 ite8872_lpt &= 0x0000ff00;
2430 pci_read_config_dword (pdev, 0x20, &ite8872_lpthi);
2431 ite8872_lpthi &= 0x0000ff00;
2432 pci_write_config_dword (pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2433 pci_write_config_dword (pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2434 pci_write_config_dword (pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2435 // SET SPP&EPP , Parallel Port NO DMA , Enable All Function
2437 pci_write_config_dword (pdev, 0x9c,
2438 ite8872set | (ite8872_irq * 0x11111));
2440 DPRINTK (KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq);
2441 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n",
2443 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
2446 /* Let the user (or defaults) steer us away from interrupts */
2448 if (autoirq != PARPORT_IRQ_AUTO)
2449 irq = PARPORT_IRQ_NONE;
2452 * Release the resource so that parport_pc_probe_port can get it.
2454 release_resource(base_res);
2455 if (parport_pc_probe_port (ite8872_lpt, ite8872_lpthi,
2456 irq, PARPORT_DMA_NONE, NULL)) {
2458 "parport_pc: ITE 8872 parallel port: io=0x%X",
2460 if (irq != PARPORT_IRQ_NONE)
2461 printk (", irq=%d", irq);
2469 /* Via support maintained by Jeff Garzik <jgarzik@pobox.com> */
2470 static int __devinit sio_via_686a_probe (struct pci_dev *pdev, int autoirq,
2475 unsigned port1, port2, have_eppecp;
2478 * unlock super i/o configuration, set 0x85_1
2480 pci_read_config_byte (pdev, 0x85, &tmp);
2482 pci_write_config_byte (pdev, 0x85, tmp);
2485 * Super I/O configuration, index port == 3f0h, data port == 3f1h
2488 /* 0xE2_1-0: Parallel Port Mode / Enable */
2492 if ((tmp & 0x03) == 0x03) {
2493 printk (KERN_INFO "parport_pc: Via 686A parallel port disabled in BIOS\n");
2497 /* 0xE6: Parallel Port I/O Base Address, bits 9-2 */
2499 port1 = inb (0x3F1) << 2;
2502 case 0x3bc: port2 = 0x7bc; break;
2503 case 0x378: port2 = 0x778; break;
2504 case 0x278: port2 = 0x678; break;
2506 printk (KERN_INFO "parport_pc: Weird Via 686A parport base 0x%X, ignoring\n",
2511 /* 0xF0_5: EPP+ECP enable */
2513 have_eppecp = (inb (0x3F1) & (1 << 5));
2516 * lock super i/o configuration, clear 0x85_1
2518 pci_read_config_byte (pdev, 0x85, &tmp);
2520 pci_write_config_byte (pdev, 0x85, tmp);
2523 * Get DMA and IRQ from PCI->ISA bridge PCI config registers
2526 /* 0x50_3-2: PnP Routing for Parallel Port DRQ */
2527 pci_read_config_byte (pdev, 0x50, &tmp);
2528 dma = ((tmp >> 2) & 0x03);
2530 /* 0x51_7-4: PnP Routing for Parallel Port IRQ */
2531 pci_read_config_byte (pdev, 0x51, &tmp);
2532 irq = ((tmp >> 4) & 0x0F);
2534 /* filter bogus IRQs */
2540 irq = PARPORT_IRQ_NONE;
2543 default: /* do nothing */
2547 /* if ECP not enabled, DMA is not enabled, assumed bogus 'dma' value */
2549 dma = PARPORT_DMA_NONE;
2551 /* Let the user (or defaults) steer us away from interrupts and DMA */
2552 if (autoirq != PARPORT_IRQ_AUTO) {
2553 irq = PARPORT_IRQ_NONE;
2554 dma = PARPORT_DMA_NONE;
2556 if (autodma != PARPORT_DMA_AUTO)
2557 dma = PARPORT_DMA_NONE;
2559 /* finally, do the probe with values obtained */
2560 if (parport_pc_probe_port (port1, port2, irq, dma, NULL)) {
2562 "parport_pc: Via 686A parallel port: io=0x%X", port1);
2563 if (irq != PARPORT_IRQ_NONE)
2564 printk (", irq=%d", irq);
2565 if (dma != PARPORT_DMA_NONE)
2566 printk (", dma=%d", dma);
2571 printk (KERN_WARNING "parport_pc: Strange, can't probe Via 686A parallel port: io=0x%X, irq=%d, dma=%d\n",
2577 enum parport_pc_sio_types {
2578 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2583 /* each element directly indexed from enum list, above */
2584 static struct parport_pc_superio {
2585 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma);
2586 } parport_pc_superio_info[] __devinitdata = {
2587 { sio_via_686a_probe, },
2588 { sio_ite_8872_probe, },
2592 enum parport_pc_pci_cards {
2593 siig_1p_10x = last_sio,
2598 lava_parallel_dual_a,
2599 lava_parallel_dual_b,
2638 /* each element directly indexed from enum list, above
2639 * (but offset by last_sio) */
2640 static struct parport_pc_pci {
2642 struct { /* BAR (base address registers) numbers in the config
2645 int hi; /* -1 if not there, >6 for offset-method (max
2649 /* If set, this is called immediately after pci_enable_device.
2650 * If it returns non-zero, no probing will take place and the
2651 * ports will not be used. */
2652 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2654 /* If set, this is called after probing for ports. If 'failed'
2655 * is non-zero we couldn't use any of the ports. */
2656 void (*postinit_hook) (struct pci_dev *pdev, int failed);
2657 } cards[] __devinitdata = {
2658 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2659 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2660 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2661 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2662 /* lava_parallel */ { 1, { { 0, -1 }, } },
2663 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2664 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2665 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2666 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2667 /* timedia_4078a */ { 1, { { 2, -1 }, } },
2668 /* timedia_4079h */ { 1, { { 2, 3 }, } },
2669 /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
2670 /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2671 /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2672 /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2673 /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2674 /* timedia_4078u */ { 1, { { 2, -1 }, } },
2675 /* timedia_4079a */ { 1, { { 2, 3 }, } },
2676 /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
2677 /* timedia_4079r */ { 1, { { 2, 3 }, } },
2678 /* timedia_4079s */ { 1, { { 2, 3 }, } },
2679 /* timedia_4079d */ { 1, { { 2, 3 }, } },
2680 /* timedia_4079e */ { 1, { { 2, 3 }, } },
2681 /* timedia_4079f */ { 1, { { 2, 3 }, } },
2682 /* timedia_9079a */ { 1, { { 2, 3 }, } },
2683 /* timedia_9079b */ { 1, { { 2, 3 }, } },
2684 /* timedia_9079c */ { 1, { { 2, 3 }, } },
2685 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2686 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2687 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2688 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2689 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2690 /* SYBA uses fixed offsets in
2692 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2693 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2694 /* titan_010l */ { 1, { { 3, -1 }, } },
2695 /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2696 /* avlab_1p */ { 1, { { 0, 1}, } },
2697 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2698 /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2699 * and 840 locks up if you write 1 to bit 2! */
2700 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
2701 /* oxsemi_840 */ { 1, { { 0, -1 }, } },
2702 /* aks_0100 */ { 1, { { 0, -1 }, } },
2703 /* mobility_pp */ { 1, { { 0, 1 }, } },
2706 static struct pci_device_id parport_pc_pci_tbl[] = {
2707 /* Super-IO onboard chips */
2708 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2709 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2710 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2713 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2714 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2715 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2716 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2717 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2718 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2719 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2720 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2721 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2722 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2723 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2724 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2725 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2726 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2727 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2728 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2729 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2730 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0,0, plx_9050 },
2731 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2732 { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
2733 { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
2734 { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
2735 { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
2736 { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
2737 { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
2738 { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
2739 { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
2740 { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
2741 { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
2742 { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
2743 { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
2744 { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
2745 { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
2746 { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
2747 { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
2748 { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
2749 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
2750 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2751 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2752 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2753 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2754 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2755 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
2756 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2757 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2758 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2759 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2760 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2761 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2762 { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 },
2763 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
2764 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p}, /* AFAVLAB_TK9902 */
2765 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
2766 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
2767 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2768 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
2769 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
2770 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
2771 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
2772 { 0, } /* terminate list */
2774 MODULE_DEVICE_TABLE(pci,parport_pc_pci_tbl);
2776 static int parport_pc_pci_probe (struct pci_dev *dev,
2777 const struct pci_device_id *id)
2779 int err, count, n, i = id->driver_data;
2782 /* This is an onboard Super-IO and has already been probed */
2785 /* This is a PCI card */
2788 if ((err = pci_enable_device (dev)) != 0)
2791 if (cards[i].preinit_hook &&
2792 cards[i].preinit_hook (dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE))
2795 for (n = 0; n < cards[i].numports; n++) {
2796 int lo = cards[i].addr[n].lo;
2797 int hi = cards[i].addr[n].hi;
2798 unsigned long io_lo, io_hi;
2799 io_lo = pci_resource_start (dev, lo);
2801 if ((hi >= 0) && (hi <= 6))
2802 io_hi = pci_resource_start (dev, hi);
2804 io_lo += hi; /* Reinterpret the meaning of
2805 "hi" as an offset (see SYBA
2807 /* TODO: test if sharing interrupts works */
2808 printk (KERN_DEBUG "PCI parallel port detected: %04x:%04x, "
2809 "I/O at %#lx(%#lx)\n",
2810 parport_pc_pci_tbl[i + last_sio].vendor,
2811 parport_pc_pci_tbl[i + last_sio].device, io_lo, io_hi);
2812 if (parport_pc_probe_port (io_lo, io_hi, PARPORT_IRQ_NONE,
2813 PARPORT_DMA_NONE, dev))
2817 if (cards[i].postinit_hook)
2818 cards[i].postinit_hook (dev, count == 0);
2820 return count == 0 ? -ENODEV : 0;
2823 static struct pci_driver parport_pc_pci_driver = {
2824 .name = "parport_pc",
2825 .id_table = parport_pc_pci_tbl,
2826 .probe = parport_pc_pci_probe,
2829 static int __init parport_pc_init_superio (int autoirq, int autodma)
2831 const struct pci_device_id *id;
2832 struct pci_dev *pdev = NULL;
2835 while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev)) != NULL) {
2836 id = pci_match_device (parport_pc_pci_tbl, pdev);
2837 if (id == NULL || id->driver_data >= last_sio)
2840 if (parport_pc_superio_info[id->driver_data].probe
2841 (pdev, autoirq, autodma)) {
2846 return ret; /* number of devices found */
2849 static struct pci_driver parport_pc_pci_driver;
2850 static int __init parport_pc_init_superio(int autoirq, int autodma) {return 0;}
2851 #endif /* CONFIG_PCI */
2854 static const struct pnp_device_id parport_pc_pnp_tbl[] = {
2855 /* Standard LPT Printer Port */
2856 {.id = "PNP0400", .driver_data = 0},
2857 /* ECP Printer Port */
2858 {.id = "PNP0401", .driver_data = 0},
2862 MODULE_DEVICE_TABLE(pnp,parport_pc_pnp_tbl);
2864 static int parport_pc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id)
2866 struct parport *pdata;
2867 unsigned long io_lo, io_hi;
2870 if (pnp_port_valid(dev,0) &&
2871 !(pnp_port_flags(dev,0) & IORESOURCE_DISABLED)) {
2872 io_lo = pnp_port_start(dev,0);
2876 if (pnp_port_valid(dev,1) &&
2877 !(pnp_port_flags(dev,1) & IORESOURCE_DISABLED)) {
2878 io_hi = pnp_port_start(dev,1);
2882 if (pnp_irq_valid(dev,0) &&
2883 !(pnp_irq_flags(dev,0) & IORESOURCE_DISABLED)) {
2884 irq = pnp_irq(dev,0);
2886 irq = PARPORT_IRQ_NONE;
2888 if (pnp_dma_valid(dev,0) &&
2889 !(pnp_dma_flags(dev,0) & IORESOURCE_DISABLED)) {
2890 dma = pnp_dma(dev,0);
2892 dma = PARPORT_DMA_NONE;
2894 printk(KERN_INFO "parport: PnPBIOS parport detected.\n");
2895 if (!(pdata = parport_pc_probe_port (io_lo, io_hi, irq, dma, NULL)))
2898 pnp_set_drvdata(dev,pdata);
2902 static void parport_pc_pnp_remove(struct pnp_dev *dev)
2904 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
2908 parport_pc_unregister_port(pdata);
2911 /* we only need the pnp layer to activate the device, at least for now */
2912 static struct pnp_driver parport_pc_pnp_driver = {
2913 .name = "parport_pc",
2914 .id_table = parport_pc_pnp_tbl,
2915 .probe = parport_pc_pnp_probe,
2916 .remove = parport_pc_pnp_remove,
2920 /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
2921 static int __init __attribute__((unused))
2922 parport_pc_find_isa_ports (int autoirq, int autodma)
2926 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL))
2928 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL))
2930 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL))
2936 /* This function is called by parport_pc_init if the user didn't
2937 * specify any ports to probe. Its job is to find some ports. Order
2938 * is important here -- we want ISA ports to be registered first,
2939 * followed by PCI cards (for least surprise), but before that we want
2940 * to do chipset-specific tests for some onboard ports that we know
2943 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
2944 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
2946 static int __init parport_pc_find_ports (int autoirq, int autodma)
2950 #ifdef CONFIG_PARPORT_PC_SUPERIO
2951 detect_and_report_winbond ();
2952 detect_and_report_smsc ();
2955 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
2956 count += parport_pc_init_superio (autoirq, autodma);
2958 /* PnP ports, skip detection if SuperIO already found them */
2960 r = pnp_register_driver (&parport_pc_pnp_driver);
2962 pnp_registered_parport = 1;
2967 /* ISA ports and whatever (see asm/parport.h). */
2968 count += parport_pc_find_nonpci_ports (autoirq, autodma);
2970 r = pci_register_driver (&parport_pc_pci_driver);
2972 pci_registered_parport = 1;
2980 * Piles of crap below pretend to be a parser for module and kernel
2981 * parameters. Say "thank you" to whoever had come up with that
2982 * syntax and keep in mind that code below is a cleaned up version.
2985 static int __initdata io[PARPORT_PC_MAX_PORTS+1] = { [0 ... PARPORT_PC_MAX_PORTS] = 0 };
2986 static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] =
2987 { [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO };
2988 static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE };
2989 static int __initdata irqval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY };
2991 static int __init parport_parse_param(const char *s, int *val,
2992 int automatic, int none, int nofifo)
2996 if (!strncmp(s, "auto", 4))
2998 else if (!strncmp(s, "none", 4))
3000 else if (nofifo && !strncmp(s, "nofifo", 4))
3004 unsigned long r = simple_strtoul(s, &ep, 0);
3008 printk(KERN_ERR "parport: bad specifier `%s'\n", s);
3015 static int __init parport_parse_irq(const char *irqstr, int *val)
3017 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3018 PARPORT_IRQ_NONE, 0);
3021 static int __init parport_parse_dma(const char *dmastr, int *val)
3023 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3024 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3028 static const char *irq[PARPORT_PC_MAX_PORTS];
3029 static const char *dma[PARPORT_PC_MAX_PORTS];
3031 MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3032 MODULE_PARM(io, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "i");
3033 MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3034 MODULE_PARM(io_hi, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "i");
3035 MODULE_PARM_DESC(irq, "IRQ line");
3036 MODULE_PARM(irq, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "s");
3037 MODULE_PARM_DESC(dma, "DMA channel");
3038 MODULE_PARM(dma, "1-" __MODULE_STRING(PARPORT_PC_MAX_PORTS) "s");
3039 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3040 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3041 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3042 MODULE_PARM(verbose_probing, "i");
3045 static int __init parse_parport_params(void)
3050 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3051 if (parport_parse_irq(irq[i], &val))
3054 if (parport_parse_dma(dma[i], &val))
3059 /* The user can make us use any IRQs or DMAs we find. */
3060 if (irq[0] && !parport_parse_irq(irq[0], &val))
3062 case PARPORT_IRQ_NONE:
3063 case PARPORT_IRQ_AUTO:
3067 printk (KERN_WARNING
3068 "parport_pc: irq specified "
3069 "without base address. Use 'io=' "
3070 "to specify one\n");
3073 if (dma[0] && !parport_parse_dma(dma[0], &val))
3075 case PARPORT_DMA_NONE:
3076 case PARPORT_DMA_AUTO:
3080 printk (KERN_WARNING
3081 "parport_pc: dma specified "
3082 "without base address. Use 'io=' "
3083 "to specify one\n");
3091 static int parport_setup_ptr __initdata = 0;
3094 * Acceptable parameters:
3098 * parport=0xBASE[,IRQ[,DMA]]
3100 * IRQ/DMA may be numeric or 'auto' or 'none'
3102 static int __init parport_setup (char *str)
3108 if (!str || !*str || (*str == '0' && !*(str+1))) {
3109 /* Disable parport if "parport=0" in cmdline */
3110 io[0] = PARPORT_DISABLE;
3114 if (!strncmp (str, "auto", 4)) {
3115 irqval[0] = PARPORT_IRQ_AUTO;
3116 dmaval[0] = PARPORT_DMA_AUTO;
3120 val = simple_strtoul (str, &endptr, 0);
3121 if (endptr == str) {
3122 printk (KERN_WARNING "parport=%s not understood\n", str);
3126 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3127 printk(KERN_ERR "parport=%s ignored, too many ports\n", str);
3131 io[parport_setup_ptr] = val;
3132 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3133 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3135 sep = strchr(str, ',');
3137 if (parport_parse_irq(sep, &val))
3139 irqval[parport_setup_ptr] = val;
3140 sep = strchr(sep, ',');
3142 if (parport_parse_dma(sep, &val))
3144 dmaval[parport_setup_ptr] = val;
3147 parport_setup_ptr++;
3151 static int __init parse_parport_params(void)
3153 return io[0] == PARPORT_DISABLE;
3156 __setup ("parport=", parport_setup);
3159 /* "Parser" ends here */
3161 static int __init parport_pc_init(void)
3165 if (parse_parport_params())
3170 /* Only probe the ports we were given. */
3172 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3175 if ((io_hi[i]) == PARPORT_IOHI_AUTO)
3176 io_hi[i] = 0x400 + io[i];
3177 if (parport_pc_probe_port(io[i], io_hi[i],
3178 irqval[i], dmaval[i], NULL))
3182 count += parport_pc_find_ports (irqval[0], dmaval[0]);
3187 static void __exit parport_pc_exit(void)
3189 if (pci_registered_parport)
3190 pci_unregister_driver (&parport_pc_pci_driver);
3191 if (pnp_registered_parport)
3192 pnp_unregister_driver (&parport_pc_pnp_driver);
3194 spin_lock(&ports_lock);
3195 while (!list_empty(&ports_list)) {
3196 struct parport_pc_private *priv;
3197 struct parport *port;
3198 priv = list_entry(ports_list.next,
3199 struct parport_pc_private, list);
3201 spin_unlock(&ports_lock);
3202 parport_pc_unregister_port(port);
3203 spin_lock(&ports_lock);
3205 spin_unlock(&ports_lock);
3208 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3209 MODULE_DESCRIPTION("PC-style parallel port driver");
3210 MODULE_LICENSE("GPL");
3211 module_init(parport_pc_init)
3212 module_exit(parport_pc_exit)