1 /* Low-level parallel-port routines for 8255-based PC-style hardware.
3 * Authors: Phil Blundell <Philip.Blundell@pobox.com>
4 * Tim Waugh <tim@cyberelk.demon.co.uk>
5 * Jose Renau <renau@acm.org>
6 * David Campbell <campbell@torque.net>
9 * based on work by Grant Guenther <grant@torque.net> and Phil Blundell.
11 * Cleaned up include files - Russell King <linux@arm.uk.linux.org>
12 * DMA support - Bert De Jonghe <bert@sophis.be>
13 * Many ECP bugs fixed. Fred Barnes & Jamie Lokier, 1999
14 * More PCI support now conditional on CONFIG_PCI, 03/2001, Paul G.
15 * Various hacks, Fred Barnes, 04/2001
16 * Updated probing logic - Adam Belay <ambx1@neo.rr.com>
19 /* This driver should work with any hardware that is broadly compatible
20 * with that in the IBM PC. This applies to the majority of integrated
21 * I/O chipsets that are commonly available. The expected register
28 * In addition, there are some optional registers:
32 * base+0x400 ECP config A
33 * base+0x401 ECP config B
34 * base+0x402 ECP control
36 * All registers are 8 bits wide and read/write. If your hardware differs
37 * only in register addresses (eg because your registers are on 32-bit
38 * word boundaries) then you can alter the constants in parport_pc.h to
41 * Note that the ECP registers may not start at offset 0x400 for PCI cards,
42 * but rather will start at port->base_hi.
45 #include <linux/config.h>
46 #include <linux/module.h>
47 #include <linux/init.h>
48 #include <linux/sched.h>
49 #include <linux/delay.h>
50 #include <linux/errno.h>
51 #include <linux/interrupt.h>
52 #include <linux/ioport.h>
53 #include <linux/kernel.h>
54 #include <linux/slab.h>
55 #include <linux/pci.h>
56 #include <linux/pnp.h>
57 #include <linux/sysctl.h>
61 #include <asm/uaccess.h>
63 #include <linux/parport.h>
64 #include <linux/parport_pc.h>
65 #include <linux/via.h>
66 #include <asm/parport.h>
68 #define PARPORT_PC_MAX_PORTS PARPORT_MAX
79 #define ECR_MODE_MASK 0xe0
80 #define ECR_WRITE(p,v) frob_econtrol((p),0xff,(v))
85 #define DPRINTK printk
87 #define DPRINTK(stuff...)
92 static struct superio_struct { /* For Super-IO chips autodetection */
96 } superios[NR_SUPERIOS] __devinitdata = { {0,},};
98 static int user_specified;
99 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
100 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
101 static int verbose_probing;
103 static int pci_registered_parport;
104 static int pnp_registered_parport;
106 /* frob_control, but for ECR */
107 static void frob_econtrol (struct parport *pb, unsigned char m,
110 unsigned char ectr = 0;
113 ectr = inb (ECONTROL (pb));
115 DPRINTK (KERN_DEBUG "frob_econtrol(%02x,%02x): %02x -> %02x\n",
116 m, v, ectr, (ectr & ~m) ^ v);
118 outb ((ectr & ~m) ^ v, ECONTROL (pb));
121 static __inline__ void frob_set_mode (struct parport *p, int mode)
123 frob_econtrol (p, ECR_MODE_MASK, mode << 5);
126 #ifdef CONFIG_PARPORT_PC_FIFO
127 /* Safely change the mode bits in the ECR
130 -EBUSY: Could not drain FIFO in some finite amount of time,
133 static int change_mode(struct parport *p, int m)
135 const struct parport_pc_private *priv = p->physport->private_data;
139 DPRINTK(KERN_INFO "parport change_mode ECP-ISA to mode 0x%02x\n",m);
142 printk (KERN_DEBUG "change_mode: but there's no ECR!\n");
146 /* Bits <7:5> contain the mode. */
147 oecr = inb (ECONTROL (p));
148 mode = (oecr >> 5) & 0x7;
149 if (mode == m) return 0;
151 if (mode >= 2 && !(priv->ctr & 0x20)) {
152 /* This mode resets the FIFO, so we may
153 * have to wait for it to drain first. */
154 unsigned long expire = jiffies + p->physport->cad->timeout;
157 case ECR_PPF: /* Parallel Port FIFO mode */
158 case ECR_ECP: /* ECP Parallel Port mode */
159 /* Busy wait for 200us */
160 for (counter = 0; counter < 40; counter++) {
161 if (inb (ECONTROL (p)) & 0x01)
163 if (signal_pending (current)) break;
168 while (!(inb (ECONTROL (p)) & 0x01)) {
169 if (time_after_eq (jiffies, expire))
170 /* The FIFO is stuck. */
172 __set_current_state (TASK_INTERRUPTIBLE);
173 schedule_timeout ((HZ + 99) / 100);
174 if (signal_pending (current))
180 if (mode >= 2 && m >= 2) {
181 /* We have to go through mode 001 */
183 oecr |= ECR_PS2 << 5;
194 #ifdef CONFIG_PARPORT_1284
195 /* Find FIFO lossage; FIFO is reset */
196 static int get_fifo_residue (struct parport *p)
200 const struct parport_pc_private *priv = p->physport->private_data;
202 /* Adjust for the contents of the FIFO. */
203 for (residue = priv->fifo_depth; ; residue--) {
204 if (inb (ECONTROL (p)) & 0x2)
211 printk (KERN_DEBUG "%s: %d PWords were left in FIFO\n", p->name,
214 /* Reset the FIFO. */
215 frob_set_mode (p, ECR_PS2);
217 /* Now change to config mode and clean up. FIXME */
218 frob_set_mode (p, ECR_CNF);
219 cnfga = inb (CONFIGA (p));
220 printk (KERN_DEBUG "%s: cnfgA contains 0x%02x\n", p->name, cnfga);
222 if (!(cnfga & (1<<2))) {
223 printk (KERN_DEBUG "%s: Accounting for extra byte\n", p->name);
227 /* Don't care about partial PWords until support is added for
228 * PWord != 1 byte. */
230 /* Back to PS2 mode. */
231 frob_set_mode (p, ECR_PS2);
233 DPRINTK (KERN_DEBUG "*** get_fifo_residue: done residue collecting (ecr = 0x%2.2x)\n", inb (ECONTROL (p)));
236 #endif /* IEEE 1284 support */
237 #endif /* FIFO support */
240 * Clear TIMEOUT BIT in EPP MODE
242 * This is also used in SPP detection.
244 static int clear_epp_timeout(struct parport *pb)
248 if (!(parport_pc_read_status(pb) & 0x01))
251 /* To clear timeout some chips require double read */
252 parport_pc_read_status(pb);
253 r = parport_pc_read_status(pb);
254 outb (r | 0x01, STATUS (pb)); /* Some reset by writing 1 */
255 outb (r & 0xfe, STATUS (pb)); /* Others by writing 0 */
256 r = parport_pc_read_status(pb);
264 * Most of these aren't static because they may be used by the
265 * parport_xxx_yyy macros. extern __inline__ versions of several
266 * of these are in parport_pc.h.
269 static irqreturn_t parport_pc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
271 parport_generic_irq(irq, (struct parport *) dev_id, regs);
272 /* FIXME! Was it really ours? */
276 void parport_pc_init_state(struct pardevice *dev, struct parport_state *s)
280 dev->port->irq != PARPORT_IRQ_NONE)
284 s->u.pc.ecr = 0x34; /* NetMos chip can cause problems 0x24;
288 void parport_pc_save_state(struct parport *p, struct parport_state *s)
290 const struct parport_pc_private *priv = p->physport->private_data;
291 s->u.pc.ctr = priv->ctr;
293 s->u.pc.ecr = inb (ECONTROL (p));
296 void parport_pc_restore_state(struct parport *p, struct parport_state *s)
298 struct parport_pc_private *priv = p->physport->private_data;
299 register unsigned char c = s->u.pc.ctr & priv->ctr_writable;
300 outb (c, CONTROL (p));
303 ECR_WRITE (p, s->u.pc.ecr);
306 #ifdef CONFIG_PARPORT_1284
307 static size_t parport_pc_epp_read_data (struct parport *port, void *buf,
308 size_t length, int flags)
312 if (flags & PARPORT_W91284PIC) {
313 unsigned char status;
314 size_t left = length;
316 /* use knowledge about data lines..:
317 * nFault is 0 if there is at least 1 byte in the Warp's FIFO
318 * pError is 1 if there are 16 bytes in the Warp's FIFO
320 status = inb (STATUS (port));
322 while (!(status & 0x08) && (got < length)) {
323 if ((left >= 16) && (status & 0x20) && !(status & 0x08)) {
324 /* can grab 16 bytes from warp fifo */
325 if (!((long)buf & 0x03)) {
326 insl (EPPDATA (port), buf, 4);
328 insb (EPPDATA (port), buf, 16);
334 /* grab single byte from the warp fifo */
335 *((char *)buf) = inb (EPPDATA (port));
340 status = inb (STATUS (port));
342 /* EPP timeout should never occur... */
343 printk (KERN_DEBUG "%s: EPP timeout occurred while talking to "
344 "w91284pic (should not have done)\n", port->name);
345 clear_epp_timeout (port);
350 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
351 if (!(((long)buf | length) & 0x03)) {
352 insl (EPPDATA (port), buf, (length >> 2));
354 insb (EPPDATA (port), buf, length);
356 if (inb (STATUS (port)) & 0x01) {
357 clear_epp_timeout (port);
362 for (; got < length; got++) {
363 *((char*)buf) = inb (EPPDATA(port));
365 if (inb (STATUS (port)) & 0x01) {
367 clear_epp_timeout (port);
375 static size_t parport_pc_epp_write_data (struct parport *port, const void *buf,
376 size_t length, int flags)
380 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
381 if (!(((long)buf | length) & 0x03)) {
382 outsl (EPPDATA (port), buf, (length >> 2));
384 outsb (EPPDATA (port), buf, length);
386 if (inb (STATUS (port)) & 0x01) {
387 clear_epp_timeout (port);
392 for (; written < length; written++) {
393 outb (*((char*)buf), EPPDATA(port));
395 if (inb (STATUS(port)) & 0x01) {
396 clear_epp_timeout (port);
404 static size_t parport_pc_epp_read_addr (struct parport *port, void *buf,
405 size_t length, int flags)
409 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
410 insb (EPPADDR (port), buf, length);
411 if (inb (STATUS (port)) & 0x01) {
412 clear_epp_timeout (port);
417 for (; got < length; got++) {
418 *((char*)buf) = inb (EPPADDR (port));
420 if (inb (STATUS (port)) & 0x01) {
421 clear_epp_timeout (port);
429 static size_t parport_pc_epp_write_addr (struct parport *port,
430 const void *buf, size_t length,
435 if ((flags & PARPORT_EPP_FAST) && (length > 1)) {
436 outsb (EPPADDR (port), buf, length);
437 if (inb (STATUS (port)) & 0x01) {
438 clear_epp_timeout (port);
443 for (; written < length; written++) {
444 outb (*((char*)buf), EPPADDR (port));
446 if (inb (STATUS (port)) & 0x01) {
447 clear_epp_timeout (port);
455 static size_t parport_pc_ecpepp_read_data (struct parport *port, void *buf,
456 size_t length, int flags)
460 frob_set_mode (port, ECR_EPP);
461 parport_pc_data_reverse (port);
462 parport_pc_write_control (port, 0x4);
463 got = parport_pc_epp_read_data (port, buf, length, flags);
464 frob_set_mode (port, ECR_PS2);
469 static size_t parport_pc_ecpepp_write_data (struct parport *port,
470 const void *buf, size_t length,
475 frob_set_mode (port, ECR_EPP);
476 parport_pc_write_control (port, 0x4);
477 parport_pc_data_forward (port);
478 written = parport_pc_epp_write_data (port, buf, length, flags);
479 frob_set_mode (port, ECR_PS2);
484 static size_t parport_pc_ecpepp_read_addr (struct parport *port, void *buf,
485 size_t length, int flags)
489 frob_set_mode (port, ECR_EPP);
490 parport_pc_data_reverse (port);
491 parport_pc_write_control (port, 0x4);
492 got = parport_pc_epp_read_addr (port, buf, length, flags);
493 frob_set_mode (port, ECR_PS2);
498 static size_t parport_pc_ecpepp_write_addr (struct parport *port,
499 const void *buf, size_t length,
504 frob_set_mode (port, ECR_EPP);
505 parport_pc_write_control (port, 0x4);
506 parport_pc_data_forward (port);
507 written = parport_pc_epp_write_addr (port, buf, length, flags);
508 frob_set_mode (port, ECR_PS2);
512 #endif /* IEEE 1284 support */
514 #ifdef CONFIG_PARPORT_PC_FIFO
515 static size_t parport_pc_fifo_write_block_pio (struct parport *port,
516 const void *buf, size_t length)
519 const unsigned char *bufp = buf;
520 size_t left = length;
521 unsigned long expire = jiffies + port->physport->cad->timeout;
522 const int fifo = FIFO (port);
523 int poll_for = 8; /* 80 usecs */
524 const struct parport_pc_private *priv = port->physport->private_data;
525 const int fifo_depth = priv->fifo_depth;
527 port = port->physport;
529 /* We don't want to be interrupted every character. */
530 parport_pc_disable_irq (port);
531 /* set nErrIntrEn and serviceIntr */
532 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
535 parport_pc_data_forward (port); /* Must be in PS2 mode */
539 unsigned char ecrval = inb (ECONTROL (port));
542 if (need_resched() && time_before (jiffies, expire))
543 /* Can't yield the port. */
546 /* Anyone else waiting for the port? */
547 if (port->waithead) {
548 printk (KERN_DEBUG "Somebody wants the port\n");
553 /* FIFO is full. Wait for interrupt. */
555 /* Clear serviceIntr */
556 ECR_WRITE (port, ecrval & ~(1<<2));
558 ret = parport_wait_event (port, HZ);
561 if (!time_before (jiffies, expire)) {
563 printk (KERN_DEBUG "FIFO write timed out\n");
566 ecrval = inb (ECONTROL (port));
567 if (!(ecrval & (1<<2))) {
568 if (need_resched() &&
569 time_before (jiffies, expire))
578 /* Can't fail now. */
579 expire = jiffies + port->cad->timeout;
582 if (signal_pending (current))
586 /* FIFO is empty. Blast it full. */
587 const int n = left < fifo_depth ? left : fifo_depth;
588 outsb (fifo, bufp, n);
592 /* Adjust the poll time. */
593 if (i < (poll_for - 2)) poll_for--;
595 } else if (i++ < poll_for) {
597 ecrval = inb (ECONTROL (port));
601 /* Half-full (call me an optimist) */
607 dump_parport_state ("leave fifo_write_block_pio", port);
608 return length - left;
611 static size_t parport_pc_fifo_write_block_dma (struct parport *port,
612 const void *buf, size_t length)
615 unsigned long dmaflag;
616 size_t left = length;
617 const struct parport_pc_private *priv = port->physport->private_data;
618 dma_addr_t dma_addr, dma_handle;
619 size_t maxlen = 0x10000; /* max 64k per DMA transfer */
620 unsigned long start = (unsigned long) buf;
621 unsigned long end = (unsigned long) buf + length - 1;
623 dump_parport_state ("enter fifo_write_block_dma", port);
624 if (end < MAX_DMA_ADDRESS) {
625 /* If it would cross a 64k boundary, cap it at the end. */
626 if ((start ^ end) & ~0xffffUL)
627 maxlen = 0x10000 - (start & 0xffff);
629 dma_addr = dma_handle = pci_map_single(priv->dev, (void *)buf, length,
632 /* above 16 MB we use a bounce buffer as ISA-DMA is not possible */
633 maxlen = PAGE_SIZE; /* sizeof(priv->dma_buf) */
634 dma_addr = priv->dma_handle;
638 port = port->physport;
640 /* We don't want to be interrupted every character. */
641 parport_pc_disable_irq (port);
642 /* set nErrIntrEn and serviceIntr */
643 frob_econtrol (port, (1<<4) | (1<<2), (1<<4) | (1<<2));
646 parport_pc_data_forward (port); /* Must be in PS2 mode */
649 unsigned long expire = jiffies + port->physport->cad->timeout;
656 if (!dma_handle) /* bounce buffer ! */
657 memcpy(priv->dma_buf, buf, count);
659 dmaflag = claim_dma_lock();
660 disable_dma(port->dma);
661 clear_dma_ff(port->dma);
662 set_dma_mode(port->dma, DMA_MODE_WRITE);
663 set_dma_addr(port->dma, dma_addr);
664 set_dma_count(port->dma, count);
667 frob_econtrol (port, 1<<3, 1<<3);
669 /* Clear serviceIntr */
670 frob_econtrol (port, 1<<2, 0);
672 enable_dma(port->dma);
673 release_dma_lock(dmaflag);
675 /* assume DMA will be successful */
678 if (dma_handle) dma_addr += count;
680 /* Wait for interrupt. */
682 ret = parport_wait_event (port, HZ);
685 if (!time_before (jiffies, expire)) {
687 printk (KERN_DEBUG "DMA write timed out\n");
690 /* Is serviceIntr set? */
691 if (!(inb (ECONTROL (port)) & (1<<2))) {
697 dmaflag = claim_dma_lock();
698 disable_dma(port->dma);
699 clear_dma_ff(port->dma);
700 count = get_dma_residue(port->dma);
701 release_dma_lock(dmaflag);
703 cond_resched(); /* Can't yield the port. */
705 /* Anyone else waiting for the port? */
706 if (port->waithead) {
707 printk (KERN_DEBUG "Somebody wants the port\n");
711 /* update for possible DMA residue ! */
714 if (dma_handle) dma_addr -= count;
717 /* Maybe got here through break, so adjust for DMA residue! */
718 dmaflag = claim_dma_lock();
719 disable_dma(port->dma);
720 clear_dma_ff(port->dma);
721 left += get_dma_residue(port->dma);
722 release_dma_lock(dmaflag);
724 /* Turn off DMA mode */
725 frob_econtrol (port, 1<<3, 0);
728 pci_unmap_single(priv->dev, dma_handle, length, PCI_DMA_TODEVICE);
730 dump_parport_state ("leave fifo_write_block_dma", port);
731 return length - left;
734 /* Parallel Port FIFO mode (ECP chipsets) */
735 size_t parport_pc_compat_write_block_pio (struct parport *port,
736 const void *buf, size_t length,
741 unsigned long expire;
742 const struct parport_pc_private *priv = port->physport->private_data;
744 /* Special case: a timeout of zero means we cannot call schedule().
745 * Also if O_NONBLOCK is set then use the default implementation. */
746 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
747 return parport_ieee1284_write_compat (port, buf,
750 /* Set up parallel port FIFO mode.*/
751 parport_pc_data_forward (port); /* Must be in PS2 mode */
752 parport_pc_frob_control (port, PARPORT_CONTROL_STROBE, 0);
753 r = change_mode (port, ECR_PPF); /* Parallel port FIFO */
754 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_PPF failed\n", port->name);
756 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
758 /* Write the data to the FIFO. */
759 if (port->dma != PARPORT_DMA_NONE)
760 written = parport_pc_fifo_write_block_dma (port, buf, length);
762 written = parport_pc_fifo_write_block_pio (port, buf, length);
765 /* For some hardware we don't want to touch the mode until
766 * the FIFO is empty, so allow 4 seconds for each position
769 expire = jiffies + (priv->fifo_depth * HZ * 4);
771 /* Wait for the FIFO to empty */
772 r = change_mode (port, ECR_PS2);
776 } while (time_before (jiffies, expire));
779 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
781 /* Prevent further data transfer. */
782 frob_set_mode (port, ECR_TST);
784 /* Adjust for the contents of the FIFO. */
785 for (written -= priv->fifo_depth; ; written++) {
786 if (inb (ECONTROL (port)) & 0x2) {
790 outb (0, FIFO (port));
793 /* Reset the FIFO and return to PS2 mode. */
794 frob_set_mode (port, ECR_PS2);
797 r = parport_wait_peripheral (port,
799 PARPORT_STATUS_BUSY);
802 "%s: BUSY timeout (%d) in compat_write_block_pio\n",
805 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
811 #ifdef CONFIG_PARPORT_1284
812 size_t parport_pc_ecp_write_block_pio (struct parport *port,
813 const void *buf, size_t length,
818 unsigned long expire;
819 const struct parport_pc_private *priv = port->physport->private_data;
821 /* Special case: a timeout of zero means we cannot call schedule().
822 * Also if O_NONBLOCK is set then use the default implementation. */
823 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
824 return parport_ieee1284_ecp_write_data (port, buf,
827 /* Switch to forward mode if necessary. */
828 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
829 /* Event 47: Set nInit high. */
830 parport_frob_control (port,
832 | PARPORT_CONTROL_AUTOFD,
834 | PARPORT_CONTROL_AUTOFD);
836 /* Event 49: PError goes high. */
837 r = parport_wait_peripheral (port,
838 PARPORT_STATUS_PAPEROUT,
839 PARPORT_STATUS_PAPEROUT);
841 printk (KERN_DEBUG "%s: PError timeout (%d) "
842 "in ecp_write_block_pio\n", port->name, r);
846 /* Set up ECP parallel port mode.*/
847 parport_pc_data_forward (port); /* Must be in PS2 mode */
848 parport_pc_frob_control (port,
849 PARPORT_CONTROL_STROBE |
850 PARPORT_CONTROL_AUTOFD,
852 r = change_mode (port, ECR_ECP); /* ECP FIFO */
853 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
854 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
856 /* Write the data to the FIFO. */
857 if (port->dma != PARPORT_DMA_NONE)
858 written = parport_pc_fifo_write_block_dma (port, buf, length);
860 written = parport_pc_fifo_write_block_pio (port, buf, length);
863 /* For some hardware we don't want to touch the mode until
864 * the FIFO is empty, so allow 4 seconds for each position
867 expire = jiffies + (priv->fifo_depth * (HZ * 4));
869 /* Wait for the FIFO to empty */
870 r = change_mode (port, ECR_PS2);
874 } while (time_before (jiffies, expire));
877 printk (KERN_DEBUG "%s: FIFO is stuck\n", port->name);
879 /* Prevent further data transfer. */
880 frob_set_mode (port, ECR_TST);
882 /* Adjust for the contents of the FIFO. */
883 for (written -= priv->fifo_depth; ; written++) {
884 if (inb (ECONTROL (port)) & 0x2) {
888 outb (0, FIFO (port));
891 /* Reset the FIFO and return to PS2 mode. */
892 frob_set_mode (port, ECR_PS2);
894 /* Host transfer recovery. */
895 parport_pc_data_reverse (port); /* Must be in PS2 mode */
897 parport_frob_control (port, PARPORT_CONTROL_INIT, 0);
898 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
900 printk (KERN_DEBUG "%s: PE,1 timeout (%d) "
901 "in ecp_write_block_pio\n", port->name, r);
903 parport_frob_control (port,
904 PARPORT_CONTROL_INIT,
905 PARPORT_CONTROL_INIT);
906 r = parport_wait_peripheral (port,
907 PARPORT_STATUS_PAPEROUT,
908 PARPORT_STATUS_PAPEROUT);
910 printk (KERN_DEBUG "%s: PE,2 timeout (%d) "
911 "in ecp_write_block_pio\n", port->name, r);
914 r = parport_wait_peripheral (port,
916 PARPORT_STATUS_BUSY);
919 "%s: BUSY timeout (%d) in ecp_write_block_pio\n",
922 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
927 size_t parport_pc_ecp_read_block_pio (struct parport *port,
928 void *buf, size_t length, int flags)
930 size_t left = length;
933 const int fifo = FIFO(port);
934 const struct parport_pc_private *priv = port->physport->private_data;
935 const int fifo_depth = priv->fifo_depth;
938 port = port->physport;
939 DPRINTK (KERN_DEBUG "parport_pc: parport_pc_ecp_read_block_pio\n");
940 dump_parport_state ("enter fcn", port);
942 /* Special case: a timeout of zero means we cannot call schedule().
943 * Also if O_NONBLOCK is set then use the default implementation. */
944 if (port->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
945 return parport_ieee1284_ecp_read_data (port, buf,
948 if (port->ieee1284.mode == IEEE1284_MODE_ECPRLE) {
949 /* If the peripheral is allowed to send RLE compressed
950 * data, it is possible for a byte to expand to 128
951 * bytes in the FIFO. */
954 fifofull = fifo_depth;
957 /* If the caller wants less than a full FIFO's worth of data,
958 * go through software emulation. Otherwise we may have to throw
960 if (length < fifofull)
961 return parport_ieee1284_ecp_read_data (port, buf,
964 if (port->ieee1284.phase != IEEE1284_PH_REV_IDLE) {
965 /* change to reverse-idle phase (must be in forward-idle) */
967 /* Event 38: Set nAutoFd low (also make sure nStrobe is high) */
968 parport_frob_control (port,
969 PARPORT_CONTROL_AUTOFD
970 | PARPORT_CONTROL_STROBE,
971 PARPORT_CONTROL_AUTOFD);
972 parport_pc_data_reverse (port); /* Must be in PS2 mode */
974 /* Event 39: Set nInit low to initiate bus reversal */
975 parport_frob_control (port,
976 PARPORT_CONTROL_INIT,
978 /* Event 40: Wait for nAckReverse (PError) to go low */
979 r = parport_wait_peripheral (port, PARPORT_STATUS_PAPEROUT, 0);
981 printk (KERN_DEBUG "%s: PE timeout Event 40 (%d) "
982 "in ecp_read_block_pio\n", port->name, r);
987 /* Set up ECP FIFO mode.*/
988 /* parport_pc_frob_control (port,
989 PARPORT_CONTROL_STROBE |
990 PARPORT_CONTROL_AUTOFD,
991 PARPORT_CONTROL_AUTOFD); */
992 r = change_mode (port, ECR_ECP); /* ECP FIFO */
993 if (r) printk (KERN_DEBUG "%s: Warning change_mode ECR_ECP failed\n", port->name);
995 port->ieee1284.phase = IEEE1284_PH_REV_DATA;
997 /* the first byte must be collected manually */
998 dump_parport_state ("pre 43", port);
999 /* Event 43: Wait for nAck to go low */
1000 r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, 0);
1002 /* timed out while reading -- no data */
1003 printk (KERN_DEBUG "PIO read timed out (initial byte)\n");
1007 *bufp++ = inb (DATA (port));
1009 dump_parport_state ("43-44", port);
1010 /* Event 44: nAutoFd (HostAck) goes high to acknowledge */
1011 parport_pc_frob_control (port,
1012 PARPORT_CONTROL_AUTOFD,
1014 dump_parport_state ("pre 45", port);
1015 /* Event 45: Wait for nAck to go high */
1016 /* r = parport_wait_peripheral (port, PARPORT_STATUS_ACK, PARPORT_STATUS_ACK); */
1017 dump_parport_state ("post 45", port);
1020 /* timed out while waiting for peripheral to respond to ack */
1021 printk (KERN_DEBUG "ECP PIO read timed out (waiting for nAck)\n");
1023 /* keep hold of the byte we've got already */
1026 /* Event 46: nAutoFd (HostAck) goes low to accept more data */
1027 parport_pc_frob_control (port,
1028 PARPORT_CONTROL_AUTOFD,
1029 PARPORT_CONTROL_AUTOFD);
1032 dump_parport_state ("rev idle", port);
1033 /* Do the transfer. */
1034 while (left > fifofull) {
1036 unsigned long expire = jiffies + port->cad->timeout;
1037 unsigned char ecrval = inb (ECONTROL (port));
1039 if (need_resched() && time_before (jiffies, expire))
1040 /* Can't yield the port. */
1043 /* At this point, the FIFO may already be full. In
1044 * that case ECP is already holding back the
1045 * peripheral (assuming proper design) with a delayed
1046 * handshake. Work fast to avoid a peripheral
1049 if (ecrval & 0x01) {
1050 /* FIFO is empty. Wait for interrupt. */
1051 dump_parport_state ("FIFO empty", port);
1053 /* Anyone else waiting for the port? */
1054 if (port->waithead) {
1055 printk (KERN_DEBUG "Somebody wants the port\n");
1059 /* Clear serviceIntr */
1060 ECR_WRITE (port, ecrval & ~(1<<2));
1062 dump_parport_state ("waiting", port);
1063 ret = parport_wait_event (port, HZ);
1064 DPRINTK (KERN_DEBUG "parport_wait_event returned %d\n", ret);
1068 if (!time_before (jiffies, expire)) {
1070 dump_parport_state ("timeout", port);
1071 printk (KERN_DEBUG "PIO read timed out\n");
1074 ecrval = inb (ECONTROL (port));
1075 if (!(ecrval & (1<<2))) {
1076 if (need_resched() &&
1077 time_before (jiffies, expire)) {
1083 /* Depending on how the FIFO threshold was
1084 * set, how long interrupt service took, and
1085 * how fast the peripheral is, we might be
1086 * lucky and have a just filled FIFO. */
1090 if (ecrval & 0x02) {
1092 dump_parport_state ("FIFO full", port);
1093 insb (fifo, bufp, fifo_depth);
1099 DPRINTK (KERN_DEBUG "*** ecp_read_block_pio: reading one byte from the FIFO\n");
1101 /* FIFO not filled. We will cycle this loop for a while
1102 * and either the peripheral will fill it faster,
1103 * tripping a fast empty with insb, or we empty it. */
1104 *bufp++ = inb (fifo);
1108 /* scoop up anything left in the FIFO */
1109 while (left && !(inb (ECONTROL (port) & 0x01))) {
1110 *bufp++ = inb (fifo);
1114 port->ieee1284.phase = IEEE1284_PH_REV_IDLE;
1115 dump_parport_state ("rev idle2", port);
1119 /* Go to forward idle mode to shut the peripheral up (event 47). */
1120 parport_frob_control (port, PARPORT_CONTROL_INIT, PARPORT_CONTROL_INIT);
1122 /* event 49: PError goes high */
1123 r = parport_wait_peripheral (port,
1124 PARPORT_STATUS_PAPEROUT,
1125 PARPORT_STATUS_PAPEROUT);
1128 "%s: PE timeout FWDIDLE (%d) in ecp_read_block_pio\n",
1132 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1136 int lost = get_fifo_residue (port);
1138 /* Shouldn't happen with compliant peripherals. */
1139 printk (KERN_DEBUG "%s: DATA LOSS (%d bytes)!\n",
1143 dump_parport_state ("fwd idle", port);
1144 return length - left;
1147 #endif /* IEEE 1284 support */
1148 #endif /* Allowed to use FIFO/DMA */
1152 * ******************************************
1153 * INITIALISATION AND MODULE STUFF BELOW HERE
1154 * ******************************************
1157 /* GCC is not inlining extern inline function later overwriten to non-inline,
1158 so we use outlined_ variants here. */
1159 struct parport_operations parport_pc_ops =
1161 .write_data = parport_pc_write_data,
1162 .read_data = parport_pc_read_data,
1164 .write_control = parport_pc_write_control,
1165 .read_control = parport_pc_read_control,
1166 .frob_control = parport_pc_frob_control,
1168 .read_status = parport_pc_read_status,
1170 .enable_irq = parport_pc_enable_irq,
1171 .disable_irq = parport_pc_disable_irq,
1173 .data_forward = parport_pc_data_forward,
1174 .data_reverse = parport_pc_data_reverse,
1176 .init_state = parport_pc_init_state,
1177 .save_state = parport_pc_save_state,
1178 .restore_state = parport_pc_restore_state,
1180 .epp_write_data = parport_ieee1284_epp_write_data,
1181 .epp_read_data = parport_ieee1284_epp_read_data,
1182 .epp_write_addr = parport_ieee1284_epp_write_addr,
1183 .epp_read_addr = parport_ieee1284_epp_read_addr,
1185 .ecp_write_data = parport_ieee1284_ecp_write_data,
1186 .ecp_read_data = parport_ieee1284_ecp_read_data,
1187 .ecp_write_addr = parport_ieee1284_ecp_write_addr,
1189 .compat_write_data = parport_ieee1284_write_compat,
1190 .nibble_read_data = parport_ieee1284_read_nibble,
1191 .byte_read_data = parport_ieee1284_read_byte,
1193 .owner = THIS_MODULE,
1196 #ifdef CONFIG_PARPORT_PC_SUPERIO
1197 /* Super-IO chipset detection, Winbond, SMSC */
1198 static void __devinit show_parconfig_smsc37c669(int io, int key)
1200 int cr1,cr4,cra,cr23,cr26,cr27,i=0;
1201 static const char *modes[]={ "SPP and Bidirectional (PS/2)",
1222 if (verbose_probing) {
1223 printk (KERN_INFO "SMSC 37c669 LPT Config: cr_1=0x%02x, 4=0x%02x, "
1224 "A=0x%2x, 23=0x%02x, 26=0x%02x, 27=0x%02x\n",
1225 cr1,cr4,cra,cr23,cr26,cr27);
1227 /* The documentation calls DMA and IRQ-Lines by letters, so
1228 the board maker can/will wire them
1229 appropriately/randomly... G=reserved H=IDE-irq, */
1230 printk (KERN_INFO "SMSC LPT Config: io=0x%04x, irq=%c, dma=%c, "
1231 "fifo threshold=%d\n", cr23*4,
1232 (cr27 &0x0f) ? 'A'-1+(cr27 &0x0f): '-',
1233 (cr26 &0x0f) ? 'A'-1+(cr26 &0x0f): '-', cra & 0x0f);
1234 printk(KERN_INFO "SMSC LPT Config: enabled=%s power=%s\n",
1235 (cr23*4 >=0x100) ?"yes":"no", (cr1 & 4) ? "yes" : "no");
1236 printk(KERN_INFO "SMSC LPT Config: Port mode=%s, EPP version =%s\n",
1237 (cr1 & 0x08 ) ? "Standard mode only (SPP)" : modes[cr4 & 0x03],
1238 (cr4 & 0x40) ? "1.7" : "1.9");
1241 /* Heuristics ! BIOS setup for this mainboard device limits
1242 the choices to standard settings, i.e. io-address and IRQ
1243 are related, however DMA can be 1 or 3, assume DMA_A=DMA1,
1244 DMA_C=DMA3 (this is true e.g. for TYAN 1564D Tomcat IV) */
1245 if(cr23*4 >=0x100) { /* if active */
1246 while((superios[i].io!= 0) && (i<NR_SUPERIOS))
1249 printk(KERN_INFO "Super-IO: too many chips!\n");
1254 superios[i].io = 0x3bc;
1255 superios[i].irq = 7;
1258 superios[i].io = 0x378;
1259 superios[i].irq = 7;
1262 superios[i].io = 0x278;
1263 superios[i].irq = 5;
1266 if((d==1) || (d==3))
1269 superios[i].dma= PARPORT_DMA_NONE;
1275 static void __devinit show_parconfig_winbond(int io, int key)
1277 int cr30,cr60,cr61,cr70,cr74,crf0,i=0;
1278 static const char *modes[] = {
1279 "Standard (SPP) and Bidirectional(PS/2)", /* 0 */
1284 "EPP-1.7 and SPP", /* 5 */
1286 "ECP and EPP-1.7" };
1287 static char *irqtypes[] = { "pulsed low, high-Z", "follows nACK" };
1289 /* The registers are called compatible-PnP because the
1290 register layout is modelled after ISA-PnP, the access
1291 method is just another ... */
1294 outb(0x07,io); /* Register 7: Select Logical Device */
1295 outb(0x01,io+1); /* LD1 is Parallel Port */
1310 if (verbose_probing) {
1311 printk(KERN_INFO "Winbond LPT Config: cr_30=%02x 60,61=%02x%02x "
1312 "70=%02x 74=%02x, f0=%02x\n", cr30,cr60,cr61,cr70,cr74,crf0);
1313 printk(KERN_INFO "Winbond LPT Config: active=%s, io=0x%02x%02x irq=%d, ",
1314 (cr30 & 0x01) ? "yes":"no", cr60,cr61,cr70&0x0f );
1315 if ((cr74 & 0x07) > 3)
1316 printk("dma=none\n");
1318 printk("dma=%d\n",cr74 & 0x07);
1319 printk(KERN_INFO "Winbond LPT Config: irqtype=%s, ECP fifo threshold=%d\n",
1320 irqtypes[crf0>>7], (crf0>>3)&0x0f);
1321 printk(KERN_INFO "Winbond LPT Config: Port mode=%s\n", modes[crf0 & 0x07]);
1324 if(cr30 & 0x01) { /* the settings can be interrogated later ... */
1325 while((superios[i].io!= 0) && (i<NR_SUPERIOS))
1328 printk(KERN_INFO "Super-IO: too many chips!\n");
1330 superios[i].io = (cr60<<8)|cr61;
1331 superios[i].irq = cr70&0x0f;
1332 superios[i].dma = (((cr74 & 0x07) > 3) ?
1333 PARPORT_DMA_NONE : (cr74 & 0x07));
1338 static void __devinit decode_winbond(int efer, int key, int devid, int devrev, int oldid)
1340 const char *type = "unknown";
1343 if (devid == devrev)
1344 /* simple heuristics, we happened to read some
1345 non-winbond register */
1348 id=(devid<<8) | devrev;
1350 /* Values are from public data sheets pdf files, I can just
1351 confirm 83977TF is correct :-) */
1352 if (id == 0x9771) type="83977F/AF";
1353 else if (id == 0x9773) type="83977TF / SMSC 97w33x/97w34x";
1354 else if (id == 0x9774) type="83977ATF";
1355 else if ((id & ~0x0f) == 0x5270) type="83977CTF / SMSC 97w36x";
1356 else if ((id & ~0x0f) == 0x52f0) type="83977EF / SMSC 97w35x";
1357 else if ((id & ~0x0f) == 0x5210) type="83627";
1358 else if ((id & ~0x0f) == 0x6010) type="83697HF";
1359 else if ((oldid &0x0f ) == 0x0a) { type="83877F"; progif=1;}
1360 else if ((oldid &0x0f ) == 0x0b) { type="83877AF"; progif=1;}
1361 else if ((oldid &0x0f ) == 0x0c) { type="83877TF"; progif=1;}
1362 else if ((oldid &0x0f ) == 0x0d) { type="83877ATF"; progif=1;}
1365 if (verbose_probing)
1366 printk(KERN_INFO "Winbond chip at EFER=0x%x key=0x%02x "
1367 "devid=%02x devrev=%02x oldid=%02x type=%s\n",
1368 efer, key, devid, devrev, oldid, type);
1371 show_parconfig_winbond(efer,key);
1374 static void __devinit decode_smsc(int efer, int key, int devid, int devrev)
1376 const char *type = "unknown";
1377 void (*func)(int io, int key);
1380 if (devid == devrev)
1381 /* simple heuristics, we happened to read some
1382 non-smsc register */
1386 id=(devid<<8) | devrev;
1388 if (id==0x0302) {type="37c669"; func=show_parconfig_smsc37c669;}
1389 else if (id==0x6582) type="37c665IR";
1390 else if (devid==0x65) type="37c665GT";
1391 else if (devid==0x66) type="37c666GT";
1393 if (verbose_probing)
1394 printk(KERN_INFO "SMSC chip at EFER=0x%x "
1395 "key=0x%02x devid=%02x devrev=%02x type=%s\n",
1396 efer, key, devid, devrev, type);
1403 static void __devinit winbond_check(int io, int key)
1405 int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
1407 if (!request_region(io, 3, __FUNCTION__))
1410 /* First probe without key */
1419 outb(key,io); /* Write Magic Sequence to EFER, extended
1420 funtion enable register */
1421 outb(0x20,io); /* Write EFIR, extended function index register */
1422 devid=inb(io+1); /* Read EFDR, extended function data register */
1427 outb(0xaa,io); /* Magic Seal */
1429 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1430 goto out; /* protection against false positives */
1432 decode_winbond(io,key,devid,devrev,oldid);
1434 release_region(io, 3);
1437 static void __devinit winbond_check2(int io,int key)
1439 int devid,devrev,oldid,x_devid,x_devrev,x_oldid;
1441 if (!request_region(io, 3, __FUNCTION__))
1444 /* First probe without the key */
1452 outb(key,io); /* Write Magic Byte to EFER, extended
1453 funtion enable register */
1454 outb(0x20,io+2); /* Write EFIR, extended function index register */
1455 devid=inb(io+2); /* Read EFDR, extended function data register */
1460 outb(0xaa,io); /* Magic Seal */
1462 if ((x_devid == devid) && (x_devrev == devrev) && (x_oldid == oldid))
1463 goto out; /* protection against false positives */
1465 decode_winbond(io,key,devid,devrev,oldid);
1467 release_region(io, 3);
1470 static void __devinit smsc_check(int io, int key)
1472 int id,rev,oldid,oldrev,x_id,x_rev,x_oldid,x_oldrev;
1474 if (!request_region(io, 3, __FUNCTION__))
1477 /* First probe without the key */
1488 outb(key,io); /* Write Magic Sequence to EFER, extended
1489 funtion enable register */
1490 outb(0x0d,io); /* Write EFIR, extended function index register */
1491 oldid=inb(io+1); /* Read EFDR, extended function data register */
1498 outb(0xaa,io); /* Magic Seal */
1500 if ((x_id == id) && (x_oldrev == oldrev) &&
1501 (x_oldid == oldid) && (x_rev == rev))
1502 goto out; /* protection against false positives */
1504 decode_smsc(io,key,oldid,oldrev);
1506 release_region(io, 3);
1510 static void __devinit detect_and_report_winbond (void)
1512 if (verbose_probing)
1513 printk(KERN_DEBUG "Winbond Super-IO detection, now testing ports 3F0,370,250,4E,2E ...\n");
1514 winbond_check(0x3f0,0x87);
1515 winbond_check(0x370,0x87);
1516 winbond_check(0x2e ,0x87);
1517 winbond_check(0x4e ,0x87);
1518 winbond_check(0x3f0,0x86);
1519 winbond_check2(0x250,0x88);
1520 winbond_check2(0x250,0x89);
1523 static void __devinit detect_and_report_smsc (void)
1525 if (verbose_probing)
1526 printk(KERN_DEBUG "SMSC Super-IO detection, now testing Ports 2F0, 370 ...\n");
1527 smsc_check(0x3f0,0x55);
1528 smsc_check(0x370,0x55);
1529 smsc_check(0x3f0,0x44);
1530 smsc_check(0x370,0x44);
1532 #endif /* CONFIG_PARPORT_PC_SUPERIO */
1534 static int __devinit get_superio_dma (struct parport *p)
1537 while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
1540 return superios[i].dma;
1541 return PARPORT_DMA_NONE;
1544 static int __devinit get_superio_irq (struct parport *p)
1547 while( (superios[i].io != p->base) && (i<NR_SUPERIOS))
1550 return superios[i].irq;
1551 return PARPORT_IRQ_NONE;
1555 /* --- Mode detection ------------------------------------- */
1558 * Checks for port existence, all ports support SPP MODE
1560 * 0 : No parallel port at this address
1561 * PARPORT_MODE_PCSPP : SPP port detected
1562 * (if the user specified an ioport himself,
1563 * this shall always be the case!)
1566 static int __devinit parport_SPP_supported(struct parport *pb)
1571 * first clear an eventually pending EPP timeout
1572 * I (sailer@ife.ee.ethz.ch) have an SMSC chipset
1573 * that does not even respond to SPP cycles if an EPP
1574 * timeout is pending
1576 clear_epp_timeout(pb);
1578 /* Do a simple read-write test to make sure the port exists. */
1580 outb (w, CONTROL (pb));
1582 /* Is there a control register that we can read from? Some
1583 * ports don't allow reads, so read_control just returns a
1584 * software copy. Some ports _do_ allow reads, so bypass the
1585 * software copy here. In addition, some bits aren't
1587 r = inb (CONTROL (pb));
1588 if ((r & 0xf) == w) {
1590 outb (w, CONTROL (pb));
1591 r = inb (CONTROL (pb));
1592 outb (0xc, CONTROL (pb));
1594 return PARPORT_MODE_PCSPP;
1598 /* That didn't work, but the user thinks there's a
1600 printk (KERN_INFO "parport 0x%lx (WARNING): CTR: "
1601 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1603 /* Try the data register. The data lines aren't tri-stated at
1604 * this stage, so we expect back what we wrote. */
1606 parport_pc_write_data (pb, w);
1607 r = parport_pc_read_data (pb);
1610 parport_pc_write_data (pb, w);
1611 r = parport_pc_read_data (pb);
1613 return PARPORT_MODE_PCSPP;
1616 if (user_specified) {
1617 /* Didn't work, but the user is convinced this is the
1619 printk (KERN_INFO "parport 0x%lx (WARNING): DATA: "
1620 "wrote 0x%02x, read 0x%02x\n", pb->base, w, r);
1621 printk (KERN_INFO "parport 0x%lx: You gave this address, "
1622 "but there is probably no parallel port there!\n",
1626 /* It's possible that we can't read the control register or
1627 * the data register. In that case just believe the user. */
1629 return PARPORT_MODE_PCSPP;
1636 * Old style XT ports alias io ports every 0x400, hence accessing ECR
1637 * on these cards actually accesses the CTR.
1639 * Modern cards don't do this but reading from ECR will return 0xff
1640 * regardless of what is written here if the card does NOT support
1643 * We first check to see if ECR is the same as CTR. If not, the low
1644 * two bits of ECR aren't writable, so we check by writing ECR and
1645 * reading it back to see if it's what we expect.
1647 static int __devinit parport_ECR_present(struct parport *pb)
1649 struct parport_pc_private *priv = pb->private_data;
1650 unsigned char r = 0xc;
1652 outb (r, CONTROL (pb));
1653 if ((inb (ECONTROL (pb)) & 0x3) == (r & 0x3)) {
1654 outb (r ^ 0x2, CONTROL (pb)); /* Toggle bit 1 */
1656 r = inb (CONTROL (pb));
1657 if ((inb (ECONTROL (pb)) & 0x2) == (r & 0x2))
1658 goto no_reg; /* Sure that no ECR register exists */
1661 if ((inb (ECONTROL (pb)) & 0x3 ) != 0x1)
1664 ECR_WRITE (pb, 0x34);
1665 if (inb (ECONTROL (pb)) != 0x35)
1669 outb (0xc, CONTROL (pb));
1671 /* Go to mode 000 */
1672 frob_set_mode (pb, ECR_SPP);
1677 outb (0xc, CONTROL (pb));
1681 #ifdef CONFIG_PARPORT_1284
1682 /* Detect PS/2 support.
1684 * Bit 5 (0x20) sets the PS/2 data direction; setting this high
1685 * allows us to read data from the data lines. In theory we would get back
1686 * 0xff but any peripheral attached to the port may drag some or all of the
1687 * lines down to zero. So if we get back anything that isn't the contents
1688 * of the data register we deem PS/2 support to be present.
1690 * Some SPP ports have "half PS/2" ability - you can't turn off the line
1691 * drivers, but an external peripheral with sufficiently beefy drivers of
1692 * its own can overpower them and assert its own levels onto the bus, from
1693 * where they can then be read back as normal. Ports with this property
1694 * and the right type of device attached are likely to fail the SPP test,
1695 * (as they will appear to have stuck bits) and so the fact that they might
1696 * be misdetected here is rather academic.
1699 static int __devinit parport_PS2_supported(struct parport *pb)
1703 clear_epp_timeout(pb);
1705 /* try to tri-state the buffer */
1706 parport_pc_data_reverse (pb);
1708 parport_pc_write_data(pb, 0x55);
1709 if (parport_pc_read_data(pb) != 0x55) ok++;
1711 parport_pc_write_data(pb, 0xaa);
1712 if (parport_pc_read_data(pb) != 0xaa) ok++;
1714 /* cancel input mode */
1715 parport_pc_data_forward (pb);
1718 pb->modes |= PARPORT_MODE_TRISTATE;
1720 struct parport_pc_private *priv = pb->private_data;
1721 priv->ctr_writable &= ~0x20;
1727 #ifdef CONFIG_PARPORT_PC_FIFO
1728 static int __devinit parport_ECP_supported(struct parport *pb)
1731 int config, configb;
1733 struct parport_pc_private *priv = pb->private_data;
1734 /* Translate ECP intrLine to ISA irq value */
1735 static const int intrline[]= { 0, 7, 9, 10, 11, 14, 15, 5 };
1737 /* If there is no ECR, we have no hope of supporting ECP. */
1741 /* Find out FIFO depth */
1742 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1743 ECR_WRITE (pb, ECR_TST << 5); /* TEST FIFO */
1744 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02); i++)
1745 outb (0xaa, FIFO (pb));
1748 * Using LGS chipset it uses ECR register, but
1749 * it doesn't support ECP or FIFO MODE
1752 ECR_WRITE (pb, ECR_SPP << 5);
1756 priv->fifo_depth = i;
1757 if (verbose_probing)
1758 printk (KERN_DEBUG "0x%lx: FIFO is %d bytes\n", pb->base, i);
1760 /* Find out writeIntrThreshold */
1761 frob_econtrol (pb, 1<<2, 1<<2);
1762 frob_econtrol (pb, 1<<2, 0);
1763 for (i = 1; i <= priv->fifo_depth; i++) {
1766 if (inb (ECONTROL (pb)) & (1<<2))
1770 if (i <= priv->fifo_depth) {
1771 if (verbose_probing)
1772 printk (KERN_DEBUG "0x%lx: writeIntrThreshold is %d\n",
1775 /* Number of bytes we know we can write if we get an
1779 priv->writeIntrThreshold = i;
1781 /* Find out readIntrThreshold */
1782 frob_set_mode (pb, ECR_PS2); /* Reset FIFO and enable PS2 */
1783 parport_pc_data_reverse (pb); /* Must be in PS2 mode */
1784 frob_set_mode (pb, ECR_TST); /* Test FIFO */
1785 frob_econtrol (pb, 1<<2, 1<<2);
1786 frob_econtrol (pb, 1<<2, 0);
1787 for (i = 1; i <= priv->fifo_depth; i++) {
1788 outb (0xaa, FIFO (pb));
1789 if (inb (ECONTROL (pb)) & (1<<2))
1793 if (i <= priv->fifo_depth) {
1794 if (verbose_probing)
1795 printk (KERN_INFO "0x%lx: readIntrThreshold is %d\n",
1798 /* Number of bytes we can read if we get an interrupt. */
1801 priv->readIntrThreshold = i;
1803 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1804 ECR_WRITE (pb, 0xf4); /* Configuration mode */
1805 config = inb (CONFIGA (pb));
1806 pword = (config >> 4) & 0x7;
1810 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
1815 printk (KERN_WARNING "0x%lx: Unsupported pword size!\n",
1819 printk (KERN_WARNING "0x%lx: Unknown implementation ID\n",
1825 priv->pword = pword;
1827 if (verbose_probing) {
1828 printk (KERN_DEBUG "0x%lx: PWord is %d bits\n", pb->base, 8 * pword);
1830 printk (KERN_DEBUG "0x%lx: Interrupts are ISA-%s\n", pb->base,
1831 config & 0x80 ? "Level" : "Pulses");
1833 configb = inb (CONFIGB (pb));
1834 printk (KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
1835 pb->base, config, configb);
1836 printk (KERN_DEBUG "0x%lx: ECP settings irq=", pb->base);
1837 if ((configb >>3) & 0x07)
1838 printk("%d",intrline[(configb >>3) & 0x07]);
1840 printk("<none or set by other means>");
1842 if( (configb & 0x03 ) == 0x00)
1843 printk("<none or set by other means>\n");
1845 printk("%d\n",configb & 0x07);
1848 /* Go back to mode 000 */
1849 frob_set_mode (pb, ECR_SPP);
1855 static int __devinit parport_ECPPS2_supported(struct parport *pb)
1857 const struct parport_pc_private *priv = pb->private_data;
1864 oecr = inb (ECONTROL (pb));
1865 ECR_WRITE (pb, ECR_PS2 << 5);
1866 result = parport_PS2_supported(pb);
1867 ECR_WRITE (pb, oecr);
1871 /* EPP mode detection */
1873 static int __devinit parport_EPP_supported(struct parport *pb)
1875 const struct parport_pc_private *priv = pb->private_data;
1879 * Bit 0 of STR is the EPP timeout bit, this bit is 0
1880 * when EPP is possible and is set high when an EPP timeout
1881 * occurs (EPP uses the HALT line to stop the CPU while it does
1882 * the byte transfer, an EPP timeout occurs if the attached
1883 * device fails to respond after 10 micro seconds).
1885 * This bit is cleared by either reading it (National Semi)
1886 * or writing a 1 to the bit (SMC, UMC, WinBond), others ???
1887 * This bit is always high in non EPP modes.
1890 /* If EPP timeout bit clear then EPP available */
1891 if (!clear_epp_timeout(pb)) {
1892 return 0; /* No way to clear timeout */
1895 /* Check for Intel bug. */
1898 for (i = 0x00; i < 0x80; i += 0x20) {
1900 if (clear_epp_timeout (pb)) {
1901 /* Phony EPP in ECP. */
1907 pb->modes |= PARPORT_MODE_EPP;
1909 /* Set up access functions to use EPP hardware. */
1910 pb->ops->epp_read_data = parport_pc_epp_read_data;
1911 pb->ops->epp_write_data = parport_pc_epp_write_data;
1912 pb->ops->epp_read_addr = parport_pc_epp_read_addr;
1913 pb->ops->epp_write_addr = parport_pc_epp_write_addr;
1918 static int __devinit parport_ECPEPP_supported(struct parport *pb)
1920 struct parport_pc_private *priv = pb->private_data;
1928 oecr = inb (ECONTROL (pb));
1929 /* Search for SMC style EPP+ECP mode */
1930 ECR_WRITE (pb, 0x80);
1931 outb (0x04, CONTROL (pb));
1932 result = parport_EPP_supported(pb);
1934 ECR_WRITE (pb, oecr);
1937 /* Set up access functions to use ECP+EPP hardware. */
1938 pb->ops->epp_read_data = parport_pc_ecpepp_read_data;
1939 pb->ops->epp_write_data = parport_pc_ecpepp_write_data;
1940 pb->ops->epp_read_addr = parport_pc_ecpepp_read_addr;
1941 pb->ops->epp_write_addr = parport_pc_ecpepp_write_addr;
1947 #else /* No IEEE 1284 support */
1949 /* Don't bother probing for modes we know we won't use. */
1950 static int __devinit parport_PS2_supported(struct parport *pb) { return 0; }
1951 #ifdef CONFIG_PARPORT_PC_FIFO
1952 static int __devinit parport_ECP_supported(struct parport *pb) { return 0; }
1954 static int __devinit parport_EPP_supported(struct parport *pb) { return 0; }
1955 static int __devinit parport_ECPEPP_supported(struct parport *pb){return 0;}
1956 static int __devinit parport_ECPPS2_supported(struct parport *pb){return 0;}
1958 #endif /* No IEEE 1284 support */
1960 /* --- IRQ detection -------------------------------------- */
1962 /* Only if supports ECP mode */
1963 static int __devinit programmable_irq_support(struct parport *pb)
1966 unsigned char oecr = inb (ECONTROL (pb));
1967 static const int lookup[8] = {
1968 PARPORT_IRQ_NONE, 7, 9, 10, 11, 14, 15, 5
1971 ECR_WRITE (pb, ECR_CNF << 5); /* Configuration MODE */
1973 intrLine = (inb (CONFIGB (pb)) >> 3) & 0x07;
1974 irq = lookup[intrLine];
1976 ECR_WRITE (pb, oecr);
1980 static int __devinit irq_probe_ECP(struct parport *pb)
1985 irqs = probe_irq_on();
1987 ECR_WRITE (pb, ECR_SPP << 5); /* Reset FIFO */
1988 ECR_WRITE (pb, (ECR_TST << 5) | 0x04);
1989 ECR_WRITE (pb, ECR_TST << 5);
1991 /* If Full FIFO sure that writeIntrThreshold is generated */
1992 for (i=0; i < 1024 && !(inb (ECONTROL (pb)) & 0x02) ; i++)
1993 outb (0xaa, FIFO (pb));
1995 pb->irq = probe_irq_off(irqs);
1996 ECR_WRITE (pb, ECR_SPP << 5);
1999 pb->irq = PARPORT_IRQ_NONE;
2005 * This detection seems that only works in National Semiconductors
2006 * This doesn't work in SMC, LGS, and Winbond
2008 static int __devinit irq_probe_EPP(struct parport *pb)
2010 #ifndef ADVANCED_DETECT
2011 return PARPORT_IRQ_NONE;
2016 if (pb->modes & PARPORT_MODE_PCECR)
2017 oecr = inb (ECONTROL (pb));
2019 irqs = probe_irq_on();
2021 if (pb->modes & PARPORT_MODE_PCECR)
2022 frob_econtrol (pb, 0x10, 0x10);
2024 clear_epp_timeout(pb);
2025 parport_pc_frob_control (pb, 0x20, 0x20);
2026 parport_pc_frob_control (pb, 0x10, 0x10);
2027 clear_epp_timeout(pb);
2029 /* Device isn't expecting an EPP read
2030 * and generates an IRQ.
2032 parport_pc_read_epp(pb);
2035 pb->irq = probe_irq_off (irqs);
2036 if (pb->modes & PARPORT_MODE_PCECR)
2037 ECR_WRITE (pb, oecr);
2038 parport_pc_write_control(pb, 0xc);
2041 pb->irq = PARPORT_IRQ_NONE;
2044 #endif /* Advanced detection */
2047 static int __devinit irq_probe_SPP(struct parport *pb)
2049 /* Don't even try to do this. */
2050 return PARPORT_IRQ_NONE;
2053 /* We will attempt to share interrupt requests since other devices
2054 * such as sound cards and network cards seem to like using the
2057 * When ECP is available we can autoprobe for IRQs.
2058 * NOTE: If we can autoprobe it, we can register the IRQ.
2060 static int __devinit parport_irq_probe(struct parport *pb)
2062 struct parport_pc_private *priv = pb->private_data;
2065 pb->irq = programmable_irq_support(pb);
2067 if (pb->irq == PARPORT_IRQ_NONE)
2068 pb->irq = irq_probe_ECP(pb);
2071 if ((pb->irq == PARPORT_IRQ_NONE) && priv->ecr &&
2072 (pb->modes & PARPORT_MODE_EPP))
2073 pb->irq = irq_probe_EPP(pb);
2075 clear_epp_timeout(pb);
2077 if (pb->irq == PARPORT_IRQ_NONE && (pb->modes & PARPORT_MODE_EPP))
2078 pb->irq = irq_probe_EPP(pb);
2080 clear_epp_timeout(pb);
2082 if (pb->irq == PARPORT_IRQ_NONE)
2083 pb->irq = irq_probe_SPP(pb);
2085 if (pb->irq == PARPORT_IRQ_NONE)
2086 pb->irq = get_superio_irq(pb);
2091 /* --- DMA detection -------------------------------------- */
2093 /* Only if chipset conforms to ECP ISA Interface Standard */
2094 static int __devinit programmable_dma_support (struct parport *p)
2096 unsigned char oecr = inb (ECONTROL (p));
2099 frob_set_mode (p, ECR_CNF);
2101 dma = inb (CONFIGB(p)) & 0x07;
2102 /* 000: Indicates jumpered 8-bit DMA if read-only.
2103 100: Indicates jumpered 16-bit DMA if read-only. */
2104 if ((dma & 0x03) == 0)
2105 dma = PARPORT_DMA_NONE;
2107 ECR_WRITE (p, oecr);
2111 static int __devinit parport_dma_probe (struct parport *p)
2113 const struct parport_pc_private *priv = p->private_data;
2115 p->dma = programmable_dma_support(p); /* ask ECP chipset first */
2116 if (p->dma == PARPORT_DMA_NONE) {
2117 /* ask known Super-IO chips proper, although these
2118 claim ECP compatible, some don't report their DMA
2119 conforming to ECP standards */
2120 p->dma = get_superio_dma(p);
2126 /* --- Initialisation code -------------------------------- */
2128 static LIST_HEAD(ports_list);
2129 static spinlock_t ports_lock = SPIN_LOCK_UNLOCKED;
2131 struct parport *parport_pc_probe_port (unsigned long int base,
2132 unsigned long int base_hi,
2134 struct pci_dev *dev)
2136 struct parport_pc_private *priv;
2137 struct parport_operations *ops;
2139 int probedirq = PARPORT_IRQ_NONE;
2140 struct resource *base_res;
2141 struct resource *ECR_res = NULL;
2142 struct resource *EPP_res = NULL;
2144 ops = kmalloc(sizeof (struct parport_operations), GFP_KERNEL);
2148 priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
2152 /* a misnomer, actually - it's allocate and reserve parport number */
2153 p = parport_register_port(base, irq, dma, ops);
2157 base_res = request_region(base, 3, p->name);
2161 memcpy(ops, &parport_pc_ops, sizeof (struct parport_operations));
2163 priv->ctr_writable = ~0x10;
2165 priv->fifo_depth = 0;
2166 priv->dma_buf = NULL;
2167 priv->dma_handle = 0;
2169 INIT_LIST_HEAD(&priv->list);
2171 p->base_hi = base_hi;
2172 p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
2173 p->private_data = priv;
2176 ECR_res = request_region(base_hi, 3, p->name);
2178 parport_ECR_present(p);
2181 if (base != 0x3bc) {
2182 EPP_res = request_region(base+0x3, 5, p->name);
2184 if (!parport_EPP_supported(p))
2185 parport_ECPEPP_supported(p);
2187 if (!parport_SPP_supported (p))
2191 parport_ECPPS2_supported(p);
2193 parport_PS2_supported(p);
2195 p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
2197 printk(KERN_INFO "%s: PC-style at 0x%lx", p->name, p->base);
2198 if (p->base_hi && priv->ecr)
2199 printk(" (0x%lx)", p->base_hi);
2200 if (p->irq == PARPORT_IRQ_AUTO) {
2201 p->irq = PARPORT_IRQ_NONE;
2202 parport_irq_probe(p);
2203 } else if (p->irq == PARPORT_IRQ_PROBEONLY) {
2204 p->irq = PARPORT_IRQ_NONE;
2205 parport_irq_probe(p);
2207 p->irq = PARPORT_IRQ_NONE;
2209 if (p->irq != PARPORT_IRQ_NONE) {
2210 printk(", irq %d", p->irq);
2211 priv->ctr_writable |= 0x10;
2213 if (p->dma == PARPORT_DMA_AUTO) {
2214 p->dma = PARPORT_DMA_NONE;
2215 parport_dma_probe(p);
2218 if (p->dma == PARPORT_DMA_AUTO) /* To use DMA, giving the irq
2219 is mandatory (see above) */
2220 p->dma = PARPORT_DMA_NONE;
2222 #ifdef CONFIG_PARPORT_PC_FIFO
2223 if (parport_ECP_supported(p) &&
2224 p->dma != PARPORT_DMA_NOFIFO &&
2225 priv->fifo_depth > 0 && p->irq != PARPORT_IRQ_NONE) {
2226 p->modes |= PARPORT_MODE_ECP | PARPORT_MODE_COMPAT;
2227 p->ops->compat_write_data = parport_pc_compat_write_block_pio;
2228 #ifdef CONFIG_PARPORT_1284
2229 p->ops->ecp_write_data = parport_pc_ecp_write_block_pio;
2230 /* currently broken, but working on it.. (FB) */
2231 /* p->ops->ecp_read_data = parport_pc_ecp_read_block_pio; */
2232 #endif /* IEEE 1284 support */
2233 if (p->dma != PARPORT_DMA_NONE) {
2234 printk(", dma %d", p->dma);
2235 p->modes |= PARPORT_MODE_DMA;
2237 else printk(", using FIFO");
2240 /* We can't use the DMA channel after all. */
2241 p->dma = PARPORT_DMA_NONE;
2242 #endif /* Allowed to use FIFO/DMA */
2245 #define printmode(x) {if(p->modes&PARPORT_MODE_##x){printk("%s%s",f?",":"",#x);f++;}}
2249 printmode(TRISTATE);
2256 #ifndef CONFIG_PARPORT_1284
2258 #endif /* CONFIG_PARPORT_1284 */
2260 if (probedirq != PARPORT_IRQ_NONE)
2261 printk(KERN_INFO "%s: irq %d detected\n", p->name, probedirq);
2263 /* If No ECP release the ports grabbed above. */
2264 if (ECR_res && (p->modes & PARPORT_MODE_ECP) == 0) {
2265 release_region(base_hi, 3);
2268 /* Likewise for EEP ports */
2269 if (EPP_res && (p->modes & PARPORT_MODE_EPP) == 0) {
2270 release_region(base+3, 5);
2273 if (p->irq != PARPORT_IRQ_NONE) {
2274 if (request_irq (p->irq, parport_pc_interrupt,
2276 printk (KERN_WARNING "%s: irq %d in use, "
2277 "resorting to polled operation\n",
2279 p->irq = PARPORT_IRQ_NONE;
2280 p->dma = PARPORT_DMA_NONE;
2283 #ifdef CONFIG_PARPORT_PC_FIFO
2284 if (p->dma != PARPORT_DMA_NONE) {
2285 if (request_dma (p->dma, p->name)) {
2286 printk (KERN_WARNING "%s: dma %d in use, "
2287 "resorting to PIO operation\n",
2289 p->dma = PARPORT_DMA_NONE;
2292 pci_alloc_consistent(priv->dev,
2295 if (! priv->dma_buf) {
2296 printk (KERN_WARNING "%s: "
2297 "cannot get buffer for DMA, "
2298 "resorting to PIO operation\n",
2301 p->dma = PARPORT_DMA_NONE;
2305 #endif /* CONFIG_PARPORT_PC_FIFO */
2308 /* Done probing. Now put the port into a sensible start-up state. */
2311 * Put the ECP detected port in PS2 mode.
2312 * Do this also for ports that have ECR but don't do ECP.
2314 ECR_WRITE (p, 0x34);
2316 parport_pc_write_data(p, 0);
2317 parport_pc_data_forward (p);
2319 /* Now that we've told the sharing engine about the port, and
2320 found out its characteristics, let the high-level drivers
2322 spin_lock(&ports_lock);
2323 list_add(&priv->list, &ports_list);
2324 spin_unlock(&ports_lock);
2325 parport_announce_port (p);
2331 release_region(base_hi, 3);
2333 release_region(base+0x3, 5);
2334 release_region(base, 3);
2336 parport_put_port(p);
2345 EXPORT_SYMBOL (parport_pc_probe_port);
2347 void parport_pc_unregister_port (struct parport *p)
2349 struct parport_pc_private *priv = p->private_data;
2350 struct parport_operations *ops = p->ops;
2352 parport_remove_port(p);
2353 spin_lock(&ports_lock);
2354 list_del_init(&priv->list);
2355 spin_unlock(&ports_lock);
2356 if (p->dma != PARPORT_DMA_NONE)
2358 if (p->irq != PARPORT_IRQ_NONE)
2359 free_irq(p->irq, p);
2360 release_region(p->base, 3);
2362 release_region(p->base + 3, p->size - 3);
2363 if (p->modes & PARPORT_MODE_ECP)
2364 release_region(p->base_hi, 3);
2365 #ifdef CONFIG_PARPORT_PC_FIFO
2367 pci_free_consistent(priv->dev, PAGE_SIZE,
2370 #endif /* CONFIG_PARPORT_PC_FIFO */
2371 kfree (p->private_data);
2372 parport_put_port(p);
2373 kfree (ops); /* hope no-one cached it */
2376 EXPORT_SYMBOL (parport_pc_unregister_port);
2380 /* ITE support maintained by Rich Liu <richliu@poorman.org> */
2381 static int __devinit sio_ite_8872_probe (struct pci_dev *pdev, int autoirq,
2382 int autodma, struct parport_pc_via_data *via)
2384 short inta_addr[6] = { 0x2A0, 0x2C0, 0x220, 0x240, 0x1E0 };
2385 struct resource *base_res;
2387 u32 ite8872_lpt, ite8872_lpthi;
2388 u8 ite8872_irq, type;
2389 char *fake_name = "parport probe";
2393 DPRINTK (KERN_DEBUG "sio_ite_8872_probe()\n");
2395 // make sure which one chip
2396 for(i = 0; i < 5; i++) {
2397 base_res = request_region(inta_addr[i], 0x8, fake_name);
2400 pci_write_config_dword (pdev, 0x60,
2401 0xe7000000 | inta_addr[i]);
2402 pci_write_config_dword (pdev, 0x78,
2403 0x00000000 | inta_addr[i]);
2404 test = inb (inta_addr[i]);
2405 if (test != 0xff) break;
2406 release_region(inta_addr[i], 0x8);
2410 printk (KERN_INFO "parport_pc: cannot find ITE8872 INTA\n");
2414 type = inb (inta_addr[i] + 0x18);
2419 printk (KERN_INFO "parport_pc: ITE8871 found (1P)\n");
2420 ite8872set = 0x64200000;
2423 printk (KERN_INFO "parport_pc: ITE8875 found (1P)\n");
2424 ite8872set = 0x64200000;
2427 printk (KERN_INFO "parport_pc: ITE8872 found (2S1P)\n");
2428 ite8872set = 0x64e00000;
2431 printk (KERN_INFO "parport_pc: ITE8873 found (1S)\n");
2434 DPRINTK (KERN_DEBUG "parport_pc: ITE8874 found (2S)\n");
2437 printk (KERN_INFO "parport_pc: unknown ITE887x\n");
2438 printk (KERN_INFO "parport_pc: please mail 'lspci -nvv' "
2439 "output to Rich.Liu@ite.com.tw\n");
2443 pci_read_config_byte (pdev, 0x3c, &ite8872_irq);
2444 pci_read_config_dword (pdev, 0x1c, &ite8872_lpt);
2445 ite8872_lpt &= 0x0000ff00;
2446 pci_read_config_dword (pdev, 0x20, &ite8872_lpthi);
2447 ite8872_lpthi &= 0x0000ff00;
2448 pci_write_config_dword (pdev, 0x6c, 0xe3000000 | ite8872_lpt);
2449 pci_write_config_dword (pdev, 0x70, 0xe3000000 | ite8872_lpthi);
2450 pci_write_config_dword (pdev, 0x80, (ite8872_lpthi<<16) | ite8872_lpt);
2451 // SET SPP&EPP , Parallel Port NO DMA , Enable All Function
2453 pci_write_config_dword (pdev, 0x9c,
2454 ite8872set | (ite8872_irq * 0x11111));
2456 DPRINTK (KERN_DEBUG "ITE887x: The IRQ is %d.\n", ite8872_irq);
2457 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O port is 0x%x.\n",
2459 DPRINTK (KERN_DEBUG "ITE887x: The PARALLEL I/O porthi is 0x%x.\n",
2462 /* Let the user (or defaults) steer us away from interrupts */
2464 if (autoirq != PARPORT_IRQ_AUTO)
2465 irq = PARPORT_IRQ_NONE;
2468 * Release the resource so that parport_pc_probe_port can get it.
2470 release_resource(base_res);
2471 if (parport_pc_probe_port (ite8872_lpt, ite8872_lpthi,
2472 irq, PARPORT_DMA_NONE, NULL)) {
2474 "parport_pc: ITE 8872 parallel port: io=0x%X",
2476 if (irq != PARPORT_IRQ_NONE)
2477 printk (", irq=%d", irq);
2485 /* VIA 8231 support by Pavel Fedin <sonic_amiga@rambler.ru>
2486 based on VIA 686a support code by Jeff Garzik <jgarzik@pobox.com> */
2487 static int __initdata parport_init_mode = 0;
2489 /* Data for two known VIA chips */
2490 static struct parport_pc_via_data via_686a_data __devinitdata = {
2499 static struct parport_pc_via_data via_8231_data __devinitdata = {
2509 static int __devinit sio_via_probe (struct pci_dev *pdev, int autoirq,
2510 int autodma, struct parport_pc_via_data *via)
2512 u8 tmp, tmp2, siofunc;
2515 unsigned port1, port2;
2516 unsigned have_epp = 0;
2518 printk(KERN_DEBUG "parport_pc: VIA 686A/8231 detected\n");
2520 switch(parport_init_mode)
2523 printk(KERN_DEBUG "parport_pc: setting SPP mode\n");
2524 siofunc = VIA_FUNCTION_PARPORT_SPP;
2527 printk(KERN_DEBUG "parport_pc: setting PS/2 mode\n");
2528 siofunc = VIA_FUNCTION_PARPORT_SPP;
2529 ppcontrol = VIA_PARPORT_BIDIR;
2532 printk(KERN_DEBUG "parport_pc: setting EPP mode\n");
2533 siofunc = VIA_FUNCTION_PARPORT_EPP;
2534 ppcontrol = VIA_PARPORT_BIDIR;
2538 printk(KERN_DEBUG "parport_pc: setting ECP mode\n");
2539 siofunc = VIA_FUNCTION_PARPORT_ECP;
2540 ppcontrol = VIA_PARPORT_BIDIR;
2543 printk(KERN_DEBUG "parport_pc: setting EPP+ECP mode\n");
2544 siofunc = VIA_FUNCTION_PARPORT_ECP;
2545 ppcontrol = VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP;
2549 printk(KERN_DEBUG "parport_pc: probing current configuration\n");
2550 siofunc = VIA_FUNCTION_PROBE;
2554 * unlock super i/o configuration
2556 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2557 tmp |= via->via_pci_superio_config_data;
2558 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2560 /* Bits 1-0: Parallel Port Mode / Enable */
2561 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2562 tmp = inb (VIA_CONFIG_DATA);
2563 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2564 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2565 tmp2 = inb (VIA_CONFIG_DATA);
2566 if (siofunc == VIA_FUNCTION_PROBE)
2568 siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
2573 tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
2575 outb(via->viacfg_function, VIA_CONFIG_INDEX);
2576 outb(tmp, VIA_CONFIG_DATA);
2577 tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
2579 outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
2580 outb(tmp2, VIA_CONFIG_DATA);
2583 /* Parallel Port I/O Base Address, bits 9-2 */
2584 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2585 port1 = inb(VIA_CONFIG_DATA) << 2;
2587 printk (KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",port1);
2588 if ((port1 == 0x3BC) && have_epp)
2590 outb(via->viacfg_parport_base, VIA_CONFIG_INDEX);
2591 outb((0x378 >> 2), VIA_CONFIG_DATA);
2592 printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n");
2597 * lock super i/o configuration
2599 pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
2600 tmp &= ~via->via_pci_superio_config_data;
2601 pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
2603 if (siofunc == VIA_FUNCTION_PARPORT_DISABLE) {
2604 printk(KERN_INFO "parport_pc: VIA parallel port disabled in BIOS\n");
2608 /* Bits 7-4: PnP Routing for Parallel Port IRQ */
2609 pci_read_config_byte(pdev, via->via_pci_parport_irq_reg, &tmp);
2610 irq = ((tmp & VIA_IRQCONTROL_PARALLEL) >> 4);
2612 if (siofunc == VIA_FUNCTION_PARPORT_ECP)
2614 /* Bits 3-2: PnP Routing for Parallel Port DMA */
2615 pci_read_config_byte(pdev, via->via_pci_parport_dma_reg, &tmp);
2616 dma = ((tmp & VIA_DMACONTROL_PARALLEL) >> 2);
2619 /* if ECP not enabled, DMA is not enabled, assumed bogus 'dma' value */
2620 dma = PARPORT_DMA_NONE;
2622 /* Let the user (or defaults) steer us away from interrupts and DMA */
2623 if (autoirq == PARPORT_IRQ_NONE) {
2624 irq = PARPORT_IRQ_NONE;
2625 dma = PARPORT_DMA_NONE;
2627 if (autodma == PARPORT_DMA_NONE)
2628 dma = PARPORT_DMA_NONE;
2631 case 0x3bc: port2 = 0x7bc; break;
2632 case 0x378: port2 = 0x778; break;
2633 case 0x278: port2 = 0x678; break;
2635 printk(KERN_INFO "parport_pc: Weird VIA parport base 0x%X, ignoring\n",
2640 /* filter bogus IRQs */
2646 irq = PARPORT_IRQ_NONE;
2649 default: /* do nothing */
2653 /* finally, do the probe with values obtained */
2654 if (parport_pc_probe_port (port1, port2, irq, dma, NULL)) {
2656 "parport_pc: VIA parallel port: io=0x%X", port1);
2657 if (irq != PARPORT_IRQ_NONE)
2658 printk (", irq=%d", irq);
2659 if (dma != PARPORT_DMA_NONE)
2660 printk (", dma=%d", dma);
2665 printk(KERN_WARNING "parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2671 enum parport_pc_sio_types {
2672 sio_via_686a = 0, /* Via VT82C686A motherboard Super I/O */
2673 sio_via_8231, /* Via VT8231 south bridge integrated Super IO */
2678 /* each element directly indexed from enum list, above */
2679 static struct parport_pc_superio {
2680 int (*probe) (struct pci_dev *pdev, int autoirq, int autodma, struct parport_pc_via_data *via);
2681 struct parport_pc_via_data *via;
2682 } parport_pc_superio_info[] __devinitdata = {
2683 { sio_via_probe, &via_686a_data, },
2684 { sio_via_probe, &via_8231_data, },
2685 { sio_ite_8872_probe, NULL, },
2688 enum parport_pc_pci_cards {
2689 siig_1p_10x = last_sio,
2694 lava_parallel_dual_a,
2695 lava_parallel_dual_b,
2742 /* each element directly indexed from enum list, above
2743 * (but offset by last_sio) */
2744 static struct parport_pc_pci {
2746 struct { /* BAR (base address registers) numbers in the config
2749 int hi; /* -1 if not there, >6 for offset-method (max
2753 /* If set, this is called immediately after pci_enable_device.
2754 * If it returns non-zero, no probing will take place and the
2755 * ports will not be used. */
2756 int (*preinit_hook) (struct pci_dev *pdev, int autoirq, int autodma);
2758 /* If set, this is called after probing for ports. If 'failed'
2759 * is non-zero we couldn't use any of the ports. */
2760 void (*postinit_hook) (struct pci_dev *pdev, int failed);
2761 } cards[] __devinitdata = {
2762 /* siig_1p_10x */ { 1, { { 2, 3 }, } },
2763 /* siig_2p_10x */ { 2, { { 2, 3 }, { 4, 5 }, } },
2764 /* siig_1p_20x */ { 1, { { 0, 1 }, } },
2765 /* siig_2p_20x */ { 2, { { 0, 1 }, { 2, 3 }, } },
2766 /* lava_parallel */ { 1, { { 0, -1 }, } },
2767 /* lava_parallel_dual_a */ { 1, { { 0, -1 }, } },
2768 /* lava_parallel_dual_b */ { 1, { { 0, -1 }, } },
2769 /* boca_ioppar */ { 1, { { 0, -1 }, } },
2770 /* plx_9050 */ { 2, { { 4, -1 }, { 5, -1 }, } },
2771 /* timedia_4078a */ { 1, { { 2, -1 }, } },
2772 /* timedia_4079h */ { 1, { { 2, 3 }, } },
2773 /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
2774 /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2775 /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2776 /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2777 /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
2778 /* timedia_4078u */ { 1, { { 2, -1 }, } },
2779 /* timedia_4079a */ { 1, { { 2, 3 }, } },
2780 /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
2781 /* timedia_4079r */ { 1, { { 2, 3 }, } },
2782 /* timedia_4079s */ { 1, { { 2, 3 }, } },
2783 /* timedia_4079d */ { 1, { { 2, 3 }, } },
2784 /* timedia_4079e */ { 1, { { 2, 3 }, } },
2785 /* timedia_4079f */ { 1, { { 2, 3 }, } },
2786 /* timedia_9079a */ { 1, { { 2, 3 }, } },
2787 /* timedia_9079b */ { 1, { { 2, 3 }, } },
2788 /* timedia_9079c */ { 1, { { 2, 3 }, } },
2789 /* timedia_4006a */ { 1, { { 0, -1 }, } },
2790 /* timedia_4014 */ { 2, { { 0, -1 }, { 2, -1 }, } },
2791 /* timedia_4008a */ { 1, { { 0, 1 }, } },
2792 /* timedia_4018 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2793 /* timedia_9018a */ { 2, { { 0, 1 }, { 2, 3 }, } },
2794 /* SYBA uses fixed offsets in
2796 /* syba_2p_epp AP138B */ { 2, { { 0, 0x078 }, { 0, 0x178 }, } },
2797 /* syba_1p_ecp W83787 */ { 1, { { 0, 0x078 }, } },
2798 /* titan_010l */ { 1, { { 3, -1 }, } },
2799 /* titan_1284p2 */ { 2, { { 0, 1 }, { 2, 3 }, } },
2800 /* avlab_1p */ { 1, { { 0, 1}, } },
2801 /* avlab_2p */ { 2, { { 0, 1}, { 2, 3 },} },
2802 /* The Oxford Semi cards are unusual: 954 doesn't support ECP,
2803 * and 840 locks up if you write 1 to bit 2! */
2804 /* oxsemi_954 */ { 1, { { 0, -1 }, } },
2805 /* oxsemi_840 */ { 1, { { 0, -1 }, } },
2806 /* aks_0100 */ { 1, { { 0, -1 }, } },
2807 /* mobility_pp */ { 1, { { 0, 1 }, } },
2808 /* netmos_9705 */ { 1, { { 0, -1 }, } }, /* untested */
2809 /* netmos_9805 */ { 1, { { 0, -1 }, } }, /* untested */
2810 /* netmos_9815 */ { 2, { { 0, -1 }, { 2, -1 }, } }, /* untested */
2811 /* netmos_9855 */ { 2, { { 0, -1 }, { 2, -1 }, } }, /* untested */
2812 /* netmos_9735 */ { 1, { { 2, 3 }, } }, /* untested */
2813 /* netmos_9835 */ { 1, { { 2, 3 }, } }, /* untested */
2814 /* netmos_9755 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */
2815 /* netmos_9715 */ { 2, { { 0, 1 }, { 2, 3 },} }, /* untested */
2818 static struct pci_device_id parport_pc_pci_tbl[] = {
2819 /* Super-IO onboard chips */
2820 { 0x1106, 0x0686, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_686a },
2821 { 0x1106, 0x8231, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_via_8231 },
2822 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
2823 PCI_ANY_ID, PCI_ANY_ID, 0, 0, sio_ite_8872 },
2826 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_10x,
2827 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_10x },
2828 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_10x,
2829 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_10x },
2830 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1P_20x,
2831 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1p_20x },
2832 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P_20x,
2833 PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p_20x },
2834 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PARALLEL,
2835 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel },
2836 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_A,
2837 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_a },
2838 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DUAL_PAR_B,
2839 PCI_ANY_ID, PCI_ANY_ID, 0, 0, lava_parallel_dual_b },
2840 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_BOCA_IOPPAR,
2841 PCI_ANY_ID, PCI_ANY_ID, 0, 0, boca_ioppar },
2842 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2843 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4014, 0,0, plx_9050 },
2844 /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
2845 { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
2846 { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
2847 { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
2848 { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
2849 { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
2850 { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
2851 { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
2852 { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
2853 { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
2854 { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
2855 { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
2856 { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
2857 { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
2858 { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
2859 { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
2860 { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
2861 { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
2862 { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
2863 { 0x1409, 0x7268, 0x1409, 0x0101, 0, 0, timedia_4006a },
2864 { 0x1409, 0x7268, 0x1409, 0x0102, 0, 0, timedia_4014 },
2865 { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
2866 { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
2867 { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
2868 { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
2869 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
2870 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
2871 { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
2872 PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_1p_ecp },
2873 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_010L,
2874 PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_010l },
2875 { 0x9710, 0x9815, 0x1000, 0x0020, 0, 0, titan_1284p2 },
2876 /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
2877 { 0x14db, 0x2120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1p}, /* AFAVLAB_TK9902 */
2878 { 0x14db, 0x2121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2p},
2879 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954PP,
2880 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
2881 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
2882 PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
2883 { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
2884 PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
2885 /* NetMos communication controllers */
2886 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
2887 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
2888 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9805,
2889 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9805 },
2890 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9815,
2891 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9815 },
2892 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
2893 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9855 },
2894 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9735,
2895 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9735 },
2896 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
2897 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9835 },
2898 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9755,
2899 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9755 },
2900 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9715,
2901 PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9715 },
2902 { 0, } /* terminate list */
2904 MODULE_DEVICE_TABLE(pci,parport_pc_pci_tbl);
2906 static int parport_pc_pci_probe (struct pci_dev *dev,
2907 const struct pci_device_id *id)
2909 int err, count, n, i = id->driver_data;
2912 /* This is an onboard Super-IO and has already been probed */
2915 /* This is a PCI card */
2918 if ((err = pci_enable_device (dev)) != 0)
2921 if (cards[i].preinit_hook &&
2922 cards[i].preinit_hook (dev, PARPORT_IRQ_NONE, PARPORT_DMA_NONE))
2925 for (n = 0; n < cards[i].numports; n++) {
2926 int lo = cards[i].addr[n].lo;
2927 int hi = cards[i].addr[n].hi;
2928 unsigned long io_lo, io_hi;
2929 io_lo = pci_resource_start (dev, lo);
2931 if ((hi >= 0) && (hi <= 6))
2932 io_hi = pci_resource_start (dev, hi);
2934 io_lo += hi; /* Reinterpret the meaning of
2935 "hi" as an offset (see SYBA
2937 /* TODO: test if sharing interrupts works */
2938 printk (KERN_DEBUG "PCI parallel port detected: %04x:%04x, "
2939 "I/O at %#lx(%#lx)\n",
2940 parport_pc_pci_tbl[i + last_sio].vendor,
2941 parport_pc_pci_tbl[i + last_sio].device, io_lo, io_hi);
2942 if (parport_pc_probe_port (io_lo, io_hi, PARPORT_IRQ_NONE,
2943 PARPORT_DMA_NONE, dev))
2947 if (cards[i].postinit_hook)
2948 cards[i].postinit_hook (dev, count == 0);
2950 return count == 0 ? -ENODEV : 0;
2953 static struct pci_driver parport_pc_pci_driver = {
2954 .name = "parport_pc",
2955 .id_table = parport_pc_pci_tbl,
2956 .probe = parport_pc_pci_probe,
2959 static int __init parport_pc_init_superio (int autoirq, int autodma)
2961 const struct pci_device_id *id;
2962 struct pci_dev *pdev = NULL;
2965 while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev)) != NULL) {
2966 id = pci_match_device (parport_pc_pci_tbl, pdev);
2967 if (id == NULL || id->driver_data >= last_sio)
2970 if (parport_pc_superio_info[id->driver_data].probe
2971 (pdev, autoirq, autodma,parport_pc_superio_info[id->driver_data].via)) {
2976 return ret; /* number of devices found */
2979 static struct pci_driver parport_pc_pci_driver;
2980 static int __init parport_pc_init_superio(int autoirq, int autodma) {return 0;}
2981 #endif /* CONFIG_PCI */
2984 static const struct pnp_device_id parport_pc_pnp_tbl[] = {
2985 /* Standard LPT Printer Port */
2986 {.id = "PNP0400", .driver_data = 0},
2987 /* ECP Printer Port */
2988 {.id = "PNP0401", .driver_data = 0},
2992 MODULE_DEVICE_TABLE(pnp,parport_pc_pnp_tbl);
2994 static int parport_pc_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *id)
2996 struct parport *pdata;
2997 unsigned long io_lo, io_hi;
3000 if (pnp_port_valid(dev,0) &&
3001 !(pnp_port_flags(dev,0) & IORESOURCE_DISABLED)) {
3002 io_lo = pnp_port_start(dev,0);
3006 if (pnp_port_valid(dev,1) &&
3007 !(pnp_port_flags(dev,1) & IORESOURCE_DISABLED)) {
3008 io_hi = pnp_port_start(dev,1);
3012 if (pnp_irq_valid(dev,0) &&
3013 !(pnp_irq_flags(dev,0) & IORESOURCE_DISABLED)) {
3014 irq = pnp_irq(dev,0);
3016 irq = PARPORT_IRQ_NONE;
3018 if (pnp_dma_valid(dev,0) &&
3019 !(pnp_dma_flags(dev,0) & IORESOURCE_DISABLED)) {
3020 dma = pnp_dma(dev,0);
3022 dma = PARPORT_DMA_NONE;
3024 printk(KERN_INFO "parport: PnPBIOS parport detected.\n");
3025 if (!(pdata = parport_pc_probe_port (io_lo, io_hi, irq, dma, NULL)))
3028 pnp_set_drvdata(dev,pdata);
3032 static void parport_pc_pnp_remove(struct pnp_dev *dev)
3034 struct parport *pdata = (struct parport *)pnp_get_drvdata(dev);
3038 parport_pc_unregister_port(pdata);
3041 /* we only need the pnp layer to activate the device, at least for now */
3042 static struct pnp_driver parport_pc_pnp_driver = {
3043 .name = "parport_pc",
3044 .id_table = parport_pc_pnp_tbl,
3045 .probe = parport_pc_pnp_probe,
3046 .remove = parport_pc_pnp_remove,
3050 /* This is called by parport_pc_find_nonpci_ports (in asm/parport.h) */
3051 static int __devinit __attribute__((unused))
3052 parport_pc_find_isa_ports (int autoirq, int autodma)
3056 if (parport_pc_probe_port(0x3bc, 0x7bc, autoirq, autodma, NULL))
3058 if (parport_pc_probe_port(0x378, 0x778, autoirq, autodma, NULL))
3060 if (parport_pc_probe_port(0x278, 0x678, autoirq, autodma, NULL))
3066 /* This function is called by parport_pc_init if the user didn't
3067 * specify any ports to probe. Its job is to find some ports. Order
3068 * is important here -- we want ISA ports to be registered first,
3069 * followed by PCI cards (for least surprise), but before that we want
3070 * to do chipset-specific tests for some onboard ports that we know
3073 * autoirq is PARPORT_IRQ_NONE, PARPORT_IRQ_AUTO, or PARPORT_IRQ_PROBEONLY
3074 * autodma is PARPORT_DMA_NONE or PARPORT_DMA_AUTO
3076 static int __init parport_pc_find_ports (int autoirq, int autodma)
3080 #ifdef CONFIG_PARPORT_PC_SUPERIO
3081 detect_and_report_winbond ();
3082 detect_and_report_smsc ();
3085 /* Onboard SuperIO chipsets that show themselves on the PCI bus. */
3086 count += parport_pc_init_superio (autoirq, autodma);
3088 /* PnP ports, skip detection if SuperIO already found them */
3090 r = pnp_register_driver (&parport_pc_pnp_driver);
3092 pnp_registered_parport = 1;
3097 /* ISA ports and whatever (see asm/parport.h). */
3098 count += parport_pc_find_nonpci_ports (autoirq, autodma);
3100 r = pci_register_driver (&parport_pc_pci_driver);
3103 pci_registered_parport = 1;
3110 * Piles of crap below pretend to be a parser for module and kernel
3111 * parameters. Say "thank you" to whoever had come up with that
3112 * syntax and keep in mind that code below is a cleaned up version.
3115 static int __initdata io[PARPORT_PC_MAX_PORTS+1] = { [0 ... PARPORT_PC_MAX_PORTS] = 0 };
3116 static int __initdata io_hi[PARPORT_PC_MAX_PORTS+1] =
3117 { [0 ... PARPORT_PC_MAX_PORTS] = PARPORT_IOHI_AUTO };
3118 static int __initdata dmaval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_DMA_NONE };
3119 static int __initdata irqval[PARPORT_PC_MAX_PORTS] = { [0 ... PARPORT_PC_MAX_PORTS-1] = PARPORT_IRQ_PROBEONLY };
3121 static int __init parport_parse_param(const char *s, int *val,
3122 int automatic, int none, int nofifo)
3126 if (!strncmp(s, "auto", 4))
3128 else if (!strncmp(s, "none", 4))
3130 else if (nofifo && !strncmp(s, "nofifo", 4))
3134 unsigned long r = simple_strtoul(s, &ep, 0);
3138 printk(KERN_ERR "parport: bad specifier `%s'\n", s);
3145 static int __init parport_parse_irq(const char *irqstr, int *val)
3147 return parport_parse_param(irqstr, val, PARPORT_IRQ_AUTO,
3148 PARPORT_IRQ_NONE, 0);
3151 static int __init parport_parse_dma(const char *dmastr, int *val)
3153 return parport_parse_param(dmastr, val, PARPORT_DMA_AUTO,
3154 PARPORT_DMA_NONE, PARPORT_DMA_NOFIFO);
3158 static int __init parport_init_mode_setup(char *str)
3160 printk(KERN_DEBUG "parport_pc.c: Specified parameter parport_init_mode=%s\n", str);
3162 if (!strcmp (str, "spp"))
3163 parport_init_mode=1;
3164 if (!strcmp (str, "ps2"))
3165 parport_init_mode=2;
3166 if (!strcmp (str, "epp"))
3167 parport_init_mode=3;
3168 if (!strcmp (str, "ecp"))
3169 parport_init_mode=4;
3170 if (!strcmp (str, "ecpepp"))
3171 parport_init_mode=5;
3177 static const char *irq[PARPORT_PC_MAX_PORTS];
3178 static const char *dma[PARPORT_PC_MAX_PORTS];
3180 MODULE_PARM_DESC(io, "Base I/O address (SPP regs)");
3181 module_param_array(io, int, NULL, 0);
3182 MODULE_PARM_DESC(io_hi, "Base I/O address (ECR)");
3183 module_param_array(io_hi, int, NULL, 0);
3184 MODULE_PARM_DESC(irq, "IRQ line");
3185 module_param_array(irq, charp, NULL, 0);
3186 MODULE_PARM_DESC(dma, "DMA channel");
3187 module_param_array(dma, charp, NULL, 0);
3188 #if defined(CONFIG_PARPORT_PC_SUPERIO) || \
3189 (defined(CONFIG_PARPORT_1284) && defined(CONFIG_PARPORT_PC_FIFO))
3190 MODULE_PARM_DESC(verbose_probing, "Log chit-chat during initialisation");
3191 module_param(verbose_probing, int, 0644);
3194 static char *init_mode;
3195 MODULE_PARM_DESC(init_mode, "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
3196 module_param(init_mode, charp, 0);
3199 static int __init parse_parport_params(void)
3206 parport_init_mode_setup(init_mode);
3209 for (i = 0; i < PARPORT_PC_MAX_PORTS && io[i]; i++) {
3210 if (parport_parse_irq(irq[i], &val))
3213 if (parport_parse_dma(dma[i], &val))
3218 /* The user can make us use any IRQs or DMAs we find. */
3219 if (irq[0] && !parport_parse_irq(irq[0], &val))
3221 case PARPORT_IRQ_NONE:
3222 case PARPORT_IRQ_AUTO:
3226 printk (KERN_WARNING
3227 "parport_pc: irq specified "
3228 "without base address. Use 'io=' "
3229 "to specify one\n");
3232 if (dma[0] && !parport_parse_dma(dma[0], &val))
3234 case PARPORT_DMA_NONE:
3235 case PARPORT_DMA_AUTO:
3239 printk (KERN_WARNING
3240 "parport_pc: dma specified "
3241 "without base address. Use 'io=' "
3242 "to specify one\n");
3250 static int parport_setup_ptr __initdata = 0;
3253 * Acceptable parameters:
3257 * parport=0xBASE[,IRQ[,DMA]]
3259 * IRQ/DMA may be numeric or 'auto' or 'none'
3261 static int __init parport_setup (char *str)
3267 if (!str || !*str || (*str == '0' && !*(str+1))) {
3268 /* Disable parport if "parport=0" in cmdline */
3269 io[0] = PARPORT_DISABLE;
3273 if (!strncmp (str, "auto", 4)) {
3274 irqval[0] = PARPORT_IRQ_AUTO;
3275 dmaval[0] = PARPORT_DMA_AUTO;
3279 val = simple_strtoul (str, &endptr, 0);
3280 if (endptr == str) {
3281 printk (KERN_WARNING "parport=%s not understood\n", str);
3285 if (parport_setup_ptr == PARPORT_PC_MAX_PORTS) {
3286 printk(KERN_ERR "parport=%s ignored, too many ports\n", str);
3290 io[parport_setup_ptr] = val;
3291 irqval[parport_setup_ptr] = PARPORT_IRQ_NONE;
3292 dmaval[parport_setup_ptr] = PARPORT_DMA_NONE;
3294 sep = strchr(str, ',');
3296 if (parport_parse_irq(sep, &val))
3298 irqval[parport_setup_ptr] = val;
3299 sep = strchr(sep, ',');
3301 if (parport_parse_dma(sep, &val))
3303 dmaval[parport_setup_ptr] = val;
3306 parport_setup_ptr++;
3310 static int __init parse_parport_params(void)
3312 return io[0] == PARPORT_DISABLE;
3315 __setup ("parport=", parport_setup);
3318 * Acceptable parameters:
3320 * parport_init_mode=[spp|ps2|epp|ecp|ecpepp]
3323 __setup("parport_init_mode=",parport_init_mode_setup);
3327 /* "Parser" ends here */
3329 static int __init parport_pc_init(void)
3333 if (parse_parport_params())
3338 /* Only probe the ports we were given. */
3340 for (i = 0; i < PARPORT_PC_MAX_PORTS; i++) {
3343 if ((io_hi[i]) == PARPORT_IOHI_AUTO)
3344 io_hi[i] = 0x400 + io[i];
3345 if (parport_pc_probe_port(io[i], io_hi[i],
3346 irqval[i], dmaval[i], NULL))
3350 count += parport_pc_find_ports (irqval[0], dmaval[0]);
3355 static void __exit parport_pc_exit(void)
3357 if (pci_registered_parport)
3358 pci_unregister_driver (&parport_pc_pci_driver);
3359 if (pnp_registered_parport)
3360 pnp_unregister_driver (&parport_pc_pnp_driver);
3362 spin_lock(&ports_lock);
3363 while (!list_empty(&ports_list)) {
3364 struct parport_pc_private *priv;
3365 struct parport *port;
3366 priv = list_entry(ports_list.next,
3367 struct parport_pc_private, list);
3369 spin_unlock(&ports_lock);
3370 parport_pc_unregister_port(port);
3371 spin_lock(&ports_lock);
3373 spin_unlock(&ports_lock);
3376 MODULE_AUTHOR("Phil Blundell, Tim Waugh, others");
3377 MODULE_DESCRIPTION("PC-style parallel port driver");
3378 MODULE_LICENSE("GPL");
3379 module_init(parport_pc_init)
3380 module_exit(parport_pc_exit)