2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<dely.l.sy@intel.com>
30 #include <linux/config.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/types.h>
34 #include <linux/slab.h>
35 #include <linux/vmalloc.h>
36 #include <linux/interrupt.h>
37 #include <linux/spinlock.h>
38 #include <linux/pci.h>
39 #include <asm/system.h>
44 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
45 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
46 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
47 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
48 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
49 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
50 /* Redefine this flagword to set debug level */
51 #define DEBUG_LEVEL DBG_K_STANDARD
53 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
55 #define DBG_PRINT( dbg_flags, args... ) \
57 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
60 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
61 __FILE__, __LINE__, __FUNCTION__ ); \
62 sprintf( __dbg_str_buf + len, args ); \
63 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
67 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
68 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
70 #define DEFINE_DBG_BUFFER
71 #define DBG_ENTER_ROUTINE
72 #define DBG_LEAVE_ROUTINE
91 } __attribute__ ((packed));
93 /* offsets to the controller registers based on the above structure layout */
95 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
96 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
97 CAPREG = offsetof(struct ctrl_reg, cap_reg),
98 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
99 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
100 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
101 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
102 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
103 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
104 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
105 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
106 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
107 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
108 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
110 static int pcie_cap_base = 0; /* Base of the PCI Express capability item structure */
112 #define PCIE_CAP_ID ( pcie_cap_base + PCIECAPID )
113 #define NXT_CAP_PTR ( pcie_cap_base + NXTCAPPTR )
114 #define CAP_REG ( pcie_cap_base + CAPREG )
115 #define DEV_CAP ( pcie_cap_base + DEVCAP )
116 #define DEV_CTRL ( pcie_cap_base + DEVCTRL )
117 #define DEV_STATUS ( pcie_cap_base + DEVSTATUS )
118 #define LNK_CAP ( pcie_cap_base + LNKCAP )
119 #define LNK_CTRL ( pcie_cap_base + LNKCTRL )
120 #define LNK_STATUS ( pcie_cap_base + LNKSTATUS )
121 #define SLOT_CAP ( pcie_cap_base + SLOTCAP )
122 #define SLOT_CTRL ( pcie_cap_base + SLOTCTRL )
123 #define SLOT_STATUS ( pcie_cap_base + SLOTSTATUS )
124 #define ROOT_CTRL ( pcie_cap_base + ROOTCTRL )
125 #define ROOT_STATUS ( pcie_cap_base + ROOTSTATUS )
127 #define hp_register_read_word(pdev, reg , value) \
128 pci_read_config_word(pdev, reg, &value)
130 #define hp_register_read_dword(pdev, reg , value) \
131 pci_read_config_dword(pdev, reg, &value)
133 #define hp_register_write_word(pdev, reg , value) \
134 pci_write_config_word(pdev, reg, value)
136 #define hp_register_dwrite_word(pdev, reg , value) \
137 pci_write_config_dword(pdev, reg, value)
139 /* Field definitions in PCI Express Capabilities Register */
140 #define CAP_VER 0x000F
141 #define DEV_PORT_TYPE 0x00F0
142 #define SLOT_IMPL 0x0100
143 #define MSG_NUM 0x3E00
145 /* Device or Port Type */
146 #define NAT_ENDPT 0x00
147 #define LEG_ENDPT 0x01
148 #define ROOT_PORT 0x04
149 #define UP_STREAM 0x05
150 #define DN_STREAM 0x06
151 #define PCIE_PCI_BRDG 0x07
152 #define PCI_PCIE_BRDG 0x10
154 /* Field definitions in Device Capabilities Register */
155 #define DATTN_BUTTN_PRSN 0x1000
156 #define DATTN_LED_PRSN 0x2000
157 #define DPWR_LED_PRSN 0x4000
159 /* Field definitions in Link Capabilities Register */
160 #define MAX_LNK_SPEED 0x000F
161 #define MAX_LNK_WIDTH 0x03F0
163 /* Link Width Encoding */
172 /*Field definitions of Link Status Register */
173 #define LNK_SPEED 0x000F
174 #define NEG_LINK_WD 0x03F0
175 #define LNK_TRN_ERR 0x0400
176 #define LNK_TRN 0x0800
177 #define SLOT_CLK_CONF 0x1000
179 /* Field definitions in Slot Capabilities Register */
180 #define ATTN_BUTTN_PRSN 0x00000001
181 #define PWR_CTRL_PRSN 0x00000002
182 #define MRL_SENS_PRSN 0x00000004
183 #define ATTN_LED_PRSN 0x00000008
184 #define PWR_LED_PRSN 0x00000010
185 #define HP_SUPR_RM 0x00000020
186 #define HP_CAP 0x00000040
187 #define SLOT_PWR_VALUE 0x000003F8
188 #define SLOT_PWR_LIMIT 0x00000C00
189 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
191 /* Field definitions in Slot Control Register */
192 #define ATTN_BUTTN_ENABLE 0x0001
193 #define PWR_FAULT_DETECT_ENABLE 0x0002
194 #define MRL_DETECT_ENABLE 0x0004
195 #define PRSN_DETECT_ENABLE 0x0008
196 #define CMD_CMPL_INTR_ENABLE 0x0010
197 #define HP_INTR_ENABLE 0x0020
198 #define ATTN_LED_CTRL 0x00C0
199 #define PWR_LED_CTRL 0x0300
200 #define PWR_CTRL 0x0400
202 /* Attention indicator and Power indicator states */
204 #define LED_BLINK 0x10
207 /* Power Control Command */
209 #define POWER_OFF 0x0400
211 /* Field definitions in Slot Status Register */
212 #define ATTN_BUTTN_PRESSED 0x0001
213 #define PWR_FAULT_DETECTED 0x0002
214 #define MRL_SENS_CHANGED 0x0004
215 #define PRSN_DETECT_CHANGED 0x0008
216 #define CMD_COMPLETED 0x0010
217 #define MRL_STATE 0x0020
218 #define PRSN_STATE 0x0040
220 struct php_ctlr_state_s {
221 struct php_ctlr_state_s *pnext;
222 struct pci_dev *pci_dev;
224 unsigned long flags; /* spinlock's */
225 u32 slot_device_offset;
227 struct timer_list int_poll_timer; /* Added for poll event */
228 php_intr_callback_t attention_button_callback;
229 php_intr_callback_t switch_change_callback;
230 php_intr_callback_t presence_change_callback;
231 php_intr_callback_t power_fault_callback;
232 void *callback_instance_id;
233 struct ctrl_reg *creg; /* Ptr to controller register space */
237 static spinlock_t hpc_event_lock;
239 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
240 static struct php_ctlr_state_s *php_ctlr_list_head = 0; /* HPC state linked list */
241 static int ctlr_seq_num = 0; /* Controller sequence # */
242 static spinlock_t list_lock;
244 static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs);
246 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
248 /* This is the interrupt polling timeout function. */
249 static void int_poll_timeout(unsigned long lphp_ctlr)
251 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
256 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
260 /* Poll for interrupt events. regs == NULL => polling */
261 pcie_isr( 0, (void *)php_ctlr, NULL );
263 init_timer(&php_ctlr->int_poll_timer);
265 if (!pciehp_poll_time)
266 pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
268 start_int_poll_timer(php_ctlr, pciehp_poll_time);
273 /* This function starts the interrupt polling timer. */
274 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
277 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
281 if ( ( seconds <= 0 ) || ( seconds > 60 ) )
282 seconds = 2; /* Clamp to sane value */
284 php_ctlr->int_poll_timer.function = &int_poll_timeout;
285 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */
286 php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
287 add_timer(&php_ctlr->int_poll_timer);
292 static int pcie_write_cmd(struct slot *slot, u16 cmd)
294 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
300 dbg("%s : Enter\n", __FUNCTION__);
301 if (!slot->ctrl->hpc_ctlr_handle) {
302 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
306 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
308 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
311 dbg("%s : hp_register_read_word SLOT_STATUS %x\n", __FUNCTION__, slot_status);
313 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
314 /* After 1 sec and CMD_COMPLETED still not set, just proceed forward to issue
315 the next command according to spec. Just print out the error message */
316 dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__);
319 dbg("%s: Before hp_register_write_word SLOT_CTRL %x\n", __FUNCTION__, cmd);
320 retval = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL, cmd | CMD_CMPL_INTR_ENABLE);
322 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
325 dbg("%s : hp_register_write_word SLOT_CTRL %x\n", __FUNCTION__, cmd | CMD_CMPL_INTR_ENABLE);
326 dbg("%s : Exit\n", __FUNCTION__);
332 static int hpc_check_lnk_status(struct controller *ctrl)
334 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) ctrl->hpc_ctlr_handle;
340 if (!ctrl->hpc_ctlr_handle) {
341 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
345 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS, lnk_status);
348 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
352 if ( (lnk_status & (LNK_TRN | LNK_TRN_ERR)) == 0x0C00) {
353 err("%s : Link Training Error occurs \n", __FUNCTION__);
363 static int hpc_get_attention_status(struct slot *slot, u8 *status)
365 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
372 if (!slot->ctrl->hpc_ctlr_handle) {
373 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
377 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl);
380 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
384 dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__,SLOT_CTRL, slot_ctrl);
386 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
388 switch (atten_led_state) {
390 *status = 0xFF; /* Reserved */
393 *status = 1; /* On */
396 *status = 2; /* Blink */
399 *status = 0; /* Off */
410 static int hpc_get_power_status(struct slot * slot, u8 *status)
412 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
419 if (!slot->ctrl->hpc_ctlr_handle) {
420 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
424 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl);
427 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
430 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL, slot_ctrl);
432 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
451 static int hpc_get_latch_status(struct slot *slot, u8 *status)
453 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
459 if (!slot->ctrl->hpc_ctlr_handle) {
460 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
464 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
467 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
471 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
477 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
479 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
486 if (!slot->ctrl->hpc_ctlr_handle) {
487 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
491 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
494 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
497 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
498 *status = (card_state == 1) ? 1 : 0;
504 static int hpc_query_power_fault(struct slot * slot)
506 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
514 if (!slot->ctrl->hpc_ctlr_handle) {
515 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
519 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
522 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
525 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
526 status = (pwr_fault != 1) ? 1 : 0;
529 /* Note: Logic 0 => fault */
533 static int hpc_set_attention_status(struct slot *slot, u8 value)
535 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
540 dbg("%s: \n", __FUNCTION__);
541 if (!slot->ctrl->hpc_ctlr_handle) {
542 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
546 if (slot->hp_slot >= php_ctlr->num_slots) {
547 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
550 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl);
553 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
556 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl);
559 case 0 : /* turn off */
560 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0;
562 case 1: /* turn on */
563 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040;
565 case 2: /* turn blink */
566 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080;
571 if (!pciehp_poll_mode)
572 slot_cmd = slot_cmd | HP_INTR_ENABLE;
574 pcie_write_cmd(slot, slot_cmd);
575 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL, slot_cmd);
581 static void hpc_set_green_led_on(struct slot *slot)
583 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
588 dbg("%s: \n", __FUNCTION__);
589 if (!slot->ctrl->hpc_ctlr_handle) {
590 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
594 if (slot->hp_slot >= php_ctlr->num_slots) {
595 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
599 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl);
602 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
605 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl);
606 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100;
607 if (!pciehp_poll_mode)
608 slot_cmd = slot_cmd | HP_INTR_ENABLE;
610 pcie_write_cmd(slot, slot_cmd);
612 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL, slot_cmd);
616 static void hpc_set_green_led_off(struct slot *slot)
618 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
623 dbg("%s: \n", __FUNCTION__);
624 if (!slot->ctrl->hpc_ctlr_handle) {
625 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
629 if (slot->hp_slot >= php_ctlr->num_slots) {
630 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
634 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl);
637 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
640 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl);
642 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300;
644 if (!pciehp_poll_mode)
645 slot_cmd = slot_cmd | HP_INTR_ENABLE;
646 pcie_write_cmd(slot, slot_cmd);
647 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL, slot_cmd);
652 static void hpc_set_green_led_blink(struct slot *slot)
654 struct php_ctlr_state_s *php_ctlr =(struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
659 dbg("%s: \n", __FUNCTION__);
660 if (!slot->ctrl->hpc_ctlr_handle) {
661 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
665 if (slot->hp_slot >= php_ctlr->num_slots) {
666 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
670 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl);
673 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
676 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl);
678 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200;
680 if (!pciehp_poll_mode)
681 slot_cmd = slot_cmd | HP_INTR_ENABLE;
682 pcie_write_cmd(slot, slot_cmd);
684 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL, slot_cmd);
688 int pcie_get_ctlr_slot_config(struct controller *ctrl,
689 int *num_ctlr_slots, /* number of slots in this HPC; only 1 in PCIE */
690 int *first_device_num, /* PCI dev num of the first slot in this PCIE */
691 int *physical_slot_num, /* phy slot num of the first slot in this PCIE */
692 int *updown, /* physical_slot_num increament: 1 or -1 */
695 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) ctrl->hpc_ctlr_handle;
701 if (!ctrl->hpc_ctlr_handle) {
702 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
706 *first_device_num = 0;
709 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP, slot_cap);
712 err("%s : hp_register_read_dword SLOT_CAP failed\n", __FUNCTION__);
716 *physical_slot_num = slot_cap >> 19;
724 static void hpc_release_ctlr(struct controller *ctrl)
726 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) ctrl->hpc_ctlr_handle;
727 struct php_ctlr_state_s *p, *p_prev;
731 if (!ctrl->hpc_ctlr_handle) {
732 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
736 if (pciehp_poll_mode) {
737 del_timer(&php_ctlr->int_poll_timer);
740 free_irq(php_ctlr->irq, ctrl);
744 if (php_ctlr->pci_dev)
745 php_ctlr->pci_dev = 0;
747 spin_lock(&list_lock);
748 p = php_ctlr_list_head;
753 p_prev->pnext = p->pnext;
755 php_ctlr_list_head = p->pnext;
762 spin_unlock(&list_lock);
770 static int hpc_power_on_slot(struct slot * slot)
772 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
779 dbg("%s: \n", __FUNCTION__);
781 if (!slot->ctrl->hpc_ctlr_handle) {
782 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
786 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
787 if (slot->hp_slot >= php_ctlr->num_slots) {
788 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
792 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl);
795 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
798 dbg("%s: SLOT_CTRL %x, value read %xn", __FUNCTION__, SLOT_CTRL,
801 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON;
803 if (!pciehp_poll_mode)
804 slot_cmd = slot_cmd | HP_INTR_ENABLE;
806 retval = pcie_write_cmd(slot, slot_cmd);
809 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
812 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL, slot_cmd);
819 static int hpc_power_off_slot(struct slot * slot)
821 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
828 dbg("%s: \n", __FUNCTION__);
830 if (!slot->ctrl->hpc_ctlr_handle) {
831 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
835 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
837 if (slot->hp_slot >= php_ctlr->num_slots) {
838 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
841 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl);
844 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
847 dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__, SLOT_CTRL,
850 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF;
852 if (!pciehp_poll_mode)
853 slot_cmd = slot_cmd | HP_INTR_ENABLE;
855 retval = pcie_write_cmd(slot, slot_cmd);
858 err("%s: Write command failed!\n", __FUNCTION__);
861 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL, slot_cmd);
868 static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs)
870 struct controller *ctrl = NULL;
871 struct php_ctlr_state_s *php_ctlr;
872 u8 schedule_flag = 0;
873 u16 slot_status, intr_detect, intr_loc;
875 int hp_slot = 0; /* only 1 slot per PCI Express port */
881 if (!pciehp_poll_mode) {
882 ctrl = (struct controller *)dev_id;
883 php_ctlr = ctrl->hpc_ctlr_handle;
885 php_ctlr = (struct php_ctlr_state_s *) dev_id;
886 ctrl = (struct controller *)php_ctlr->callback_instance_id;
890 dbg("%s: dev_id %p ctlr == NULL\n", __FUNCTION__, (void*) dev_id);
895 dbg("%s: php_ctlr == NULL\n", __FUNCTION__);
899 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
901 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
905 intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED |
906 PRSN_DETECT_CHANGED | CMD_COMPLETED );
908 intr_loc = slot_status & intr_detect;
910 /* Check to see if it was our interrupt */
914 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
915 /* Mask Hot-plug Interrupt Enable */
916 if (!pciehp_poll_mode) {
917 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, temp_word);
919 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
923 dbg("%s: Set Mask Hot-plug Interrupt Enable\n", __FUNCTION__);
924 dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
925 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
927 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL, temp_word);
929 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
932 dbg("%s: hp_register_write_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
934 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
936 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
939 dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status);
941 /* Clear command complete interrupt caused by this write */
943 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word);
945 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
948 dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word);
951 if (intr_loc & CMD_COMPLETED) {
953 * Command Complete Interrupt Pending
955 dbg("%s: In Command Complete Interrupt Pending\n", __FUNCTION__);
956 wake_up_interruptible(&ctrl->queue);
959 if ((php_ctlr->switch_change_callback) && (intr_loc & MRL_SENS_CHANGED))
960 schedule_flag += php_ctlr->switch_change_callback(
961 hp_slot, php_ctlr->callback_instance_id);
962 if ((php_ctlr->attention_button_callback) && (intr_loc & ATTN_BUTTN_PRESSED))
963 schedule_flag += php_ctlr->attention_button_callback(
964 hp_slot, php_ctlr->callback_instance_id);
965 if ((php_ctlr->presence_change_callback) && (intr_loc & PRSN_DETECT_CHANGED))
966 schedule_flag += php_ctlr->presence_change_callback(
967 hp_slot , php_ctlr->callback_instance_id);
968 if ((php_ctlr->power_fault_callback) && (intr_loc & PWR_FAULT_DETECTED))
969 schedule_flag += php_ctlr->power_fault_callback(
970 hp_slot, php_ctlr->callback_instance_id);
972 /* Clear all events after serving them */
974 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word);
976 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
979 /* Unmask Hot-plug Interrupt Enable */
980 if (!pciehp_poll_mode) {
981 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, temp_word);
983 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
987 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
988 dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
989 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
991 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL, temp_word);
993 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
996 dbg("%s: hp_register_write_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
998 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
1000 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1003 dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status);
1005 /* Clear command complete interrupt caused by this write */
1007 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word);
1009 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1012 dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word);
1018 static int hpc_get_max_lnk_speed (struct slot *slot, enum pcie_link_speed *value)
1020 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
1021 enum pcie_link_speed lnk_speed;
1027 if (!slot->ctrl->hpc_ctlr_handle) {
1028 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1032 if (slot->hp_slot >= php_ctlr->num_slots) {
1033 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1037 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP, lnk_cap);
1040 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1044 switch (lnk_cap & 0x000F) {
1046 lnk_speed = PCIE_2PT5GB;
1049 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1054 dbg("Max link speed = %d\n", lnk_speed);
1059 static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value)
1061 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
1062 enum pcie_link_width lnk_wdth;
1068 if (!slot->ctrl->hpc_ctlr_handle) {
1069 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1073 if (slot->hp_slot >= php_ctlr->num_slots) {
1074 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1078 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP, lnk_cap);
1081 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1085 switch ((lnk_cap & 0x03F0) >> 4){
1087 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1090 lnk_wdth = PCIE_LNK_X1;
1093 lnk_wdth = PCIE_LNK_X2;
1096 lnk_wdth = PCIE_LNK_X4;
1099 lnk_wdth = PCIE_LNK_X8;
1102 lnk_wdth = PCIE_LNK_X12;
1105 lnk_wdth = PCIE_LNK_X16;
1108 lnk_wdth = PCIE_LNK_X32;
1111 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1116 dbg("Max link width = %d\n", lnk_wdth);
1121 static int hpc_get_cur_lnk_speed (struct slot *slot, enum pcie_link_speed *value)
1123 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
1124 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
1130 if (!slot->ctrl->hpc_ctlr_handle) {
1131 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1135 if (slot->hp_slot >= php_ctlr->num_slots) {
1136 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1140 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS, lnk_status);
1143 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1147 switch (lnk_status & 0x0F) {
1149 lnk_speed = PCIE_2PT5GB;
1152 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1157 dbg("Current link speed = %d\n", lnk_speed);
1162 static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value)
1164 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
1165 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1171 if (!slot->ctrl->hpc_ctlr_handle) {
1172 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1176 if (slot->hp_slot >= php_ctlr->num_slots) {
1177 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1181 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS, lnk_status);
1184 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1188 switch ((lnk_status & 0x03F0) >> 4){
1190 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1193 lnk_wdth = PCIE_LNK_X1;
1196 lnk_wdth = PCIE_LNK_X2;
1199 lnk_wdth = PCIE_LNK_X4;
1202 lnk_wdth = PCIE_LNK_X8;
1205 lnk_wdth = PCIE_LNK_X12;
1208 lnk_wdth = PCIE_LNK_X16;
1211 lnk_wdth = PCIE_LNK_X32;
1214 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1219 dbg("Current link width = %d\n", lnk_wdth);
1224 static struct hpc_ops pciehp_hpc_ops = {
1225 .power_on_slot = hpc_power_on_slot,
1226 .power_off_slot = hpc_power_off_slot,
1227 .set_attention_status = hpc_set_attention_status,
1228 .get_power_status = hpc_get_power_status,
1229 .get_attention_status = hpc_get_attention_status,
1230 .get_latch_status = hpc_get_latch_status,
1231 .get_adapter_status = hpc_get_adapter_status,
1233 .get_max_bus_speed = hpc_get_max_lnk_speed,
1234 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
1235 .get_max_lnk_width = hpc_get_max_lnk_width,
1236 .get_cur_lnk_width = hpc_get_cur_lnk_width,
1238 .query_power_fault = hpc_query_power_fault,
1239 .green_led_on = hpc_set_green_led_on,
1240 .green_led_off = hpc_set_green_led_off,
1241 .green_led_blink = hpc_set_green_led_blink,
1243 .release_ctlr = hpc_release_ctlr,
1244 .check_lnk_status = hpc_check_lnk_status,
1247 int pcie_init(struct controller * ctrl,
1248 struct pci_dev * pdev,
1249 php_intr_callback_t attention_button_callback,
1250 php_intr_callback_t switch_change_callback,
1251 php_intr_callback_t presence_change_callback,
1252 php_intr_callback_t power_fault_callback)
1254 struct php_ctlr_state_s *php_ctlr, *p;
1255 void *instance_id = ctrl;
1257 static int first = 1;
1262 int cap_base, saved_cap_base;
1263 u16 slot_status, slot_ctrl;
1267 spin_lock_init(&list_lock);
1268 php_ctlr = (struct php_ctlr_state_s *) kmalloc(sizeof(struct php_ctlr_state_s), GFP_KERNEL);
1270 if (!php_ctlr) { /* allocate controller state data */
1271 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1275 memset(php_ctlr, 0, sizeof(struct php_ctlr_state_s));
1277 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1279 dbg("%s: pdev->vendor %x pdev->device %x\n", __FUNCTION__,
1280 pdev->vendor, pdev->device);
1282 saved_cap_base = pcie_cap_base;
1284 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
1285 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1286 goto abort_free_ctlr;
1289 pcie_cap_base = cap_base;
1291 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, pcie_cap_base);
1293 rc = hp_register_read_word(pdev, CAP_REG, cap_reg);
1295 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1296 goto abort_free_ctlr;
1298 dbg("%s: CAP_REG offset %x cap_reg %x\n", __FUNCTION__, CAP_REG, cap_reg);
1300 if (((cap_reg & SLOT_IMPL) == 0) || ((cap_reg & DEV_PORT_TYPE) != 0x0040)){
1301 dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__);
1302 goto abort_free_ctlr;
1305 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP, slot_cap);
1307 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1308 goto abort_free_ctlr;
1310 dbg("%s: SLOT_CAP offset %x slot_cap %x\n", __FUNCTION__, SLOT_CAP, slot_cap);
1312 if (!(slot_cap & HP_CAP)) {
1313 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1314 goto abort_free_ctlr;
1316 /* For debugging purpose */
1317 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
1319 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1320 goto abort_free_ctlr;
1322 dbg("%s: SLOT_STATUS offset %x slot_status %x\n", __FUNCTION__, SLOT_STATUS, slot_status);
1324 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL, slot_ctrl);
1326 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1327 goto abort_free_ctlr;
1329 dbg("%s: SLOT_CTRL offset %x slot_ctrl %x\n", __FUNCTION__, SLOT_CTRL, slot_ctrl);
1332 spin_lock_init(&hpc_event_lock);
1336 dbg("pdev = %p: b:d:f:irq=0x%x:%x:%x:%x\n", pdev, pdev->bus->number,
1337 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), pdev->irq);
1338 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1339 if (pci_resource_len(pdev, rc) > 0)
1340 dbg("pci resource[%d] start=0x%lx(len=0x%lx)\n", rc,
1341 pci_resource_start(pdev, rc), pci_resource_len(pdev, rc));
1343 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device,
1344 pdev->subsystem_vendor, pdev->subsystem_device);
1346 init_MUTEX(&ctrl->crit_sect);
1347 /* setup wait queue */
1348 init_waitqueue_head(&ctrl->queue);
1351 php_ctlr->irq = pdev->irq;
1352 dbg("HPC interrupt = %d\n", php_ctlr->irq);
1354 /* Save interrupt callback info */
1355 php_ctlr->attention_button_callback = attention_button_callback;
1356 php_ctlr->switch_change_callback = switch_change_callback;
1357 php_ctlr->presence_change_callback = presence_change_callback;
1358 php_ctlr->power_fault_callback = power_fault_callback;
1359 php_ctlr->callback_instance_id = instance_id;
1361 /* return PCI Controller Info */
1362 php_ctlr->slot_device_offset = 0;
1363 php_ctlr->num_slots = 1;
1365 /* Mask Hot-plug Interrupt Enable */
1366 rc = hp_register_read_word(pdev, SLOT_CTRL, temp_word);
1368 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1369 goto abort_free_ctlr;
1372 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL, temp_word);
1373 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
1375 rc = hp_register_write_word(pdev, SLOT_CTRL, temp_word);
1377 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1378 goto abort_free_ctlr;
1380 dbg("%s : Mask HPIE hp_register_write_word SLOT_CTRL %x\n", __FUNCTION__, temp_word);
1382 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
1384 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1385 goto abort_free_ctlr;
1387 dbg("%s: Mask HPIE SLOT_STATUS offset %x reads slot_status %x\n", __FUNCTION__, SLOT_STATUS, slot_status);
1389 temp_word = 0x1F; /* Clear all events */
1390 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word);
1392 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1393 goto abort_free_ctlr;
1395 dbg("%s: SLOT_STATUS offset %x writes slot_status %x\n", __FUNCTION__, SLOT_STATUS, temp_word);
1397 if (pciehp_poll_mode) {/* Install interrupt polling code */
1398 /* Install and start the interrupt polling timer */
1399 init_timer(&php_ctlr->int_poll_timer);
1400 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1402 /* Installs the interrupt handler */
1403 dbg("%s: pciehp_msi_quirk = %x\n", __FUNCTION__, pciehp_msi_quirk);
1404 if (!pciehp_msi_quirk) {
1405 rc = pci_enable_msi(pdev);
1407 info("Can't get msi for the hotplug controller\n");
1408 info("Use INTx for the hotplug controller\n");
1409 dbg("%s: rc = %x\n", __FUNCTION__, rc);
1411 php_ctlr->irq = pdev->irq;
1413 rc = request_irq(php_ctlr->irq, pcie_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
1414 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1416 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1417 goto abort_free_ctlr;
1421 rc = hp_register_read_word(pdev, SLOT_CTRL, temp_word);
1423 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1424 goto abort_free_ctlr;
1426 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL, temp_word);
1428 intr_enable = ATTN_BUTTN_ENABLE | PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
1431 temp_word = (temp_word & ~intr_enable) | intr_enable;
1433 if (pciehp_poll_mode) {
1434 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1436 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1438 dbg("%s: temp_word %x\n", __FUNCTION__, temp_word);
1440 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */
1441 rc = hp_register_write_word(pdev, SLOT_CTRL, temp_word);
1443 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1444 goto abort_free_ctlr;
1446 dbg("%s : Unmask HPIE hp_register_write_word SLOT_CTRL with %x\n", __FUNCTION__, temp_word);
1447 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS, slot_status);
1449 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1450 goto abort_free_ctlr;
1452 dbg("%s: Unmask HPIE SLOT_STATUS offset %x reads slot_status %x\n", __FUNCTION__,
1453 SLOT_STATUS, slot_status);
1455 temp_word = 0x1F; /* Clear all events */
1456 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS, temp_word);
1458 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1459 goto abort_free_ctlr;
1461 dbg("%s: SLOT_STATUS offset %x writes slot_status %x\n", __FUNCTION__, SLOT_STATUS, temp_word);
1463 /* Add this HPC instance into the HPC list */
1464 spin_lock(&list_lock);
1465 if (php_ctlr_list_head == 0) {
1466 php_ctlr_list_head = php_ctlr;
1467 p = php_ctlr_list_head;
1470 p = php_ctlr_list_head;
1475 p->pnext = php_ctlr;
1477 spin_unlock(&list_lock);
1480 ctrl->hpc_ctlr_handle = php_ctlr;
1481 ctrl->hpc_ops = &pciehp_hpc_ops;
1486 /* We end up here for the many possible ways to fail this API. */
1488 pcie_cap_base = saved_cap_base;