3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
10 #include <linux/irq.h>
11 #include <linux/interrupt.h>
12 #include <linux/init.h>
13 #include <linux/config.h>
14 #include <linux/ioport.h>
15 #include <linux/smp_lock.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
19 #include <asm/errno.h>
25 static spinlock_t msi_lock = SPIN_LOCK_UNLOCKED;
26 static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL };
27 static kmem_cache_t* msi_cachep;
29 static int pci_msi_enable = 1;
30 static int last_alloc_vector = 0;
31 static int nr_released_vectors = 0;
32 static int nr_reserved_vectors = NR_HP_RESERVED_VECTORS;
33 static int nr_msix_devices = 0;
35 #ifndef CONFIG_X86_IO_APIC
36 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
37 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
40 static void msi_cache_ctor(void *p, kmem_cache_t *cache, unsigned long flags)
42 memset(p, 0, NR_IRQS * sizeof(struct msi_desc));
45 static int msi_cache_init(void)
47 msi_cachep = kmem_cache_create("msi_cache",
48 NR_IRQS * sizeof(struct msi_desc),
49 0, SLAB_HWCACHE_ALIGN, msi_cache_ctor, NULL);
56 static void msi_set_mask_bit(unsigned int vector, int flag)
58 struct msi_desc *entry;
60 entry = (struct msi_desc *)msi_desc[vector];
61 if (!entry || !entry->dev || !entry->mask_base)
63 switch (entry->msi_attrib.type) {
67 unsigned int mask_bits;
69 pos = entry->mask_base;
70 entry->dev->bus->ops->read(entry->dev->bus, entry->dev->devfn,
74 entry->dev->bus->ops->write(entry->dev->bus, entry->dev->devfn,
80 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
81 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
82 writel(flag, entry->mask_base + offset);
91 static void set_msi_affinity(unsigned int vector, cpumask_t cpu_mask)
93 struct msi_desc *entry;
94 struct msg_address address;
96 entry = (struct msi_desc *)msi_desc[vector];
97 if (!entry || !entry->dev)
100 switch (entry->msi_attrib.type) {
105 if (!(pos = pci_find_capability(entry->dev, PCI_CAP_ID_MSI)))
108 entry->dev->bus->ops->read(entry->dev->bus, entry->dev->devfn,
109 msi_lower_address_reg(pos), 4,
110 &address.lo_address.value);
111 address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
112 address.lo_address.value |= (cpu_mask_to_apicid(cpu_mask) <<
113 MSI_TARGET_CPU_SHIFT);
114 entry->msi_attrib.current_cpu = cpu_mask_to_apicid(cpu_mask);
115 entry->dev->bus->ops->write(entry->dev->bus, entry->dev->devfn,
116 msi_lower_address_reg(pos), 4,
117 address.lo_address.value);
120 case PCI_CAP_ID_MSIX:
122 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
123 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET;
125 address.lo_address.value = readl(entry->mask_base + offset);
126 address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
127 address.lo_address.value |= (cpu_mask_to_apicid(cpu_mask) <<
128 MSI_TARGET_CPU_SHIFT);
129 entry->msi_attrib.current_cpu = cpu_mask_to_apicid(cpu_mask);
130 writel(address.lo_address.value, entry->mask_base + offset);
138 #ifdef CONFIG_IRQBALANCE
139 static inline void move_msi(int vector)
141 if (!cpus_empty(pending_irq_balance_cpumask[vector])) {
142 set_msi_affinity(vector, pending_irq_balance_cpumask[vector]);
143 cpus_clear(pending_irq_balance_cpumask[vector]);
146 #endif /* CONFIG_IRQBALANCE */
147 #endif /* CONFIG_SMP */
149 static void mask_MSI_irq(unsigned int vector)
151 msi_set_mask_bit(vector, 1);
154 static void unmask_MSI_irq(unsigned int vector)
156 msi_set_mask_bit(vector, 0);
159 static unsigned int startup_msi_irq_wo_maskbit(unsigned int vector)
161 return 0; /* never anything pending */
164 static void pci_disable_msi(unsigned int vector);
165 static void shutdown_msi_irq(unsigned int vector)
167 pci_disable_msi(vector);
170 #define shutdown_msi_irq_wo_maskbit shutdown_msi_irq
171 static void enable_msi_irq_wo_maskbit(unsigned int vector) {}
172 static void disable_msi_irq_wo_maskbit(unsigned int vector) {}
173 static void ack_msi_irq_wo_maskbit(unsigned int vector) {}
174 static void end_msi_irq_wo_maskbit(unsigned int vector)
180 static unsigned int startup_msi_irq_w_maskbit(unsigned int vector)
182 unmask_MSI_irq(vector);
183 return 0; /* never anything pending */
186 #define shutdown_msi_irq_w_maskbit shutdown_msi_irq
187 #define enable_msi_irq_w_maskbit unmask_MSI_irq
188 #define disable_msi_irq_w_maskbit mask_MSI_irq
189 #define ack_msi_irq_w_maskbit mask_MSI_irq
191 static void end_msi_irq_w_maskbit(unsigned int vector)
194 unmask_MSI_irq(vector);
199 * Interrupt Type for MSI-X PCI/PCI-X/PCI-Express Devices,
200 * which implement the MSI-X Capability Structure.
202 static struct hw_interrupt_type msix_irq_type = {
203 .typename = "PCI MSI-X",
204 .startup = startup_msi_irq_w_maskbit,
205 .shutdown = shutdown_msi_irq_w_maskbit,
206 .enable = enable_msi_irq_w_maskbit,
207 .disable = disable_msi_irq_w_maskbit,
208 .ack = ack_msi_irq_w_maskbit,
209 .end = end_msi_irq_w_maskbit,
210 .set_affinity = set_msi_irq_affinity
214 * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices,
215 * which implement the MSI Capability Structure with
216 * Mask-and-Pending Bits.
218 static struct hw_interrupt_type msi_irq_w_maskbit_type = {
219 .typename = "PCI MSI",
220 .startup = startup_msi_irq_w_maskbit,
221 .shutdown = shutdown_msi_irq_w_maskbit,
222 .enable = enable_msi_irq_w_maskbit,
223 .disable = disable_msi_irq_w_maskbit,
224 .ack = ack_msi_irq_w_maskbit,
225 .end = end_msi_irq_w_maskbit,
226 .set_affinity = set_msi_irq_affinity
230 * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices,
231 * which implement the MSI Capability Structure without
232 * Mask-and-Pending Bits.
234 static struct hw_interrupt_type msi_irq_wo_maskbit_type = {
235 .typename = "PCI MSI",
236 .startup = startup_msi_irq_wo_maskbit,
237 .shutdown = shutdown_msi_irq_wo_maskbit,
238 .enable = enable_msi_irq_wo_maskbit,
239 .disable = disable_msi_irq_wo_maskbit,
240 .ack = ack_msi_irq_wo_maskbit,
241 .end = end_msi_irq_wo_maskbit,
242 .set_affinity = set_msi_irq_affinity
245 static void msi_data_init(struct msg_data *msi_data,
248 memset(msi_data, 0, sizeof(struct msg_data));
249 msi_data->vector = (u8)vector;
250 msi_data->delivery_mode = MSI_DELIVERY_MODE;
251 msi_data->level = MSI_LEVEL_MODE;
252 msi_data->trigger = MSI_TRIGGER_MODE;
255 static void msi_address_init(struct msg_address *msi_address)
257 unsigned int dest_id;
259 memset(msi_address, 0, sizeof(struct msg_address));
260 msi_address->hi_address = (u32)0;
261 dest_id = (MSI_ADDRESS_HEADER << MSI_ADDRESS_HEADER_SHIFT);
262 msi_address->lo_address.u.dest_mode = MSI_DEST_MODE;
263 msi_address->lo_address.u.redirection_hint = MSI_REDIRECTION_HINT_MODE;
264 msi_address->lo_address.u.dest_id = dest_id;
265 msi_address->lo_address.value |= (MSI_TARGET_CPU << MSI_TARGET_CPU_SHIFT);
268 static int assign_msi_vector(void)
270 static int new_vector_avail = 1;
275 * msi_lock is provided to ensure that successful allocation of MSI
276 * vector is assigned unique among drivers.
278 spin_lock_irqsave(&msi_lock, flags);
280 if (!new_vector_avail) {
282 * vector_irq[] = -1 indicates that this specific vector is:
283 * - assigned for MSI (since MSI have no associated IRQ) or
284 * - assigned for legacy if less than 16, or
285 * - having no corresponding 1:1 vector-to-IOxAPIC IRQ mapping
286 * vector_irq[] = 0 indicates that this vector, previously
287 * assigned for MSI, is freed by hotplug removed operations.
288 * This vector will be reused for any subsequent hotplug added
290 * vector_irq[] > 0 indicates that this vector is assigned for
291 * IOxAPIC IRQs. This vector and its value provides a 1-to-1
292 * vector-to-IOxAPIC IRQ mapping.
294 for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) {
295 if (vector_irq[vector] != 0)
297 vector_irq[vector] = -1;
298 nr_released_vectors--;
299 spin_unlock_irqrestore(&msi_lock, flags);
302 spin_unlock_irqrestore(&msi_lock, flags);
305 vector = assign_irq_vector(AUTO_ASSIGN);
306 last_alloc_vector = vector;
307 if (vector == LAST_DEVICE_VECTOR)
308 new_vector_avail = 0;
310 spin_unlock_irqrestore(&msi_lock, flags);
314 static int get_new_vector(void)
318 if ((vector = assign_msi_vector()) > 0)
319 set_intr_gate(vector, interrupt[vector]);
324 static int msi_init(void)
326 static int status = -ENOMEM;
331 if ((status = msi_cache_init()) < 0) {
333 printk(KERN_INFO "WARNING: MSI INIT FAILURE\n");
336 printk(KERN_INFO "MSI INIT SUCCESS\n");
341 static int get_msi_vector(struct pci_dev *dev)
343 return get_new_vector();
346 static struct msi_desc* alloc_msi_entry(void)
348 struct msi_desc *entry;
350 entry = (struct msi_desc*) kmem_cache_alloc(msi_cachep, SLAB_KERNEL);
354 memset(entry, 0, sizeof(struct msi_desc));
355 entry->link.tail = entry->link.head = 0; /* single message */
361 static void attach_msi_entry(struct msi_desc *entry, int vector)
365 spin_lock_irqsave(&msi_lock, flags);
366 msi_desc[vector] = entry;
367 spin_unlock_irqrestore(&msi_lock, flags);
370 static void irq_handler_init(int cap_id, int pos, int mask)
372 spin_lock(&irq_desc[pos].lock);
373 if (cap_id == PCI_CAP_ID_MSIX)
374 irq_desc[pos].handler = &msix_irq_type;
377 irq_desc[pos].handler = &msi_irq_wo_maskbit_type;
379 irq_desc[pos].handler = &msi_irq_w_maskbit_type;
381 spin_unlock(&irq_desc[pos].lock);
384 static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
388 dev->bus->ops->read(dev->bus, dev->devfn,
389 msi_control_reg(pos), 2, &control);
390 if (type == PCI_CAP_ID_MSI) {
391 /* Set enabled bits to single MSI & enable MSI_enable bit */
392 msi_enable(control, 1);
393 dev->bus->ops->write(dev->bus, dev->devfn,
394 msi_control_reg(pos), 2, control);
396 msix_enable(control);
397 dev->bus->ops->write(dev->bus, dev->devfn,
398 msi_control_reg(pos), 2, control);
400 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
401 /* PCI Express Endpoint device detected */
403 dev->bus->ops->read(dev->bus, dev->devfn, PCI_COMMAND, 2, &cmd);
404 cmd |= PCI_COMMAND_INTX_DISABLE;
405 dev->bus->ops->write(dev->bus, dev->devfn, PCI_COMMAND, 2, cmd);
409 static void disable_msi_mode(struct pci_dev *dev, int pos, int type)
413 dev->bus->ops->read(dev->bus, dev->devfn,
414 msi_control_reg(pos), 2, &control);
415 if (type == PCI_CAP_ID_MSI) {
416 /* Set enabled bits to single MSI & enable MSI_enable bit */
417 msi_disable(control);
418 dev->bus->ops->write(dev->bus, dev->devfn,
419 msi_control_reg(pos), 2, control);
421 msix_disable(control);
422 dev->bus->ops->write(dev->bus, dev->devfn,
423 msi_control_reg(pos), 2, control);
425 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
426 /* PCI Express Endpoint device detected */
428 dev->bus->ops->read(dev->bus, dev->devfn, PCI_COMMAND, 2, &cmd);
429 cmd &= ~PCI_COMMAND_INTX_DISABLE;
430 dev->bus->ops->write(dev->bus, dev->devfn, PCI_COMMAND, 2, cmd);
434 static int msi_lookup_vector(struct pci_dev *dev)
439 spin_lock_irqsave(&msi_lock, flags);
440 for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) {
441 if (!msi_desc[vector] || msi_desc[vector]->dev != dev ||
442 msi_desc[vector]->msi_attrib.entry_nr ||
443 msi_desc[vector]->msi_attrib.default_vector != dev->irq)
444 continue; /* not entry 0, skip */
445 spin_unlock_irqrestore(&msi_lock, flags);
446 /* This pre-assigned entry-0 MSI vector for this device
447 already exits. Override dev->irq with this vector */
451 spin_unlock_irqrestore(&msi_lock, flags);
456 void pci_scan_msi_device(struct pci_dev *dev)
461 if (pci_find_capability(dev, PCI_CAP_ID_MSIX) > 0) {
462 nr_reserved_vectors++;
464 } else if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0)
465 nr_reserved_vectors++;
469 * msi_capability_init - configure device's MSI capability structure
470 * @dev: pointer to the pci_dev data structure of MSI device function
472 * Setup the MSI capability structure of device funtion with a single
473 * MSI vector, regardless of device function is capable of handling
474 * multiple messages. A return of zero indicates the successful setup
475 * of an entry zero with the new MSI vector or non-zero for otherwise.
477 static int msi_capability_init(struct pci_dev *dev)
479 struct msi_desc *entry;
480 struct msg_address address;
481 struct msg_data data;
485 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
489 dev->bus->ops->read(dev->bus, dev->devfn, msi_control_reg(pos),
491 if (control & PCI_MSI_FLAGS_ENABLE)
494 if (!msi_lookup_vector(dev)) {
496 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
499 /* MSI Entry Initialization */
500 if (!(entry = alloc_msi_entry()))
503 if ((vector = get_msi_vector(dev)) < 0) {
504 kmem_cache_free(msi_cachep, entry);
507 entry->msi_attrib.type = PCI_CAP_ID_MSI;
508 entry->msi_attrib.entry_nr = 0;
509 entry->msi_attrib.maskbit = is_mask_bit_support(control);
510 entry->msi_attrib.default_vector = dev->irq;
511 dev->irq = vector; /* save default pre-assigned ioapic vector */
513 if (is_mask_bit_support(control)) {
514 entry->mask_base = msi_mask_bits_reg(pos,
515 is_64bit_address(control));
517 /* Replace with MSI handler */
518 irq_handler_init(PCI_CAP_ID_MSI, vector, entry->msi_attrib.maskbit);
519 /* Configure MSI capability structure */
520 msi_address_init(&address);
521 msi_data_init(&data, vector);
522 entry->msi_attrib.current_cpu = ((address.lo_address.u.dest_id >>
523 MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
524 dev->bus->ops->write(dev->bus, dev->devfn, msi_lower_address_reg(pos),
525 4, address.lo_address.value);
526 if (is_64bit_address(control)) {
527 dev->bus->ops->write(dev->bus, dev->devfn,
528 msi_upper_address_reg(pos), 4, address.hi_address);
529 dev->bus->ops->write(dev->bus, dev->devfn,
530 msi_data_reg(pos, 1), 2, *((u32*)&data));
532 dev->bus->ops->write(dev->bus, dev->devfn,
533 msi_data_reg(pos, 0), 2, *((u32*)&data));
534 if (entry->msi_attrib.maskbit) {
535 unsigned int maskbits, temp;
536 /* All MSIs are unmasked by default, Mask them all */
537 dev->bus->ops->read(dev->bus, dev->devfn,
538 msi_mask_bits_reg(pos, is_64bit_address(control)), 4,
540 temp = (1 << multi_msi_capable(control));
541 temp = ((temp - 1) & ~temp);
543 dev->bus->ops->write(dev->bus, dev->devfn,
544 msi_mask_bits_reg(pos, is_64bit_address(control)), 4,
547 attach_msi_entry(entry, vector);
548 /* Set MSI enabled bits */
549 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
555 * msix_capability_init - configure device's MSI-X capability
556 * @dev: pointer to the pci_dev data structure of MSI-X device function
558 * Setup the MSI-X capability structure of device funtion with a
559 * single MSI-X vector. A return of zero indicates the successful setup
560 * of an entry zero with the new MSI-X vector or non-zero for otherwise.
561 * To request for additional MSI-X vectors, the device drivers are
562 * required to utilize the following supported APIs:
563 * 1) msi_alloc_vectors(...) for requesting one or more MSI-X vectors
564 * 2) msi_free_vectors(...) for releasing one or more MSI-X vectors
565 * back to PCI subsystem before calling free_irq(...)
567 static int msix_capability_init(struct pci_dev *dev)
569 struct msi_desc *entry;
570 struct msg_address address;
571 struct msg_data data;
572 int vector = 0, pos, dev_msi_cap, i;
573 u32 phys_addr, table_offset;
578 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
582 /* Request & Map MSI-X table region */
583 dev->bus->ops->read(dev->bus, dev->devfn, msi_control_reg(pos), 2,
585 if (control & PCI_MSIX_FLAGS_ENABLE)
588 if (!msi_lookup_vector(dev)) {
590 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
594 dev_msi_cap = multi_msix_capable(control);
595 dev->bus->ops->read(dev->bus, dev->devfn,
596 msix_table_offset_reg(pos), 4, &table_offset);
597 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
598 phys_addr = pci_resource_start (dev, bir);
599 phys_addr += (u32)(table_offset & ~PCI_MSIX_FLAGS_BIRMASK);
600 if (!request_mem_region(phys_addr,
601 dev_msi_cap * PCI_MSIX_ENTRY_SIZE,
602 "MSI-X iomap Failure"))
604 base = ioremap_nocache(phys_addr, dev_msi_cap * PCI_MSIX_ENTRY_SIZE);
607 /* MSI Entry Initialization */
608 entry = alloc_msi_entry();
611 if ((vector = get_msi_vector(dev)) < 0)
614 entry->msi_attrib.type = PCI_CAP_ID_MSIX;
615 entry->msi_attrib.entry_nr = 0;
616 entry->msi_attrib.maskbit = 1;
617 entry->msi_attrib.default_vector = dev->irq;
618 dev->irq = vector; /* save default pre-assigned ioapic vector */
620 entry->mask_base = (unsigned long)base;
621 /* Replace with MSI handler */
622 irq_handler_init(PCI_CAP_ID_MSIX, vector, 1);
623 /* Configure MSI-X capability structure */
624 msi_address_init(&address);
625 msi_data_init(&data, vector);
626 entry->msi_attrib.current_cpu = ((address.lo_address.u.dest_id >>
627 MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
628 writel(address.lo_address.value, base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
629 writel(address.hi_address, base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
630 writel(*(u32*)&data, base + PCI_MSIX_ENTRY_DATA_OFFSET);
631 /* Initialize all entries from 1 up to 0 */
632 for (i = 1; i < dev_msi_cap; i++) {
633 writel(0, base + i * PCI_MSIX_ENTRY_SIZE +
634 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
635 writel(0, base + i * PCI_MSIX_ENTRY_SIZE +
636 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
637 writel(0, base + i * PCI_MSIX_ENTRY_SIZE +
638 PCI_MSIX_ENTRY_DATA_OFFSET);
640 attach_msi_entry(entry, vector);
641 /* Set MSI enabled bits */
642 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
647 kmem_cache_free(msi_cachep, entry);
651 release_mem_region(phys_addr, dev_msi_cap * PCI_MSIX_ENTRY_SIZE);
653 return ((vector < 0) ? -EBUSY : -ENOMEM);
657 * pci_enable_msi - configure device's MSI(X) capability structure
658 * @dev: pointer to the pci_dev data structure of MSI(X) device function
660 * Setup the MSI/MSI-X capability structure of device function with
661 * a single MSI(X) vector upon its software driver call to request for
662 * MSI(X) mode enabled on its hardware device function. A return of zero
663 * indicates the successful setup of an entry zero with the new MSI(X)
664 * vector or non-zero for otherwise.
666 int pci_enable_msi(struct pci_dev* dev)
668 int status = -EINVAL;
670 if (!pci_msi_enable || !dev)
676 if ((status = msix_capability_init(dev)) == -EINVAL)
677 status = msi_capability_init(dev);
679 nr_reserved_vectors--;
684 static int msi_free_vector(struct pci_dev* dev, int vector);
685 static void pci_disable_msi(unsigned int vector)
687 int head, tail, type, default_vector;
688 struct msi_desc *entry;
692 spin_lock_irqsave(&msi_lock, flags);
693 entry = msi_desc[vector];
694 if (!entry || !entry->dev) {
695 spin_unlock_irqrestore(&msi_lock, flags);
699 type = entry->msi_attrib.type;
700 head = entry->link.head;
701 tail = entry->link.tail;
702 default_vector = entry->msi_attrib.default_vector;
703 spin_unlock_irqrestore(&msi_lock, flags);
705 disable_msi_mode(dev, pci_find_capability(dev, type), type);
706 /* Restore dev->irq to its default pin-assertion vector */
707 dev->irq = default_vector;
708 if (type == PCI_CAP_ID_MSIX && head != tail) {
709 /* Bad driver, which do not call msi_free_vectors before exit.
710 We must do a cleanup here */
712 spin_lock_irqsave(&msi_lock, flags);
713 entry = msi_desc[vector];
714 head = entry->link.head;
715 tail = entry->link.tail;
716 spin_unlock_irqrestore(&msi_lock, flags);
719 if (msi_free_vector(dev, entry->link.tail))
725 static int msi_alloc_vector(struct pci_dev* dev, int head)
727 struct msi_desc *entry;
728 struct msg_address address;
729 struct msg_data data;
730 int i, offset, pos, dev_msi_cap, vector;
731 u32 low_address, control;
732 unsigned long base = 0L;
735 spin_lock_irqsave(&msi_lock, flags);
736 entry = msi_desc[dev->irq];
738 spin_unlock_irqrestore(&msi_lock, flags);
741 base = entry->mask_base;
742 spin_unlock_irqrestore(&msi_lock, flags);
744 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
745 dev->bus->ops->read(dev->bus, dev->devfn, msi_control_reg(pos),
747 dev_msi_cap = multi_msix_capable(control);
748 for (i = 1; i < dev_msi_cap; i++) {
749 if (!(low_address = readl(base + i * PCI_MSIX_ENTRY_SIZE)))
752 if (i >= dev_msi_cap)
755 /* MSI Entry Initialization */
756 if (!(entry = alloc_msi_entry()))
759 if ((vector = get_new_vector()) < 0) {
760 kmem_cache_free(msi_cachep, entry);
763 entry->msi_attrib.type = PCI_CAP_ID_MSIX;
764 entry->msi_attrib.entry_nr = i;
765 entry->msi_attrib.maskbit = 1;
767 entry->link.head = head;
768 entry->mask_base = base;
769 irq_handler_init(PCI_CAP_ID_MSIX, vector, 1);
770 /* Configure MSI-X capability structure */
771 msi_address_init(&address);
772 msi_data_init(&data, vector);
773 entry->msi_attrib.current_cpu = ((address.lo_address.u.dest_id >>
774 MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
775 offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
776 writel(address.lo_address.value, base + offset +
777 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
778 writel(address.hi_address, base + offset +
779 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
780 writel(*(u32*)&data, base + offset + PCI_MSIX_ENTRY_DATA_OFFSET);
781 writel(1, base + offset + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
782 attach_msi_entry(entry, vector);
787 static int msi_free_vector(struct pci_dev* dev, int vector)
789 struct msi_desc *entry;
791 unsigned long base = 0L;
794 spin_lock_irqsave(&msi_lock, flags);
795 entry = msi_desc[vector];
796 if (!entry || entry->dev != dev) {
797 spin_unlock_irqrestore(&msi_lock, flags);
800 type = entry->msi_attrib.type;
801 entry_nr = entry->msi_attrib.entry_nr;
802 base = entry->mask_base;
803 if (entry->link.tail != entry->link.head) {
804 msi_desc[entry->link.head]->link.tail = entry->link.tail;
805 if (entry->link.tail)
806 msi_desc[entry->link.tail]->link.head = entry->link.head;
809 vector_irq[vector] = 0;
810 nr_released_vectors++;
811 msi_desc[vector] = NULL;
812 spin_unlock_irqrestore(&msi_lock, flags);
814 kmem_cache_free(msi_cachep, entry);
815 if (type == PCI_CAP_ID_MSIX) {
818 offset = entry_nr * PCI_MSIX_ENTRY_SIZE;
819 writel(1, base + offset + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
820 writel(0, base + offset + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
827 * msi_alloc_vectors - allocate additional MSI-X vectors
828 * @dev: pointer to the pci_dev data structure of MSI-X device function
829 * @vector: pointer to an array of new allocated MSI-X vectors
830 * @nvec: number of MSI-X vectors requested for allocation by device driver
832 * Allocate additional MSI-X vectors requested by device driver. A
833 * return of zero indicates the successful setup of MSI-X capability
834 * structure with new allocated MSI-X vectors or non-zero for otherwise.
836 int msi_alloc_vectors(struct pci_dev* dev, int *vector, int nvec)
838 struct msi_desc *entry;
839 int i, head, pos, vec, free_vectors, alloc_vectors;
840 int *vectors = (int *)vector;
844 if (!pci_msi_enable || !dev)
847 if (!(pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)))
850 dev->bus->ops->read(dev->bus, dev->devfn, msi_control_reg(pos), 2, &control);
851 if (nvec > multi_msix_capable(control))
854 spin_lock_irqsave(&msi_lock, flags);
855 entry = msi_desc[dev->irq];
856 if (!entry || entry->dev != dev || /* legal call */
857 entry->msi_attrib.type != PCI_CAP_ID_MSIX || /* must be MSI-X */
858 entry->link.head != entry->link.tail) { /* already multi */
859 spin_unlock_irqrestore(&msi_lock, flags);
863 * msi_lock is provided to ensure that enough vectors resources are
864 * available before granting.
866 free_vectors = pci_vector_resources(last_alloc_vector,
867 nr_released_vectors);
868 /* Ensure that each MSI/MSI-X device has one vector reserved by
869 default to avoid any MSI-X driver to take all available
871 free_vectors -= nr_reserved_vectors;
872 /* Find the average of free vectors among MSI-X devices */
873 if (nr_msix_devices > 0)
874 free_vectors /= nr_msix_devices;
875 spin_unlock_irqrestore(&msi_lock, flags);
877 if (nvec > free_vectors)
882 for (i = 0; i < nvec; i++) {
883 if ((vec = msi_alloc_vector(dev, head)) < 0)
885 *(vectors + i) = vec;
889 if (alloc_vectors != nvec) {
890 for (i = 0; i < alloc_vectors; i++) {
891 vec = *(vectors + i);
892 msi_free_vector(dev, vec);
894 spin_lock_irqsave(&msi_lock, flags);
895 msi_desc[dev->irq]->link.tail = msi_desc[dev->irq]->link.head;
896 spin_unlock_irqrestore(&msi_lock, flags);
899 if (nr_msix_devices > 0)
906 * msi_free_vectors - reclaim MSI-X vectors to unused state
907 * @dev: pointer to the pci_dev data structure of MSI-X device function
908 * @vector: pointer to an array of released MSI-X vectors
909 * @nvec: number of MSI-X vectors requested for release by device driver
911 * Reclaim MSI-X vectors released by device driver to unused state,
912 * which may be used later on. A return of zero indicates the
913 * success or non-zero for otherwise. Device driver should call this
914 * before calling function free_irq.
916 int msi_free_vectors(struct pci_dev* dev, int *vector, int nvec)
918 struct msi_desc *entry;
925 spin_lock_irqsave(&msi_lock, flags);
926 entry = msi_desc[dev->irq];
927 if (!entry || entry->dev != dev ||
928 entry->msi_attrib.type != PCI_CAP_ID_MSIX ||
929 entry->link.head == entry->link.tail) { /* Nothing to free */
930 spin_unlock_irqrestore(&msi_lock, flags);
933 spin_unlock_irqrestore(&msi_lock, flags);
935 for (i = 0; i < nvec; i++) {
936 if (*(vector + i) == dev->irq)
937 continue;/* Don't free entry 0 if mistaken by driver */
938 msi_free_vector(dev, *(vector + i));
945 * msi_remove_pci_irq_vectors - reclaim MSI(X) vectors to unused state
946 * @dev: pointer to the pci_dev data structure of MSI(X) device function
948 * Being called during hotplug remove, from which the device funciton
949 * is hot-removed. All previous assigned MSI/MSI-X vectors, if
950 * allocated for this device function, are reclaimed to unused state,
951 * which may be used later on.
953 void msi_remove_pci_irq_vectors(struct pci_dev* dev)
955 struct msi_desc *entry;
959 if (!pci_msi_enable || !dev)
962 if (!pci_find_capability(dev, PCI_CAP_ID_MSI)) {
963 if (!pci_find_capability(dev, PCI_CAP_ID_MSIX))
967 if (msi_lookup_vector(dev))
970 spin_lock_irqsave(&msi_lock, flags);
971 entry = msi_desc[dev->irq];
972 if (!entry || entry->dev != dev) {
973 spin_unlock_irqrestore(&msi_lock, flags);
976 type = entry->msi_attrib.type;
977 spin_unlock_irqrestore(&msi_lock, flags);
979 msi_free_vector(dev, dev->irq);
980 if (type == PCI_CAP_ID_MSIX) {
981 int i, pos, dev_msi_cap;
982 u32 phys_addr, table_offset;
986 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
987 dev->bus->ops->read(dev->bus, dev->devfn, msi_control_reg(pos), 2, &control);
988 dev_msi_cap = multi_msix_capable(control);
989 dev->bus->ops->read(dev->bus, dev->devfn,
990 msix_table_offset_reg(pos), 4, &table_offset);
991 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
992 phys_addr = pci_resource_start (dev, bir);
993 phys_addr += (u32)(table_offset & ~PCI_MSIX_FLAGS_BIRMASK);
994 for (i = FIRST_DEVICE_VECTOR; i < NR_IRQS; i++) {
995 spin_lock_irqsave(&msi_lock, flags);
996 if (!msi_desc[i] || msi_desc[i]->dev != dev) {
997 spin_unlock_irqrestore(&msi_lock, flags);
1000 spin_unlock_irqrestore(&msi_lock, flags);
1001 msi_free_vector(dev, i);
1003 writel(1, entry->mask_base + PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
1004 iounmap((void*)entry->mask_base);
1005 release_mem_region(phys_addr, dev_msi_cap * PCI_MSIX_ENTRY_SIZE);
1008 nr_reserved_vectors++;
1011 EXPORT_SYMBOL(pci_enable_msi);
1012 EXPORT_SYMBOL(msi_alloc_vectors);
1013 EXPORT_SYMBOL(msi_free_vectors);