2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
12 #include <linux/delay.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <asm/dma.h> /* isa_dma_bridge_buggy */
22 #define DBG(x...) printk(x)
28 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
29 * @bus: pointer to PCI bus structure to search
31 * Given a PCI bus, returns the highest PCI bus number present in the set
32 * including the given PCI bus and its list of child PCI buses.
34 unsigned char __devinit
35 pci_bus_max_busnr(struct pci_bus* bus)
37 struct list_head *tmp;
41 list_for_each(tmp, &bus->children) {
42 n = pci_bus_max_busnr(pci_bus_b(tmp));
50 * pci_max_busnr - returns maximum PCI bus number
52 * Returns the highest PCI bus number present in the system global list of
55 unsigned char __devinit
58 struct pci_bus *bus = NULL;
62 while ((bus = pci_find_next_bus(bus)) != NULL) {
63 n = pci_bus_max_busnr(bus);
70 static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap)
76 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
77 if (!(status & PCI_STATUS_CAP_LIST))
81 case PCI_HEADER_TYPE_NORMAL:
82 case PCI_HEADER_TYPE_BRIDGE:
83 pci_bus_read_config_byte(bus, devfn, PCI_CAPABILITY_LIST, &pos);
85 case PCI_HEADER_TYPE_CARDBUS:
86 pci_bus_read_config_byte(bus, devfn, PCI_CB_CAPABILITY_LIST, &pos);
91 while (ttl-- && pos >= 0x40) {
93 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, &id);
98 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_NEXT, &pos);
104 * pci_find_capability - query for devices' capabilities
105 * @dev: PCI device to query
106 * @cap: capability code
108 * Tell if a device supports a given PCI capability.
109 * Returns the address of the requested capability structure within the
110 * device's PCI configuration space or 0 in case the device does not
111 * support it. Possible values for @cap:
113 * %PCI_CAP_ID_PM Power Management
114 * %PCI_CAP_ID_AGP Accelerated Graphics Port
115 * %PCI_CAP_ID_VPD Vital Product Data
116 * %PCI_CAP_ID_SLOTID Slot Identification
117 * %PCI_CAP_ID_MSI Message Signalled Interrupts
118 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
119 * %PCI_CAP_ID_PCIX PCI-X
120 * %PCI_CAP_ID_EXP PCI Express
122 int pci_find_capability(struct pci_dev *dev, int cap)
124 return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap);
128 * pci_bus_find_capability - query for devices' capabilities
129 * @bus: the PCI bus to query
130 * @devfn: PCI device to query
131 * @cap: capability code
133 * Like pci_find_capability() but works for pci devices that do not have a
134 * pci_dev structure set up yet.
136 * Returns the address of the requested capability structure within the
137 * device's PCI configuration space or 0 in case the device does not
140 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
144 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
146 return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap);
150 * pci_find_ext_capability - Find an extended capability
151 * @dev: PCI device to query
152 * @cap: capability code
154 * Returns the address of the requested extended capability structure
155 * within the device's PCI configuration space or 0 if the device does
156 * not support it. Possible values for @cap:
158 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
159 * %PCI_EXT_CAP_ID_VC Virtual Channel
160 * %PCI_EXT_CAP_ID_DSN Device Serial Number
161 * %PCI_EXT_CAP_ID_PWR Power Budgeting
163 int pci_find_ext_capability(struct pci_dev *dev, int cap)
166 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
169 if (dev->cfg_size <= 256)
172 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
176 * If we have no capabilities, this is indicated by cap ID,
177 * cap version and next pointer all being 0.
183 if (PCI_EXT_CAP_ID(header) == cap)
186 pos = PCI_EXT_CAP_NEXT(header);
190 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
198 * pci_find_parent_resource - return resource region of parent bus of given region
199 * @dev: PCI device structure contains resources to be searched
200 * @res: child resource record for which parent is sought
202 * For given resource region of given device, return the resource
203 * region of parent bus the given region is contained in or where
204 * it should be allocated from.
207 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
209 const struct pci_bus *bus = dev->bus;
211 struct resource *best = NULL;
213 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
214 struct resource *r = bus->resource[i];
217 if (res->start && !(res->start >= r->start && res->end <= r->end))
218 continue; /* Not contained */
219 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
220 continue; /* Wrong type */
221 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
222 return r; /* Exact match */
223 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
224 best = r; /* Approximating prefetchable by non-prefetchable */
230 * pci_set_power_state - Set the power state of a PCI device
231 * @dev: PCI device to be suspended
232 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
234 * Transition a device to a new power state, using the Power Management
235 * Capabilities in the device's config space.
238 * -EINVAL if trying to enter a lower state than we're already in.
239 * 0 if we're already in the requested state.
240 * -EIO if device does not support PCI PM.
241 * 0 if we can successfully change the power state.
245 pci_set_power_state(struct pci_dev *dev, pci_power_t state)
250 /* bound the state we're entering */
251 if (state > PCI_D3hot)
254 /* Validate current state:
255 * Can enter D0 from any state, but if we can only go deeper
256 * to sleep if we're already in a low power state
258 if (state != PCI_D0 && dev->current_state > state)
260 else if (dev->current_state == state)
261 return 0; /* we're already there */
263 /* find PCI PM capability in list */
264 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
266 /* abort if the device doesn't support PM capabilities */
270 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
271 if ((pmc & PCI_PM_CAP_VER_MASK) > 2) {
273 "PCI: %s has unsupported PM cap regs version (%u)\n",
274 dev->slot_name, pmc & PCI_PM_CAP_VER_MASK);
278 /* check if this device supports the desired state */
279 if (state == PCI_D1 || state == PCI_D2) {
280 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
282 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
286 /* If we're in D3, force entire word to 0.
287 * This doesn't affect PME_Status, disables PME_En, and
288 * sets PowerState to 0.
290 if (dev->current_state >= PCI_D3hot)
293 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
294 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
298 /* enter specified state */
299 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
301 /* Mandatory power management transition delays */
302 /* see PCI PM 1.1 5.6.1 table 18 */
303 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
305 else if (state == PCI_D2 || dev->current_state == PCI_D2)
307 dev->current_state = state;
313 * pci_choose_state - Choose the power state of a PCI device
314 * @dev: PCI device to be suspended
315 * @state: target sleep state for the whole system
317 * Returns PCI power state suitable for given device and given system
321 pci_power_t pci_choose_state(struct pci_dev *dev, u32 state)
323 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
327 case 0: return PCI_D0;
328 case 2: return PCI_D2;
329 case 3: return PCI_D3hot;
335 EXPORT_SYMBOL(pci_choose_state);
338 * pci_save_state - save the PCI configuration space of a device before suspending
339 * @dev: - PCI device that we're dealing with
340 * @buffer: - buffer to hold config space context
342 * @buffer must be large enough to hold the entire PCI 2.2 config space
346 pci_save_state(struct pci_dev *dev)
349 /* XXX: 100% dword access ok here? */
350 for (i = 0; i < 16; i++)
351 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
356 * pci_restore_state - Restore the saved state of a PCI device
357 * @dev: - PCI device that we're dealing with
358 * @buffer: - saved PCI config space
362 pci_restore_state(struct pci_dev *dev)
366 for (i = 0; i < 16; i++)
367 pci_write_config_dword(dev,i * 4, dev->saved_config_space[i]);
372 * pci_enable_device_bars - Initialize some of a device for use
373 * @dev: PCI device to be initialized
374 * @bars: bitmask of BAR's that must be configured
376 * Initialize device before it's used by a driver. Ask low-level code
377 * to enable selected I/O and memory resources. Wake up the device if it
378 * was suspended. Beware, this function can fail.
382 pci_enable_device_bars(struct pci_dev *dev, int bars)
386 pci_set_power_state(dev, PCI_D0);
387 if ((err = pcibios_enable_device(dev, bars)) < 0)
393 * pci_enable_device - Initialize device before it's used by a driver.
394 * @dev: PCI device to be initialized
396 * Initialize device before it's used by a driver. Ask low-level code
397 * to enable I/O and memory. Wake up the device if it was suspended.
398 * Beware, this function can fail.
401 pci_enable_device(struct pci_dev *dev)
406 if ((err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1)))
408 pci_fixup_device(pci_fixup_enable, dev);
413 * pcibios_disable_device - disable arch specific PCI resources for device dev
414 * @dev: the PCI device to disable
416 * Disables architecture specific PCI resources for the device. This
417 * is the default implementation. Architecture implementations can
420 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
423 * pci_disable_device - Disable PCI device after use
424 * @dev: PCI device to be disabled
426 * Signal to the system that the PCI device is not in use by the system
427 * anymore. This only involves disabling PCI bus-mastering, if active.
430 pci_disable_device(struct pci_dev *dev)
435 dev->is_busmaster = 0;
437 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
438 if (pci_command & PCI_COMMAND_MASTER) {
439 pci_command &= ~PCI_COMMAND_MASTER;
440 pci_write_config_word(dev, PCI_COMMAND, pci_command);
443 pcibios_disable_device(dev);
447 * pci_enable_wake - enable device to generate PME# when suspended
448 * @dev: - PCI device to operate on
449 * @state: - Current state of device.
450 * @enable: - Flag to enable or disable generation
452 * Set the bits in the device's PM Capabilities to generate PME# when
453 * the system is suspended.
455 * -EIO is returned if device doesn't have PM Capabilities.
456 * -EINVAL is returned if device supports it, but can't generate wake events.
457 * 0 if operation is successful.
460 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
465 /* find PCI PM capability in list */
466 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
468 /* If device doesn't support PM Capabilities, but request is to disable
469 * wake events, it's a nop; otherwise fail */
471 return enable ? -EIO : 0;
473 /* Check device's ability to generate PME# */
474 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
476 value &= PCI_PM_CAP_PME_MASK;
477 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
479 /* Check if it can generate PME# from requested state. */
480 if (!value || !(value & (1 << state)))
481 return enable ? -EINVAL : 0;
483 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
485 /* Clear PME_Status by writing 1 to it and enable PME# */
486 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
489 value &= ~PCI_PM_CTRL_PME_ENABLE;
491 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
497 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
501 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
505 while (dev->bus->self) {
506 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
507 dev = dev->bus->self;
514 * pci_release_region - Release a PCI bar
515 * @pdev: PCI device whose resources were previously reserved by pci_request_region
516 * @bar: BAR to release
518 * Releases the PCI I/O and memory resources previously reserved by a
519 * successful call to pci_request_region. Call this function only
520 * after all use of the PCI regions has ceased.
522 void pci_release_region(struct pci_dev *pdev, int bar)
524 if (pci_resource_len(pdev, bar) == 0)
526 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
527 release_region(pci_resource_start(pdev, bar),
528 pci_resource_len(pdev, bar));
529 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
530 release_mem_region(pci_resource_start(pdev, bar),
531 pci_resource_len(pdev, bar));
535 * pci_request_region - Reserved PCI I/O and memory resource
536 * @pdev: PCI device whose resources are to be reserved
537 * @bar: BAR to be reserved
538 * @res_name: Name to be associated with resource.
540 * Mark the PCI region associated with PCI device @pdev BR @bar as
541 * being reserved by owner @res_name. Do not access any
542 * address inside the PCI regions unless this call returns
545 * Returns 0 on success, or %EBUSY on error. A warning
546 * message is also printed on failure.
548 int pci_request_region(struct pci_dev *pdev, int bar, char *res_name)
550 if (pci_resource_len(pdev, bar) == 0)
553 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
554 if (!request_region(pci_resource_start(pdev, bar),
555 pci_resource_len(pdev, bar), res_name))
558 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
559 if (!request_mem_region(pci_resource_start(pdev, bar),
560 pci_resource_len(pdev, bar), res_name))
567 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n",
568 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
569 bar + 1, /* PCI BAR # */
570 pci_resource_len(pdev, bar), pci_resource_start(pdev, bar),
577 * pci_release_regions - Release reserved PCI I/O and memory resources
578 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
580 * Releases all PCI I/O and memory resources previously reserved by a
581 * successful call to pci_request_regions. Call this function only
582 * after all use of the PCI regions has ceased.
585 void pci_release_regions(struct pci_dev *pdev)
589 for (i = 0; i < 6; i++)
590 pci_release_region(pdev, i);
594 * pci_request_regions - Reserved PCI I/O and memory resources
595 * @pdev: PCI device whose resources are to be reserved
596 * @res_name: Name to be associated with resource.
598 * Mark all PCI regions associated with PCI device @pdev as
599 * being reserved by owner @res_name. Do not access any
600 * address inside the PCI regions unless this call returns
603 * Returns 0 on success, or %EBUSY on error. A warning
604 * message is also printed on failure.
606 int pci_request_regions(struct pci_dev *pdev, char *res_name)
610 for (i = 0; i < 6; i++)
611 if(pci_request_region(pdev, i, res_name))
617 pci_release_region(pdev, i);
623 * pci_set_master - enables bus-mastering for device dev
624 * @dev: the PCI device to enable
626 * Enables bus-mastering on the device and calls pcibios_set_master()
627 * to do the needed arch specific settings.
630 pci_set_master(struct pci_dev *dev)
634 pci_read_config_word(dev, PCI_COMMAND, &cmd);
635 if (! (cmd & PCI_COMMAND_MASTER)) {
636 DBG("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
637 cmd |= PCI_COMMAND_MASTER;
638 pci_write_config_word(dev, PCI_COMMAND, cmd);
640 dev->is_busmaster = 1;
641 pcibios_set_master(dev);
644 #ifndef HAVE_ARCH_PCI_MWI
645 /* This can be overridden by arch code. */
646 u8 pci_cache_line_size = L1_CACHE_BYTES >> 2;
649 * pci_generic_prep_mwi - helper function for pci_set_mwi
650 * @dev: the PCI device for which MWI is enabled
652 * Helper function for generic implementation of pcibios_prep_mwi
653 * function. Originally copied from drivers/net/acenic.c.
654 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
656 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
659 pci_generic_prep_mwi(struct pci_dev *dev)
663 if (!pci_cache_line_size)
664 return -EINVAL; /* The system doesn't support MWI. */
666 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
667 equal to or multiple of the right value. */
668 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
669 if (cacheline_size >= pci_cache_line_size &&
670 (cacheline_size % pci_cache_line_size) == 0)
673 /* Write the correct value. */
674 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
676 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
677 if (cacheline_size == pci_cache_line_size)
680 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
681 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
685 #endif /* !HAVE_ARCH_PCI_MWI */
688 * pci_set_mwi - enables memory-write-invalidate PCI transaction
689 * @dev: the PCI device for which MWI is enabled
691 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
692 * and then calls @pcibios_set_mwi to do the needed arch specific
693 * operations or a generic mwi-prep function.
695 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
698 pci_set_mwi(struct pci_dev *dev)
703 #ifdef HAVE_ARCH_PCI_MWI
704 rc = pcibios_prep_mwi(dev);
706 rc = pci_generic_prep_mwi(dev);
712 pci_read_config_word(dev, PCI_COMMAND, &cmd);
713 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
714 DBG("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
715 cmd |= PCI_COMMAND_INVALIDATE;
716 pci_write_config_word(dev, PCI_COMMAND, cmd);
723 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
724 * @dev: the PCI device to disable
726 * Disables PCI Memory-Write-Invalidate transaction on the device
729 pci_clear_mwi(struct pci_dev *dev)
733 pci_read_config_word(dev, PCI_COMMAND, &cmd);
734 if (cmd & PCI_COMMAND_INVALIDATE) {
735 cmd &= ~PCI_COMMAND_INVALIDATE;
736 pci_write_config_word(dev, PCI_COMMAND, cmd);
740 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
742 * These can be overridden by arch-specific implementations
745 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
747 if (!pci_dma_supported(dev, mask))
750 dev->dma_mask = mask;
756 pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask)
758 if (!pci_dac_dma_supported(dev, mask))
761 dev->dma_mask = mask;
767 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
769 if (!pci_dma_supported(dev, mask))
772 dev->dev.coherent_dma_mask = mask;
778 static int __devinit pci_init(void)
780 struct pci_dev *dev = NULL;
782 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
783 pci_fixup_device(pci_fixup_final, dev);
788 static int __devinit pci_setup(char *str)
791 char *k = strchr(str, ',');
794 if (*str && (str = pcibios_setup(str)) && *str) {
795 /* PCI layer options should be handled here */
796 printk(KERN_ERR "PCI: Unknown option `%s'\n", str);
803 device_initcall(pci_init);
805 __setup("pci=", pci_setup);
807 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
808 /* FIXME: Some boxes have multiple ISA bridges! */
809 struct pci_dev *isa_bridge;
810 EXPORT_SYMBOL(isa_bridge);
813 EXPORT_SYMBOL(pci_enable_device_bars);
814 EXPORT_SYMBOL(pci_enable_device);
815 EXPORT_SYMBOL(pci_disable_device);
816 EXPORT_SYMBOL(pci_max_busnr);
817 EXPORT_SYMBOL(pci_bus_max_busnr);
818 EXPORT_SYMBOL(pci_find_capability);
819 EXPORT_SYMBOL(pci_bus_find_capability);
820 EXPORT_SYMBOL(pci_release_regions);
821 EXPORT_SYMBOL(pci_request_regions);
822 EXPORT_SYMBOL(pci_release_region);
823 EXPORT_SYMBOL(pci_request_region);
824 EXPORT_SYMBOL(pci_set_master);
825 EXPORT_SYMBOL(pci_set_mwi);
826 EXPORT_SYMBOL(pci_clear_mwi);
827 EXPORT_SYMBOL(pci_set_dma_mask);
828 EXPORT_SYMBOL(pci_dac_set_dma_mask);
829 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
830 EXPORT_SYMBOL(pci_assign_resource);
831 EXPORT_SYMBOL(pci_find_parent_resource);
833 EXPORT_SYMBOL(pci_set_power_state);
834 EXPORT_SYMBOL(pci_save_state);
835 EXPORT_SYMBOL(pci_restore_state);
836 EXPORT_SYMBOL(pci_enable_wake);
840 EXPORT_SYMBOL(isa_dma_bridge_buggy);
841 EXPORT_SYMBOL(pci_pci_problems);